Memory, preparation method and electronic equipment

Abstract

The invention provides a memory, a preparation method and electronic equipment. The memory comprises a first substrate which comprises a plurality of memory areas and a dummy area surrounding the plurality of memory areas; wherein the plurality of storage areas are arranged in an array and are mutually spaced; a plurality of active regions are arranged in the first substrate, and the plurality of active regions spread all over the plurality of storage regions and the dummy region; the plurality of active regions extend along a first direction; in the first direction, the distance between any two adjacent active regions in the storage region and the dummy region is equal to the distance between two adjacent active regions in the dummy region; and the plurality of storage structures are positioned on the first substrate and are respectively coupled with the corresponding active areas in the plurality of storage areas.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to a memory, a manufacturing method, and an electronic device. Background Art

[0002] With the development of semiconductor technology, the integration requirements of memories are getting higher and higher, and the performance standards are getting higher and higher. The existing semiconductor structures are increasingly difficult to meet the development needs. Therefore, it is necessary to further optimize the structure of the memory to improve the integration. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory, a manufacturing method, and an electronic device, which reduce the distance between adjacent memory blocks, thereby being able to reduce the chip size and improve the integration to increase the number of chips per wafer.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] The present disclosure provides a memory, including: a first substrate including a plurality of memory regions and a dummy region surrounding the plurality of memory regions; wherein, the plurality of memory regions are arranged in an array and spaced apart from each other; a plurality of active regions are provided in the first substrate, and the plurality of active regions cover the plurality of memory regions and the dummy region; the plurality of active regions all extend along a first direction; in the first direction, the distance between any two adjacent active regions respectively located in the memory region and the dummy region is equal to the distance between two adjacent active regions in the dummy region; a plurality of memory structures are located on the first substrate and are respectively coupled to the corresponding active regions in the plurality of memory regions.

[0006] In the above solution, it further includes: a plurality of word lines located in the first substrate and extending along a second direction, and respectively coupled to the corresponding active regions in the plurality of memory regions; a plurality of bit lines extending along a third direction and respectively coupled to the corresponding active regions in the plurality of memory regions; the second direction intersects the third direction.

[0007] In the above solution, the memory further includes: a plurality of first contact plugs, a plurality of first connection lines, and a plurality of first contact structures, all located in the dummy region between two adjacent memory regions in the second direction; wherein, two word lines located on the same straight line in two adjacent memory regions are respectively coupled through one first contact plug and the same first connection line; the word lines coupled to the plurality of first connection lines in two adjacent memory regions are odd-order word lines or even-order word lines; the plurality of first contact structures are located on the side of the plurality of first connection lines away from the plurality of word lines, and each first connection line is coupled to one first contact structure.

[0008] In the above solution, a plurality of the first contact structures in the dummy region between two adjacent ones of the storage regions in the second direction are arranged in a staggered manner; a plurality of the first connection lines all extend in the second direction, and the width of each of the first connection lines has a local maximum value at the coupling position with the first contact plug and / or the first contact structure.

[0009] In the above solution, the memory further includes: a plurality of second contact plugs, a plurality of second connection lines, and a plurality of second contact structures, which are located in the dummy region between two adjacent ones of the storage regions in the third direction; wherein, two bit lines in the same straight line in two adjacent ones of the storage regions are respectively coupled through a second contact plug and a second connection line, and the two second connection lines respectively coupled to the two bit lines are arranged at intervals in the third direction; the bit lines coupled to the plurality of second connection lines in two adjacent ones of the storage regions are odd-order bit lines or even-order bit lines; the plurality of second contact structures are located on one side of the plurality of second connection lines away from the plurality of bit lines, and each bit line is coupled to a second contact structure.

[0010] In the above solution, a plurality of the second contact structures in the dummy region between two adjacent ones of the storage regions in the third direction are arranged in a staggered manner; a plurality of the second connection lines all extend in the third direction, and the width of each second connection line has a local maximum value at the coupling position with the second contact structure.

[0011] In the above solution, it further includes: a plurality of contact pads; wherein, the plurality of storage structures are respectively coupled to the corresponding active regions in the plurality of storage regions through the plurality of contact pads; the plurality of contact pads, the plurality of first connection lines, and the plurality of second connection lines are arranged in the same layer.

[0012] In the above solution, the memory further includes: a second substrate, which is bonded to the first substrate and is provided with a control circuit; the control circuit is respectively coupled to the plurality of first contact structures and the plurality of second contact structures.

[0013] In the above solution, a plurality of the bit lines are located between the first substrate and the plurality of storage structures; or, a plurality of the bit lines are located on one side of the plurality of active regions away from the plurality of storage structures.

[0014] In the above solution, the storage structure includes any one of a capacitor, a magnetic tunnel junction, a phase change memory device, and a ferroelectric crystal memory device.

[0015] The present disclosure also provides a method for manufacturing a semiconductor structure, including: providing a first substrate; wherein, the first substrate has a plurality of storage regions and a dummy region surrounding the plurality of storage regions, and the plurality of storage regions are arranged in an array and spaced apart from each other; forming a plurality of active regions on the top surfaces of the plurality of storage regions and the dummy region; wherein, the plurality of active regions all extend in a first direction; in the first direction, the distance between any two adjacent active regions respectively located in a storage region and the dummy region is equal to the distance between two adjacent active regions in the dummy region; forming a plurality of storage structures on the plurality of active regions; wherein, the plurality of storage structures are respectively coupled to the corresponding active regions in the plurality of storage regions.

[0016] In the above solution, the manufacturing method further includes: forming a plurality of word lines extending in a second direction in the substrate; wherein, the plurality of word lines are respectively coupled to the corresponding active regions in the plurality of storage regions; forming a plurality of bit lines extending in a third direction between the first substrate and the plurality of storage structures, or on a side of the plurality of active regions away from the plurality of storage structures; wherein, the plurality of bit lines are respectively coupled to the corresponding active regions in the plurality of storage regions; the second direction intersects the third direction.

[0017] In the above solution, the manufacturing method further includes: forming a plurality of first contact plugs, a plurality of first connection lines and a plurality of first contact structures in the dummy region between two adjacent storage regions in the second direction; wherein, two word lines located on the same straight line in two adjacent storage regions are respectively coupled through one first contact plug and the same first connection line; the word lines coupled to the plurality of first connection lines in two adjacent storage regions are odd-order word lines or even-order word lines. The plurality of first contact structures are located on a side of the plurality of first connection lines away from the plurality of word lines, and each first connection line is coupled to one first contact structure.

[0018] In the above solution, the manufacturing method further includes: forming a plurality of second contact plugs, a plurality of second connection lines and a plurality of second contact structures in the dummy region between two adjacent storage regions in the third direction; wherein, two bit lines located on the same straight line in two adjacent storage regions are respectively coupled through one second contact plug and one second connection line, and the two second connection lines respectively coupled to the two bit lines are spaced apart in the third direction; the bit lines coupled to the plurality of second connection lines in two adjacent storage regions are odd-order bit lines or even-order bit lines; the plurality of second contact structures are located on a side of the plurality of second connection lines away from the plurality of bit lines, and each bit line is coupled to one second contact structure.

[0019] The present disclosure also provides an electronic device, including: a processor and the memory described in the above solution; the memory is coupled to the processor.

[0020] The present disclosure provides a memory, including: a first substrate including a plurality of storage regions and dummy regions surrounding the plurality of storage regions; wherein, the plurality of storage regions are arranged in an array and spaced apart from each other; a plurality of active regions are provided in the first substrate, and the plurality of active regions cover the plurality of storage regions and the dummy regions; the plurality of active regions all extend in a first direction; in the first direction, the distance between two adjacent active regions located in the storage region and the dummy region respectively is equal to the distance between two adjacent active regions in the dummy region; a plurality of memory structures are located on the first substrate and are respectively coupled to the corresponding active regions in the plurality of storage regions. In this way, two memory array chips formed on two adjacent storage regions share the dummy region therebetween. Thus, the present disclosure can reduce the distance between adjacent memory array chips, and further, can reduce the area of the chip and improve the integration degree. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Structural schematic diagram of the memory provided by an embodiment of the present disclosure Figure 1 ;

[0022] Figure 2 Structural schematic diagram of the prior art provided by an embodiment of the present disclosure;

[0023] Figure 3 Structural schematic diagram of the memory provided by an embodiment of the present disclosure Figure 2 ;

[0024] Figure 4 Structural schematic diagram of the memory provided by an embodiment of the present disclosure Figure 3 ;

[0025] Figure 5 Structural schematic diagram of the memory provided by an embodiment of the present disclosure Figure 4 ;

[0026] Figure 6 Structural schematic diagram of the memory provided by an embodiment of the present disclosure Figure 5 ;

[0027] Figure 7 Structural schematic diagram of the memory provided by an embodiment of the present disclosure Figure 6 ;

[0028] Figure 8 Structural schematic diagram of the memory provided by an embodiment of the present disclosure Figure 7 ;

[0029] Figure 9 Structural schematic diagram of the memory provided by an embodiment of the present disclosureFigure 8 ;

[0030] Figure 10 Structural schematic of the memory provided by an embodiment of the present disclosure Figure 9 ;

[0031] Figure 11 Flow schematic of the method for manufacturing the memory provided by an embodiment of the present disclosure;

[0032] Figure 12 Structural schematic of the electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations to the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0034] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0035] If similar descriptions such as "first / second" appear in the disclosure document, the following explanation is added. In the following description, the terms "first / second / third" only distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art belonging to the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0037] It should be noted that in the present disclosure, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element.

[0038] Figure 1 is a schematic structural diagram of an optional memory provided by an embodiment of the present disclosure. Refer to Figure 1 , the memory 100 includes: a first substrate 10, including a plurality of storage regions 101 and a dummy area 102 surrounding the plurality of storage regions 101; wherein, the plurality of storage regions 101 are arranged in an array and spaced apart from each other. A plurality of active regions (ACT) 110 are provided in the first substrate 10, and the plurality of active regions 110 are distributed throughout the plurality of storage regions 101 and the dummy area 102; the plurality of active regions 110 all extend along a first direction U; in the first direction U, the distance between two adjacent active regions 110 located in the storage region 101 and the dummy area 102 respectively is equal to the distance between any two adjacent active regions 101 in the dummy area 102. A plurality of memory structures are located on the first substrate 10 and are respectively coupled to the corresponding active regions 110 in the plurality of storage regions 101.

[0039] It should be noted that in the related art, refer to Figure 2 , in the field of chips, a dummy area refers to an unused area in a chip. Usually, dummy structures are provided in the dummy area to ensure that the structures and performances of other parts can be maintained. These dummy structures are usually made of the same materials as the chip, but they are not used for any circuit or logic function. A plurality of memory array tiles (MAT) are all formed on the substrate. To ensure the performance of the memory array tiles, dummy areas are provided at the edges of each memory array tile, and gaps are provided between adjacent memory array tiles for arranging control circuits (including word line driving circuits and sense amplifying circuits, etc.). Thus, the distance between adjacent memory array tiles is relatively large.

[0040] In the embodiment of the present disclosure, refer to Figure 1 , the first substrate 10 includes a plurality of storage regions 101 and a dummy area 102 surrounding the plurality of storage regions 101. The plurality of storage regions 101 are arranged in an array and spaced apart from each other. For example, the first substrate 10 may include 4 storage regions 101, and the 4 storage regions 101 are arranged in a rectangular array.

[0041] It should be noted that microloading refers to the difference in etching rate caused by the difference in pattern density within the same design pattern. In a region with a dense pattern, the limited components of the reactive ions are consumed quickly, resulting in a supply imbalance and a decrease in the etching rate. Thus, the etching depth in the dense pattern region is less than that in the sparse pattern region, causing non-uniform distribution of the overall etching depth of the sample.

[0042] In the embodiment of the present disclosure, refer to Figure 1, a plurality of active regions 110 are provided in the first substrate 10, and the plurality of active regions 110 all extend along the first direction U. The plurality of active regions 110 are distributed throughout the plurality of storage regions 101 and dummy regions 102. For example, the plurality of active regions 110 may be formed on the top surface of the first substrate 10, and each active region 110 is strip-shaped. In the first direction U, the distance between two adjacent active regions 110 located in the storage region 101 and the dummy region 102 respectively is equal to the distance between any two adjacent active regions 101 in the dummy region 102. For example, the active regions 110a, 110b, and 110c are on the same straight line, the active region 110c is located in the storage region 101, and the active regions 110a and 110b are located in the dummy region 102. In the first direction U, both the active region 110a and the active region 110c are adjacent to the active region 110b; and, the distance between the active region 110a and the active region 110b in the first direction U is equal to the distance between the active region 110b and the active region 110c in the first direction U. That is to say, the arrangement of the active regions 110 in the dummy region 102 and the storage region 101 is the same, and the plurality of active regions 110 are evenly distributed on the top surface of the first substrate 10. In this way, the active regions 110 are evenly distributed in the storage region 101, the active regions 110 are evenly distributed in the dummy region 102, and the active regions 110 are evenly distributed at the transition position between the storage region 101 and the dummy region 102, that is, the pattern density of the active regions 110 at the transition position between the storage region 101 and the dummy region 102 is the same as the pattern density of the active regions 110 in the storage region 101 and the dummy region 101. Thus, during the process of etching to form the active regions 110, the etching rates at the transition position between the storage region 101 and the dummy region 102 and in the dummy region 101 can be kept consistent, and further, the influence of the microloading effect is reduced.

[0043] It should be noted that during the process of forming the active regions 110, the influence of process errors on the distance between the active regions 110 can be ignored.

[0044] Furthermore, referring to Figure 1 , the transistor formed by each active region 110 may be a buried transistor. In some other examples, the transistor formed by each active region 110 may also be a vertical transistor, such as a gate all around (GAA) transistor, etc. Each active region 110 may have at least one gate structure, at least one source structure, and at least one drain structure. It should be noted that when the transistor formed by each active region 110 is a vertical transistor, the first direction U may be the same as one of the second direction X and the third direction Y.

[0045] For example, the transistors formed in each active region 110 are buried transistors. Each active region 110 is separated into three parts by two word lines (WL) 130, namely: two ends of the active region 110 and a middle part located between the two word lines 130. The two ends of each active region 110 can be source structures, and the middle part of each active region 110 can be a drain structure. The word line 130 can be coupled to the active region 110 through a gate dielectric layer to form a gate structure.

[0046] In the embodiments of the present disclosure, with reference to Figure 1 , the storage structure can be any one of storage elements such as a capacitor, a magnetic tunnel junction (MTJ), a phase change memory device (PCM), and a ferroelectric memory device (e.g., a ferroelectric capacitor). A plurality of storage structures are located on the first substrate 10 and are respectively coupled to the corresponding active regions 110 in the plurality of storage regions 101. For example, a storage structure can be correspondingly connected to the middle part of each active region 110 located in the plurality of storage regions 101.

[0047] It can be understood that the dummy regions 102 in the embodiments of the present disclosure surround the plurality of storage regions 101. In this way, a storage array chip can be formed on each storage region 101, and the two storage array chips formed on two adjacent storage regions 101 share the dummy region 102 located therebetween; moreover, the gap between adjacent storage array chips is eliminated. Thus, compared with the related art, the embodiments of the present disclosure can reduce the pitch between adjacent storage array chips, and further, can reduce the area of the chip and improve the integration degree.

[0048] Figure 3 FIG. is a schematic structural diagram of an optional storage region provided by the embodiments of the present disclosure. It should be noted that the vertical direction Z can be perpendicular to the top surface of the first substrate. The second direction X can be perpendicular to the third direction Y, and both the second direction X and the third direction Y intersect at the first direction U and are perpendicular to the vertical direction Z. Figure 3 The plurality of bit lines 140 shown are disposed between the first substrate 10 and the plurality of storage structures. The plurality of bit lines 140 can also have other arrangement manners, which are not limited herein.

[0049] In some embodiments of the present disclosure, in combination with Figure 1 and Figure 3 , the memory 100 further includes a plurality of word lines 130 and a plurality of bit lines 140. The plurality of word lines 130 are located in the first substrate 10 and extend along the second direction X and are respectively coupled to the corresponding active regions 110 in the plurality of storage regions 101. The plurality of bit lines (BL) 140 extend along the third direction Y and are respectively coupled to the corresponding active regions 110 in the plurality of storage regions 101; the second direction X intersects the third direction Y.

[0050] In the embodiments of the present disclosure, with reference to Figure 3, A plurality of word lines 130 are located in the first substrate 10 and extend along the second direction X, and are respectively coupled to corresponding active regions 110 in a plurality of storage regions 101. The plurality of word lines 130 may be arranged at equal intervals along the third direction Y. The gate structures of all the active regions 110 in each storage region 101 are connected to the corresponding word lines 130. A plurality of bit lines 140 extend along the third direction Y and are respectively coupled to corresponding active regions 110 in a plurality of storage regions 101. The plurality of bit lines 140 may be arranged at equal intervals along the second direction X. The source structures of all the active regions 110 in each storage region 101 are connected to the corresponding bit lines 140. All the active regions 110 in each storage region 101 are coupled to the word lines 130 through a gate dielectric layer. That is to say, the plurality of word lines 130 and the plurality of bit lines 140 are only coupled to the active regions 110 within the storage region 101.

[0051] Figure 4 and Figure 5 are schematic structural diagrams of an optional memory provided by an embodiment of the present disclosure, Figure 4 which is a top view; Figure 5 which is a front sectional view, and the sectional position is at Figure 4 A - A' in. It should be noted that, Figure 5 the active region 110c is located in the storage region, and the active region 110b is located in the dummy region.

[0052] In some embodiments of the present disclosure, referring to Figure 4 , the memory 100 further includes a plurality of first contact plugs 151, a plurality of first connection lines 161, and a plurality of first contact structures 171. The plurality of first contact plugs 151, the plurality of first connection lines 161, and the plurality of first contact structures 171 are all located in the dummy region 102 between two adjacent storage regions 101 in the second direction X. Among them, two word lines 130 on the same straight line in two adjacent storage regions 101 are respectively coupled through a first contact plug 151 and the same first connection line 161. The word lines 130 coupled to the plurality of first connection lines 161 in two adjacent storage regions 101 are odd - numbered word lines or even - numbered word lines. The plurality of first contact structures 171 are located at positions of the plurality of first connection lines 161 far from the plurality of word lines 130, and each first connection line 161 is coupled to a first contact structure 171.

[0053] In the embodiments of the present disclosure, in combination with Figure 4 and Figure 5, the memory 100 further includes a plurality of first contact plugs 151, a plurality of first connection lines 161, and a plurality of first contact structures 171. The plurality of first contact plugs 151, the plurality of first connection lines 161, and the plurality of first contact structures 171 are all located in the dummy region 102 between two adjacent storage regions 101 in the second direction X. In this way, both the first contact plug 151 and the first contact structure 171 are far from the memory array chips formed on the storage region 101; thus, it is possible to avoid the formation process of the first contact plug 151 and the first contact structure 171 from interfering with the circuits in the memory array chips.

[0054] In the embodiments of the present disclosure, in combination with Figure 4 and Figure 5 , two word lines 130 located on the same straight line in two adjacent storage regions 101 are respectively coupled through a first contact plug 151 and the same first connection line 161. For example, two fourth word lines 130 in two storage regions 101 are both connected to the same first connection line 161 through a corresponding first contact plug 151. The word lines 130 coupled to the plurality of first connection lines 161 in two adjacent storage regions 101 are odd-order word lines or even-order word lines. For example, Figure 5 the word lines 130 in the even sequence in Figure 5 are all connected through the plurality of first connection lines 161 shown in the figure,

[0055] In the embodiments of the present disclosure, in combination with Figure 4 and Figure 5 , the plurality of first contact structures 171 are located on the side of the plurality of first connection lines 161 away from the plurality of word lines 130. For example, the first contact structure 171 is disposed above a corresponding first connection line 161.

[0056] In some embodiments of the present disclosure, in combination with Figure 4 and Figure 5 , the plurality of first contact structures 171 located in the dummy region 102 between two adjacent storage regions 101 in the second direction X are arranged in a staggered manner; the plurality of first connection lines 161 all extend along the second direction X, and the width of each first connection line 161 has a local maximum value at the coupling portion with the first contact plug 151 and / or the first contact structure 171.

[0057] It should be noted that the local maximum value means that: compared with other sections near a certain section of the first connection line (which may not be all the remaining sections, for example, it may be some sections on both sides of this section), the width of the first connection line at this section is the largest.

[0058] In the embodiments of the present disclosure, in combination with Figure 4 and Figure 5 , a plurality of first contact structures 171 in the dummy region 102 located between two adjacent storage regions 101 in the second direction X are arranged in a staggered manner. For example, the plurality of first contact structures 171 are arranged in a zigzag pattern in the third direction Y.

[0059] In the embodiments of the present disclosure, in combination with Figure 4 and Figure 5 , a plurality of first connection lines 161 all extend along the second direction X, and the width of each first connection line 161 has a local maximum value at the coupling position with the first contact plug 151 and / or the first contact structure 171. Thus, the contact area between the first connection line 161 and the first contact plug 151 and / or the first contact structure 171 can be increased, and further, the contact resistance between the first connection line 161 and the first contact plug 151 and / or the contact resistance between the first connection line 161 and the first contact structure 171 can be reduced.

[0060] Figure 6 and Figure 7 are schematic structural diagrams of an optional memory provided by the embodiments of the present disclosure, Figure 7 is a top view, Figure 6 is a front sectional view, and the sectional position is at Figure 7 B - B' in

[0061] In some embodiments of the present disclosure, in combination with Figure 6 and Figure 7 , the memory 100 further includes: a plurality of second contact plugs 152, a plurality of second connection lines 162, and a plurality of second contact structures 172, which are located in the dummy region 102 between two adjacent storage regions 101 in the third direction. Among them, two bit lines 140 located on the same straight line in two adjacent storage regions 101 are respectively coupled through a second contact plug 152 and a second connection line 162, and the two second connection lines 162 respectively coupled to these two bit lines 140 are arranged at intervals in the third direction. The bit lines 140 coupled to the plurality of second connection lines 162 in two adjacent storage regions 101 are odd - numbered bit lines or even - numbered bit lines. A plurality of second contact structures 172 are located at positions of the plurality of second connection lines 162 far from the plurality of bit lines 140, and each bit line 140 is coupled to a second contact structure 172.

[0062] In the embodiments of the present disclosure, in combination with Figure 6 andFigure 7 The memory 100 further includes a plurality of second contact plugs 152, a plurality of second connection lines 162, and a plurality of second contact structures 172. The plurality of second contact plugs 152, the plurality of second connection lines 162, and the plurality of second contact structures 172 are all located in the dummy region 102 between two adjacent memory regions 101 in the third direction Y. In this way, it is possible to avoid interference with the circuits in the memory array chip during the formation process of the second contact plugs 152 and the second contact structures 172.

[0063] In the embodiments of the present disclosure, in combination with Figure 6 and Figure 7 , two bit lines 140 located on the same straight line in two adjacent memory regions 101 are respectively coupled through a second contact plug 152 and a second connection line 162, and the two second connection lines 162 respectively coupled to the two bit lines 140 are arranged at intervals in the third direction. For example, the 4th bit lines 140 in the two memory regions 101 are both connected to a second connection line 162 through a corresponding second contact plug 152; and, the two second connection lines 162 are located on the same straight line. The bit lines 140 coupled to the plurality of second connection lines 162 in two adjacent memory regions 101 are odd-order bit lines or even-order bit lines. For example, Figure 7 the even-sequence bit lines 140 in Figure 7 are all connected through the plurality of second connection lines 162 shown in Figure 7 the odd-sequence bit lines 140 in

[0064] In the embodiments of the present disclosure, in combination with Figure 6 and Figure 7 , the plurality of second contact structures 172 are located on the side of the plurality of second connection lines 162 away from the plurality of bit lines 140. For example, the second contact structure 172 is disposed above a corresponding second connection line 162.

[0065] In some embodiments of the present disclosure, in combination with Figure 6 and Figure 7, a plurality of second contact structures 172 in a dummy region 102 located between two adjacent storage regions 101 in a third direction Y are arranged in a staggered manner. A plurality of second connection lines 162 all extend along the third direction Y, and the width of each second connection line 162 has a local maximum value at the coupling portion with the second contact structure 172.

[0066] In an embodiment of the present disclosure, in combination with Figure 6 and Figure 7 , a plurality of second contact structures 172 in a dummy region 102 located between two adjacent storage regions 101 in a third direction Y are arranged in a staggered manner. For example, a plurality of first contact structures 171 corresponding to each storage region 101 are arranged in a zigzag pattern in the third direction Y.

[0067] In an embodiment of the present disclosure, in combination with Figure 6 and Figure 7 , a plurality of second connection lines 162 all extend along the third direction Y, and the width of each second connection line 162 has a local maximum value at the coupling portion with the second contact structure 172. Thus, the contact area between the second connection line 162 and the second contact structure 172 can be increased, and further, the contact resistance between the second connection line 162 and the second contact structure 172 can be reduced.

[0068] In an embodiment of the present disclosure, in combination with Figure 4 and Figure 7 , the widths of the dummy region 102 in a second direction X and a third direction Y are set based on the number of word lines 130, bit lines 140, the spacing between adjacent second contact structures 172 and adjacent first contact structures 171, and the spacing between adjacent first contact plugs 151 and adjacent second contact plugs 152. In an embodiment of the present disclosure, the first contact structure 171, the second contact structure 172, the first contact plug 151, and the second contact plug 152 are all arranged in a staggered manner. In this way, when the spacing between adjacent memory array chips is reduced, the embodiment of the present disclosure can also increase the spacing between adjacent contact plugs and adjacent contact structures; thus, weakening the coupling effect between adjacent contact plugs and adjacent contact structures.

[0069] In some embodiments of the present disclosure, referring to Figure 4 , the memory 100 further includes a plurality of contact pads 163. Among them, a plurality of storage structures 120 are respectively coupled to corresponding active regions 110 in a plurality of storage regions 101 through the plurality of contact pads 163. The plurality of contact pads 163, the plurality of first connection lines 161, and the plurality of second connection lines 162 are provided on the same layer.

[0070] In an embodiment of the present disclosure, referring to Figure 4, the memory 100 further includes a plurality of contact pads 163. The plurality of contact pads 163, the plurality of first connection lines 161, and the plurality of second connection lines 162 are disposed on the same layer. For example, the plurality of contact pads 163, the plurality of first connection lines 161, and the plurality of second connection lines 162 may be disposed on the same metal layer. The storage structure 120 may be a capacitor, and the lower electrode plate of the capacitor may be connected to the plurality of contact pads 163. In this way, in the embodiments of the present disclosure, the plurality of first connection lines 161 and the plurality of second connection lines 162 can be formed simultaneously during the process of forming the plurality of contact pads 163, thereby simplifying the process and improving the efficiency.

[0071] Figure 8 FIG. 4 is a schematic structural diagram of an optional memory provided by an embodiment of the present disclosure. It should be noted that the memory 100 may be a WoW (Wafer on Wafer) structure, and two wafers are connected by a bonding structure (Hybird Bonding) 202. Figure 8 On both sides of the bonding structure (Hybird Bonding) 202 are the back-end circuits (BEOL) of the corresponding wafers.

[0072] In some embodiments of the present disclosure, with reference to Figure 8 , the memory 100 further includes: a second substrate 20, bonded to the first substrate 10, and provided with a control circuit 201; the control circuit 201 is respectively coupled to the plurality of first contact structures and the plurality of second contact structures.

[0073] In the embodiments of the present disclosure, with reference to Figure 8 , the control circuit 201 is respectively coupled to the plurality of first contact structures and the plurality of second contact structures. For example, the control circuit 201 may include a word line driving circuit and a sense amplifier circuit. Figure 8 On both sides of the bonding structure (Hybird Bonding) 202 are the back-end circuits (BEOL) of the corresponding wafers. The back-end circuit formed on the second substrate 20 is used to connect the word line driving circuit and the sense amplifier circuit including the control circuit 201. The back-end circuit formed on the first substrate 10 is used to connect Figure 4 the plurality of first contact structures 171 in Figure 7 and the plurality of second contact structures 172 in

[0074] In some embodiments of the present disclosure, with reference to Figure 3 , a plurality of bit lines 140 are located between the first substrate and the plurality of storage structures; or, the plurality of bit lines 140 are located on a side of the plurality of active regions 110 away from the plurality of storage structures.

[0075] Figure 9 andFigure 10 It is a schematic diagram of the optional distribution position of the bit line provided by an embodiment of the present disclosure. It should be noted that Figure 9 In, the insulating layer 142 is used to isolate the storage structure 120 and the bit line 140, the bit line contact plug 141 is used to couple the bit line 140 to the corresponding active region 110, and the insulating layer 143 is used to isolate two adjacent bit line contact plugs 141; Figure 10 In, the word line includes a gate dielectric layer 131 and a gate conductive layer 132. Both the gate dielectric layer 131 and the gate conductive layer 132 are disposed around the active region 110, and the gate conductive layer 132 is located on the side surface of the gate dielectric layer 131. The storage structure 120 is coupled to the corresponding active region 110 through the contact pad 163 in the insulating layer 142, and the insulating layers 10a and 10b are used to isolate two adjacent active regions 110.

[0076] In an embodiment of the present disclosure, in combination with Figure 3 and Figure 9 , a plurality of bit lines 140 are located between the first substrate 10 and the plurality of storage structures 120. For example, the plurality of bit lines 140 may be as Figure 9 shown, located between the first substrate 10 and the storage structure 120.

[0077] In an embodiment of the present disclosure, in combination with Figure 3 and Figure 10 , a plurality of bit lines 140 are located on a side of the plurality of active regions 110 away from the plurality of storage structures 120. For example, the bit line 140 may be as Figure 10 shown, disposed on a side away from the storage structure 120, that is, the bit line 140 is disposed in the first substrate 10.

[0078] In some embodiments of the present disclosure, referring to Figure 8 , the storage structure 120 includes any one of a capacitor, a magnetic tunnel junction, a phase change memory device, and a ferroelectric crystal memory device.

[0079] In an embodiment of the present disclosure, referring to Figure 4, the storage structure 120 includes any one of a capacitor, a magnetic tunnel junction, a phase change memory device, and a ferroelectric memory device (e.g., a ferroelectric capacitor). Correspondingly, the memory 100 can be any one of a dynamic random access memory (DRAM), a resistive random access memory (RRAM), a phase change random access memory (PCRAM), a magnetoresistive random access memory (MRAM), and a ferroelectric random access memory (FeRAM).

[0080] Figure 11 is an optional flowchart of a method for manufacturing a memory provided by an embodiment of the present disclosure, which will be described in conjunction with Figure 11 the steps shown.

[0081] S101. Provide a first substrate; wherein, the first substrate includes a plurality of storage regions and dummy regions surrounding the plurality of storage regions, and the plurality of storage regions are arranged in an array and spaced apart from each other.

[0082] S102. Form a plurality of active regions on the top surfaces of the plurality of storage regions and the dummy regions; wherein, the plurality of active regions all extend in a first direction; in the first direction, the distance between two adjacent active regions located in the storage region and the dummy region respectively is equal to the distance between any two adjacent active regions in the dummy region.

[0083] In an embodiment of the present disclosure, with reference to Figure 1 , the plurality of active regions 110 in the plurality of storage regions 101 and the dummy regions 102 are formed simultaneously. That is to say, an embodiment of the present disclosure can form a bank on the first substrate 10. Wherein, during the process of forming the bank, the formation of structures such as the active regions 110, the storage structure 120, the word lines 130, and the bit lines 140 in each memory array slice can be defined by the storage region 101, so that the bit lines and word lines between adjacent memory array slices are not physically connected to each other.

[0084] In an embodiment of the present disclosure, with reference to Figure 1, in the embodiments of the present disclosure, the dummy region 102 surrounds a plurality of storage regions 101. A memory array slice can be formed on each storage region 101. The active region 110 formed on the dummy region 102 between two adjacent storage regions 101 can serve as a dummy structure for the two memory array slices formed on the two adjacent storage regions 101, that is, the two memory array slices share the dummy region 102 between them. Thus, compared with the related art, the embodiments of the present disclosure can reduce the pitch between adjacent memory array slices, and further reduce the area of the chip and improve the integration degree.

[0085] S103. Form a plurality of memory structures on a plurality of active regions; wherein, the plurality of memory structures are respectively coupled to the corresponding active regions in the plurality of storage regions.

[0086] In the embodiments of the present disclosure, refer to Figure 1 and Figure 5 , a plurality of memory structures 120 are formed on a plurality of active regions 110. The memory structure 120 can be a memory element such as a capacitor. The plurality of memory structures 120 are respectively coupled to the corresponding active regions 110 in the plurality of storage regions 101. For example, the lower electrode plate of the memory structure 120 can be coupled to the active region 110 through the corresponding contact pad 163.

[0087] In some embodiments of the present disclosure, the preparation of the partial structure of the memory can be implemented through S201 to S202, and each step will be described in combination.

[0088] S201. In a first substrate, form a plurality of word lines extending along a second direction; wherein, the plurality of word lines are respectively coupled to the corresponding active regions in the plurality of storage regions.

[0089] In the embodiments of the present disclosure, refer to Figure 1 , a plurality of word line trenches extending along the second direction X are formed in the plurality of storage regions 101, and then, the plurality of word line trenches are filled to form a plurality of word lines 130.

[0090] S202. Between the first substrate and the plurality of memory structures, or on a side of the plurality of active regions away from the plurality of memory structures, form a plurality of bit lines extending along a third direction; wherein, the plurality of bit lines are respectively coupled to the corresponding active regions in the plurality of storage regions; the second direction intersects the third direction.

[0091] In the embodiments of the present disclosure, in combination with Figure 3 and Figure 9 , the embodiments of the present disclosure can form a plurality of bit lines 140 extending along the third direction Y between the first substrate 10 and the plurality of memory structures 120.

[0092] In the embodiments of the present disclosure, in combination with Figure 3 and Figure 10, in the embodiments of the present disclosure, the first substrate 10 can be thinned, and then, on the side of the plurality of active regions 110 away from the plurality of memory structures 120, a plurality of bit lines 140 extending along the third direction Y are formed.

[0093] In some embodiments of the present disclosure, the preparation of the partial structure of the memory can be implemented through S301, and each step will be described in combination.

[0094] S301: In the dummy region between two adjacent memory regions in the second direction, a plurality of first contact plugs, a plurality of first connection lines, and a plurality of first contact structures are formed; wherein, two word lines located on the same straight line in two adjacent memory regions are coupled through a first contact plug and the same first connection line respectively; the word lines coupled to the plurality of first connection lines in two adjacent memory regions are odd-order word lines or even-order word lines. The plurality of first contact structures are located on the side of the plurality of first connection lines away from the plurality of word lines, and each first connection line is coupled to a first contact structure.

[0095] In the embodiments of the present disclosure, in combination with Figure 4 and Figure 5 , in the dummy region 102 between two adjacent memory regions 101 in the second direction X, a plurality of first contact plugs 151, a plurality of first connection lines 161, and a plurality of first contact structures 171 are sequentially formed. Thus, in the embodiments of the present disclosure, the word lines 130 can be coupled to the word line driving circuit through the first contact plugs 151, the first connection lines 161, and the first contact structures 171.

[0096] In some embodiments of the present disclosure, the further preparation of the partial structure of the memory can be implemented through S401, and each step will be described in combination.

[0097] S401: In the dummy region between two adjacent memory regions in the third direction, a plurality of second contact plugs, a plurality of second connection lines, and a plurality of second contact structures are formed; wherein, two bit lines located on the same straight line in two adjacent memory regions are coupled through a second contact plug and a second connection line respectively, and the two second connection lines respectively coupled to the two bit lines are arranged at intervals in the third direction; the bit lines coupled to the plurality of second connection lines in two adjacent memory regions are odd-order bit lines or even-order bit lines; the plurality of second contact structures are located on the side of the plurality of second connection lines away from the plurality of bit lines, and each bit line is coupled to a second contact structure.

[0098] In the embodiments of the present disclosure, in combination with Figure 6 and Figure 7, a plurality of second contact plugs 152, a plurality of second connection lines 162, and a plurality of second contact structures 172 are located in a dummy region 102 between two adjacent storage regions 101 in a third direction. In an embodiment of the present disclosure, the bit line 140 can be coupled to the same sense amplifier circuit through the second contact plug 152, the second connection line 162, and the second contact structure 172.

[0099] Figure 12 is a schematic structural diagram of an optional electronic device 200 provided by an embodiment of the present disclosure. Refer to Figure 12 , the electronic device 200 includes: a processor 210 and the memory 100 in the above embodiment; the memory 100 is coupled to the processor 200.

[0100] In an embodiment of the present disclosure, refer to Figure 12 , the hardware entities of the electronic device 200 include: a processor 210, a memory 100, and a communication interface 220. The memory 100 is coupled to the processor 210 through the communication interface 220. The processor 210 generally controls the overall operation of the electronic device 200. The communication interface 220 can enable the electronic device 200 to communicate with other devices or equipment through a network. The memory 100 is configured to store instructions and applications executable by the processor 210, and can also cache data to be processed or already processed by the processor 210 and each module in the electronic device 200 (for example, image data, audio data, voice communication data, and video communication data).

[0101] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0102] As mentioned above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that, Comprising: A first substrate, including a plurality of storage regions and dummy regions surrounding the plurality of storage regions; wherein, the plurality of storage regions are arranged in an array and spaced apart from each other; a plurality of active regions are provided in the first substrate, and the plurality of active regions cover the plurality of storage regions and the dummy regions; the plurality of active regions all extend in a first direction; in the first direction, the distance between two adjacent active regions respectively located in the storage region and the dummy region is equal to the distance between any two adjacent active regions in the dummy region; A plurality of memory structures, located on the first substrate, and respectively coupled to the corresponding active regions in the plurality of storage regions.

2. The memory according to claim 1, wherein The memory further includes: A plurality of word lines, located in the first substrate, extending in a second direction, and respectively coupled to the corresponding active regions in the plurality of storage regions; A plurality of bit lines, extending in a third direction, and respectively coupled to the corresponding active regions in the plurality of storage regions; the second direction intersects the third direction.

3. The memory according to claim 2, wherein The memory further includes: A plurality of first contact plugs, a plurality of first connection lines, and a plurality of first contact structures, all located in the dummy region between two adjacent storage regions in the second direction; Wherein, two word lines located on the same straight line in two adjacent storage regions are respectively coupled through one first contact plug and the same first connection line; the word lines coupled to the plurality of first connection lines in two adjacent storage regions are odd-order word lines or even-order word lines; The plurality of first contact structures are located on the side of the plurality of first connection lines away from the plurality of word lines, and each first connection line is coupled to one first contact structure.

4. The memory according to claim 3, wherein The plurality of first contact structures located in the dummy region between two adjacent storage regions in the second direction are arranged in a staggered manner; The plurality of first connection lines all extend in the second direction, and the width of each first connection line has a local maximum value at the coupling position with the first contact plug and / or the first contact structure.

5. The memory according to claim 3, wherein The memory further includes: A plurality of second contact plugs, a plurality of second connection lines, and a plurality of second contact structures, located in the dummy region between two adjacent storage regions in the third direction; Wherein, two bit lines located on the same straight line in two adjacent storage regions are respectively coupled through one second contact plug and one second connection line, and the two second connection lines respectively coupled to the two bit lines are spaced apart in the third direction; the bit lines coupled to the plurality of second connection lines in two adjacent storage regions are odd-order bit lines or even-order bit lines; The plurality of second contact structures are located on the side of the plurality of second connection lines away from the plurality of bit lines, and each bit line is coupled to one second contact structure.

6. The memory according to claim 5, wherein A plurality of the second contact structures in the dummy region between two adjacent ones of the storage regions in the third direction are arranged in a staggered manner; A plurality of the second connection lines all extend along the third direction, and the width of each second connection line has a local maximum value at the coupling portion with the second contact structure.

7. The memory according to claim 5, wherein The memory further includes: a plurality of contact pads; wherein, A plurality of the storage structures are respectively coupled to corresponding active regions in a plurality of the storage regions through a plurality of the contact pads; The plurality of contact pads, a plurality of the first connection lines, and a plurality of the second connection lines are disposed on the same layer.

8. The memory according to claim 5, characterized in that, The memory further includes: A second substrate, bonded to the first substrate, and provided with a control circuit; The control circuit is respectively coupled to a plurality of the first contact structures and a plurality of the second contact structures.

9. The memory according to any one of claims 2-8, characterized in that, A plurality of the bit lines are located between the first substrate and the plurality of storage structures; or, a plurality of the bit lines are located on a side of a plurality of the active regions away from the plurality of storage structures.

10. The memory according to any one of claims 1-8, characterized in that, The storage structure includes any one of a capacitor, a magnetic tunnel junction, a phase change memory device, and a ferroelectric memory device.

11. A method for preparing a semiconductor structure, characterized in that, Including: Providing a first substrate; wherein, the first substrate has a plurality of storage regions and a dummy region surrounding the plurality of storage regions, and the plurality of storage regions are arranged in an array and spaced apart from each other; On the top surfaces of the plurality of storage regions and the dummy region, forming a plurality of active regions; wherein, the plurality of active regions all extend along a first direction; in the first direction, the distance between two adjacent active regions respectively located in the storage region and the dummy region is equal to the distance between any two adjacent active regions in the dummy region; Forming a plurality of storage structures on the plurality of active regions; wherein, the plurality of storage structures are respectively coupled to corresponding active regions in a plurality of the storage regions.

12. The preparation method according to claim 11, characterized in that, The manufacturing method further includes: In the substrate, forming a plurality of word lines extending along a second direction; wherein, the plurality of word lines are respectively coupled to corresponding active regions in a plurality of the storage regions; Forming a plurality of bit lines extending along a third direction between the first substrate and the plurality of storage structures, or on a side of a plurality of the active regions away from the plurality of storage structures; wherein, the plurality of bit lines are respectively coupled to corresponding active regions in a plurality of the storage regions; the second direction intersects the third direction.

13. The preparation method according to claim 12, characterized in that, The manufacturing method further includes: In the dummy region between two adjacent storage regions in the second direction, forming a plurality of first contact plugs, a plurality of first connection lines, and a plurality of first contact structures; wherein, two word lines located on the same straight line in two adjacent storage regions are respectively coupled through one of the first contact plugs and the same first connection line; the word lines coupled to the plurality of first connection lines in two adjacent storage regions are odd-order word lines or even-order word lines; the plurality of first contact structures are located on a side of the plurality of first connection lines away from the plurality of word lines, and each of the first connection lines is coupled to one first contact structure.

14. The preparation method according to claim 12, wherein, The manufacturing method further includes: In the dummy region between two adjacent ones of the storage regions in the third direction, a plurality of second contact plugs, a plurality of second connection lines, and a plurality of second contact structures are formed; wherein, two bit lines that are collinear in two adjacent ones of the storage regions are respectively coupled through one of the second contact plugs and one of the second connection lines, and the two second connection lines respectively coupled to the two bit lines are arranged at intervals in the third direction; the bit lines coupled to the plurality of second connection lines in two adjacent ones of the storage regions are odd-order bit lines or even-order bit lines; the plurality of second contact structures are located on a side of the plurality of second connection lines away from the plurality of bit lines, and each bit line is coupled to one of the second contact structures.

15. An electronic device, characterized in that, Comprising: a processor and the memory according to any one of claims 1-10; the memory is coupled to the processor.

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