Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a plurality of active regions in a substrate; a gate trench formed in at least one of the plurality of active regions, the gate trench including a first sidewall, a second sidewall opposite to the first sidewall, and a bottom sidewall; a growth promotion region formed on a first sidewall of the gate trench; a first gate dielectric layer formed on a first sidewall of the gate trench to contact the growth promotion region; a second gate dielectric layer formed on a second sidewall of the gate trench to be thinner than the first gate dielectric layer; and a gate electrode partially filling the gate trench over the first gate dielectric layer and the second gate dielectric layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0193016, filed on December 27, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to semiconductor devices, and more particularly, to semiconductor devices including a buried - gate structure and methods of manufacturing the same. Background Art

[0004] Metal gate electrodes are used to ensure high performance of transistors. Specifically, a buried - gate transistor is a special type of transistor in which the gate electrode is buried in a trench of a semiconductor substrate. The buried - gate transistor requires controlling the threshold voltage for high - performance operation. In addition, the gate - induced drain leakage (GIDL) characteristics have a significant impact on the performance of the buried - gate type transistor. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a semiconductor device including a buried - gate structure with improved reliability and a method of manufacturing the same.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes: a plurality of active regions in a substrate; a gate trench formed in at least one of the plurality of active regions, the gate trench including a first sidewall, a second sidewall opposite the first sidewall, and a bottom sidewall; a growth - promoting region formed on the first sidewall of the gate trench; a first gate dielectric layer formed on the first sidewall of the gate trench to contact the growth - promoting region; a second gate dielectric layer formed on the second sidewall of the gate trench to be thinner than the first gate dielectric layer; and a gate electrode partially filling the gate trench over the first gate dielectric layer and the second gate dielectric layer.

[0007] According to an embodiment of the present disclosure, a semiconductor device includes: a substrate; an isolation layer defining an active region including a first node and a second node in the substrate; a gate trench formed between the first node and the second node and including a first sidewall and a second sidewall; a growth - promoting region formed on the first sidewall of the gate trench; a first gate dielectric layer formed on the first sidewall of the gate trench to contact the growth - promoting region; a second gate dielectric layer formed on the second sidewall of the gate trench to be thinner than the first gate dielectric layer; a gate electrode partially filling the gate trench over the first gate dielectric layer and the second gate dielectric layer; and a barrier region formed in the second node below the second sidewall of the gate trench.

[0008] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device includes: forming a plurality of active regions in a substrate; forming gate trenches in each of the active regions, the gate trenches including first sidewalls and second sidewalls facing the first sidewalls; doping the first sidewalls of the gate trenches with a growth promoting material; forming a first gate dielectric layer and a second gate dielectric layer on the first sidewalls and the second sidewalls of the gate trenches, respectively; and forming a gate electrode on the first gate dielectric layer and the second gate dielectric layer to partially fill the gate trenches.

[0009] According to an embodiment of the present disclosure, a semiconductor device includes: a substrate; an isolation layer that defines active regions including a first node and a second node in the substrate; a gate trench formed between the first node and the second node and including first sidewalls and second sidewalls; a first gate dielectric layer formed on the first sidewalls of the gate trench; a second gate dielectric layer formed on the second sidewalls of the gate trench to be thinner than the first gate dielectric layer; a gate electrode that partially fills the gate trench on the first gate dielectric layer and the second gate dielectric layer; and a highly doped region formed in the second node below the second sidewalls of the gate trench.

[0010] According to an embodiment of the present disclosure, a semiconductor device includes: a substrate; an isolation layer that defines active regions including a first node and a second node in the substrate; a gate trench formed between the first node and the second node and including first sidewalls and second sidewalls; a first gate dielectric layer formed on the first sidewalls of the gate trench; a second gate dielectric layer formed on the second sidewalls of the gate trench to be thinner than the first gate dielectric layer; a gate electrode that partially fills the gate trench on the first gate dielectric layer and the second gate dielectric layer; and a highly doped region formed in the first node below the first sidewalls of the gate trench.

[0011] According to an embodiment of the present disclosure, a semiconductor device includes: a bit line extending in a first direction; a gate electrode extending in a second direction intersecting the first direction; an active region disposed at an intersection of the gate electrode and the bit line and including a first node coupled to the bit line and a second node facing the first node; data storage elements respectively coupled to the second node of the active region; a first gate dielectric layer formed between the second node and the gate electrode; and a second gate dielectric layer formed between the first node and the gate electrode to be thinner than the first gate dielectric layer, wherein the first node, the gate electrode, and the second node are unidirectional, and one gate electrode can be disposed in each of the active regions in the active region. From the following detailed description in conjunction with the accompanying drawings, these and other features and advantages of the embodiments of the present disclosure will become apparent to those skilled in the art. Description of the Drawings

[0012] Figure 1Ais a plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 1B is a cross-sectional view taken along Figure 1A line A-A' shown in

[0014] Figure 1C is a cross-sectional view taken along Figure 1A line B-B' shown in

[0015] Figure 1D shows Figure 1B the data storage element shown in

[0016] Figures 2A to 7A is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figures 2B to 7B is a cross-sectional view taken along Figures 2A to 7A line A-A' shown in

[0018] Figure 8A is a plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 8B is a cross-sectional view taken along Figure 8A line A-A' shown in

[0020] Figure 8C is a cross-sectional view taken along Figure 8A line C-C' shown in

[0021] Figure 9A shows a method for forming Figure 8B the highly doped region shown in

[0022] Figure 9B is another embodiment of a method for forming Figure 8B the highly doped region shown in

[0023] Figure 10A and Figure 10B are cross-sectional views taken along Figure 8A line A-A' and line C-C' shown in

[0024] Figures 11 to 14 is a cross-sectional view showing a semiconductor device according to other embodiments of the present disclosure.

[0025] Figure 15 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. Detailed Description

[0026] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Throughout this disclosure, the same reference numerals represent the same components in multiple figures and embodiments of the present disclosure. The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When a first layer is referred to as being "on" a second layer or on a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where there is a third layer between the first layer and the second layer or the substrate.

[0027] In the following embodiments of the present disclosure, a buried gate structure may be provided in a trench. The buried gate structure may include a stack of a gate dielectric layer, a gate electrode, and a capping layer. The gate dielectric layer may cover the surface of the trench, while the gate electrode may partially fill the trench above the gate dielectric layer and the capping layer may fill the other part of the trench above the gate electrode. Thus, the gate electrode may be referred to as a "buried gate electrode".

[0028] The gate electrode may include a single gate or a dual gate. A single gate may refer to a gate formed only of polysilicon or only of a metal-based material. A single gate may include a polysilicon single gate or a metal single gate. A dual gate may refer to a bilayer stack of different gate materials. A dual gate may include a homogenous metal dual gate formed by a stack of the same metal, a heterogeneous metal dual gate formed by a stack of different metals, or a heterogeneous material dual gate formed by a stack of a metal and polysilicon.

[0029] The gate electrode may include a barrier layer and a low-resistance material. The barrier layer may be used to block dopants diffusing from the low-resistance material or to prevent interdiffusion and reaction between different materials. The low-resistance material may be used to reduce the sheet resistance of the gate electrode.

[0030] The gate electrode may include a material having an engineered work function. Work function engineering may refer to a material or method by which the work function can be adjusted to have a reduced work function (i.e., a low work function) or an increased work function (i.e., a high work function).

[0031] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B is along Figure 1A The cross-sectional view taken along the line A-A' shown in Figure 1C is along Figure 1A The cross-sectional view taken along the line B-B' shown in Figure 1D shows Figure 1B The data storage element 150 shown in

[0032] Reference Figures 1A to 1D , the semiconductor device 100 may include a substrate 101, a plurality of buried gate structures 100G, a plurality of bit lines 140, and a plurality of data storage elements 150. The semiconductor device 100 may include a plurality of memory cells. For example, the semiconductor device 100 may include a portion of a dynamic random access memory (DRAM). Each memory cell may include a buried gate structure 100G, a bit line 140, and a data storage element 150. The bit lines 140 may extend in a first direction D1, while the buried gate structures 100G may extend in a second direction D2. The first direction D1 and the second direction D2 may be orthogonal to each other.

[0033] The substrate 101 may include a material suitable for semiconductor processing. The substrate 101 may include a semiconductor substrate. The substrate 101 may include a silicon-containing material. The substrate 101 may include, for example, silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multiple layers thereof. The substrate 101 may also include other semiconductor materials, such as germanium. The substrate 101 may include a III / V group semiconductor substrate, for example, a compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0034] An isolation layer 102 and a plurality of active regions 104 may be formed over the substrate 101. The plurality of active regions 104 may be defined by the isolation layer 102. The isolation layer 102 may include a shallow trench isolation (STI) region formed by a trench etching process. The isolation layer 102 may be formed by filling a shallow trench (such as isolation trench 103) with a dielectric material (such as, for example, silicon oxide, silicon nitride, or a combination thereof).

[0035] A gate trench 105 may be formed in the substrate 101. From Figure 1A the top-down view shown, the gate trench 105 may have a linear shape extending in the second direction D2. The gate trench 105 may be deep and narrow. The gate trench 105 may extend deeply in the D3 direction. The gate trench 105 may have a narrow width in the D1 direction. This width may vary according to the application. The gate trench 105 may have a linear shape passing through the active regions 104 and the isolation layer 102. The gate trench 105 may have a depth shallower than that of the isolation trench 103. According to an embodiment of the present disclosure, the gate trench 105 may include a space in which the buried gate structure 100G is to be formed, and the gate trench 105 may also be referred to as a 'buried gate trench'. The gate trench 105 may include a first sidewall 105A, a second sidewall 105B, and a bottom surface 105C. The bottom surface 105C of the gate trench 105 may be disposed at a first horizontal height L1 (also referred to as a first depth).

[0036] The active region 104 may be formed in a strip shape and may be arranged in an array form. The array of active regions 104 may include a column array and a row array. The column array of active regions 104 may include active regions 104 arranged along a first direction D1. The row array of active regions 104 may include active regions 104 arranged along a second direction D2. The longitudinal direction of the active region 104, i.e., the third direction D3, may be non-orthogonal to the first direction D1 and the second direction D2, forming an intersection angle θ. The range of the intersection angle θ between the second direction D2 and the third direction D3 of the active region 104 may range from about 10° to 80°, but embodiments of the present disclosure may not be limited thereto. The range of the intersection angle θ may be affected by parameters such as the area of the active region 104, the line width of the bit line 140, the line width of the buried gate structure 100G, etc. From a top view angle, the cross-section of each active region 104 may include a parallelogram, such as a parallelogram with rounded edges.

[0037] The active regions 104 may be arranged unidirectionally along the third direction D3.

[0038] Each gate trench 105 may divide each active region 104 arranged along the second direction D2 into a first node 104A and a second node 104B. The first node 104A and the second node 104B may be respectively referred to as a first contact region and a second contact region. The first node 104A and the second node 104B may be respectively referred to as a first active node and a second active node. The first node 104A and the second node 104B may be asymmetric with respect to each other in the third direction D3. The first node 104A and the second node 104B may respectively include flat sidewalls FS1 and FS2 and curved sidewalls BS. The flat sidewalls FS1 and FS2 of the first node 104A and the second node 104B may be exposed through the gate trench 105. The curved sidewalls BS of the first node 104A and the second node 104B may be covered by the isolation layer 102. The first sidewall 105A and the second sidewall 105B of the gate trench 105 may be provided by the flat sidewalls FS1 and FS2 of the first node 104A and the second node 104B and the isolation layer 102. Therefore, the first sidewall 105A of the gate trench 105 may include the flat sidewall FS1 of the first node 104A, and the second sidewall 105B of the gate trench 105 may include the flat sidewall FS2 of the second node 104B. The flat sidewalls FS1 and FS2 and the curved sidewalls BS may be referred to as sidewall surfaces. According to an embodiment of the present disclosure, the cross-sections of the first node 104A and the second node 104B may have a rectangular, square, circular, elliptical, or polygonal shape. When the cross-sections of the first node 104A and the second node 104B are polygonal, they may have at least four sidewall surfaces.

[0039] In each active region 104, a first doped region 107 and a second doped region 108 may be formed. The first doped region 107 may be formed in the first node 104A, while the second doped region 108 may be formed in the second node 104B. The first doped region 107 and the second doped region 108 may be regions doped with a conductive dopant. For example, the conductive dopant may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first doped region 107 and the second doped region 108 may be doped with dopants of the same conductive type. The first doped region 107 and the second doped region 108 may be disposed in the active region 104 on both sides of the gate trench 105. The bottom surfaces of the first doped region 107 and the second doped region 108 may be disposed at a predetermined depth from the top surface of the active region 104. The first doped region 107 and the second doped region 108 may contact the sidewalls of the gate trench 105. The bottom surfaces of the first doped region 107 and the second doped region 108 may be higher than the bottom surface 105C of the gate trench 105. The first doped region 107 may be referred to as the "first source / drain region", while the second doped region 108 may be referred to as the "second source / drain region". The buried gate structure 100G may define a channel between the first doped region 107 and the second doped region 108. The channel may be defined along the contour of the gate trench 105. The depth H1 of the first doped region 107 may be less than the depth H2 of the second doped region 108. Since the first doped region 107 and the second doped region 108 have different depths, an asymmetric junction structure may be formed.

[0040] A growth promoting region 106 may be formed in the active region 104. The growth promoting region 106 may directly contact the first doped region 107. The growth promoting region 106 may be formed by an inclined implantation process. The growth promoting region 106 may include a growth promoting substance. The growth promoting region 106 may be formed by implanting the growth promoting substance to a desired depth and dose by controlling the amount of the growth promoting substance per unit area, its acceleration energy, and the tilt angle via an inclined implantation process. The growth promoting substance is selected to promote the growth rate of the oxide during a subsequent oxidation process. The growth promoting substance may also be referred to as an oxidation promoting substance. The growth promoting substance may include, for example, oxygen, fluorine, or a combination thereof. The growth promoting region 106 may be formed on the flat sidewall FS1 of the first node 104A. The growth promoting region 106 may not be formed on the flat sidewall FS2 of the second node 104B. The bottom surface of the growth promoting region 106 may be disposed at a second level height L2. The second level height L2 may be disposed at a level height lower than the first level height L1. The bottom surface of the growth promoting region 106 may be disposed at a level height lower than the bottom surface 105C of the gate trench 105. The growth promoting region 106 may cover a small portion of the bottom surface 105C of the gate trench 105. The growth promoting region 106 may have a uniform width, except for its lowermost end region, which may have a tapered width that decreases towards its end.

[0041] The active region 104 may include a fin region 104F. The fin region 104F may be disposed below the gate trench 105. Due to the depression of the portion of the isolation layer 102 below the gate trench 105, the fin region 104F may be formed. The sidewalls of the fin region 104F may be exposed by the depressed isolation layer 102. The fin region 104F may include a portion of the portion forming the channel. The fin region 104F may be referred to as a saddle fin. The fin region 104F may increase the channel width and improve electrical characteristics. According to an embodiment of the present disclosure, the fin region 104F may be omitted. A portion of the growth promoting region 106 may extend into the fin region 104F. The bottom surface of the growth promoting region 106 may extend to the top surface of the fin region 104F.

[0042] According to an embodiment of the present disclosure, the active region 104 and the fin region 104F may include an oxide semiconductor material, such as InGaZnO (IGZO). In this case, the first doped region 107 and the second doped region 108 may also include an oxide semiconductor material, such as IGZO. The active region 104 and the fin region 104F may be IGZO, while the first doped region 107 and the second doped region 108 may be an oxide semiconductor material having a resistance lower than that of IGZO.

[0043] From Figure 1A As viewed from the perspective shown in the top view, the buried gate structure 100G may extend along the second direction D2. The buried gate structure 100G may include a gate dielectric layer 110 covering the bottom and sidewalls of the gate trench 105, a gate electrode 120 partially filling the gate trench 105 on the gate dielectric layer 110, and a covering layer 130 on the gate electrode 120.

[0044] The gate dielectric layer 110 may include a first gate dielectric layer 110A and a second gate dielectric layer 110B. The first gate dielectric layer 110A may be formed on the flat sidewall FS1 of the first node 104A. The second gate dielectric layer 110B may be formed on the flat sidewall FS2 of the second node 104B. The thickness T1 of the first gate dielectric layer 110A may be greater than the thickness T2 of the second gate dielectric layer 110B. The first gate dielectric layer 110A may be formed on the growth promoting region 106.

[0045] During the oxidation process of forming the gate dielectric layer 110, the growth rates of the first gate dielectric layer 110A and the second gate dielectric layer 110B can be different from each other. The first gate dielectric layer 110A can grow faster than the second gate dielectric layer 110B. Due to the growth promoting region 106, the first gate dielectric layer 110A can grow faster on the flat sidewall FS1 of the first node 104A than the second gate dielectric layer 110B on the surface of the flat sidewall FS2 of the second node 104B. Oxygen and / or fluorine in the growth promoting region 106 function to promote the growth rate of the first gate dielectric layer 110A.

[0046] The first gate dielectric layer 110A can include, for example, silicon oxide, while the growth promoting region 106 can include an oxygen-containing silicon layer. The first gate dielectric layer 110A can, for example, include silicon oxide, while the growth promoting region 106 can include a fluorine-containing silicon layer. The first gate dielectric layer 110A can, for example, include silicon oxide, while the growth promoting region 106 can include a silicon layer containing oxygen and fluorine.

[0047] According to an embodiment of the present disclosure, the growth promoting region 106 can be partially converted or completely converted to form the first gate dielectric layer 110A. For example, the growth promoting region 106 can be partially oxidized or completely oxidized to become a part of the first gate dielectric layer 110A. The first gate dielectric layer 110A can be fluorinated silicon oxide, or can have a dual structure of undoped silicon oxide and fluorinated silicon oxide. Fluorinated silicon oxide as used herein as a term refers to silicon oxide doped with fluorine.

[0048] As described above, the first gate dielectric layer 110A and the second gate dielectric layer 110B can have different thicknesses, so the gate dielectric layer 110 can include an asymmetric structure. A third gate dielectric layer 110C can also grow on the bottom surface 105C of the gate trench 105. The thickness of a part of the third gate dielectric layer 110C can be the same as the thickness of the second gate dielectric layer 110B. The thickness of the first gate dielectric layer 110A can be thicker than the thickness of a part of the third gate dielectric layer 110C. The third gate dielectric layer 110C can have a variable thickness. For example, it can include a first part having the same thickness as the thickness of the second gate dielectric layer 110B, and a second part having the same thickness as the thickness of the first gate dielectric layer 110A. Since the growth promoting region 106 extends to a part of the surface of the fin region 104F, the second part of the third gate dielectric layer 110C can be formed thickly on the surface of the fin region 104F.

[0049] According to an embodiment of the present disclosure, the gate dielectric layer 110 may further include an additional gate dielectric layer. The additional gate dielectric layer may be formed on the first gate dielectric layer 110A and the second gate dielectric layer 110B. The additional gate dielectric layer may be formed by a deposition method, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The additional gate dielectric layer formed by the deposition method may include a high-k material, an oxide, a nitride, a oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to an embodiment of the present disclosure, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other known high-k materials may be optionally used for the high-k material.

[0050] According to an embodiment of the present disclosure, the gate dielectric layer 110 may include a stack of silicon oxide and a high-k material. The silicon oxide may be the first gate dielectric layer 110A and the second gate dielectric layer 110B, and the high-k material may be the additional gate dielectric layer. The high-k material may include a material having an oxygen atomic surface density higher than that of silicon oxide. According to an embodiment of the present disclosure, the high-k material may include a material having an oxygen atomic surface density lower than that of silicon oxide. For example, the stack of silicon oxide and the high-k material may include a silicon oxide / lanthanum oxide (SiO2 / La2O3) stack, and the lanthanum oxide may horizontally overlap with the first doped region 107 and the second doped region 108.

[0051] The gate electrode 120 may include a buried gate electrode that partially fills the gate trench 105. The gate electrode 120 may be disposed at a horizontal height lower than the top surface of the active region 104 (i.e., the first doped region 107 and the second doped region 108). The gate electrode 120 may include a semiconductor material, a metal-based material, or a combination thereof. The gate electrode 120 may include a metal, a metal nitride, or a combination thereof. The gate electrode 120 may include polysilicon, tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), ruthenium (Ru), or a combination thereof. The gate electrode 120 may be formed only of titanium nitride. According to an embodiment of the present disclosure, the gate electrode 120 may have a high work function. For example, a high work function may refer to a work function higher than the mid-gap work function of silicon. A low work function may refer to a work function lower than the mid-gap work function of silicon. The high work function may have a work function higher than about 4.5 eV, while the low work function may have a work function lower than about 4.5 eV. The gate electrode 120 may include p-type polysilicon or nitrogen-rich titanium nitride (nitrogen-rich TiN).

[0052] According to an embodiment of the present disclosure, the gate electrode 120 may have an increased high work function. The gate electrode 120 may include a metal silicon nitride. The metal silicon nitride may be obtained by doping a metal nitride with silicon. The gate electrode 120 may include a metal silicon nitride with a controlled silicon content. For example, the gate electrode 120 may include tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function, and in order to further increase the work function of titanium nitride, silicon may be contained in the titanium nitride. The content of silicon may be adjusted to increase the high work function of titanium silicon nitride. According to an embodiment of the present disclosure, the gate electrode 120 may include titanium aluminum nitride (TiAlN).

[0053] The capping layer 130 may serve to protect the gate electrode 120. The capping layer 130 may fill the upper part of the gate trench 105 above the gate electrode 120. The top surface of the capping layer 130 may be disposed at the same level as the top surfaces of the first doped region 107 and the second doped region 108. The capping layer 130 may include, for example, silicon oxide, silicon nitride, silicon carbon oxide, fluorine-containing silicon oxide, or a combination thereof.

[0054] The bit line 140 may be electrically connected to the second doped region 108. For example, the bit line 140 may be coupled to the second doped region 108 through the first contact node 141. The data storage element 150 may be electrically connected to the first doped region 107. For example, the data storage element 150 may be coupled to the first doped region 107 through the second contact node 151. The first contact node 141 may also be referred to as a bit line contact plug, and the second contact node 151 may also be referred to as a storage contact plug.

[0055] The first contact node 141 and the second contact node 151 may include a semiconductor material, a doped semiconductor material, a metal-based material, a metal nitride-based material, a conductive metal oxide, or a combination thereof. For example, the first contact node 141 may include doped polysilicon, and the second contact node 151 may include a stacked structure of polysilicon, titanium nitride, and tungsten.

[0056] The bit line 140 may include a semiconductor material, a doped semiconductor material, a metal-based material, a metal nitride-based material, a conductive metal oxide, or a combination thereof. For example, the bit line 140 may include a stacked structure of titanium nitride and tungsten.

[0057] The data storage element 150 may include a storage element, such as a capacitor.

[0058] Reference Figure 1D, the data storage element 150 may include a first electrode SN, a second electrode PN located above the first electrode SN, and a dielectric layer DE located between the first electrode SN and the second electrode PN. The first electrode SN may have a cylindrical shape. According to an embodiment of the present disclosure, the first electrode SN may have a cylindrical shape, a plate shape, or a columnar cylindrical shape. The columnar cylindrical shape may refer to a structure in which a cylindrical shape and a tubular shape are combined.

[0059] The outer wall of the first electrode SN of the data storage element 150 may be supported by multi-level supports SP1 and SP2. The multi-level supports SP1 and SP2 may include, for example, silicon nitride, silicon carbonitride, or a combination thereof as a dielectric material. According to an embodiment of the present disclosure, the multi-level support may include three or more supports. The bottom of the first electrode SN of the data storage element 150 may be supported by an etch stop layer EST. The etch stop layer EST may include, for example, silicon nitride, silicon carbonitride, or a combination thereof. The bottom of the first electrode SN of the data storage element 150 may be coupled to the second contact node 151 through the etch stop layer EST.

[0060] The first electrode SN and the second electrode PN of the data storage element 150 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may include a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, the silicon germanium may include a gap filling material that fills the inside of the first electrode SN, while the titanium nitride (TiN) may serve as the second electrode PN of the data storage element 150, and the tungsten nitride may include a low-resistance material.

[0061] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include, for example, silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), niobium pentoxide (Nb2O5), or strontium titanate (SrTiO3). According to an embodiment of the present disclosure, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0062] The dielectric layer DE can be formed of a zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure including zirconia (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which alumina (Al2O3) is stacked on zirconia (ZrO2). The ZAZ stack can have a structure in which zirconia (ZrO2), alumina (Al2O3), and zirconia (ZrO2) are sequentially stacked. The ZA stack and the ZAZ stack can be referred to as zirconia (ZrO2)-based layers. According to an embodiment of the present disclosure, the dielectric layer DE can be formed of a hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including hafnia (HfO2). The dielectric layer DE can include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack can have a structure in which alumina (Al2O3) is stacked on hafnia (HfO2). The HAH stack can have a structure in which hafnia (HfO2), alumina (Al2O3), and hafnia (HfO2) are sequentially stacked. The HA stack and the HAH stack can be referred to as hafnia (HfO2)-based layers. In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, alumina (Al2O3) can have a larger bandgap energy than zirconia (ZrO2) and hafnia (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconia (ZrO2) and hafnia (HfO2). Accordingly, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material having a larger bandgap energy than the high-k material. The dielectric layer DE can include, for example, silicon dioxide (SiO2) as a high-bandgap material different from alumina (Al2O3). Since the dielectric layer DE includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. According to an embodiment of the present disclosure, the dielectric layer DE can include a stacked structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE can include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O2 / ZrO2) stack, an HZAZH (HfO 2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAA (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacked structures, alumina (Al2O3) can be thinner than zirconia (ZrO2) and hafnia (HfO2).

[0063] According to an embodiment of the present disclosure, the dielectric layer DE may include a high-k material and a high bandgap material, and may have a laminated structure in which a plurality of high-k materials and a plurality of high bandgap materials are stacked, or a hybrid structure in which the high-k material and the high bandgap material are mixed with each other.

[0064] According to an embodiment of the present disclosure, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0065] According to an embodiment of the present disclosure, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material.

[0066] According to an embodiment of the present disclosure, an interface control layer may also be formed between the first electrode SN and the dielectric layer DE to improve leakage current prevention. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium oxynitride (NbON), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0067] According to an embodiment of the present disclosure, the data storage element 150 may include a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0068] Reference Figures 1A to 1D , the semiconductor device 100 may include a plurality of memory cells, and adjacent memory cells may be isolated from each other by the isolation layer 102. One memory cell may be formed over one active region 104. In each memory cell, one gate electrode 120 may be formed in one active region 104, which may be referred to as a "memory cell with a one-gate-one-active-region (1G1A) structure". In the memory cell with a 1G1A structure, since the bit line 140 is coupled to one active region 104, the memory cell may be coupled to one bit line 140. The memory cell with a 1G1A structure may include a one-transistor-one-capacitor (1T1C). As a comparative example, in a typical DRAM, two memory cells may be formed in one active region, two gate electrodes may be formed in one active region, and two adjacent memory cells may share one bit line.

[0069] In the semiconductor device 100 including the memory cell with a 1G1A structure, the active regions 104 may be arranged unidirectionally along the third direction D3. The isolation layer 102, the second node 104B, the second gate dielectric layer 110B, the gate electrode 120, the first gate dielectric layer 110A, the first node 104A, and the isolation layer 102 may be arranged in a unidirectional order along the third direction D3.

[0070] A semiconductor device 100 including a memory cell of a 1G1A structure may include a gate dielectric layer 110 having an asymmetric structure. Specifically, since the thickness of the first gate dielectric layer 110A is greater than the thickness of the second gate dielectric layer 110B, leakage such as gate-induced drain leakage (GIDL) can be suppressed, and since the leakage is suppressed, the refresh operation can be improved.

[0071] Figures 2A to 7A is a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 2B to 7B is along Figures 2A to 7A a cross-sectional view taken along line A-A' shown in

[0072] Referring to Figure 2A and Figure 2B , an isolation layer 12 and a plurality of active regions 14 may be formed over a substrate 11. The plurality of active regions 14 may be defined by the isolation layer 12. The substrate 11 may include a material suitable for semiconductor processing. The substrate 11 may include at least one of a conductive material, a dielectric material, and a semiconductor material. A variety of materials may be formed over the substrate 11. The substrate 11 may include a semiconductor substrate. The substrate 11 may include a silicon-containing material. The substrate 11 may include, for example, silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multi-layer thereof. The substrate 11 may further include other semiconductor materials, such as germanium. The substrate 11 may include a III / V group semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0073] The isolation layer 12 may be formed by a shallow trench isolation (STI) process. For example, isolation trenches 13 may be formed by etching the substrate 11. Subsequently, the isolation trenches 13 may be filled with a dielectric material to form the isolation layer 12. The isolation layer 12 may include, for example, silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be used to fill the isolation trenches 13 with the dielectric material. A planarization process, such as chemical mechanical polishing (CMP), may also be additionally used.

[0074] Each active region 14 may have an island shape. Each active region 14 may include a first end surface E1 and a second end surface E2 facing the first end surface E1. Each active region 14 may further include a plurality of rounded edges RE1 and RE2. The curvature of the first rounded edge RE1 and the curvature of the second rounded edge RE2 may be different from each other.

[0075] The active regions 14 may be regularly arranged in a first direction D1. The active regions 14 may be regularly arranged in a second direction D2. The active regions 14 may be regularly arranged in a third direction D3. The active regions 14 adjacent to each other in the second direction D2 may be parallel in the third direction D3. The first end surfaces E1 of the active regions 14 adjacent to each other in the first direction D1 may be arranged in a fourth direction D4, and the second end surfaces E2 of the active regions 14 adjacent to each other in the first direction D1 may be arranged in a fifth direction D5. The fourth direction D4 and the fifth direction D5 may be directions parallel to the first direction D1. The first end surface E1 and the second end surface E2 of the active region 14 may be arranged in the third direction D3, so that the active regions 14 may be arranged in the third direction D3. The active regions 14 may be arranged in a one-way A1 of the third direction D3.

[0076] See Figure 3A and Figure 3B , a gate trench 15 may be formed in the substrate 11. The gate trench 15 may be formed in a linear shape intersecting the active regions 14 and the isolation layer 12. For example, the gate trench 15 may extend along the second direction D2.

[0077] The gate trench 15 may be formed by etching the substrate 11 using the hard mask layer GM as an etching mask. The hard mask layer GM may be formed on the substrate 11 and may have a linear opening for allowing the formation of the gate trench 15. The hard mask layer GM may be formed of a material having an etching selectivity with respect to the active regions 14 and the isolation layer 12. The hard mask layer GM may include silicon oxide, such as TEOS (tetraethyl orthosilicate). The gate trench 15 may be formed shallower than the isolation trench 13. The depth of the gate trench 15 may be less than the depth of the isolation trench 13, but should be deep enough to increase the average cross-sectional area of the gate electrode to be formed subsequently. Therefore, the resistance of the gate electrode may be reduced. The bottom edge of the gate trench 15 may be flat or may have a curvature.

[0078] Each active region 14 may be divided into two nodes 14A and 14B by the gate trench 15. For example, each active region 14 may be divided into a first node 14A and a second node 14B. The first node 14A and the second node 14B may be asymmetric in the one-way of the third direction D3. The first node 14A and the second node 14B may respectively include flat sidewalls FS1 and FS2 and curved sidewalls BS (see Figure 3A)). The flat sidewalls FS1 and FS2 of the first node 14A and the second node 14B can be exposed by the gate trench 15. The curved sidewalls BS of the first node 14A and the second node 14B can be covered by the isolation layer 12. The flat sidewalls FS1 and FS2 and the curved sidewalls BS can be referred to as sidewall surfaces. According to an embodiment of the present disclosure, the cross-sections of the first node 14A and the second node 14B can be rectangular, square, circular, elliptical, or polygonal. When the cross-sections of the first node 14A and the second node 14B are polygonal, they can have at least four sidewall surfaces.

[0079] The gate trench 15 can include a first sidewall 15A, a second sidewall 15B, and a bottom surface 15C. The first sidewall 15A and the second sidewall 15B of the gate trench 15 can be provided by the flat sidewalls FS1 and FS2 of the first node 14A and the second node 14B and the isolation layer 12. Thus, the first sidewall 15A of the gate trench 15 can include the flat sidewall FS1 of the first node 14A, and the second sidewall 15B of the gate trench 15 can include the flat sidewall FS2 of the second node 14B.

[0080] After forming the gate trench 15, the fin region 14F can be subsequently formed. To form the fin region 14F, the isolation layer 12 below the gate trench 15 can be selectively recessed in the second direction D2.

[0081] Reference Figure 4A and Figure 4B , a doping process 16 can be performed on the first sidewall 15A of the gate trench 15. The doping process 16 can be performed on the flat sidewall FS1 of the first node 14A. The doping process 16 can include an inclined implantation process. In the inclined implantation process, the doping process can be performed at an inclined angle. In contrast, due to the shadow effect that may be caused by the inclined implantation process and the hard mask layer GM, the doping process 16 is not performed on the flat sidewall FS2 of the second node 14B.

[0082] A growth promoting substance (such as an oxidation promoting substance) can be doped by the doping process 16. The oxidation promoting substance can include oxygen, fluorine, or a combination thereof. The oxidation promoting substance can include a non-conductive substance. For example, the doping concentration range of the growth promoting substance can be from about 1.0×10 12 atoms / cm 3 to about 1.0×10 16 atoms / cm 3 .

[0083] By doping process 16, a growth promoting region 16D can be formed on the flat sidewall FS1 of the first node 14A. The growth promoting region 16D is not formed on the flat sidewall FS2 of the second node 14B. The growth promoting region 16D can extend to form on a part of the surface of the fin region 14F. The bottom surface of the growth promoting region 16D can be set at a level lower than the bottom surface 15C of the gate trench 15.

[0084] Reference Figure 5A and Figure 5B , a gate dielectric layer 17 can be formed on the first sidewall 15A and the second sidewall 15B of the gate trench 15. Before forming the gate dielectric layer 17, the etching damage on the surface of the gate trench 15 can be repaired. For example, after forming a sacrificial oxide by thermal oxidation treatment, the sacrificial oxide can be removed. The gate dielectric layer 17 can be formed by a thermal oxidation process. The gate dielectric layer 17 can include, for example, silicon oxide.

[0085] The gate dielectric layer 17 can be selectively formed on the flat sidewall FS1 of the first node 14A and the flat sidewall FS2 of the second node 14B.

[0086] The gate dielectric layer 17 can include a first gate dielectric layer 17A and a second gate dielectric layer 17B. The first gate dielectric layer 17A can be formed on the flat sidewall FS1 of the first node 14A. The second gate dielectric layer 17B can be selectively formed on the flat sidewall FS2 of the second node 14B. The thickness T1 of the first gate dielectric layer 17A can be greater than the thickness T2 of the second gate dielectric layer 17B. The first gate dielectric layer 17A can be formed on top of the growth promoting region 16D.

[0087] During the oxidation process for forming the gate dielectric layer 17, the growth rates of the first gate dielectric layer 17A and the second gate dielectric layer 17B can be different. For example, the first gate dielectric layer 17A can grow faster on the flat sidewall FS1 of the first node 14A where the growth promoting region 16D is formed than the second gate dielectric layer 17B on the surface of the flat sidewall FS2 of the second node 14B. Oxygen and / or fluorine in the growth promoting region 16D can play a role in promoting the growth rate of the first gate dielectric layer 17A.

[0088] The first gate dielectric layer 17A and the second gate dielectric layer 17B can include, for example, silicon oxide. The first gate dielectric layer 17A can include thick silicon oxide, while the second gate dielectric layer 17B can include thin silicon oxide. The first gate dielectric layer 17A can include, for example, silicon oxide, while the growth promoting region 16D can include an oxygen-containing silicon layer. The first gate dielectric layer 17A can include, for example, silicon oxide, while the growth promoting region 16D can include a fluorine-containing silicon layer. The first gate dielectric layer 17A can include, for example, silicon oxide, while the growth promoting region 16D can include an oxygen- and fluorine-containing silicon layer.

[0089] According to an embodiment of the present disclosure, the growth promoting region 16D may be partially or fully transformed to form the first gate dielectric layer 17A. For example, the growth promoting region 16D may be partially or fully oxidized to become part of the first gate dielectric layer 17A. The first gate dielectric layer 17A may have a dual structure of undoped silicon oxide and fluorine-containing silicon oxide.

[0090] As described above, the first gate dielectric layer 17A and the second gate dielectric layer 17B may have different thicknesses, so the gate dielectric layer 17 may include an asymmetric structure. A third gate dielectric layer (see the reference numeral '110C' shown in Figure 1B the attached drawings) may also be grown on the bottom surface 15C of the gate trench 15. A part of the third gate dielectric layer and the second gate dielectric layer 17B may have the same thickness. The thickness of the first gate dielectric layer 17A may be greater than the thickness of a part of the third gate dielectric layer. The third gate dielectric layer may have a variable thickness. For example, it may include a first part having the same thickness as the second gate dielectric layer 17B, and a second part having the same thickness as the first gate dielectric layer 17A. Since the growth promoting region 16D extends to a part of the surface of the fin region 14F, the second part of the third gate dielectric layer may be formed thickly on the surface of the fin region 14F.

[0091] According to an embodiment of the present disclosure, the gate dielectric layer 17 may further include an additional gate dielectric layer. The additional gate dielectric layer may be formed on the first gate dielectric layer 17A and the second gate dielectric layer 17B. The additional gate dielectric layer may be formed by a deposition method, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The additional gate dielectric layer formed by the deposition process may include a high-k material, an oxide, a nitride, a oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to an embodiment of the present disclosure, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. For the high-k material, other known high-k materials may be optionally used.

[0092] According to an embodiment of the present disclosure, the gate dielectric layer 17 may include a stack of silicon oxide and a high-k material. The silicon oxide may be the first gate dielectric layer 17A and the second gate dielectric layer 17B, and the high-k material may be the additional gate dielectric layer. The high-k material may include a material having an oxygen atomic surface density higher than that of the silicon oxide.

[0093] See Figure 6A and Figure 6B , a gate electrode 18 may be formed on the gate dielectric layer 17 to partially fill the gate trench 15.

[0094] The gate electrode 18 may be disposed at a horizontal height lower than the top surface of the active region 14. The gate electrode 18 may include a metal-based material. The gate electrode 18 may include a semiconductor material, a metal, a metal nitride, or a combination thereof. The gate electrode 18 may include polysilicon, tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), ruthenium (Ru), or a combination thereof. The gate electrode 18 may be formed of a stack of titanium nitride and tungsten, a stack of titanium nitride and polysilicon, or titanium nitride alone. According to an embodiment of the present disclosure, the gate electrode 18 may have a high work function. For example, a high work function may refer to a work function higher than the mid-gap work function of silicon. A low work function may refer to a work function lower than the mid-gap work function of silicon. The high work function may have a work function higher than about 4.5 eV, while the low work function may have a work function lower than about 4.5 eV. The gate electrode 18 may include p-type polysilicon or nitrogen-rich titanium nitride.

[0095] According to an embodiment of the present disclosure, the gate electrode 18 may have an increased high work function. The gate electrode 18 may include a metal silicon nitride. The metal silicon nitride may be obtained by doping a metal nitride with silicon. The gate electrode 18 may include a metal silicon nitride with a controlled silicon content. For example, the gate electrode 18 may include tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function. Titanium nitride may contain silicon to further increase the work function of titanium nitride. The high work function of titanium silicon nitride may be increased by adjusting the silicon content. According to an embodiment of the present disclosure, the gate electrode 18 may include titanium aluminum nitride (TiAlN).

[0096] Return reference Figure 6A , a first sidewall of the gate electrode 18 may contact the first gate dielectric layer 17A and the isolation layer 12, while a second sidewall of the gate electrode 18 may contact the second gate dielectric layer 17B and the isolation layer 12. The first sidewall and the second sidewall of the gate electrode 18 may include a plurality of flat surfaces and a plurality of recessed surfaces. For example, the flat surface refers to the portion contacting the isolation layer 12, while the recessed surface refers to the portion contacting the first gate dielectric layer 17A and the second gate dielectric layer 17B.

[0097] Reference Figure 7A and Figure 7B, a covering layer 19 may be formed over the gate electrode 18 and may cover the exposed top surface of the gate electrode. The covering layer 19 may be used to protect the gate electrode 18. The covering layer 19 may fill the upper part of the gate trench 15 over the gate electrode 18. The top surface of the covering layer 19 may be set at the same horizontal height as the top surface of the hard mask layer GM. The covering layer 19 may include, for example, silicon oxide, silicon nitride, or a combination thereof. According to an embodiment of the present disclosure, the covering layer 19 may include fluorinated silicon oxide, fluorinated silicon nitride, or a combination thereof. Fluorinated silicon nitride refers to a silicon nitride layer doped with fluorine.

[0098] After forming the covering layer 19, a first doped region 20A and a second doped region 20B may be formed in the first node 14A and the second node 14B respectively. The first doped region 20A and the second doped region 20B may be formed by a doping process with a conductive dopant. The first doped region 20A may be formed in the first node 14A, while the second doped region 20B may be formed in the second node 14B. The first doped region 20A and the second doped region 20B may be referred to as source / drain regions.

[0099] The first doped region 20A and the second doped region 20B may be regions doped with a conductive dopant. For example, the conductive dopant may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first doped region 20A and the second doped region 20B may be doped with dopants of the same conductive type. The first doped region 20A and the second doped region 20B may be disposed in the active region 14 on both sides of the gate trench 15. The bottom surfaces of the first doped region 20A and the second doped region 20B may be set at a predetermined depth from the top surface of the active region 14. The first doped region 20A may contact the growth promoting region 16D. The depth H1 of the first doped region 20A may be less than the depth H2 of the second doped region 20B. The depth H1 of the first doped region 20A may be less than the depth of the growth promoting region 16D. The bottom surfaces of the first doped region 20A and the second doped region 20B may be higher than the bottom surface 15C of the gate trench 15. The first doped region 20A may be referred to as the "first source / drain region", while the second doped region 20B may be referred to as the "second source / drain region". A channel may be defined between the first doped region 20A and the second doped region 20B by the gate electrode 18. The channel may be defined along the contour of the gate trench 15.

[0100] Subsequently, a first contact node 141, a bit line 140, a second contact node 151, and a data storage element 150 as shown in Figure 1A and Figure 1B may be formed in sequence. For example, forming the first contact node 141 and the bit line 140 coupled to the second doped region 20B, and forming the second contact node 151 and the data storage element 150 coupled to the first doped region 20A may be performed.

[0101] Figure 8A is a plan view showing a semiconductor device according to an embodiment of the present disclosure. Figure 8B is a cross-sectional view taken along Figure 8A line A-A' shown in, while Figure 8C is a cross-sectional view taken along Figure 8A line C-C' shown in. Figures 8A to 8C The semiconductor device 200 of can be similar to Figure 1B the semiconductor device 100 of. Hereinafter, a detailed description of the constituent elements that also appear in Figure 1B will be omitted.

[0102] Referring to Figures 8A to 8C , the semiconductor device 200 may include: a substrate 101; an isolation layer 102; an active region 104, the active region 104 including a first node 104A and a second node 104B isolated from each other by a gate trench 105; a first gate dielectric layer 110A formed on a flat sidewall FS1 of the first node 104A; a second gate dielectric layer 110B formed on a flat sidewall FS2 of the second node 104B; a third gate dielectric layer 110C formed on a bottom surface of the gate trench 105; a gate electrode 120 that partially fills the gate trench 105 above the first to third gate dielectric layers 110A, 110B, and 110C; a cover layer 130 located above the gate electrode 120; a first doped region 107 formed in the first node 104A; a second doped region 108 formed in the second node 104B; a first contact node 141 and a bit line 140 coupled to the second doped region 108; a second contact node 151 and a data storage element 150 coupled to the first doped region 107; and a growth promotion region 106 located between the first gate dielectric layer 110A and the first doped region 107. The bit line 140 may extend along a first direction D1, while the gate electrode 120 may extend along a second direction D2. The first direction D1 and the second direction D2 may be orthogonal to each other. The active regions 104 may be arranged unidirectionally along a third direction D3.

[0103] In the semiconductor device 200, one gate electrode 120 may be formed in one active region 104. The semiconductor device 200 may include a memory cell of a 1G1A structure.

[0104] The semiconductor device 200 may further include a highly doped region 111. The highly doped region 111 may be formed in the second node 104B. The highly doped region 111 may be vertically spaced apart from the second doped region 108. The highly doped region 111 may be adjacent to the third gate dielectric layer 110C. The highly doped region 111 may include a dopant different from the dopants of the first doped region 107 and the second doped region 108. The highly doped region 111 may contain a P-type dopant, such as boron, while the first doped region 107 and the second doped region 108 may contain an N-type dopant. The highly doped region 111 may contact the fin region 104F, the isolation layer 102, and the third gate dielectric layer 110C. According to an embodiment of the present disclosure, the highly doped region 111 may include an N-type dopant. For example, the highly doped region 111 may include arsenic (As), phosphorus (P), or antimony (Sb).

[0105] As described above, a single-doped region of the first doped region 107 may be formed in the first node 104A, and a double-doped region of the second doped region 108 and the highly doped region 111 may be provided in the second node 104B. After the above operations are completed, the semiconductor device 200 including the memory cell of the 1G1A structure may include a doped region of an asymmetric structure.

[0106] The highly doped region 111 may serve to increase the barrier. Therefore, the row hammering that may be caused by the passing gates PG1 and PG2 during the operation of the main gate MG can be improved.

[0107] Row hammering refers to the phenomenon in which data stored in a capacitor operated by the main gate MG is distorted when the passing gates PG1 and PG2 located near the main gate MG continuously operate. When the passing gates PG1 and PG2 are turned on, electrons stored in the capacitor disposed adjacent to the main gate MG may migrate and be trapped at the interface between the active region 104 adjacent to the passing gates PG1 and PG2 and the isolation layer 102. When the passing gates PG1 and PG2 are turned off, some of the discharged electrons may recombine with holes or cross the barrier of the main gate MG, distorting the data. Row hammering may cause gate-induced drain leakage (GIDL), thereby reducing the reliability of the semiconductor device.

[0108] The highly doped region 111 according to this embodiment of the present disclosure may serve to increase the barrier. Therefore, the row hammering can be improved, and the off-state leakage and the refresh time Tref can be improved. The refresh time Tref refers to the time interval for receiving a refresh command.

[0109] Figure 9A A method for forming the Figure 8B shown highly doped region 111 is shown. The method of manufacturing the Figures 8A to 8C shown semiconductor device 200 may be the same as Figures 3A to 7BThe method shown is similar.

[0110] A series of operations shown in Figures 3A to 7B can be performed.

[0111] After forming the first doped region 20A and the second doped region 20B after Figure 7A and Figure 7B as shown in Figure 9A a mask layer MK can be formed which selectively exposes only the second node 14B among the first node 14A and the second node 14B.

[0112] The high doping process 21 of the dopant can be carried out using the mask layer MK as a barrier. The high doping process 21 can include a doping process of a P-type dopant. For example, the high doping process 21 can include a boron implantation process. The high doping process 21 can adopt a spin method. As used herein, "high doping" means that the concentration of the dopant is high such that there is a significant interaction between the dopant atoms. For example, the range of the dopant concentration of the high doping process 21 can be from about 1.0×10 12 atoms / cm 3 to about 1.0×10 16 atoms / cm 3 . According to an embodiment of the present disclosure, the high doping process 21 can include a doping process of an N-type dopant such as arsenic (As), phosphorus (P), or antimony (Sb).

[0113] The high doping region 22 can be formed in the second node 14B by the high doping process 21.

[0114] Figure 9B is another embodiment of the method for forming Figure 8B the high doping region 111 shown in

[0115] A series of operations shown in Figures 3A to 4B can be performed.

[0116] After forming the growth promoting region 16D after Figure 4A and Figure 4B the high doping process 21 of the dopant can be carried out using the hard mask layer GM as a barrier as shown in Figure 9B The high doping process 21 can include a doping process of a P-type dopant. For example, the high doping process 21 can include a boron implantation process. The high doping process 21 can adopt an inclined implantation method. According to an embodiment of the present disclosure, the high doping process 21 can include a doping process of an N-type dopant such as arsenic (As), phosphorus (P), or antimony (Sb).

[0117] The high doping region 22 can be formed in the second node 14B by the high doping process 21.

[0118] Figure 10A and Figure 10B are cross-sectional views taken along lines A-A' and C-C' shown in Figure 8A respectively. Figure 10A and Figure 10B The semiconductor devices of Figure 8B and Figure 8C are similar to the semiconductor device 100 of Figure 8B and Figure 8C . In the following, the detailed description of the constituent elements that also appear in

[0119] Reference Figure 10A and Figure 10B , the highly doped region 111A can be formed in the first node 104A close to the third gate dielectric layer 110C. The highly doped region 111A can overlap with the first doped region 107. The highly doped region 111A can be vertically spaced apart from the first doped region 107. The highly doped region 111A can be adjacent to the third gate dielectric layer 110C. The highly doped region 111A can include dopants different from those of the first doped region 107 and the second doped region 108. The highly doped region 111A can contain a P-type dopant such as boron, while the first doped region 107 and the second doped region 108 can contain an N-type dopant. The highly doped region 111A can contact the fin region 104F, the isolation layer 102, and the growth promotion region 106. According to an embodiment of the present disclosure, the highly doped region 111A can include an N-type dopant such as arsenic (As), phosphorus (P), or antimony (Sb).

[0120] As described above, the single-doped region of the second doped region 108 can be formed in the second node 104B, while the double-doped region of the first doped region 107 and the highly doped region 111A can be provided in the first node 104A. Eventually, the semiconductor device can include a doped region with an asymmetric structure.

[0121] The highly doped region 111A can serve to increase the potential barrier. Therefore, the row hammering caused by the transmission gates PG1 and PG2 during the operation of the main gate MG can be improved.

[0122] The highly doped region 111A can be referred to as a potential barrier region. The highly doped region 111A can contact the isolation layer 102 and the fin region 104F.

[0123] To form the highly doped region 111A, as Figure 9A shown, after forming the first doped region 20A and the second doped region 20B, a high-doping process 21 of dopants can be performed using the mask layer MK as a barrier. In addition, to form the highly doped region 111A, as Figure 9B shown, after forming the growth promotion region 16D, a high-doping process of dopants can be performed using the hard mask layer GM as a barrier.

[0124] Reference Figures 8A to 10B As shown in Figures 8A to 10B , highly doped regions 111 and 111A can be formed in the first node 104A and the second node 104B, respectively. Accordingly, a doped region having an asymmetric structure can be formed.

[0125] Figure 11 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figure 11 The semiconductor device 300 shown can be similar to Figure 1B the semiconductor device 100 shown. Hereinafter, a detailed description of the constituent elements that also appear in Figure 1B may be omitted.

[0126] The semiconductor device 300 may include: a substrate 101; an isolation layer 102; an active region 104 including a first node 104A and a second node 104B isolated from each other by a gate trench 105; a first gate dielectric layer 110A' formed on a flat sidewall FS1 of the first node 104A; a second gate dielectric layer 110B formed on a flat sidewall FS2 of the second node 104B; a third gate dielectric layer 110C formed on a bottom surface of the gate trench 105; a gate electrode 120 partially filling the gate trench 105 on the first to third gate dielectric layers 110A', 110B, and 110C; a capping layer 130 on the gate electrode 120; a first doped region 107 formed in the first node 104A; a second doped region 108 formed in the second node 104B; a first contact node 141 and a bit line 140 coupled to the second doped region 108; a second contact node 151 and a data storage element 150 coupled to the first doped region 107; and a growth promoting region 106' located between the first gate dielectric layer 110A' and the first doped region 107. According to an embodiment of the present disclosure, the semiconductor device 300 may further include Figure 8B the highly doped region 111 shown in Figure 8B .

[0127] The semiconductor device 300 may include a memory cell having a 1G1A structure.

[0128] Reference Figure 11 As shown in Figure 11 , the thickness of the first gate dielectric layer 110A' may be greater than the thickness of the second gate dielectric layer 110B. The bottom surface 105C of the gate trench 105 may be disposed at a first horizontal height L1, while the bottom surface of the growth promoting region 106' may be disposed at a second horizontal height L2. The second horizontal height L2 may be shallower than the first horizontal height L1. The first gate dielectric layer 110A' may include a thin portion 110AT, and the thin portion 110AT may be disposed between the first horizontal height L1 and the second horizontal height L2.

[0129] Figure 11 The growth promoting region 106' shown in

[0129] may have a ratio greater thanFigure 1B The growth promoting region 106 shown has a small vertical height.

[0130] Figure 12 It is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figure 12 The semiconductor device 310 shown can be similar to Figure 1B the semiconductor device 100 shown and Figure 11 the semiconductor device 300 shown. Hereinafter, the detailed description of the constituent elements that also appear in Figure 1B and Figure 11 can be omitted.

[0131] The semiconductor device 310 may include: a substrate 101; an isolation layer 102; an active region 104 including a first node 104A and a second node 104B isolated from each other by a gate trench 105; a first gate dielectric layer 110A” formed on the flat sidewall FS1 of the first node 104A; a second gate dielectric layer 110B formed on the flat sidewall FS2 of the second node 104B; a third gate dielectric layer 110C formed on the bottom surface of the gate trench 105; a gate electrode 120 partially filling the gate trench 105 above the first to third gate dielectric layers 110A”, 110B, and 110C; a capping layer 130 above the gate electrode 120; a first doped region 107 formed in the first node 104A; a second doped region 108 formed in the second node 104B; a first contact node 141 and a bit line 140 coupled to the second doped region 108; a second contact node 151 and a data storage element 150 coupled to the first doped region 107; a growth promoting region 106” located between the first gate dielectric layer 110” and the first doped region 107. According to an embodiment of the present disclosure, the semiconductor device 310 may further include Figure 8B the highly doped region 111 shown.

[0132] The semiconductor device 310 may include a memory cell of a 1G1A structure.

[0133] The first gate dielectric layer 110A” may include a first portion 110A1 and a second portion 110A2, and the first portion 110A1 may be thicker than the second portion 110A2. The growth promoting region 106” may be provided between the first portion 110A1 of the first gate dielectric layer 110A” and the first doped region 107. The second portion 110A2 of the first gate dielectric layer 110A” may not contact the growth promoting region 106”.

[0134] See Figure 12, the thickness of the first part 110A1 of the first gate dielectric layer 110A" can be greater than the thickness of the second gate dielectric layer 110B. The bottom surface 105C of the gate trench 105 can be set at a first horizontal height L1, while the bottom surface of the growth promoting region 106" can be set at a second horizontal height L2. The bottom surfaces of the first doped region 107 and the growth promoting region 106" can be set at the second horizontal height L2. The second horizontal height L2 can be shallower than the first horizontal height L1. The second part 110A2 of the first gate dielectric layer 110A" can be set between the first horizontal height L1 and the second horizontal height L2.

[0135] Figure 12 The vertical height of the shown growth promoting region 106" can be less than Figure 1B the shown growth promoting region 106 and Figure 11 the shown growth promoting region 106'.

[0136] Figure 13 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figure 13 The shown semiconductor device 400 can be similar to Figure 1B the shown semiconductor device 100. Hereinafter, the detailed description of the constituent elements that also appear in Figure 1B can be omitted.

[0137] The semiconductor device 400 can include: a substrate 101; an isolation layer 102; an active region 104 including a first node 104A and a second node 104B isolated from each other by a gate trench 105; a first gate dielectric layer 110A formed on the flat sidewall FS1 of the first node 104A; a second gate dielectric layer 110B formed on the flat sidewall FS2 of the second node 104B; a third gate dielectric layer 110C formed on the bottom surface of the gate trench 105; a buried gate electrode BG1 partially filling the gate trench 105 above the first to third gate dielectric layers 110A, 110B, and 110C; a capping layer 130 above the buried gate electrode BG1; a first doped region 107 formed in the first node 104A; a second doped region 108 formed in the second node 104B; a first contact node 141 and a bit line 140 coupled to the second doped region 108; a second contact node 151 and a data storage element 150 coupled to the first doped region 107; and a growth promoting region 106 located between the first gate dielectric layer 110A and the first doped region 107. According to an embodiment of the present disclosure, the semiconductor device 400 may further include Figure 8B the shown highly doped region 111. The first gate dielectric layer 110A can be thicker than the second gate dielectric layer 110B. The growth promoting region 106 can be set between the first gate dielectric layer 110A and the first doped region 107.

[0138] The semiconductor device 400 may include a memory cell of a 1G1A structure.

[0139] Figure 13 The buried gate electrode BG1 of the semiconductor device 400 shown may have a dual work function structure. The buried gate electrode BG1 may include a lower gate electrode 121 and an upper gate electrode 122. The lower gate electrode 121 may include a high work function material, and the upper gate electrode 122 may include a low work function material. The lower gate electrode 121 may include a metal-based material, and the upper gate electrode 122 may include a semiconductor material. The lower gate electrode 121 may be titanium nitride, tungsten, or a stack thereof, and the upper gate electrode 122 may be doped polysilicon. Doped polysilicon may refer to polysilicon doped with an N-type dopant. According to an embodiment of the present disclosure, the lower gate electrode 121 may be high work function titanium nitride, and the upper gate electrode 122 may include low work function titanium nitride. The difference between the work function of the high work function titanium nitride and the work function of the low work function titanium nitride may be adjusted according to the nitrogen content. Titanium nitride rich in nitrogen (N-rich TiN) with a nitrogen content higher than that of stoichiometric titanium nitride may have a high work function.

[0140] The upper gate electrode 122 may horizontally overlap with the growth promotion region 106, the first doped region 107, and the second doped region 108.

[0141] GIDL may be further improved by the low work function upper gate electrode 122.

[0142] Figure 14 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure. Figure 14 The semiconductor device 410 may be similar to Figure 1B the semiconductor device 100 shown in Figure 13 and Figure 1B and Figure 13 the semiconductor device 400 shown in. Hereinafter, a detailed description of the constituent elements that also appear in

[0143] The semiconductor device 410 may include: a substrate 101; an isolation layer 102; an active region 104 including a first node 104A and a second node 104B isolated from each other by a gate trench 105; a first gate dielectric layer 110A formed on a flat sidewall FS1 of the first node 104A; a second gate dielectric layer 110B formed on a flat sidewall FS2 of the second node 104B; a third gate dielectric layer 110C formed on a bottom surface of the gate trench 105; a buried gate electrode BG2 partially filling the gate trench 105 over the first to third gate dielectric layers 110A, 110B, and 110C; a capping layer 130 over the buried gate electrode BG2; a first doped region 107 formed in the first node 104A; a second doped region 108 formed in the second node 104B; a first contact node 141 and a bit line 140 coupled to the second doped region 108; a second contact node 151 and a data storage element 150 coupled to the first doped region 107; and a growth promoting region 106 located between the first gate dielectric layer 110A and the first doped region 107. According to an embodiment of the present disclosure, the semiconductor device 400 may further include Figure 8B the highly doped region 111 shown. The first gate dielectric layer 110A may be thicker than the second gate dielectric layer 110B. The growth promoting region 106 may be disposed between the first gate dielectric layer 110A and the first doped region 107. The semiconductor device 410 may include a memory cell of a 1G1A structure.

[0144] Figure 14 The buried gate electrode BG2 of the semiconductor device 410 shown in may have a triple work function structure. The buried gate electrode BG2 may include a lower gate electrode 121, an upper gate electrode 122, and an intermediate gate electrode 123 disposed between the lower gate electrode 121 and the upper gate electrode 122. The lower gate electrode 121 may include a high work function material, the upper gate electrode 122 may include a low work function material, and the intermediate gate electrode 123 may include an intermediate work function material. The intermediate work function of the intermediate gate electrode 123 may be greater than the low work function of the upper gate electrode 122 and less than the high work function of the lower gate electrode 121. The lower gate electrode 121 may include a metal-based material, and the upper gate electrode 122 may include a semiconductor material. The lower gate electrode 121 may include titanium nitride, tungsten, or a stack thereof, and the upper gate electrode 122 may include doped polysilicon. The doped polysilicon may refer to polysilicon doped with an N-type dopant. According to an embodiment of the present disclosure, the lower gate electrode 121 may include high work function titanium nitride, and the upper gate electrode 122 may include low work function titanium nitride. The difference between the work function of the high work function titanium nitride and the work function of the low work function titanium nitride may be adjusted according to the nitrogen content. Nitrogen-rich titanium nitride (nitrogen-rich TiN) with a nitrogen content higher than stoichiometric titanium nitride may have a high work function.

[0145] The upper gate electrode 122 may horizontally overlap with the growth promotion region 106, the first doped region 107, and the second doped region 108.

[0146] GIDL can be further improved by the upper gate electrode 122 with a low work function.

[0147] Figure 15 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. Figure 15 The semiconductor device 500 shown may be similar to Figure 1A the semiconductor device 100 shown. Hereinafter, a detailed description of the constituent elements that also appear in Figure 1A may be omitted.

[0148] Referring to Figure 1A and Figure 15 , the semiconductor device 500 may include: a substrate 101; an isolation layer 102; an active region 104 including a first node 104A and a second node 104B isolated from each other by a gate trench 105; a first gate dielectric layer 110A formed on the flat sidewalls of the first node 104A; a second gate dielectric layer 110B formed on the flat sidewalls of the second node 104B; a gate electrode 120 that partially fills the gate trench 105 above the first and second gate dielectric layers 110A and 110B; a capping layer 130 above the gate electrode 120; a first doped region 107 formed in the first node 104A; a second doped region 108 formed in the second node 104B; a first contact node 141 and a bit line 140 coupled to the second doped region 108; a second contact node 151 and a data storage element 150 coupled to the first doped region 107; and a growth promotion region 106 located between the first gate dielectric layer 110A and the first doped region 107. According to an embodiment of the present disclosure, the semiconductor device 310 may further include Figure 8B the highly doped region 111 shown.

[0149] In the semiconductor device 500, the gate electrode 120 may extend along a first direction D1, while the bit line 140 may extend along a second direction D2. The gate trench 105 in which the gate electrode 120 is formed may divide one active region 104 into a first node 104A and a second node 104B.

[0150] The semiconductor device 500 may include a memory cell of a 1G1A structure.

[0151] According to an embodiment of the present disclosure, by asymmetrically forming the thickness of the buried gate structure's gate dielectric layer, leakage and refresh can be improved.

[0152] Furthermore, according to an embodiment of the present disclosure, by forming an asymmetrically structured doped region, row hammering and refresh operations can be improved.

[0153] Although embodiments of the present disclosure have been described with respect to specific embodiments, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined in the following claims. Additionally, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: a plurality of active regions in a substrate; a gate trench formed in at least one of the plurality of active regions, the gate trench comprising a first sidewall, a second sidewall opposite to the first sidewall, and a bottom sidewall; a growth promotion region formed on the first sidewall of the gate trench; a first gate dielectric layer formed on the first sidewall of the gate trench to contact the growth promotion region; a second gate dielectric layer formed on the second sidewall of the gate trench to be thinner than the first gate dielectric layer; and A gate electrode partially fills the gate trench over the first gate dielectric layer and the second gate dielectric layer.

2. The semiconductor device according to claim 1, wherein The growth promoting region includes a growth promoting substance for increasing a growth rate of the first gate dielectric layer.

3. The semiconductor device according to claim 1, wherein The growth promoting zone includes oxygen, fluorine or a combination thereof.

4. The semiconductor device according to claim 1, wherein: The first gate dielectric layer includes silicon oxide, and the growth promoting region includes an oxygen-containing silicon layer.

5. The semiconductor device according to claim 1, wherein The first gate dielectric layer includes silicon oxide, and the growth promoting region includes a fluorine-containing silicon layer.

6. The semiconductor device according to claim 1, wherein The first gate dielectric layer includes silicon oxide, and the growth promoting region includes a silicon layer containing oxygen and fluorine.

7. The semiconductor device according to claim 1, wherein The first gate dielectric layer includes silicon oxide, and The growth promoting region includes silicon oxide or fluorine-containing silicon oxide.

8. The semiconductor device according to claim 1, wherein A gate electrode is disposed in each of the active regions.

9. The semiconductor device according to claim 1, wherein: The active region includes a first node and a second node obtained by being divided by the gate trench.

10. The semiconductor device according to claim 9, further comprising: a first doped region formed in the first node; a second doping region formed in the second node to be deeper than the first doping region; a data storage element coupled to the first doped region; as well as A bit line is coupled to the second doped region.

11. A semiconductor device comprising: substrate; an isolation layer defining an active region in the substrate, the active region including a first node and a second node; a gate trench formed between the first node and the second node and including a first sidewall and a second sidewall; a growth promotion region formed on the first sidewall of the gate trench; a first gate dielectric layer formed on the first sidewall of the gate trench to contact the growth promotion region; a second gate dielectric layer formed on the second sidewall of the gate trench to be thinner than the first gate dielectric layer; a gate electrode partially filling the gate trench over the first gate dielectric layer and the second gate dielectric layer; as well as A barrier region is formed below the second sidewall of the gate trench in the second node.

12. The semiconductor device according to claim 11, further comprising: a first doped region formed in the first node; as well as a second doping region formed in the second node to be deeper than the first doping region, Wherein, the barrier region is arranged below the second doping region.

13. The semiconductor device according to claim 12, wherein: The barrier region includes a P-type dopant, and The first doped region and the second doped region include N-type dopants.

14. The semiconductor device according to claim 11, wherein The growth promoting region includes a growth promoting substance to increase a growth rate of the first gate dielectric layer.

15. The semiconductor device according to claim 11, wherein The growth promoting zone includes oxygen, fluorine or a combination thereof.

16. The semiconductor device according to claim 11, wherein The first gate dielectric layer includes silicon oxide, and The growth promoting region includes an oxygen-containing silicon layer, a fluorine-containing silicon layer, or a silicon layer containing oxygen and fluorine.

17. The semiconductor device according to claim 11, wherein The first gate dielectric layer includes silicon oxide, and The growth promoting region includes silicon oxide or fluorine-containing silicon oxide.

18. The semiconductor device according to claim 11, further comprising: a data storage element coupled to the first doped region; as well as A bit line is coupled to the second doped region.

19. The semiconductor device according to claim 11, wherein A gate electrode is disposed in each of the active regions.

20. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of active regions in a substrate; forming a gate trench in each of the active regions, the gate trench comprising a first sidewall and a second sidewall facing the first sidewall; doping the first sidewall of the gate trench with a growth promoting substance; forming a first gate dielectric layer and a second gate dielectric layer on the first sidewall and the second sidewall of the gate trench, respectively; as well as A gate electrode is formed over the first gate dielectric layer and the second gate dielectric layer, the gate electrode partially filling the gate trench.

21. The method according to claim 20, wherein: The growth promoting substance includes an oxidation promoting substance to increase a growth rate of the first gate dielectric layer.

22. The method according to claim 20, wherein: The growth promoting substance includes oxygen, fluorine or a combination thereof.

23. The method according to claim 20, wherein: Doping the first sidewall of the gate trench with the growth promoting substance includes: Tilt implantation process.

24. The method according to claim 20, wherein: When forming the gate trench, Each of the active regions includes a first node and a second node obtained by being divided by the gate trench.

25. The method according to claim 24, further comprising: forming a first doped region in a first node of the active region; forming a second doped region in a second node of the active region; as well as A barrier region is formed under one of the first doping region and the second doping region.

26. The method according to claim 25, wherein: The barrier region includes a P-type dopant.

27. The method of claim 20, further comprising: forming an isolation layer defining the active area in the substrate, Wherein, a gate electrode is arranged in each of the active regions.

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