Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the reliability problem of a trench type semiconductor device. The semiconductor device comprises a collector region, a drift region, an emitter region, a gate dielectric layer, a gate region and a first shielding part, the drift region is arranged on the collector region, a first groove is formed in the surface, away from the collector region, of the drift region, the emitter region is arranged on the side, away from the collector region, of the drift region, and the gate dielectric layer is arranged on the bottom surface and the side wall surface of the first groove; the gate region is arranged in the first groove and is wrapped by the gate dielectric layer, the first shielding part is arranged at the bottom of the first groove and is in contact with the gate dielectric layer, the drift region comprises a first sub-drift region and a second sub-drift region which are stacked, the second sub-drift region is located on one side, far away from the collector region, of the first sub-drift region, and the first shielding part is arranged at the bottom of the second sub-drift region. The doping types of the first sub-drift region and the second sub-drift region are different, and the first shielding part is in contact with the second sub-drift region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As a composite power semiconductor device that combines the advantages of high input impedance of MOSFET and low on-state voltage drop of bipolar transistors, insulated gate bipolar transistors (IGBTs) are widely used in power electronic systems, such as new energy power generation inverters, electric vehicle drive modules, industrial motor controllers and other fields. With the continuous improvement of the power system's demand for high efficiency and high power density, the performance optimization of IGBT devices has become a hot research topic in the industry.

[0003] In a traditional planar gate structure IGBT, a conductive channel is formed by horizontally arranging the gate region. However, due to the mobility limitation of the surface channel and the tortuosity of the current path under the gate region, there is a significant trade-off relationship between the on-resistance and the blocking voltage. In addition, the tail current formed between the collector region and the emitter region during the turn-off process will cause higher turn-off losses, restricting the improvement of the switching frequency.

[0004] To break through the above bottleneck, the industry has proposed a trench gate structure, which replaces the planar gate region by vertically etching trenches, so that the channel is distributed perpendicular to the chip surface. This vertical conduction mode can shorten the carrier path, reduce the on-impedance, and at the same time increase the cell density. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, aiming to solve the reliability problem of trench-type semiconductor devices.

[0006] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions: On the one hand, a semiconductor device is provided, including a collector region, a drift region, an emitter region, a gate dielectric layer, a gate region, and a first shielding portion. The drift region is disposed on the collector region, and a first groove is provided on the surface of the drift region away from the collector region. The emitter region is disposed on the side of the drift region away from the collector region. The gate dielectric layer is disposed on the bottom surface and the side wall surface of the first groove. The gate region is disposed in the first groove and is covered by the gate dielectric layer. The first shielding portion is disposed at the bottom of the first groove and is in contact with the gate dielectric layer. Wherein, the drift region includes a first sub-drift region and a second sub-drift region which are stacked, the second sub-drift region is located on the side of the first sub-drift region away from the collector region, and the doping types of the first sub-drift region and the second sub-drift region are different. The first shielding portion is in contact with the second sub-drift region.

[0007] When the semiconductor device operates in the breakdown voltage withstand state, the channel in the gate region is turned off. When the blocking voltage is applied between the collector region and the emitter region, the first shielding portion can reduce the electric field borne by the gate dielectric layer, thereby protecting the gate dielectric layer. In addition, the PN junction formed by the second sub-drift region and the first sub-drift region is in the reverse bias state and bears part of the electric field, which can further reduce the electric field borne by the gate dielectric layer, make the electric field distribution more uniform, and is beneficial to improving the breakdown voltage of the semiconductor device, thereby increasing the expected lifespan and reliability of the semiconductor device. The improvement of the electric field distribution can also make the temperature distribution more uniform, avoid local overheating of the semiconductor device, and further enhance the expected lifespan and reliability of the semiconductor device.

[0008] In some feasible embodiments, the semiconductor device further includes a second groove, an emitter region dielectric layer, an emitter region conductor, and a second shielding portion. The second groove is disposed on the surface of the drift region away from the collector region, and the second groove and the first groove are respectively located on both sides of the emitter region. The emitter region dielectric layer is disposed on the bottom surface and the side wall surface of the second groove. The emitter region conductor is disposed in the second groove and is covered by the emitter region dielectric layer. The second shielding portion is disposed at the bottom of the second groove and is in contact with the emitter region dielectric layer. The second shielding portion is also in contact with the second sub-drift region.

[0009] When the semiconductor device operates in the breakdown voltage withstand state, the channel in the gate region is turned off. When the blocking voltage is applied between the collector region and the emitter region, the second shielding portion can reduce the electric field borne by the emitter region dielectric layer, thereby protecting the emitter region dielectric layer. In addition, the PN junction formed by the second sub-drift region and the first sub-drift region is in the reverse bias state and bears part of the electric field, which can further reduce the electric field borne by the emitter region dielectric layer, make the electric field distribution more uniform, and is beneficial to improving the breakdown voltage of the semiconductor device, thereby increasing the expected lifespan and reliability of the semiconductor device.

[0010] In some feasible embodiments, the first shielding portion has the same doping type as the second sub-drift region, and the doping concentration of the first shielding portion is greater than the doping concentration of the second sub-drift region.

[0011] In some feasible embodiments, the semiconductor device further includes a carrier storage layer. The carrier storage layer is located between the emitter region and the second sub-drift region, and is located between the first groove and the second groove. The carrier storage layer is in contact with the gate dielectric layer and the emitter region dielectric layer respectively. The doping type of the carrier storage layer is different from that of the second sub-drift region.

[0012] When the semiconductor device is in the conduction state, holes injected from the collector region are partially blocked by the carrier storage layer during diffusion in the drift region, forming local hole accumulation, significantly increasing the carrier concentration in the drift region, and thereby reducing the on-resistance of the semiconductor device.

[0013] In some feasible embodiments, along the first direction, the first shielding portion and the second shielding portion do not contact each other. The first direction is the arrangement direction of the first groove and the second groove.

[0014] In some feasible embodiments, the first shielding portion includes a carrier storage layer, and the carrier storage layer extends from the bottom of the first groove to the second shielding portion and contacts the second shielding portion. The doping types of the carrier storage layer and the second sub-drift region are different.

[0015] Using the carrier storage layer as the first shielding portion, on the one hand, the interval between the first shielding portion and the second shielding portion does not need to be considered, and the cell width of the semiconductor device can be reduced. On the other hand, during the turn-on process of the semiconductor device, holes are not easily accumulated at the bottom of the gate region, effectively avoiding the negative capacitance phenomenon in the gate region and improving the gate region control ability of the semiconductor device.

[0016] The carrier storage layer serving as the first shielding portion surrounds the gate dielectric layer and the gate region. During the turn-on process of the semiconductor device, due to the blocking of the first shielding portion, holes injected from the emitter region are not easily accumulated around the gate dielectric layer, which can reduce the influence of hole injection on the gate region current during the turn-on process of the semiconductor device and improve the gate region control ability of the semiconductor device.

[0017] In some feasible embodiments, the carrier storage layer also contacts the emitter region dielectric layer.

[0018] In some feasible embodiments, the second shielding portion has the same doping type as the second sub-drift region, and the doping concentration of the second shielding portion is greater than that of the second sub-drift region.

[0019] In some feasible embodiments, the bottom of the gate dielectric layer extends into the first shielding portion, and the first shielding portion contacts a part of the side surface of the gate dielectric layer; and / or, the bottom of the emitter region dielectric layer extends into the second shielding portion, and the second shielding portion contacts a part of the side surface of the emitter region dielectric layer.

[0020] In some feasible embodiments, the size of the gate region in the thickness direction of the second sub-drift region is smaller than the size of the emitter conductor in the thickness direction of the second sub-drift region; or, the size of the gate region in the thickness direction of the second sub-drift region is equal to the size of the emitter conductor in the thickness direction of the second sub-drift region.

[0021] The size of the gate region in the thickness direction of the second sub-drift region is smaller than the size of the emitter conductor in the thickness direction of the second sub-drift region, and the first shielding portion at the bottom of the first groove uses a carrier storage layer. During the turn-on process of the semiconductor device, the holes injected from the collector region will flow to the region with a lower electric potential. For holes, there is a certain potential barrier height for the first shielding portion including the carrier storage layer, and there is no potential barrier for the second shielding portion. Therefore, holes are more likely to accumulate towards the second shielding portion and are not easily to pass through the first shielding portion with a certain potential barrier and a longer distance, reducing the influence of holes on the gate region capacitance and improving the gate control ability of the semiconductor device.

[0022] In some feasible embodiments, the semiconductor device further includes a first well region, which is located between the emitter region and the carrier storage layer, and between the first groove and the second groove. The first well region is in contact with the gate dielectric layer and the emitter region dielectric layer respectively.

[0023] When the semiconductor device operates in the breakdown voltage withstand state and the gate region channel is closed, when the blocking voltage is applied between the collector region and the emitter region, the first shielding portion and / or the second shielding portion can assist in the depletion of the carrier storage layer to reduce the electric field between the first well region and the carrier storage layer, thereby reducing the electric field borne by the gate dielectric layer and / or the emitter region dielectric layer, which is beneficial to improving the breakdown voltage of the semiconductor device, and thus improving the expected lifetime and reliability of the semiconductor device.

[0024] When the semiconductor device operates in the forward conduction state and the gate region channel is open, when a positive voltage is applied between the collector region and the emitter region, due to the opening of the channel, an electron inversion layer is formed on the surface of the first well region, and the second sub-emitter region is connected to the carrier storage layer through the electron inversion layer on the surface of the first well region. The P-type collector region, the N-type buffer layer, the N-type first sub-drift region, the P-type second sub-drift region, and the N-type carrier storage layer form a PNPN thyristor, and this PNPN thyristor gradually turns on as the collector region current increases. If the PNPN thyristor is fully turned on, there are a large number of free carriers in the first sub-drift region, the second sub-drift region, and the second well region, then the PN junction formed by the well region and the carrier storage layer is in the reverse bias state.

[0025] When the semiconductor device switches from the conduction state to the breakdown voltage withstand state, that is, when it is turned off, the gate region channel changes from open to closed, and the voltage between the collector region and the emitter region gradually increases. Due to the gradual turn-off of the channel, the depletion region of the semiconductor device gradually expands, and the depletion region gradually expands from the PN junction formed by the first well region and the carrier storage layer towards the second sub-drift region. The existence of the second sub-drift region makes the electric field here very small, and the holes in the second sub-drift region can be extracted at a lower voltage, accelerating the hole extraction during turn-off, improving the turn-off speed, thereby reducing the turn-off loss of the semiconductor device and enhancing the reliability of the semiconductor device.

[0026] In addition, when preparing the first well region and the carrier storage layer, the same mask (such as a photomask) can be used for both, which is beneficial to saving process steps and reducing production costs.

[0027] In some feasible embodiments, the semiconductor device further includes a second well region. The second well region is disposed on a side of the second sub-drift region away from the collector region, and the first well region and the second well region are respectively located on two sides of the second groove.

[0028] In some feasible embodiments, the emitter region includes a first sub-emitter region and a second sub-emitter region. The first sub-emitter region and the second sub-emitter region are arranged along a first direction, and the first direction is the arrangement direction of the first groove and the second groove; the doping types of the first sub-emitter region and the second sub-emitter region are different.

[0029] In some feasible embodiments, the semiconductor device further includes a first metal layer, a second metal layer, and an isolation dielectric layer. The first metal layer is located on a side of the collector region away from the drift region. The second metal layer is located on a side of the drift region away from the collector region, and is in ohmic contact with the emitter region and the emitter conductor respectively. The isolation dielectric layer is located between the second metal layer and the second well region, and is also located between the second metal layer and the gate region.

[0030] On the other hand, a method for manufacturing a semiconductor device is provided, including: sequentially forming a stacked collector region, a first sub-drift region, and a second sub-drift region, where the doping types of the first sub-drift region and the second sub-drift region are different; forming an emitter region on a side of the second sub-drift region away from the collector region; etching the second sub-drift region to form a first groove; forming a first shielding portion at the bottom of the first groove; forming a gate dielectric layer on the bottom surface and side wall surface of the first groove, and forming a gate region in the first groove; the gate dielectric layer wraps the gate region.

[0031] It can be understood that for the method for manufacturing a semiconductor device provided in the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the semiconductor device in the above text, and will not be elaborated here. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required to be used in some embodiments of the present disclosure will be briefly introduced below.

[0033] Figure 1 It is a structural diagram of an electronic device according to some embodiments; Figure 2 It is a structural diagram of a chip according to some embodiments; Figure 3Structural diagram of a semiconductor device provided according to some embodiments; Figure 4 Structural diagram of another semiconductor device provided according to some embodiments; Figure 5 Structural diagram of another semiconductor device provided according to some embodiments; Figure 6 Structural diagram of another semiconductor device provided according to some embodiments; Figure 7 Structural diagram of another semiconductor device provided according to some embodiments; Figure 8 Flowchart of a method for manufacturing a semiconductor device provided according to some embodiments; Figure 9 Flowchart of another method for manufacturing a semiconductor device provided according to some embodiments; Figure 10 Flowchart of another method for manufacturing a semiconductor device provided according to some embodiments; Figures 11 - 20 For Figure 10 Semiconductor structural diagrams of the respective steps in the manufacturing method. Detailed implementation manners

[0034] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0035] In the description of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0036] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0037] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0038] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0039] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0040] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0041] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude devices suitable for or configured to perform additional tasks or steps.

[0042] As used herein, "about", "substantially" or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0043] In the context of the present disclosure, the meanings of "on", "above", and "over" should be construed in the broadest manner such that "on" not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0044] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0045] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The materials added on the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the associative relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A alone, A and B present simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refer to any combination of these items, including any combination of single item(s) or plural item(s). For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Additionally, in the embodiments of this application, terms such as "first", "second", etc. do not limit the quantity and order.

[0047] It should be noted that in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or having more advantages than other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0048] Figure 1 FIG. is a structural diagram of an electronic device provided according to some embodiments. As Figure 1 shown, embodiments of the present disclosure provide an electronic device 1000. The electronic device 1000 may be a product or component with a power conversion function such as a power conversion system of an electric vehicle, a charging device of a mobile phone, or a power adapter of a laptop computer. The electronic device 1000 may also be different types of user devices or terminal devices such as a laptop computer, a tablet computer, a mobile phone, a wearable device, and a vehicle-mounted device, or may be a power amplifier device applied to the above electronic devices. It should be understood that the electronic device 1000 may also be a device or component with a signal receiving / transmitting function in devices such as an amplifier, a modulator, a base station, and a radar. The embodiments of the present application do not impose special restrictions on the specific form of the above electronic device 1000.

[0049] Hereinafter, some embodiments of the present disclosure will be schematically described by taking the electronic device 1000 as an electronic device with a power conversion function as an example. However, the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical idea is applied.

[0050] In Figure 1 , the electronic device 1000 includes, for example, a chip 1001 and a circuit board 1002. The chip 1001 is coupled to the circuit board 1002, and the circuit board 1002 is configured to supply power to the chip 1001 and transmit signals. Exemplarily, referring to Figure 2 , Figure 2 FIG. is a structural diagram of a chip provided according to some embodiments. The chip 1001 includes a semiconductor device 100 and a package substrate 200, and the semiconductor device 100 is coupled to the package substrate 200.

[0051] Figure 3A structural diagram of a semiconductor device provided according to some embodiments. The semiconductor device 100 can be a semiconductor device such as silicon, silicon carbide, or gallium nitride. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, an emitter region 107, a gate region 302, and a gate dielectric layer 303. Exemplarily, the buffer layer 102 is located on one side of the collector region 101. The drift region 103 is located on the side of the buffer layer 102 away from the collector region 101, and at least one first groove 401 is provided on the surface of the drift region 103 away from the emitter region 107. The emitter region 107 is located on the side of the drift region 103 away from the collector region 101, and the projection of the emitter region 107 on the first reference plane overlaps with the projection of the collector region 101 on the first reference plane. Herein, the first reference plane is parallel to the thickness direction z of the drift region 103. Exemplarily, the doping type of the collector region 101 is P-type, and the doping types of the buffer layer 102 and the drift region 103 are N-type.

[0052] The gate dielectric layer 303 is provided on the bottom surface and the side wall surface of the first groove 401, and the gate region 302 is provided in the first groove 401 and is covered by the gate dielectric layer 303.

[0053] In some feasible embodiments, the emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b with different doping types. The first sub-emitter region 107a and the second sub-emitter region 107b are arranged along the first direction x, and the first sub-emitter region 107a is farther from the gate region 302 than the second sub-emitter region 107b. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type.

[0054] In Figure 3 , taking the semiconductor device 100 including two gate regions 302 as an example, the two gate regions 302 are arranged along the first direction x, and between the two gate regions 302, there are arranged the second sub-emitter region 107b, the first sub-emitter region 107a, and the second sub-emitter region 107b in sequence along the first direction x. Figure 3 shows the case where the semiconductor device 100 includes two gate regions 302. In the first direction x, the first sub-emitter region 107a, the second sub-emitter region 107b, the gate region 302, the second sub-emitter region 107b, the first sub-emitter region 107a, the second sub-emitter region 107b, the gate region 302, the second sub-emitter region 107b, and the first sub-emitter region 107a are arranged in sequence.

[0055] In some possible embodiments, the semiconductor device 100 further includes a well region 106, a first metal layer 301, an isolation dielectric layer 304, and a second metal layer 305. The first metal layer 301 is located on a side of the collector region 101 away from the buffer layer 102. The second metal layer 305 is located on a side of the drift region 103 away from the collector region 101 and is in ohmic contact with the emitter region 107. The isolation dielectric layer 304 is located on a side of the gate region 302 away from the collector region 101, that is, between the gate region 302 and the second metal layer 305, to electrically isolate the gate region 302 and the second metal layer 305.

[0056] Exemplarily, the material of the gate dielectric layer 303 and / or the isolation dielectric layer 304 includes any one or a combination of several of silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), and silicon nitride (Si3N4). Among them, the material included in the gate dielectric layer 303 may be the same as or different from that of the isolation dielectric layer 304. If the material of the gate dielectric layer 303 is the same as that of the isolation dielectric layer 304, the gate dielectric layer 303 and the isolation dielectric layer 304 can be regarded as a whole.

[0057] The well region 106 is located between the drift region 103 and the emitter region 107. Exemplarily, the doping type of the well region 106 is P-type, and the doping concentration of the well region 106 is less than the doping concentration of the first sub-emitter region 107a.

[0058] Figure 4 It is a structural diagram of another semiconductor device provided according to some embodiments. Exemplarily, the semiconductor device 100 includes a silicon carbide material as an example for illustration. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, a carrier storage layer 105, a well region 106, an emitter region 107, a first shielding portion 108, a gate region 302, and a gate dielectric layer 303.

[0059] The buffer layer 102 is located on one side of the collector region 101. The drift region 103 is located on a side of the buffer layer 102 away from the collector region 101. The drift region 103 includes a first sub-drift region 103a and a second sub-drift region 103b. The first sub-drift region 103a is located on a side of the buffer layer 102 away from the collector region 101. The second sub-drift region 103b is located on a side of the first sub-drift region 103a away from the collector region 101, and the doping types of the first sub-drift region 103a and the second sub-drift region 103b are different. Exemplarily, the doping type of the first sub-drift region 103a is N-type, and the doping type of the second sub-drift region 103b is P-type.

[0060] The emitter region 107 is located on the side of the second sub-drift region 103b away from the collector region 101, and the projection of the emitter region 107 on the first reference plane overlaps with the projection of the drift region 103 on the first reference plane. The first reference plane is parallel to the thickness direction z of the drift region 103.

[0061] A first groove 401 is provided on the surface of the drift region 103 away from the collector region 101. For example, a first groove 401 is provided on the surface of the second sub-drift region 103b away from the collector region 101. The gate dielectric layer 303 is provided on the bottom surface and the side wall surface of the first groove 401. The gate region 302 is provided in the first groove 401 and is coated by the gate dielectric layer 303. A first shielding portion 108 is provided at the bottom of the first groove 401. The first shielding portion 108 is in contact with the gate dielectric layer 303 and is in contact with the second sub-drift region 103b. The bottom of the gate dielectric layer 303 extends into the first shielding portion 108, and the first shielding portion 108 is also in contact with a part of the side surface of the gate dielectric layer 303. Exemplarily, the first shielding portion 108 has the same doping type as the second sub-drift region 103b, and the doping concentration of the first shielding portion 108 is greater than the doping concentration of the second sub-drift region 103b.

[0062] In some feasible embodiments, the semiconductor device 100 further includes an emitter conductor 307 and an emitter dielectric layer 308. A second groove 402 is further provided on the surface of the drift region 103 away from the collector region 101. For example, a second groove 402 is further provided on the surface of the second sub-drift region 103b away from the collector region 101. The emitter dielectric layer 308 is provided on the bottom surface and the side wall surface of the second groove 402. The emitter conductor 307 is provided in the second groove 402 and is coated by the emitter dielectric layer 308. A second shielding portion 109 is provided at the bottom of the second groove 402. The second shielding portion 109 is in contact with the gate dielectric layer 303 and is in contact with the second sub-drift region 103b. The bottom of the emitter dielectric layer 308 extends into the second shielding portion 109, and the second shielding portion 109 is also in contact with a part of the side surface of the emitter dielectric layer 308. Exemplarily, the second shielding portion 109 has the same doping type as the second sub-drift region 103b, and the doping concentration of the second shielding portion 109 is greater than the doping concentration of the second sub-drift region 103b.

[0063] In some feasible embodiments, there is a gap between the first shielding portion 108 and the second shielding portion 109, that is, they do not contact each other, and a part of the second sub-drift region 103b is located within this gap.

[0064] Continue to refer to Figure 4, the carrier storage layer 105 is located between the second sub-drift region 103b and the emitter region 107, and is also located between the first groove 401 and the second groove 402. The carrier storage layer 105 is in contact with the gate dielectric layer 303 and the emitter dielectric layer 308. When the semiconductor device 100 is in the on state, holes injected from the collector region 101 are partially blocked by the carrier storage layer 105 during diffusion in the drift region 103, forming local hole accumulation, which significantly increases the carrier concentration in the drift region 103, thereby reducing the on-resistance of the semiconductor device 100.

[0065] In some feasible embodiments, the well region 106 includes a first well region 106a. The first well region 106a is located between the carrier storage layer 105 and the emitter region 107, and is also located between the first groove 401 and the second groove 402. The first well region 106a is in contact with the gate dielectric layer 303 and the emitter dielectric layer 308 respectively.

[0066] When preparing the carrier storage layer 105 and the first well region 106a, the same mask (such as a photolithography mask) can be used for both, which is beneficial to saving process steps and reducing production costs.

[0067] In some feasible embodiments, the well region 106 further includes a second well region 106b, as Figure 5 shown, Figure 5 is a structural diagram of another semiconductor device provided according to some embodiments. The second well region 106b is provided on the side of the second sub-drift region 103b away from the collector region 101, and is located on both sides of the second groove 402 with the first well region 106a respectively. The first well region 106a and the second well region 106b are arranged along the first direction x, for example. And the second well region 106b is in contact with the second sub-drift region 103b, and the second well region 106b is also in contact with the isolation dielectric layer 304 and the emitter dielectric layer 308 respectively.

[0068] There is no carrier storage layer on the side of the second well region 106b close to the collector region 101, so that the size in the first direction x at this position is not limited by the carrier storage layer, and the width of the semiconductor device 100 can be flexibly adjusted according to the requirements of the actual application scenario, improving the breakdown voltage of the semiconductor device 100.

[0069] In Figure 5 the shown semiconductor device 100, the contact area between the second well region 106b and the gate dielectric layer 303 is small. During the turn-on process of the semiconductor device 100, the charging effect of holes on the gate region 302 and / or the gate dielectric layer 303 is smaller, which is beneficial to improving the gate region control ability of the semiconductor device 100.

[0070] The emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b with different doping types. The first sub-emitter region 107a and the second sub-emitter region 107b are arranged along a first direction x, which is, for example, the arrangement direction of the first groove 401 and the second groove 402. The first sub-emitter region 107a is in contact with the emitter dielectric layer 308, the second sub-emitter region 107b is in contact with the first sub-emitter region 107a, and the second sub-emitter region 107b is in contact with the gate dielectric layer 303. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type.

[0071] In some possible embodiments, the semiconductor device 100 further includes a first metal layer 301, an isolation dielectric layer 304, and a second metal layer 305. The first metal layer 301 is located on the side of the collector region 101 away from the buffer layer 102. The second metal layer 305 is located on the side of the second sub-drift region 103b away from the collector region 101 and forms an ohmic contact with the emitter regions 107 and 207. The isolation dielectric layer 304 is located between the gate region 302 and the second metal layer 305 to electrically isolate the gate region 302 and the second metal layer 305. The isolation dielectric layer 304 is also located between the second well region 106b and the second metal layer 305 to electrically isolate the second well region 106b and the second metal layer 305.

[0072] When the semiconductor device 100 operates in a breakdown voltage withstand state, the voltage of the gate region 302 is less than or equal to 0V, the voltage of the second metal layer 305, i.e., the emitter region 107, is equal to 0V, and the voltage of the first metal layer 301, i.e., the collector region 101, is greater than 0V. At this time, the channel of the gate region 302 is closed, and the blocking voltage is borne between the collector region 101 and the emitter region 107. Due to the existence of the first shielding portion 108 and the second shielding portion 109, the depletion of the carrier storage layer 105 can be assisted, thereby reducing the electric field between the first well region 106a and the carrier storage layer 105; and due to the existence of the first shielding portion 108 and the second shielding portion 109, the electric fields borne by the gate dielectric layer 303 and the emitter dielectric layer 308 can be reduced, thereby protecting the gate dielectric layer 303 and the emitter dielectric layer 308. In addition, the PN junction formed by the second sub-drift region 103b and the first sub-drift region 103a is in a reverse bias state and bears part of the electric field. Therefore, the electric fields at the gate dielectric layer 303, the emitter dielectric layer 308, and the carrier storage layer 105 can be further reduced, making the electric field distribution more uniform, increasing the breakdown voltage of the semiconductor device 100, and thus increasing the expected life and reliability of the semiconductor device 100. The improvement of the electric field distribution can also make the temperature distribution more uniform, avoid local overheating of the semiconductor device 100, and further improve the expected life and reliability of the semiconductor device 100.

[0073] If the semiconductor device 100 operates in the forward conduction state, the voltage of the gate region 302 is greater than 0V, the voltage of the second metal layer 305, i.e., the emitter region 107, is equal to 0V, and the voltage of the first metal layer 301, i.e., the collector region 101, is greater than 0V. At this time, the channel of the gate region 302 is turned on. Since the channel of the gate region 302 is turned on, an electron inversion layer is formed on the surface of the first well region 106a, and the second sub-emitter region 107b is connected to the carrier storage layer 105 through the electron inversion layer on the surface of the first well region 106a. The P-type collector region 101, the N-type buffer layer 102, the N-type first sub-drift region 103a, the P-type second sub-drift region 103b, and the N-type carrier storage layer 105 form a PNPN thyristor, and this PNPN thyristor gradually turns on as the current of the collector region 101 increases. If after this PNPN thyristor is fully turned on, there are a large number of free carriers in the first sub-drift region 103a, the second sub-drift region 103b, and the second well region 106b, then the PN junction formed by the well region 106 and the carrier storage layer 105 is in the reverse bias state.

[0074] When the semiconductor device 100 switches from the conduction state to the voltage withstand state, i.e., turns off, the voltage of the gate region 302 changes from greater than 0V to less than or equal to 0V. At this time, the channel of the gate region 302 changes from being turned on to being turned off, and the voltage between the collector region 101 and the emitter region 107 gradually increases. Since the channel is gradually turned off, the depletion region of the semiconductor device 100 gradually expands, and the depletion region gradually expands from the PN junction formed by the first well region 106a and the carrier storage layer 105 to the second sub-drift region 103b. The existence of the second sub-drift region 103b makes the electric field here very small, and holes in the second sub-drift region 103b can be extracted at a lower voltage, accelerating the hole extraction during turn-off, improving the turn-off speed, thereby reducing the turn-off loss of the semiconductor device 100 and enhancing the reliability of the semiconductor device 100.

[0075] Figure 6 FIG. is a structural diagram of another semiconductor device according to some embodiments. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, a well region 106, an emitter region 107, a first metal layer 301, a gate region 302, a gate dielectric layer 303, an isolation dielectric layer 304, a second metal layer 305, an emitter conductor 307, and an emitter dielectric layer 308. In Figure 6 the illustrated embodiment, the first shielding portion 108 includes a carrier storage layer 105, that is, the bottom of the gate dielectric layer 303 is located within the carrier storage layer 105. In Figure 6 the first shielding portion 108 extends from the bottom of the first groove 401 to the emitter dielectric layer 308, and the first shielding portion 108 is in contact with the emitter dielectric layer 308.

[0076] In some feasible embodiments, the size of the emitter region conductor 307 in the thickness direction z of the drift region 103 is larger than the size of the gate region 302 in the thickness direction z of the drift region 103. Figure 6 The remaining structure of the semiconductor device 100 shown is the same as Figure 4 the semiconductor device 100 shown, and thus will not be described in detail.

[0077] In Figure 6 the semiconductor device 100 shown, the depth of the first groove 401 is less than the depth of the second groove 402, the size of the gate dielectric layer 303 or the gate region 302 in the thickness direction z of the second sub-drift region 103b is less than the size of the emitter region dielectric layer 308 or the emitter region conductor 307 in the thickness direction z of the second sub-drift region 103b, and the first shielding portion 108 at the bottom of the first groove 401 uses the carrier storage layer 105. During the turn-on process of the semiconductor device 100, the holes injected by the collector region 101 will flow to the region with a lower electric potential. For the holes, there is a certain potential barrier height for the first shielding portion 108 including the carrier storage layer 105, and there is no potential barrier for the second shielding portion 109. Therefore, the holes are more likely to accumulate towards the second shielding portion 109 and are not easy to pass through the first shielding portion 108 with a certain potential barrier and farther from the collector region 101, reducing the influence of the holes on the capacitance of the gate region 302 and improving the gate control ability of the semiconductor device 100. In addition, without considering the interval between the first shielding portion 108 and the second shielding portion 109, the cell width of the semiconductor device 100 can be reduced.

[0078] Compared with the emitter region conductor 307, the size of the gate region 302 in the thickness direction z of the drift region 103 is smaller. During the turn-on process of the semiconductor device 100, holes are not easy to accumulate at the bottom of the gate region 302, and the charging effect of the holes on the gate current is not obvious, so the gate control ability of the semiconductor device 100 is stronger. In addition, the size of the emitter region conductor 307 in the thickness direction z of the drift region 103 is larger, and the second shielding portion 109 at its bottom can better shield the electric field of the gate dielectric layer 303 at the bottom of the first groove 401, reducing the probability of breakdown of the gate dielectric layer 303 and improving its reliability.

[0079] Figure 7 FIG. is a structural diagram of another semiconductor device provided according to some embodiments. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, a well region 106, an emitter region 107, a first metal layer 301, a gate region 302, a gate dielectric layer 303, an isolation dielectric layer 304, a second metal layer 305, an emitter region conductor 307, and an emitter region dielectric layer 308. In Figure 6 the embodiment shown, the first shielding portion 108 includes the carrier storage layer 105, that is, the bottom of the gate dielectric layer 303 is located within the carrier storage layer 105. In Figure 6In the first shielding portion 108 extends from the bottom of the first groove 401 to the second shielding portion 109, and the first shielding portion 108 is in contact with the second shielding portion 109. Figure 7 The remaining structure of the semiconductor device 100 shown is the same as that of Figure 6 the semiconductor device 100 shown, and thus will not be described in detail.

[0080] In some feasible embodiments, the first shielding portion 108 is also in contact with the emitter region dielectric layer 308.

[0081] In some feasible embodiments, the first groove 401 and the second groove 402 have the same size in the thickness direction z of the drift region 103.

[0082] In Figure 7 In the semiconductor device 100 shown, the carrier storage layer 105 serving as the first shielding portion 108 surrounds the gate dielectric layer 303 and the gate region 302. During the turn-on process of the semiconductor device 100, due to the blocking of the first shielding portion 108, the holes injected from the emitter region 107 are not likely to accumulate around the gate dielectric layer 303, which can reduce the influence of hole injection on the gate region current during the turn-on process of the semiconductor device 100 and improve the gate region control ability of the semiconductor device 100.

[0083] Figure 8 FIG. is a flowchart of a method for manufacturing a semiconductor device according to some embodiments. The manufacturing method of the semiconductor device 100 includes steps S10 - step S50.

[0084] In step S10, a collector region 101, a first sub-drift region 103a, and a second sub-drift region 103b are sequentially formed in a stacked manner. The doping types of the first sub-drift region 103a and the second sub-drift region 103b are different, obtaining a semiconductor structure as shown in Figure 11 FIG. Exemplarily, the doping type of the collector region 101 is P-type, the doping type of the first sub-drift region 103a is N-type, and the doping type of the second sub-drift region 103b is P-type.

[0085] In step S20, an emitter region 107 is formed on the side of the second sub-drift region 103b away from the collector region 101, obtaining a semiconductor structure as shown in Figure 12 FIG.

[0086] The projection of the emitter region 107 on the first reference plane overlaps with the projection of the second sub-drift region 103b on the first reference plane, and the first reference plane is parallel to the thickness direction z of the second sub-drift region 103b. The emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b with different doping types, and the first sub-emitter region 107a and the second sub-emitter region 107b are arranged along the first direction x. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type.

[0087] In step S30, the second sub-drift region 103b is etched to form a first groove 401, obtaining a semiconductor structure as Figure 13 shown.

[0088] In step S40, a first shielding portion 108 is formed at the bottom of the first groove 401, and the bottom of the first groove 401 is located on the surface or inside the first shielding portion 108, obtaining a semiconductor structure as Figure 14 shown.

[0089] In step S50, a gate dielectric layer 303 is formed on the bottom surface and the side wall surface of the first groove 401, and a gate region 302 is formed in the first groove 401, and the gate dielectric layer 303 wraps the gate region 302, obtaining the semiconductor device 100 as Figure 4 shown.

[0090] Figure 9 It is a flowchart of a preparation method for another semiconductor device according to some embodiments. The preparation method of the semiconductor device 100 includes step S10, step S60, step S70, and step S80.

[0091] In step S10, a collector region 101, a first sub-drift region 103a, and a second sub-drift region 103b are sequentially formed in a stacked manner. The first sub-drift region 103a and the second sub-drift region 103b have different doping types, obtaining a semiconductor structure as Figure 11 shown. Exemplarily, the doping type of the collector region 101 is P-type, the doping type of the first sub-drift region 103a is N-type, and the doping type of the second sub-drift region 103b is P-type.

[0092] In step S60, a first shielding portion and an emitter region 107 are formed on the side of the second sub-drift region 103b away from the collector region 101. The first shielding portion is closer to the collector region 101 than the emitter region 107, obtaining a semiconductor structure as Figure 12 shown. Exemplarily, the first shielding portion includes a carrier storage layer 105, and the doping type of the first shielding portion is N-type.

[0093] The projection of the emission region 107 on the first reference plane overlaps with the projection of the second sub-drift region 103b on the first reference plane, and the first reference plane is parallel to the thickness direction z of the second sub-drift region 103b. The emission region 107 includes a first sub-emission region 107a and a second sub-emission region 107b with different doping types, and the first sub-emission region 107a and the second sub-emission region 107b are arranged along the first direction x. Exemplarily, the doping type of the first sub-emission region 107a is P-type, and the doping type of the second sub-emission region 107b is N-type.

[0094] In step S70, the second sub-drift region 103b is etched to form a first groove 401, and the bottom of the first groove 401 is located on or inside the surface of the first shielding portion 108.

[0095] In step S80, a gate dielectric layer 303 is formed on the bottom surface and the side wall surface of the first groove 401, and a gate region 302 is formed in the first groove 401. The gate dielectric layer 303 wraps the gate region 302, obtaining the semiconductor device 100 as shown in Figure 6 or Figure 7 Figure.

[0096] Figure 10 It is a flowchart of a preparation method for another semiconductor device provided according to some embodiments. Figures 11 - 20 It is Figure 10 The semiconductor structure diagrams of each step in the preparation method. The preparation method of the semiconductor device 100 will be described below in combination with Figure 10 and Figures 11 - 20 . The preparation method of the semiconductor device 100 includes step S11, step S21, step S31, step S41, step S51, step S52, and step S61-step S65.

[0097] In step S11, a collector region 101, a buffer layer 102, a first sub-drift region 103a, and a second sub-drift region 103b are sequentially formed on one side of the substrate 306, obtaining the semiconductor structure as shown in Figure 11 Figure. In some feasible embodiments, the collector region 101, the buffer layer 102, the first sub-drift region 103a, and the second sub-drift region 103b can be sequentially formed on one side of the substrate 306 by epitaxial growth. Exemplarily, the second metal layer 305 is an N-type substrate, the doping type of the collector region 101 is P-type, the doping type of the buffer layer 102 is N-type, the doping type of the first sub-drift region 103a is N-type, and the doping type of the second sub-drift region 103b is P-type.

[0098] The doping concentration of the substrate 306 is, for example, greater than the doping concentration of the buffer layer 102, and the doping concentration of the collector region 101 is, for example, greater than the doping concentration of the second sub-drift region 103b.

[0099] In step S21, a carrier storage layer 105, an initial well region 106c, and an emitter region 107 are formed on a side of the second sub-drift region 103b away from the collector region 101.

[0100] In some feasible embodiments, the initial well region 106c has the same size as the carrier storage layer 105 in the first direction x, and finally the semiconductor device 100 as shown in Figure 4 is obtained. In this case, when the carrier storage layer 105 and the initial well region 106c are respectively formed by an ion implantation process, the same mask, that is, the same photolithographic plate, can be used, which is beneficial to saving process steps and reducing production costs.

[0101] In some feasible embodiments, a hard mask layer is formed on a side of the second sub-drift region 103b away from the collector region 101, the hard mask layer is patterned, and ion implantation is performed on a side of the second sub-drift region 103b away from the collector region 101 by an ion implantation process to form a carrier storage layer 105 with an N-type doping type, an initial well region 106c with a P-type doping type, and an emitter region 107. The emitter region 107 includes a first sub-emitter region 107a with a P-type doping type and a second sub-emitter region 107b with an N-type doping type. The semiconductor structure as shown in Figure 12 is obtained.

[0102] In step S31, the second sub-drift region 103b is etched to form a first groove 401 and a second groove 402, and the semiconductor structure as shown in Figure 13 is obtained. Exemplarily, the second groove 402 cuts off the initial well region 106c, thereby obtaining the well region 106. The well region 106 includes a first well region 106a and a second well region 106b located on both sides of the second groove 402 respectively. The first well region 106a and the second well region 106b are arranged along the first direction x, and the first direction x is the arrangement direction of the first groove 401 and the second groove 402.

[0103] In step S41, a first shielding portion 108 is formed at the bottom of the first groove 401, and a second shielding portion 109 is formed at the bottom of the second groove 402, and the semiconductor structure as shown in Figure 14 is obtained.

[0104] In some feasible embodiments, P-type impurities are selectively implanted to form a first shielding portion 108 at the bottom of the first groove 401 and a second shielding portion 109 at the bottom of the second groove 402, and the implanted impurities are activated by high-temperature annealing.

[0105] In step S51, a first initial dielectric layer 303a and an initial conductor layer 302a are sequentially formed on a side of the second sub-drift region 103b away from the collector region 101, and the semiconductor structure as shown in Figure 15The semiconductor structure shown. The first initial dielectric layer 303a is located on the surface of the second sub-drift region 103b away from the collector region 101, as well as on the bottom and sidewall surfaces of the first groove 401 and the second groove 402. The initial conductor layer 302a is located on the surface of the first initial dielectric layer 303a away from the collector region 101, as well as in the first groove 401 and the second groove 402.

[0106] In step S52, the first initial dielectric layer 303a and the initial conductor layer 302a located on the surface of the second sub-drift region 103b away from the collector region 101 are removed, obtaining the semiconductor structure as Figure 16 shown. Exemplarily, only the first initial dielectric layer 303a and the initial conductor layer 302a located in the first groove 401 and the second groove 402 are retained, obtaining the gate region 302, the gate dielectric layer 303, the emitter region conductor 307, and the emitter region dielectric layer 308.

[0107] In step S61, a second initial dielectric layer 304a is formed on the side of the second sub-drift region 103b away from the collector region 101, obtaining the semiconductor structure as Figure 17 shown.

[0108] In step S62, a selected region of the second initial dielectric layer 304a is etched to form the isolation dielectric layer 304, obtaining the semiconductor structure as Figure 18 shown. At least part of the surface of the emitter region 107 away from the collector region 101 and the surface of the emitter region conductor 307 away from the collector region 101 are exposed to form an emitter region contact area. At least part of the surface of the gate region 302 away from the collector region 101 is exposed to form a gate region contact area (not shown in the figure). Exemplarily, the emitter region contact area and the gate region contact area can be contact holes.

[0109] In step S63, a second metal layer 305 is formed on the side of the second sub-drift region 103b away from the collector region 101, obtaining the semiconductor structure as Figure 19 shown. The second metal layer 305 covers at least the surface of the isolation dielectric layer 304 away from the collector region 101. Exemplarily, processes such as sputtering are used to fill the source electrode contact area and the gate region contact area, and cover the surface of the isolation dielectric layer 304 away from the collector region 101 to form the second metal layer 305.

[0110] In a feasible embodiment, a conductor layer is formed on the side of the second sub-drift region 103b away from the collector region 101. The conductor layer covers at least the surface of the isolation dielectric layer 304 away from the collector region 101, and selective etching is performed on the conductor layer to form the second metal layer 305 and a gate region conductive layer (not shown in the figure).

[0111] In step S64, the substrate 306 is thinned until the collector region 101 is exposed, obtaining the semiconductor structure asFigure 20 The semiconductor structure shown. Exemplarily, a back thinning process is adopted to remove the substrate 306 until the surface of the collector region 101 away from the buffer layer 102 is exposed. In some feasible embodiments, the collector region 101 can also be over-etched, that is, when the substrate 306 is back-thinned to expose the surface of the collector region 101, the thinning continues to thin part of the collector region 101.

[0112] In step S65, a first metal layer 301 is formed on the side of the collector region 101 away from the buffer layer 102, obtaining the semiconductor device 100 as Figure 4 shown. Exemplarily, the first metal layer 301 is formed on the side of the collector region 101 away from the buffer layer 102 by sputtering. Exemplarily, the first metal layer 301 is formed on the side of the collector region 101 away from the drift region 103 by sputtering.

[0113] The above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A collector region; A drift region provided above the collector region, with a first groove provided on a surface of the drift region away from the collector region; An emitter region provided on a side of the drift region away from the collector region; A gate dielectric layer provided on a bottom surface and side wall surfaces of the first groove; A gate region provided in the first groove and covered by the gate dielectric layer; A first shielding portion provided at a bottom of the first groove and in contact with the gate dielectric layer; Wherein, the drift region includes a first sub-drift region and a second sub-drift region arranged in a stacked manner, the second sub-drift region is located on a side of the first sub-drift region away from the collector region, and doping types of the first sub-drift region and the second sub-drift region are different; the first shielding portion is in contact with the second sub-drift region.

2. The semiconductor device according to claim 1, wherein Further comprising: A second groove provided on a surface of the drift region away from the collector region, the second groove and the first groove are respectively located on two sides of the emitter region; An emitter region dielectric layer provided on a bottom surface and side wall surfaces of the second groove; An emitter region conductor provided in the second groove and covered by the emitter region dielectric layer; A second shielding portion provided at a bottom of the second groove and in contact with the emitter region dielectric layer; the second shielding portion is further in contact with the second sub-drift region.

3. The semiconductor device according to claim 2, wherein The first shielding portion has the same doping type as the second sub-drift region, and a doping concentration of the first shielding portion is greater than a doping concentration of the second sub-drift region.

4. The semiconductor device according to claim 3, wherein Further comprising: A carrier storage layer located between the emitter region and the second sub-drift region, and between the first groove and the second groove, the carrier storage layer is respectively in contact with the gate dielectric layer and the emitter region dielectric layer; Doping types of the carrier storage layer and the second sub-drift region are different.

5. The semiconductor device according to claim 3, wherein Along a first direction, the first shielding portion and the second shielding portion do not contact each other; the first direction is an arrangement direction of the first groove and the second groove.

6. The semiconductor device according to claim 2, wherein The first shielding portion includes: A carrier storage layer, the carrier storage layer extends from a bottom of the first groove to the second shielding portion and is in contact with the second shielding portion; Doping types of the carrier storage layer and the second sub-drift region are different.

7. The semiconductor device according to claim 6, wherein The carrier storage layer is further in contact with the emitter region dielectric layer.

8. The semiconductor device according to claim 2, wherein, The second shielding portion has the same doping type as the second sub-drift region, and a doping concentration of the second shielding portion is greater than a doping concentration of the second sub-drift region.

9. The semiconductor device according to claim 2, wherein A bottom of the gate dielectric layer extends into the first shielding portion, and the first shielding portion is in contact with a partial side surface of the gate dielectric layer; And / or, a bottom of the emitter region dielectric layer extends into the second shielding portion, and the second shielding portion is in contact with a partial side surface of the emitter region dielectric layer.

10. The semiconductor device according to claim 6, wherein A dimension of the gate region in a thickness direction of the second sub-drift region is smaller than a dimension of the emitter region conductor in the thickness direction of the second sub-drift region; Or, a dimension of the gate region in the thickness direction of the second sub-drift region is equal to a dimension of the emitter region conductor in the thickness direction of the second sub-drift region.

11. The semiconductor device according to claim 3 or 6, characterized in that, Further comprising: The first well region is located between the emitter region and the carrier storage layer, and between the first groove and the second groove; The first well region is in contact with the gate dielectric layer and the emitter region dielectric layer respectively.

12. The semiconductor device according to claim 11, wherein, It further includes: The second well region is disposed on a side of the second sub-drift region away from the collector region, and the first well region and the second well region are respectively located on two sides of the second groove.

13. The semiconductor device according to any one of claims 1-7, characterized in that, The emitter region includes: The first sub-emitter region and the second sub-emitter region, the first sub-emitter region and the second sub-emitter region are arranged along a first direction, and the first direction is the arrangement direction of the first groove and the second groove; The doping types of the first sub-emitter region and the second sub-emitter region are different.

14. The semiconductor device according to any one of claims 2-7, characterized in that, It further includes: The first metal layer is located on a side of the collector region away from the drift region; The second metal layer is located on a side of the drift region away from the collector region, and is in ohmic contact with the emitter region and the emitter conductor respectively; The isolation dielectric layer is located between the second metal layer and the second well region, and between the second metal layer and the gate region.

15. A method for manufacturing a semiconductor device, characterized in that, It includes: The collector region, the first sub-drift region and the second sub-drift region are formed in a stacked manner in sequence, and the doping types of the first sub-drift region and the second sub-drift region are different: The emitter region is formed on a side of the second sub-drift region away from the collector region; The second sub-drift region is etched to form the first groove; The first shielding portion is formed at the bottom of the first groove; The gate dielectric layer is formed on the bottom surface and the side wall surface of the first groove, and the gate region is formed in the first groove; the gate dielectric layer wraps the gate region.

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