Super-junction laterally diffused metal oxide semiconductor device and preparation method thereof

Abstract

The invention relates to a super junction laterally diffused metal oxide semiconductor device and a preparation method thereof, the super junction laterally diffused metal oxide semiconductor device comprises a substrate structure, the substrate structure is internally provided with a first well region, a source region and a drain region, the drain region and the first well region are arranged at an interval, and the source region is located in the first well region; the surface super junction structure is arranged in the substrate structure, and at least part of the surface super junction structure is located between the first well region and the drain region; the super junction drift region is arranged in the substrate structure at the bottom of the surface super junction structure; the super junction drift region comprises P-type regions and N-type regions which are alternately arranged along a first direction; the first direction is perpendicular to the thickness direction of the substrate structure. The breakdown voltage of the device can be improved, and the on-resistance of the device can be reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a superjunction laterally diffused metal oxide semiconductor device and a method for manufacturing the same. Background Art

[0002] Lateral double-diffused MOSFET (LDMOS) is a key technology for high-voltage integrated circuits (HVIC) and power integrated circuits (PIC). Its main feature is that a relatively long lightly doped drift region is added between the channel region and the drain region. The doping type of this drift region is the same as that of the drain end. By adding the drift region, it can play a role in sharing the breakdown voltage.

[0003] Superjunction LDMOS is an improved type of LDMOS, that is, the low-doped N-type drift region of traditional LDMOST is replaced by a group of alternately arranged N-type column regions and P-type column regions. In theory, if the charges between the P / N column regions can be perfectly compensated and the drift region is completely depleted, the superjunction LDMOS can obtain a higher breakdown voltage than traditional LDMOS, while the highly doped N-type column regions can obtain a very low on-resistance. Therefore, the superjunction LDMOS device can achieve a good balance between the two key parameters of breakdown voltage and on-resistance.

[0004] However, when a high voltage is applied to the drain end of a traditional superjunction LDMOS device, due to the influence of the substrate-assisted depletion effect, the breakdown voltage withstand of the superjunction LDMOS device is reduced. Summary of the Invention

[0005] Based on this, it is necessary to provide a superjunction laterally diffused metal oxide semiconductor device and a method for manufacturing the same in view of the above problems.

[0006] To achieve the above object, in a first aspect, the present application provides a superjunction laterally diffused metal oxide semiconductor device, including:

[0007] A substrate structure, in which a first well region, a source region, and a drain region are provided. The drain region and the first well region are arranged at intervals, and the source region is located within the first well region;

[0008] A surface superjunction structure, which is provided within the substrate structure, and at least a part of the surface superjunction structure is located between the first well region and the drain region;

[0009] The superjunction drift region is disposed in the substrate structure at the bottom of the surface superjunction structure; the superjunction drift region includes P-type regions and N-type regions arranged alternately in a first direction; the first direction is perpendicular to the thickness direction of the substrate structure.

[0010] In one embodiment, the surface superjunction structure includes a first doped region and a second doped region arranged in a second direction, the second doped region is adjacent to the superjunction drift region, the first doped region is located on a side of the second doped region closer to the front surface of the substrate structure, and the doping types of the first doped region, the source region, and the drain region are the same; the doping types of the second doped region and the first well region are the same;

[0011] The second direction is parallel to the thickness direction of the substrate structure.

[0012] In one embodiment, the surface superjunction structure includes a first doped region and a second doped region arranged in a second direction, the first doped region is adjacent to the superjunction drift region, the second doped region is located on a side of the first doped region closer to the front surface of the substrate structure, and the doping types of the first doped region, the source region, and the drain region are the same; the doping types of the second doped region and the first well region are the same;

[0013] The second direction is parallel to the thickness direction of the substrate structure.

[0014] In one embodiment, the doping types of the first doped region, the source region, and the drain region are the same; the doping types of the second doped region and the first well region are the same.

[0015] In one embodiment, the first doped region includes a plurality of first sub-doped regions;

[0016] Along the direction from the first well region to the drain region, the plurality of first sub-doped regions are arranged in sequence, and the doping concentration of each first sub-doped region gradually increases.

[0017] In one embodiment, the second doped region includes a plurality of second sub-doped regions;

[0018] Along the direction from the first well region to the drain region, the plurality of second sub-doped regions are arranged in sequence, and the doping concentration of each second sub-doped region gradually decreases.

[0019] In one embodiment, the surface superjunction structure includes a first doped region and a second doped region embedded in the first doped region, and the doping types of the first doped region, the source region, and the drain region are the same; the doping types of the second doped region and the first well region are the same;

[0020] Wherein, the second doping region includes a plurality of second sub-doping regions, and the plurality of second sub-doping regions are arranged at intervals along the direction from the first well region to the drain region.

[0021] In one embodiment, along the direction from the first well region to the drain region, the orthographic projection area of each of the second sub-doping regions on the substrate structure gradually decreases.

[0022] In one embodiment, the surface superjunction structure includes a second doping region and a first doping region embedded in the second doping region. The doping types of the first doping region, the source region, and the drain region are the same; the doping type of the second doping region is the same as that of the first well region;

[0023] Wherein, the first doping region includes a plurality of first sub-doping regions, and the plurality of first sub-doping regions are arranged at intervals along the direction from the first well region to the drain region.

[0024] In one embodiment, along the direction from the first well region to the drain region, the orthographic projection area of each of the first sub-doping regions on the substrate structure gradually increases.

[0025] In a second aspect, the present application provides a method for manufacturing a superjunction laterally diffused metal oxide semiconductor device, including:

[0026] Providing a substrate structure;

[0027] Forming a superjunction drift region in the substrate structure, the superjunction drift region including P-type regions and N-type regions arranged alternately along a first direction; the first direction is perpendicular to the thickness direction of the substrate structure;

[0028] Forming a first well region, a surface superjunction structure, a source region, and a drain region in the substrate structure. The drain region and the first well region are arranged at intervals, the source region is located in the first well region, at least a part of the surface superjunction structure is located between the first well region and the drain region, and the superjunction drift region is located in the substrate structure at the bottom of the surface superjunction structure.

[0029] The superjunction laterally diffused metal oxide semiconductor device and the manufacturing method thereof provided by the embodiments of the present application, by providing a surface superjunction structure in the substrate structure and a superjunction drift region in the substrate structure at the bottom of the surface superjunction structure, thus, the surface superjunction structure can weaken the substrate-assisted depletion effect, enabling the charges in the P-type regions and N-type regions to reach balance, which can not only increase the breakdown voltage but also reduce the on-resistance of the device, effectively optimizing the contradictory relationship between the breakdown voltage and the on-resistance. Description of the Drawings

[0030] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments or exemplary embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0031] Figure 1 Schematic diagram of the three-dimensional structure of a superjunction laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0032] Figure 2 Schematic diagram of the three-dimensional structure of another superjunction laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0033] Figure 3 Schematic diagram of the three-dimensional structure of still another superjunction laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0034] Figure 4 Schematic diagram of the three-dimensional structure of yet another superjunction laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0035] Figure 5 Schematic diagram of the three-dimensional structure of yet another superjunction laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0036] Figure 6 Schematic flow chart of a preparation method of a superjunction laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0037] Description of the reference numerals:

[0038] 1. Superjunction laterally diffused metal oxide semiconductor device; 11. Substrate structure; 11a. Substrate; 11b. Epitaxial layer; 111. First well region; 112. Source region; 113. Drain region; 114. Body lead-out region; 12. Surface superjunction structure; 121. First doping region; 1211. First sub-doping region A; 1212. First sub-doping region B; 1213. First sub-doping region C; 1214. First sub-doping region D; 1215. First sub-doping region E; 122. Second doping region; 1221. Second sub-doping region A; 1222. Second sub-doping region B; 1223. Second sub-doping region C; 1224. Second sub-doping region D; 1225. Second sub-doping region E; 13. Superjunction drift region; 131. P-type region; 132. N-type region; 14. Gate. Detailed implementation manners

[0039] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or part discussed below can be referred to as the second element, component, region, layer, or part; for example, the first doping type can be referred to as the second doping type, and similarly, the second doping type can be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.

[0042] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also have additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0043] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0044] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, and variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as rectangular typically has rounded or curved features at its edges and / or an implanted concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0045] In a first aspect, with reference to Figures 1 - 4 shown, embodiments of the present application provide a superjunction laterally diffused metal oxide semiconductor device 1. Taking the N-type superjunction laterally diffused metal oxide semiconductor device 1 as an example, the first doping type is P-type and the second doping type is N-type. In other embodiments, the superjunction laterally diffused metal oxide semiconductor device 1 may also be a P-type superjunction laterally diffused metal oxide semiconductor device 1, with the first doping type being N-type and the second doping type being P-type.

[0046] Specifically, the superjunction laterally diffused metal oxide semiconductor device 1 includes a substrate structure 11, in which a first well region 111, a source region 112, and a drain region 113 are provided. The drain region 113 and the first well region 111 are arranged at intervals, and the source region 112 is located within the first well region 111.

[0047] Furthermore, the superjunction laterally diffused metal oxide semiconductor device 1 further includes a surface superjunction structure 12 and a superjunction drift region 13. The surface superjunction structure 12 is provided within the substrate structure 11, and at least a part of the surface superjunction structure 12 is located between the first well region 111 and the drain region 113. The superjunction drift region 13 is provided within the substrate structure 11 at the bottom of the surface superjunction structure 12; the superjunction drift region 13 includes P-type regions 131 and N-type regions 132 that are alternately arranged along a first direction X; the first direction X is perpendicular to the thickness direction of the substrate structure 11.

[0048] It can be understood that "the superjunction drift region 13 is provided within the substrate structure 11 at the bottom of the surface superjunction structure 12" means that the superjunction drift region 13 is provided on the side of the surface superjunction structure 12 away from the front surface of the substrate structure 11.

[0049] Here, it should be noted that the superjunction drift region 13 may include one P-type region 131 and one N-type region 132, or may include multiple P-type regions 131 and multiple N-type regions 132. When the numbers of both the P-type regions 131 and the N-type regions 132 are multiple, the P-type regions 131 and the N-type regions 132 are alternately arranged in sequence along the first direction X.

[0050] In the superjunction laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application, by providing the surface superjunction structure 12 within the substrate structure 11 and providing the superjunction drift region 13 within the substrate structure 11 at the bottom of the surface superjunction structure 12, in this way, the surface superjunction structure 12 can weaken the substrate-assisted depletion effect, enabling the charges of the P-type regions 131 and the N-type regions 132 to reach balance, which can not only increase the breakdown voltage but also reduce the on-resistance of the device, effectively optimizing the contradictory relationship between the breakdown voltage and the on-resistance.

[0051] In one embodiment, the material of the substrate structure 11 may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium-silicon compound, silicon-on-insulator (SOI), or low temperature poly-silicon (LTPS), etc., or other materials known to those skilled in the art.

[0052] In one embodiment, the substrate structure 11 may include a substrate 11a and an epitaxial layer 11b disposed on the substrate 11a. The first well region 111, the source region 112, the drain region 113, the surface superjunction structure 12, and the superjunction drift region 13 are all disposed within the epitaxial layer 11b. The material of the substrate 11a may be single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, silicon-on-insulator (SOI), or low-temperature poly-silicon (LTPS), etc.

[0053] In one embodiment, referring to Figure 1 As shown, the surface superjunction structure 12 includes a first doped region 121 and a second doped region 122 arranged along the second direction Y. The second doped region 122 is adjacent to the superjunction drift region 13, and the first doped region 121 is located on the side of the second doped region 122 closer to the front surface of the substrate structure 11; the doping types of the first doped region 121, the source region 112, and the drain region 113 are the same, and the doping types of the second doped region 122 and the first well region 111 are the same. The second direction Y is parallel to the thickness direction of the substrate structure 11.

[0054] In the embodiments of the present application, the surface superjunction structure 12 is equivalent to a vertical superjunction structure, and the superjunction drift region 13 is equivalent to a horizontal superjunction structure. Thus, a horizontal and vertical double superjunction structure is arranged in the device body, that is, a horizontal and vertical double superjunction path is formed. The superjunction drift region 13 shields the influence of the substrate structure 11 on the surface superjunction structure 12, and the surface superjunction structure 12 can weaken the substrate-assisted depletion effect, thereby improving the breakdown voltage.

[0055] Further, the doping types of the first doped region 121, the source region 112, and the drain region 113 are the second doping type, and the doping types of the second doped region 122, the first well region 111, and the substrate structure 11 are the first doping type.

[0056] Thus, a surface superjunction structure 12 of "N on top and P at the bottom" is formed, which is beneficial to shielding the influence of the substrate structure 11 on the surface superjunction structure 12 and beneficial to improving the device performance.

[0057] In one embodiment, the surface superjunction structure includes a first doped region and a second doped region arranged along the second direction. The first doped region is adjacent to the superjunction drift region, the second doped region is located on the side of the first doped region closer to the front surface of the substrate structure, and the doping types of the first doped region, the source region, and the drain region are the same; the doping types of the second doped region and the first well region are the same; the second direction is parallel to the thickness direction of the substrate structure. Further, the doping types of the first doped region, the source region, and the drain region are the second doping type, and the doping types of the second doped region, the first well region, and the substrate structure are the first doping type. It should be noted that in this embodiment, Figure 1The difference in the device structure shown is that the positions of the first doping region and the second doping region are opposite.

[0058] In this way, a surface superjunction structure of "P on top and N at the bottom" is formed, which is beneficial to reducing the on-resistance of the device.

[0059] In one embodiment, referring to Figure 2 as shown, the first doping region 121 includes a plurality of first sub-doping regions, and only 5 first sub-doping regions are shown in Figure 2 . Along the direction from the first well region 111 to the drain region 113, the plurality of first sub-doping regions are arranged in sequence, and the doping concentration of each first sub-doping region gradually increases.

[0060] Specifically, referring to the embodiment shown in Figure 2 , the plurality of first sub-doping regions include a first sub-doping region A 1211, a first sub-doping region B 1212, a first sub-doping region C 1213, a first sub-doping region D 1214, and a first sub-doping region E 1215. Taking the orientation in Figure 2 as an example, from left to right, the doping concentration of each first sub-doping region gradually increases. Among two adjacent first sub-doping regions, the doping concentration of the right first sub-doping region is greater than that of the left first sub-doping region. Further, the doping concentration ranking of each first sub-doping region is as follows: first sub-doping region A 1211 < first sub-doping region B 1212 < first sub-doping region C 1213 < first sub-doping region D 1214 < first sub-doping region E 1215. In the embodiment shown in Figure 2 , the second doping region 122 is adjacent to the superjunction drift region 13, and the first doping region 121 is located on the side of the second doping region 122 close to the front surface of the substrate structure 11. In other embodiments, it may also be that the first doping region 121 is adjacent to the superjunction drift region 13, and the second doping region 122 is located on the side of the first doping region 121 close to the front surface of the substrate structure 11. It should be noted that the embodiment of the present application does not limit the change gradient of the doping concentration of the first sub-doping region.

[0061] In this way, the charge balance of the surface superjunction structure 12 can be matched with the trend of the substrate-assisted depletion effect of the LDMOS device, so that the introduced surface superjunction structure 12 can reduce the on-resistance of the device without affecting the longitudinal breakdown voltage and the lateral breakdown voltage.

[0062] It can be understood that two adjacent first sub-doping regions can be adjacent or spaced apart.

[0063] In one embodiment, referring to Figure 3 as shown, the second doping region 122 includes a plurality of second sub-doping regions, and in Figure 3Only five second sub-doped regions are shown. Along the direction from the first well region 111 to the drain region 113, a plurality of second sub-doped regions are arranged in sequence, and the doping concentration of each second sub-doped region gradually decreases.

[0064] Specifically, referring to Figure 3 In the illustrated embodiment, the plurality of second sub-doped regions include a second sub-doped region A 1221, a second sub-doped region B 1222, a second sub-doped region C 1223, a second sub-doped region D 1224, and a second sub-doped region E 1225. Taking the Figure 3 orientation in as an example, from left to right, the doping concentration of each second sub-doped region gradually decreases, that is: among two adjacent second sub-doped regions, the doping concentration of the second sub-doped region on the right is less than that of the second sub-doped region on the left. Further, the doping concentration ranking of each second sub-doped region is as follows: second sub-doped region A 1221 > second sub-doped region B 1222 > second sub-doped region C 1223 > second sub-doped region D 1224 > second sub-doped region E 1225. In the Figure 3 illustrated embodiment, the second doped region 122 is adjacent to the superjunction drift region 13, and the first doped region 121 is located on the side of the second doped region 122 close to the front surface of the substrate structure 11. In other embodiments, it may also be that the first doped region 121 is adjacent to the superjunction drift region 13, and the second doped region 122 is located on the side of the first doped region 121 close to the front surface of the substrate structure 11. It should be noted that the embodiment of the present application does not limit the change gradient of the doping concentration of the second sub-doped region.

[0065] In this way, the charge balance of the surface superjunction structure 12 can be made to match the trend of the substrate-assisted depletion effect of the LDMOS device, so that the introduced surface superjunction structure 12 can reduce the on-resistance of the device without affecting the longitudinal breakdown voltage and the lateral breakdown voltage.

[0066] It can be understood that two adjacent second sub-doped regions may be adjacent or spaced apart.

[0067] In one of the embodiments, referring to Figure 4 shown, the surface superjunction structure 12 includes a first doped region 121 and a second doped region 122 embedded in the first doped region 121; the first doped region 121, the source region 112, and the drain region 113 have the same doping type, and the second doped region 122 and the first well region 111 have the same doping type.

[0068] Among them, the second doped region 122 includes a plurality of second sub-doped regions. Along the direction from the first well region 111 to the drain region 113, the plurality of second sub-doped regions are arranged at intervals. In Figure 4 only four second sub-doped regions are shown.

[0069] Further, the doping type of the first doping region 121, the source region 112, and the drain region 113 is the second doping type, and the doping type of the second doping region 122, the first well region 111, and the substrate structure 11 is the first doping type.

[0070] Specifically, continue to refer to Figure 4 As shown, the multiple second sub-doping regions include a second sub-doping region A 1221, a second sub-doping region B 1222, a second sub-doping region C 1223, and a second sub-doping region D 1224.

[0071] In this way, during the process of fabricating the surface superjunction structure 12, for example, during the process of forming the second sub-doping region by ion implantation, there is no need to overly pursue the accuracy of ion implantation, which is beneficial to reducing the fabrication difficulty of the second doping region 122, and further reducing the device fabrication cost.

[0072] In one embodiment, along the direction from the first well region 111 to the drain region 113, the positive projection area of each second sub-doping region on the substrate structure 11 gradually decreases.

[0073] Taking Figure 4 the orientation in as an example, from left to right, the positive projection area of each second sub-doping region on the substrate structure 11 gradually decreases, that is: among two adjacent second sub-doping regions, the positive projection area of the right second sub-doping region is smaller than that of the left second sub-doping region. Further, the positive projection area sorting of each second sub-doping region is as follows: second sub-doping region A 1221 > second sub-doping region B 1222 > second sub-doping region C 1223 > second sub-doping region D 1224. It should be noted that the application embodiment does not limit the change gradient of the positive projection area of the second sub-doping region.

[0074] In this way, the charge balance of the surface superjunction structure 12 can be matched with the trend of the substrate-assisted depletion effect of the LDMOS device, so that the introduced surface superjunction structure 12 can reduce the on-resistance of the device without affecting the vertical breakdown voltage and the lateral breakdown voltage.

[0075] In one embodiment, referring to Figure 5 as shown, the surface superjunction structure 12 includes a second doping region 122 and a first doping region 121 embedded in the second doping region 122. The doping types of the first doping region 121, the source region 112, and the drain region 113 are the same; the doping types of the second doping region 122 and the first well region 111 are the same;

[0076] Among them, the first doping region 121 includes multiple first sub-doping regions. Along the direction from the first well region 111 to the drain region 113, the multiple first sub-doping regions are arranged at intervals. In Figure 5 only 4 first sub-doping regions are shown.

[0077] Furthermore, the doping types of the second doping region 122, the source region 112, the drain region 113, and the epitaxial layer 11b of the substrate structure 11 are the second doping type, and the doping types of the first doping region 121 and the first well region 111 are the first doping type.

[0078] Specifically, as Figure 5 shown, the plurality of first sub-doping regions include a first sub-doping region A 1211, a first sub-doping region B 1212, a first sub-doping region C 1213, and a first sub-doping region D 1214.

[0079] In this way, during the manufacturing process of the surface superjunction structure 12, for example, during the process of forming the first sub-doping region by ion implantation, there is no need to excessively pursue the accuracy of ion implantation, which is beneficial to reducing the manufacturing difficulty of the first doping region 121, and further reducing the manufacturing cost of the device.

[0080] In one embodiment, along the direction from the first well region 111 to the drain region 113, the orthographic projection areas of the first sub-doping regions on the substrate structure 11 gradually increase.

[0081] Taking Figure 5 the orientation in [the reference] as an example, from left to right, the orthographic projection areas of the second sub-doping regions on the substrate structure 11 gradually increase, that is: among two adjacent first sub-doping regions, the orthographic projection area of the right first sub-doping region is larger than that of the left first sub-doping region. Further, the orthographic projection area sorting of the first sub-doping regions is as follows: first sub-doping region A 1211 < first sub-doping region B 1212 < first sub-doping region C 1213 < first sub-doping region D 1214. It should be noted that the embodiment of the present application does not limit the change gradient of the orthographic projection area of the first sub-doping region.

[0082] In this way, the charge balance of the surface superjunction structure 12 can be matched with the trend of the substrate-assisted depletion effect of the LDMOS device, so that the introduced surface superjunction structure 12 can reduce the on-resistance of the device without affecting the longitudinal breakdown voltage and the lateral breakdown voltage.

[0083] In one embodiment, a body extraction region 114 is further provided in the first well region 111. A gate 14 is further provided on the front surface of the substrate structure 11. Exemplarily, the gate 14 includes a gate dielectric layer (not shown in the drawings of the present application) and a gate conductive layer (not shown in the drawings of the present application) stacked in sequence on the front surface of the substrate structure 11.

[0084] In one embodiment, the source region 112 and the drain region 113 are arranged at intervals along the third direction Z, and the third direction Z, the first direction X, and the second direction Y are perpendicular to each other in pairs.

[0085] In a second aspect, referring toFigure 6 As shown in Figure 6 , an embodiment of the present application provides a method for manufacturing a superjunction lateral diffused metal oxide semiconductor device, which specifically includes the following steps:

[0086] S100: Provide a substrate structure. Exemplarily, the substrate structure may include a substrate and an epitaxial layer disposed on the substrate.

[0087] S200: Form a superjunction drift region in the substrate structure. The superjunction drift region includes a P-type region and an N-type region alternately arranged along a first direction. The first direction is perpendicular to the thickness direction of the substrate structure. Exemplarily, the superjunction drift region can be formed in the epitaxial layer by an ion implantation process.

[0088] S300: Form a first well region, a surface superjunction structure, a source region, and a drain region in the substrate structure. The drain region and the first well region are arranged at intervals, the source region is located within the first well region, at least a part of the surface superjunction structure is located between the first well region and the drain region, and the superjunction drift region is located in the substrate structure at the bottom of the surface superjunction structure. Exemplarily, the first well region, the surface superjunction structure, the source region, and the drain region can be formed in the epitaxial layer by an ion implantation process.

[0089] It should be noted that since ion implantation will damage the substrate structure, greatly reducing the mobility and lifetime of electron-hole pairs. In addition, most of the implanted ions do not occupy lattice positions in a substitutional form. In order to activate the ions and restore the original mobility, the substrate structure must be annealed at an appropriate temperature. Annealing can repair lattice defects and also move impurity atoms to lattice sites to activate the impurities. Generally, repairing lattice defects requires about 450 - 550 °C, and activating impurities requires 900 - 1000 °C. The activation of impurities is related to time and temperature. The longer the time and the higher the temperature, the more fully the impurities are activated. Commonly used annealing methods for the substrate structure are high-temperature thermal annealing and rapid thermal annealing (RTA). In one example, a high-temperature thermal annealing process can be used for annealing treatment. Specifically, the silicon wafer is heated to 800 - 1000 °C in a high-temperature furnace and maintained for 20 - 40 min. In another example, a rapid thermal annealing process can be used for annealing treatment. The rapid thermal annealing process has a shorter annealing time compared to the high-temperature thermal annealing process, which can avoid the diffusion of doped ions caused by long-term high temperature and reduce the transient enhanced diffusion of doped ions.

[0090] The manufacturing method of the superjunction laterally diffused metal oxide semiconductor device provided by the embodiments of the present application weakens the substrate-assisted depletion effect by setting a surface superjunction structure in the substrate structure and a superjunction drift region in the substrate structure at the bottom of the surface superjunction structure, so that the charges in the P-type region and the N-type region reach equilibrium, which can not only increase the breakdown voltage, but also reduce the on-resistance of the device, effectively optimizing the contradictory relationship between the breakdown voltage and the on-resistance.

[0091] In one embodiment, S300 specifically includes the following steps:

[0092] S310: Form a first well region in the substrate structure.

[0093] S320: Form a surface superjunction structure in the substrate structure. It should be noted that, before forming the surface superjunction structure, an oxide layer can also be formed on the front surface of the substrate structure.

[0094] S330: Form a gate on the front surface of the substrate structure.

[0095] S340: Form a source region, a drain region and a body extraction region in the substrate structure.

[0096] In one embodiment, if the first doping region of the surface superjunction structure is a doping region with a gradually changing concentration, for example, the first doping region includes a plurality of first sub-doping regions. Along the direction from the source region to the drain region, the plurality of first sub-doping regions are arranged in sequence, and the doping concentration of each first sub-doping region gradually decreases. Then, in S320, on the one hand, the plurality of first sub-doping regions can be formed by a multi-step implantation process; on the other hand, it can also be formed by a single-step implantation process, that is, the implantation window corresponding to the first sub-doping region with a high doping concentration is large, and the implantation window corresponding to the first sub-doping region with a low doping concentration is small.

[0097] If the second doping region of the surface superjunction structure is a doping region with a gradually changing concentration, the formation method of the second doping region is similar to that of the first doping region, and the embodiments of the present application will not elaborate here.

[0098] It should be understood that, in the embodiments of the present application, although the steps in the flowchart of the accompanying drawings are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0099] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0100] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0101] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A superjunction laterally diffused metal oxide semiconductor device, characterized in that, Comprising: A substrate structure, in which a first well region, a source region, and a drain region are provided. The drain region and the first well region are arranged at intervals, and the source region is located within the first well region; A surface superjunction structure, which is provided within the substrate structure, and at least a part of the surface superjunction structure is located between the first well region and the drain region; A superjunction drift region, which is provided within the substrate structure at the bottom of the surface superjunction structure; the superjunction drift region includes P-type regions and N-type regions alternately arranged in a first direction; the first direction is perpendicular to the thickness direction of the substrate structure.

2. The superjunction laterally diffused metal oxide semiconductor device according to claim 1, wherein The surface superjunction structure includes a first doped region and a second doped region arranged in a second direction. The second doped region is adjacent to the superjunction drift region. The first doped region is located on the side of the second doped region close to the front surface of the substrate structure. The doping types of the first doped region, the source region, and the drain region are the same; The doping type of the second doped region is the same as that of the first well region; The second direction is parallel to the thickness direction of the substrate structure.

3. The superjunction lateral diffusion metal oxide semiconductor device according to claim 1, wherein The surface superjunction structure includes a first doped region and a second doped region arranged in a second direction. The first doped region is adjacent to the superjunction drift region. The second doped region is located on the side of the first doped region close to the front surface of the substrate structure. The doping types of the first doped region, the source region, and the drain region are the same; The doping type of the second doped region is the same as that of the first well region; The second direction is parallel to the thickness direction of the substrate structure.

4. The superjunction laterally diffused metal oxide semiconductor device according to claim 2 or 3, characterized in that, The first doped region includes a plurality of first sub-doped regions; Along the direction from the first well region to the drain region, the plurality of first sub-doped regions are arranged in sequence, and the doping concentration of each first sub-doped region gradually increases.

5. The super junction laterally diffused metal oxide semiconductor device according to claim 2 or 3, characterized in that, The second doped region includes a plurality of second sub-doped regions; Along the direction from the first well region to the drain region, the plurality of second sub-doped regions are arranged in sequence, and the doping concentration of each second sub-doped region gradually decreases.

6. The superjunction laterally diffused metal oxide semiconductor device according to claim 1, wherein The surface superjunction structure includes a first doped region and a second doped region embedded in the first doped region. The doping types of the first doped region, the source region, and the drain region are the same; the doping type of the second doped region is the same as that of the first well region; Wherein, the second doped region includes a plurality of second sub-doped regions, and the plurality of second sub-doped regions are arranged at intervals along the direction from the first well region to the drain region.

7. The superjunction laterally diffused metal oxide semiconductor device according to claim 6, wherein Along the direction from the first well region to the drain region, the positive projection area of each second sub-doped region on the substrate structure gradually decreases.

8. The superjunction laterally diffused metal oxide semiconductor device according to claim 1, characterized in that, The surface superjunction structure includes a second doped region and a first doped region embedded in the second doped region. The doping types of the first doped region, the source region, and the drain region are the same; the doping type of the second doped region is the same as that of the first well region; Wherein, the first doped region includes a plurality of first sub-doped regions, and the plurality of first sub-doped regions are arranged at intervals along the direction from the first well region to the drain region.

9. The superjunction laterally diffused metal oxide semiconductor device according to claim 8, wherein Along the direction from the first well region to the drain region, the positive projection area of each first sub-doped region on the substrate structure gradually increases.

10. A method for manufacturing a superjunction laterally diffused metal oxide semiconductor device, characterized in that, Comprising: Providing a substrate structure; Forming a superjunction drift region within the substrate structure, the superjunction drift region including P-type regions and N-type regions alternately arranged along a first direction; the first direction is perpendicular to the thickness direction of the substrate structure; Forming a first well region, a surface superjunction structure, a source region and a drain region within the substrate structure, the drain region and the first well region are arranged at intervals, the source region is located within the first well region, at least a part of the surface superjunction structure is located between the first well region and the drain region, and the superjunction drift region is located within the substrate structure at the bottom of the surface superjunction structure.

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