High-voltage ldmos and method of manufacturing the same

Abstract

This invention provides a high-voltage LDMOS and its manufacturing method. The shallow region of the substrate has two mutually spaced-apart STI regions. The first STI region includes multiple mutually spaced-apart segmented structures. The deep region of the substrate has a drift region that encloses the first STI region. A shallow inversion region is located at the bottom of the multiple mutually spaced-apart segmented structures, formed by boron ion implantation. A first N+ region is located between the first and second STI regions. A second N+ region is located on the side of the second STI region away from the first STI region. A deep well is located on the side of the second STI region away from the first STI region, enclosing a portion of the second STI region. An N-well enclosing the second N+ region is located within the deep well. A P-well is located on the side of the first STI region away from the second STI region. A field plate is located on the upper surface of the substrate. A P+ region and a third N+ region are also located within the P-well. The LDMOS of this invention employs field plate STI segmentation and boron ion implantation after STI. The high-voltage NLDMOS structure can simultaneously improve low on-resistance and high breakdown voltage performance, thus improving device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-voltage LDMOS and its manufacturing method. Background Technology

[0002] Conventional high-voltage NLDMOS devices require high withstand voltage and low on-resistance, and the drift region injection is difficult to balance. The typical process uses a polysilicon field plate and a surface-tunable inductor (STI) to bear the voltage, shifting the electric field backward from the channel to improve the device's withstand voltage performance. However, when the length of the polysilicon field plate and STI reaches a certain size, after the drift region is completely exhausted, increasing the field plate size will no longer improve the device's withstand voltage performance. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-voltage LDMOS and its manufacturing method, so as to solve the problem that the prior art cannot simultaneously improve the low on-resistance and high-voltage withstand performance of LDMOS.

[0004] To achieve the above and other related objectives, the present invention provides a high-voltage LDMOS, comprising at least:

[0005] The substrate and its shallow region are provided with first and second STI regions spaced apart from each other; the first STI region includes multiple segmented structures spaced apart from each other; the deep region of the substrate is provided with a drift region that encloses the first STI region; a shallow inversion region is provided at the bottom of the multiple segmented structures spaced apart from each other; the shallow inversion region is formed by boron ion implantation; the upper surface of the first STI region and the upper surface of the drift region are both located on the upper surface of the substrate; a portion of the second STI region is enclosed by the drift region;

[0006] A first N+ region is provided between the first and second STI regions, and a second N+ region is provided on the side of the second STI region away from the first STI region; the upper surfaces of the first N+ region and the second N+ region are both located on the upper surface of the substrate.

[0007] A deep well is provided on the side of the second STI region away from the first STI region; the deep well encloses a portion of the second STI region; and an N-well is provided in the deep well to enclose the second N+ region.

[0008] A P-well is provided on the side of the first STI region away from the second STI region; a field plate is provided on the upper surface of the substrate covering the side of the P-well, the side of the drift region, and the side of the first STI region; a P+ region and a third N+ region are also provided in the P-well.

[0009] Preferably, the first STI region comprises two segmented structures that are spaced apart from each other.

[0010] Preferably, the substrate has a buried oxygen layer; the drift region, deep trap, N trap and P trap are all located above the buried oxygen layer.

[0011] Preferably, the buried oxide layer is an N-type buried oxide layer; the drift region is an N-type drift region; and the deep trap is an N-type deep trap.

[0012] Preferably, the depth of the N-type deep trap is greater than the depth of the N-type drift region.

[0013] Preferably, the implantation energy of boron ions in the shallow inversion region is 20-30 keV, and the implantation dose is 1-e12 / cm2.

[0014] Preferably, the field plate is polycrystalline silicon, and a metal lead is used to form the gate; the first and second N+ regions are led out by metal to form the drain; and the P+ region and the third N+ region are led out by metal to form the source and base.

[0015] The present invention also provides a method for manufacturing a high-voltage LDMOS, comprising at least:

[0016] Step 1: Provide a substrate, define an active region on the substrate, and etch the substrate to form first and second STI trenches in the shallow region of the substrate to isolate the active region; wherein the first and second STI trenches are spaced apart from each other, and the first STI trench includes a plurality of segmented trenches spaced apart from each other.

[0017] Step 2: Form an inner oxide lining layer on the inner wall of the first and second STI trenches;

[0018] Step 3: Inject boron ions to form a shallow inversion layer on the sidewalls and bottom of the segmented trenches of the first STI trench; then fill the first and second STI trenches to form the first and second STI regions; the multiple segmented trenches that are spaced apart after being filled form multiple segmented structures that are spaced apart.

[0019] Step 4: Form a drift region, a deep well, an N-well, and a P-well in the substrate by ion implantation; wherein the drift region encloses the first STI region; during the ion implantation process of the drift region, the shallow inversion layers of the peripheral sidewalls of the multiple segmented structures that are spaced apart from each other are consumed, while the shallow inversion layers at the bottom periphery of the segmented structures are retained.

[0020] The upper surface of the first STI region and the upper surface of the drift region are both located on the upper surface of the substrate; a portion of the second STI region is enveloped by the drift region; the deep well is located on the side of the second STI region away from the first STI region; the deep well encloses a portion of the second STI region; the N-well is located in the deep well; the P-well is located on the side of the first STI region away from the second STI region;

[0021] Step 5: Form the first to third N+ regions and the P+ region; wherein the first N+ region is located between the first and second STI regions; the second N+ region is located on the side of the second STI region away from the first STI region and is surrounded by the N-well; the third N+ region and the P+ region are located within the P-well;

[0022] Step 6: Form a gate oxide layer on the upper surface of the substrate, the gate oxide layer covering the P-well side, the drift region side, and the first STI region side; then form a field plate on the gate oxide layer.

[0023] As described above, the high-voltage LDMOS and its manufacturing method of the present invention have the following beneficial effects: the LDMOS of the present invention adopts field plate STI segmentation and boron ion implantation after STI; the high-voltage NLDMOS structure can simultaneously improve the performance of low on-resistance and high withstand voltage, thereby improving device performance. Attached Figure Description

[0024] Figure 1 The diagram shown is a cross-sectional view of the high-voltage LDMOS of the present invention.

[0025] Figure 2 The diagram shows a comparison of the electric field distribution between a conventional LDMOS and the high-voltage LDMOS of this invention. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please see Figures 1 to 2 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] This invention provides a high-voltage LDMOS, comprising at least:

[0029] The substrate and its shallow region are provided with first and second STI regions spaced apart from each other; the first STI region includes multiple segmented structures spaced apart from each other; the deep region of the substrate is provided with a drift region that encloses the first STI region; a shallow inversion region is provided at the bottom of the multiple segmented structures spaced apart from each other; the shallow inversion region is implanted with boron ions; the upper surface of the first STI region and the upper surface of the drift region are both located on the upper surface of the substrate; a portion of the second STI region is enclosed by the drift region; a first N+ region is provided between the first and second STI regions, and the second STI... A second N+ region is provided on the side of the region away from the first STI region; the upper surfaces of both the first N+ region and the second N+ region are located on the upper surface of the substrate; a deep well is provided on the side of the second STI region away from the first STI region; the deep well encloses a portion of the second STI region; an N-well is provided in the deep well to enclose the second N+ region; a P-well is provided on the side of the first STI region away from the second STI region; a field plate is provided on the upper surface of the substrate covering one side of the P-well, one side of the drift region, and one side of the first STI region; a P+ region and a third N+ region are also provided in the P-well.

[0030] like Figure 1 As shown, Figure 1 The diagram shows a cross-sectional structure of the high-voltage LDMOS of the present invention. The shallow region of the substrate is provided with a first STI region and a second STI region 01 that are spaced apart from each other. The first STI region includes a plurality of segmented structures that are spaced apart from each other. Further, in this embodiment, the first STI region includes two segmented structures that are spaced apart from each other (i.e., it includes segmented structures 02 and 03).

[0031] like Figure 1 As shown, the deep region of the substrate is provided with a drift region that encloses the first STI region; the drift region is an N-type drift region; the bottom of the multiple mutually spaced segmented structures (two mutually spaced segmented structures 02 and 03 in this embodiment) is provided with a shallow inversion region; the shallow inversion region 09 is provided on the outer bottom of the segmented structure 02; the shallow inversion region 10 is provided on the outer bottom of the segmented structure 03.

[0032] The shallow inversion regions (09 and 10) are formed by boron ion implantation; in this embodiment, the implantation energy of boron ions in the shallow inversion regions is 20-30 keV, and the implantation dose is 1-e12 / cm2. The upper surface of the first STI region and the upper surface of the drift region are both located on the upper surface of the substrate; a portion of the second STI region 01 is enveloped by the drift region; a first N+ region 05 is provided between the first and second STI regions, and a second N+ region 04 is provided on the side of the second STI region 01 away from the first STI region; the upper surfaces of the first N+ region 05 and the second N+ region 04 are both located on the upper surface of the substrate; a deep well is provided on the side of the second STI region 01 away from the first STI region; in this embodiment, the deep well is an N-type deep well (DNW).

[0033] The deep well encloses a portion of the second STI region 01; the deep well contains an N-well that encloses the second N+ region 01; a P-well is provided on the side of the first STI region away from the second STI region 01; a field plate 08 is provided on the upper surface of the substrate, covering one side of the P-well, one side of the drift region, and one side of the first STI region; a P+ region 07 and a third N+ region 06 are also provided within the P-well. Further, in this embodiment, the field plate is made of polysilicon and formed by metal leads to form a gate; the first and second N+ regions are formed by metal leads to form drains; the P+ region 07 and the third N+ region 06 are formed by metal leads to form a source and a base (S&B).

[0034] Furthermore, in this embodiment, the substrate is provided with a buried oxide layer (NBL); the drift region, deep trap, N trap, and P trap are all located above the buried oxide layer.

[0035] like Figure 1 As shown, in this embodiment, the buried oxide layer is an N-type buried oxide layer (NBL); the drift region is an N-type drift region (N-Drift); and the deep well is an N-type deep well (DNW).

[0036] like Figure 2 As shown, Figure 2 The diagram shows a comparison of the electric field distribution of a traditional LDMOS and the high-voltage LDMOS of this invention. The high-voltage LDMOS of this invention uses a segmented STI region to segment the electric field in the drift region, reducing the highest electric field point under the original polysilicon field plate and introducing two low electric field peak points (A and B), expanding the entire electric field bearing area and improving the voltage withstand performance of the device.

[0037] The present invention also provides a method for manufacturing the high-voltage LDMOS, comprising at least:

[0038] Step 1: Provide a substrate, define an active region on the substrate, and etch the substrate to form first and second STI trenches in the shallow region of the substrate to isolate the active region; wherein the first and second STI trenches are spaced apart from each other, and the first STI trench includes a plurality of segmented trenches spaced apart from each other.

[0039] Step 2: Form an inner oxide lining layer on the inner wall of the first and second STI trenches;

[0040] Step 3: Inject boron ions to form a shallow inversion layer on the sidewalls and bottom of the segmented trenches of the first STI trench; then fill the first and second STI trenches to form the first and second STI regions; the multiple segmented trenches that are spaced apart after being filled form multiple segmented structures that are spaced apart.

[0041] Step 4: Form a drift region, a deep well, an N-well, and a P-well in the substrate by ion implantation; wherein the drift region encloses the first STI region; during the ion implantation process of the drift region, the shallow inversion layers of the peripheral sidewalls of the multiple segmented structures that are spaced apart from each other are consumed, while the shallow inversion layers at the bottom periphery of the segmented structures are retained.

[0042] The upper surface of the first STI region and the upper surface of the drift region are both located on the upper surface of the substrate; a portion of the second STI region is enveloped by the drift region; the deep well is located on the side of the second STI region away from the first STI region; the deep well encloses a portion of the second STI region; the N-well is located in the deep well; the P-well is located on the side of the first STI region away from the second STI region;

[0043] Step 5: Form the first to third N+ regions and the P+ region; wherein the first N+ region is located between the first and second STI regions; the second N+ region is located on the side of the second STI region away from the first STI region and is surrounded by the N-well; the third N+ region and the P+ region are located within the P-well;

[0044] Step 6: Form a gate oxide layer on the upper surface of the substrate, the gate oxide layer covering the P-well side, the drift region side, and the first STI region side; then form a field plate on the gate oxide layer.

[0045] In the high-voltage LDMOS manufacturing method of the present invention, the STI (Surface Inductance Tire) is etched in segments in the STI field plate region, and boron ions are implanted after the STI liner oxide layer (Liner OX) for doping. This increases the doping concentration in the drift region, reduces the on-resistance, and improves the on-state breakdown voltage. Taking a 100V breakdown voltage device as an example: the on-resistance is reduced by 1%, and the breakdown voltage is increased by 5V. The high-voltage LDMOS of the present invention can simultaneously improve both low on-resistance and high breakdown voltage performance.

[0046] In summary, the LDMOS of this invention employs field plate STI segmentation and boron ion implantation after STI; the high-voltage NLDMOS structure can simultaneously improve both low on-resistance and high withstand voltage performance, thus enhancing device performance. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage LDMOS, characterized in that, At least including: The substrate and its shallow region are provided with first and second STI regions spaced apart from each other; the first STI region includes multiple segmented structures spaced apart from each other; the deep region of the substrate is provided with a drift region that encloses the first STI region; a shallow inversion region is provided at the bottom of the multiple segmented structures spaced apart from each other; the shallow inversion region is formed by boron ion implantation; the upper surface of the first STI region and the upper surface of the drift region are both located on the upper surface of the substrate; a portion of the second STI region is enclosed by the drift region; A first N+ region is provided between the first and second STI regions, and a second N+ region is provided on the side of the second STI region away from the first STI region; the upper surfaces of the first N+ region and the second N+ region are both located on the upper surface of the substrate. A deep well is provided on the side of the second STI region away from the first STI region; the deep well encloses a portion of the second STI region; and an N-well is provided in the deep well to enclose the second N+ region. A P-well is provided on the side of the first STI region away from the second STI region; a field plate is provided on the upper surface of the substrate, covering one side of the P-well, one side of the drift region, and one side of the first STI region, and the field plate only covers a portion of the segment structure that is farthest from the first N+ region among the multiple mutually spaced segment structures; a P+ region and a third N+ region are also provided in the P-well.

2. The high-voltage LDMOS according to claim 1, characterized in that: The first STI region comprises two segmented structures that are spaced apart from each other.

3. The high-voltage LDMOS according to claim 2, characterized in that: The substrate contains a buried oxygen layer; the drift region, deep trap, N trap, and P trap are all located above the buried oxygen layer.

4. The high-voltage LDMOS according to claim 3, characterized in that: The buried oxide layer is an N-type buried oxide layer; the drift region is an N-type drift region; and the deep trap is an N-type deep trap.

5. The high-voltage LDMOS according to claim 4, characterized in that: The depth of the N-type deep trap is greater than the depth of the N-type drift region.

6. The high-voltage LDMOS according to claim 1, characterized in that: The implantation energy of boron ions in the shallow inversion region is 20-30 keV, and the implantation dose is 1-e12 / cm2.

7. The high-voltage LDMOS according to claim 1, characterized in that: The field plate is made of polycrystalline silicon and is formed by metal leads to form the gate; the first and second N+ regions are formed by metal leads to form the drain; and the P+ and third N+ regions are formed by metal leads to form the source and base.

8. The method for manufacturing a high-voltage LDMOS according to any one of claims 1 to 7, characterized in that, At least including: Step 1: Provide a substrate, define an active region on the substrate, and etch the substrate to form first and second STI trenches in the shallow region of the substrate to isolate the active region; wherein the first and second STI trenches are spaced apart from each other, and the first STI trench includes a plurality of segmented trenches spaced apart from each other. Step 2: Form an inner oxide lining layer on the inner wall of the first and second STI trenches; Step 3: Inject boron ions to form a shallow inversion layer on the sidewalls and bottom of the segmented trenches of the first STI trench; then fill the first and second STI trenches to form the first and second STI regions; the multiple segmented trenches that are spaced apart after being filled form multiple segmented structures that are spaced apart. Step 4: Form a drift region, a deep well, an N-well, and a P-well in the substrate by ion implantation; wherein the drift region encloses the first STI region; during the ion implantation process of the drift region, the shallow inversion layers of the peripheral sidewalls of the multiple segmented structures that are spaced apart from each other are consumed, while the shallow inversion layers at the bottom periphery of the segmented structures are retained. The upper surface of the first STI region and the upper surface of the drift region are both located on the upper surface of the substrate; a portion of the second STI region is enveloped by the drift region; the deep well is located on the side of the second STI region away from the first STI region; the deep well encloses a portion of the second STI region; the N-well is located in the deep well; the P-well is located on the side of the first STI region away from the second STI region; Step 5: Form the first to third N+ regions and the P+ region; wherein the first N+ region is located between the first and second STI regions; the second N+ region is located on the side of the second STI region away from the first STI region and is surrounded by the N-well; the third N+ region and the P+ region are located within the P-well; Step 6: Form a gate oxide layer on the upper surface of the substrate, the gate oxide layer covering the P-well side, the drift region side, and the first STI region side; then form a field plate on the gate oxide layer.

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