SiC IGBT device and preparation method thereof

Abstract

According to the SiC IGBT device and the preparation method thereof, heterojunction polycrystalline silicon is introduced into the front surface structure of the device, a polycrystalline silicon-SiC heterojunction is formed at the junction of the heterojunction polycrystalline silicon and a semiconductor layer, and due to the fact that the forbidden band width of the heterojunction polycrystalline silicon and the semiconductor layer is large, an energy band is bent downwards to form a large potential barrier on one side of SiC, and the energy band is bent downwards to form a large potential barrier on the other side of SiC. The potential barrier bent downwards inhibits holes from flowing out of the device through the emitter, in order to maintain electric neutrality, the holes induce electrons, the conductivity modulation effect is improved, and the conduction voltage drop is reduced. Meanwhile, when the device is turned off from turning on, the voltage of the drain electrode is further increased, the voltage is loaded to the heterojunction, the bent energy band is flattened, and the valence band of the polycrystalline silicon is higher than that of SiC, so that holes can flow into the polycrystalline silicon and finally flow out of the device through the emitter, the formation of trailing current is inhibited, and the device can be turned off quickly. That is to say, the turn-off characteristic can be improved while the forward conduction voltage drop of the device is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and relates to a SiC IGBT device and a preparation method thereof. Background Art

[0002] The performance improvement of silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) includes the compromise of various static characteristics, such as conduction characteristics and blocking characteristics. In the prior art, the forward conduction characteristics are improved by improving the conductivity modulation effect in the IGBT, for example, adding a Schottky contact on the top of the SiC IGBT so that the holes emitted from the collector accumulate in the Schottky contact part, thereby reducing the on-resistance and on-voltage drop.

[0003] Thanks to the conductivity modulation effect, SiC IGBT has a lower on-state voltage drop, but SiC IGBT plays the role of a switch in the circuit, so it is also necessary to pay attention to the switching characteristics of the device. Due to the conductivity modulation effect, there are excess carriers in the device body. When the device changes from the on state to the off state, the excess carriers in the body need to be extracted. The process of extracting excess carriers causes the device to form a tail current during the shutdown process, and the shutdown time and shutdown loss increase. When the conductivity modulation effect is enhanced, the carrier concentration in the device body is further increased, resulting in a more serious tail current phenomenon during the shutdown process. Therefore, for the improvement of the performance of SiC IGBT devices, it is necessary to consider the compromise between forward conduction characteristics and switching characteristics.

[0004] Therefore, how to provide a SiC IGBT device and a preparation method thereof to reduce the forward conduction voltage drop while improving the turn-off characteristics has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a SiC IGBT device and a preparation method thereof, so as to solve the problem that the prior art may cause the turn-off characteristics to deteriorate while reducing the forward conduction voltage drop of the SiC IGBT device.

[0007] To achieve the above object and other related objects, the present invention provides a method for preparing a SiC IGBT device, comprising the following steps:

[0008] Provide a semiconductor layer, the material of the semiconductor layer including SiC;

[0009] Form a gate trench in the semiconductor layer, the gate trench opening from the top surface of the semiconductor layer and extending downward;

[0010] Form a gate dielectric layer on the inner wall of the gate trench;

[0011] Form a heterojunction trench on one side of the gate trench, the heterojunction trench opening from the top surface of the semiconductor layer and extending downward, one side surface of the heterojunction trench exposing the gate dielectric layer, the bottom surface of the heterojunction trench being higher than the bottom surface of the gate trench;

[0012] Form a polysilicon layer, the polysilicon layer including gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, the junction between the heterojunction polysilicon and the semiconductor layer constituting a polysilicon-SiC heterojunction;

[0013] Form a protective layer on the top surface of the gate polysilicon;

[0014] Form an emitter metal layer on the semiconductor layer, the emitter metal layer covering the heterojunction polysilicon and the protective layer;

[0015] Form a collector metal layer on the back surface of the semiconductor layer.

[0016] Optionally, the semiconductor layer includes a P-type heavily doped SiC collector region layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P well arranged in sequence from bottom to top. A P-type heavily doped contact region and an N-type heavily doped contact region are provided in a preset region on the upper surface layer of the P well. The side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region. The gate trench is located on one side of the N-type heavily doped contact region and is adjacent to the N-type heavily doped contact region. The bottom surface of the gate trench is located in the charge storage layer. The heterojunction trench is located on the side of the gate trench away from the N-type heavily doped contact region, and the bottom surface of the heterojunction trench is located in the P well. The emitter metal layer further covers the P-type heavily doped contact region and the N-type heavily doped contact region.

[0017] Optionally, forming the semiconductor layer includes the following steps:

[0018] Provide an N-type heavily doped SiC substrate, and epitaxially grow the P-type heavily doped SiC collector region layer on the N-type heavily doped SiC substrate;

[0019] Epitaxially grow the N-type lightly doped SiC buffer layer on the P-type heavily doped SiC collector region layer;

[0020] The N-type doped SiC drift layer is epitaxially grown on the N-type lightly doped SiC buffer layer;

[0021] The upper surface layer of the N-type doped SiC drift layer is ion-implanted to obtain the N-type doped charge storage layer;

[0022] The upper surface layer of the N-type doped charge storage layer is ion-implanted to obtain the P-well

[0023] The preset area of the upper surface layer of the P-well is ion-implanted to obtain the P-type heavily doped contact region and the N-type heavily doped contact region;

[0024] Wherein, before forming the collector metal layer, the step of removing the N-type heavily doped SiC substrate is further included, and the collector metal layer is formed on the back surface of the P-type heavily doped SiC collector region layer.

[0025] Optionally, the doping concentration range of the P-type heavily doped SiC collector region layer is 1E18 - 1E20 cm -3 , and the thickness is less than 5 microns; the doping concentration range of the N-type lightly doped SiC buffer layer is 1E15 - 1E16 cm -3 , and the thickness is less than 3 microns; the doping concentration range of the N-type doped SiC drift layer is 1E14 - 1E15 cm -3 , and the thickness is less than 200 microns; the doping concentration range of the N-type doped charge storage layer is 1E15 - 1E16 cm -3 , and the thickness is less than 3 microns; the doping concentration range of the P-well is 1E16 - 1E18 cm -3 , and the thickness is less than 5 microns; the doping concentration range of the P-type heavily doped contact region is 1E18 - 1E20cm -3 , and the doping concentration range of the N-type heavily doped contact region is 1E18~1E20 cm -3 .

[0026] Optionally, the gate dielectric layer includes a thermal silicon oxide layer, and the thickness range of the gate dielectric layer is 40 - 60 nanometers.

[0027] Optionally, the depth of the heterojunction trench is less than 2 microns.

[0028] Optionally, the protective layer includes a silicon oxide layer.

[0029] Optionally, the emitter metal layer includes one or more of a Ni layer, a Ti layer, and an Al layer, and the collector metal layer includes one or more of a Ti layer and an Al layer.

[0030] The present invention also provides a SiC IGBT device, including:

[0031] A semiconductor layer, the material of the semiconductor layer including SiC;

[0032] A gate trench, located in the semiconductor layer, the gate trench opening from the top surface of the semiconductor layer and extending downward;

[0033] A gate dielectric layer, located on the inner wall of the gate trench;

[0034] A heterojunction trench, located on one side of the gate trench, the heterojunction trench opening from the top surface of the semiconductor layer and extending downward, one side surface of the heterojunction trench exposing the gate dielectric layer, the bottom surface of the heterojunction trench being higher than the bottom surface of the gate trench;

[0035] A polysilicon layer, including gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, the junction between the heterojunction polysilicon and the semiconductor layer forming a polysilicon-SiC heterojunction;

[0036] A protective layer, located on the top surface of the gate polysilicon;

[0037] An emitter metal layer, located on the semiconductor layer, the emitter metal layer covering the heterojunction polysilicon and the protective layer;

[0038] A collector metal layer, located on the back surface of the semiconductor layer.

[0039] Optionally, the semiconductor layer includes a P-type heavily doped SiC collector region layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P well arranged in sequence from bottom to top. A P-type heavily doped contact region and an N-type heavily doped contact region are provided in a preset area on the upper surface layer of the P well. The side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region. The gate trench is located on one side of the N-type heavily doped contact region and is adjacent to the N-type heavily doped contact region. The bottom surface of the gate trench is located in the charge storage layer. The heterojunction trench is located on the side of the gate trench away from the N-type heavily doped contact region. The bottom surface of the heterojunction trench is located in the P well. The emitter metal layer also covers the P-type heavily doped contact region and the N-type heavily doped contact region. The collector metal layer is located on the back surface of the P-type heavily doped SiC collector region layer.

[0040] As described above, the SiC IGBT device and its manufacturing method according to the present invention can achieve the improvement of the turn-off characteristics while reducing the forward conduction voltage drop of the device. Among them, a heterojunction polysilicon is introduced into the front structure of the SiC IGBT device, and a polysilicon-SiC heterojunction is formed at the junction of the heterojunction polysilicon and the semiconductor layer. Since the band gaps of both are relatively large, on the SiC side, the energy band bends downward to form a relatively large potential barrier. The downward-bent potential barrier inhibits holes from flowing out of the device through the emitter. To maintain electrical neutrality, holes induce electrons, enhancing the conductance modulation effect and reducing the conduction voltage drop. At the same time, when the device switches from on to off, the drain voltage further rises, and the voltage is applied to the heterojunction, making the bent energy band flat. Since the valence band of polysilicon is higher than that of SiC, holes can flow into the polysilicon and finally flow out of the device through the emitter, inhibiting the formation of the tail current, and enabling the device to turn off quickly. Description of the Drawings

[0041] Figure 1 It shows a process flow chart of the manufacturing method of the SiC IGBT device according to the present invention.

[0042] Figure 2 It shows a schematic diagram of the structure obtained after successively epitaxially growing a P-type heavily doped SiC collector region layer, an N-type lightly doped SiC buffer layer, and an N-type doped SiC drift layer on an N-type heavily doped SiC substrate in the manufacturing method of the SiC IGBT device according to the present invention.

[0043] Figure 3 It shows a schematic diagram of the structure obtained after forming an N-type doped charge storage layer on the upper surface layer of the N-type doped SiC drift layer in the manufacturing method of the SiC IGBT device according to the present invention.

[0044] Figure 4 It shows a schematic diagram of the structure obtained after forming a P well on the upper surface layer of the N-type doped charge storage layer in the manufacturing method of the SiC IGBT device according to the present invention.

[0045] Figure 5 It shows a schematic diagram of the structure obtained after forming a P-type heavily doped contact region on the upper surface layer of the P well in the manufacturing method of the SiC IGBT device according to the present invention.

[0046] Figure 6 It shows a schematic diagram of the structure obtained after forming an N-type heavily doped contact region on the upper surface layer of the P well in the manufacturing method of the SiC IGBT device according to the present invention.

[0047] Figure 7 It shows a schematic diagram of the structure obtained after forming a gate trench in the semiconductor layer in the manufacturing method of the SiC IGBT device according to the present invention.

[0048] Figure 8Schematic diagram of the structure obtained after forming a gate dielectric layer on the inner wall of the gate trench in the manufacturing method of the SiC IGBT device of the present invention.

[0049] Figure 9 Schematic diagram of the structure obtained after forming a heterojunction trench on one side of the gate trench in the manufacturing method of the SiC IGBT device of the present invention.

[0050] Figure 10 Schematic diagram of the structure obtained after forming a polysilicon layer in the manufacturing method of the SiC IGBT device of the present invention.

[0051] Figure 11 Schematic diagram of the energy band of the polysilicon-SiC heterojunction.

[0052] Figure 12 Schematic diagram of the structure obtained after forming a protective layer on the top surface of the gate polysilicon in the manufacturing method of the SiC IGBT device of the present invention.

[0053] Figure 13 Schematic diagram of the structure obtained after forming an emitter metal layer on the semiconductor layer in the manufacturing method of the SiC IGBT device of the present invention.

[0054] Figure 14 Schematic diagram of the structure obtained after forming a collector metal layer on the back surface of the semiconductor layer in the manufacturing method of the SiC IGBT device of the present invention.

[0055] Description of reference numerals

[0056] Steps S1 to S8

[0057] 1 Semiconductor layer

[0058] 101 P-type heavily doped SiC collector region layer

[0059] 102 N-type lightly doped SiC buffer layer

[0060] 103 N-type doped SiC drift layer

[0061] 104 N-type doped charge storage layer

[0062] 105 P-well

[0063] 106 P-type heavily doped contact region

[0064] 107 N-type heavily doped contact region

[0065] 2 Gate trench

[0066] 3 N-type heavily doped SiC substrate

[0067] 4 Gate dielectric layer

[0068] 5 Heterojunction trench

[0069] 6 Gate polysilicon

[0070] 7 Heterojunction polysilicon

[0071] 8 Protective layer

[0072] 9 Emitter metal layer

[0073] 10 Collector metal layer Detailed implementation manners

[0074] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] Please refer to Figures 1 to 14 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components during actual implementation. The types, quantities, and proportions of the components during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0076] Embodiment 1

[0077] The present invention provides a preparation method for a SiC IGBT device. Please refer to Figure 1 , which shows the process flow chart of this method, including the following steps:

[0078] S1: Provide a semiconductor layer, and the material of the semiconductor layer includes SiC;

[0079] S2: Form a gate trench in the semiconductor layer, and the gate trench opens from the top surface of the semiconductor layer and extends downward;

[0080] S3: Form a gate dielectric layer on the inner wall of the gate trench;

[0081] S4: Form a heterojunction trench on one side of the gate trench. The heterojunction trench opens from the top surface of the semiconductor layer and extends downward. One side surface of the heterojunction trench exposes the gate dielectric layer, and the bottom surface of the heterojunction trench is higher than the bottom surface of the gate trench;

[0082] S5: Form a polysilicon layer, where the polysilicon layer includes gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, and the junction between the heterojunction polysilicon and the semiconductor layer forms a polysilicon-SiC heterojunction;

[0083] S6: Form a protective layer on the top surface of the gate polysilicon;

[0084] S7: Form an emitter metal layer on the semiconductor layer, where the emitter metal layer covers the heterojunction polysilicon and the protective layer;

[0085] S8: Form a collector metal layer on the back surface of the semiconductor layer.

[0086] The following will specifically describe the implementation manners of the above steps in conjunction with the structure diagrams.

[0087] First, please refer to Figures 2 to 7 , and perform the step S1: Provide a semiconductor layer 1, where the material of the semiconductor layer 1 includes SiC.

[0088] As an example, the semiconductor layer 1 includes a P-type heavily doped SiC collector region layer 101, an N-type lightly doped SiC buffer layer 102, an N-type doped SiC drift layer 103, an N-type doped charge storage layer 104, and a P well 105 arranged in sequence from bottom to top. A P-type heavily doped contact region 106 and an N-type heavily doped contact region 107 are provided in a preset area on the upper surface layer of the P well 105. The side surface of the P-type heavily doped contact region 106 is adjacent to the side surface of the N-type heavily doped contact region 107. The gate trench 2 is located on one side of the N-type heavily doped contact region 107 and is adjacent to the N-type heavily doped contact region 107. The bottom surface of the gate trench 2 is located in the charge storage layer 104.

[0089] It should be noted that in the above statement, "heavily doped", "doped", and "lightly doped" are relative concepts. For ion doping of the same conduction type, the doping concentration magnitudes satisfy "heavily doped" > "doped" > "lightly doped", and the specific doping concentration can be adjusted according to the performance requirements of the actual device, and the protection scope of the present invention should not be unduly limited herein.

[0090] In some embodiments, the doping concentration range of the P-type heavily doped SiC collector region layer 101 is 1E18 - 1E20 cm -3 , and the thickness is less than 5 microns; the doping concentration range of the N-type lightly doped SiC buffer layer 102 is 1E15 - 1E16 cm -3 , and the thickness is less than 3 microns; the doping concentration range of the N-type doped SiC drift layer 103 is 1E14 - 1E15 cm -3, with a thickness less than 200 microns; the doping concentration of the N-type doped charge storage layer 104 is higher than that of the N-type doped SiC drift layer 103, and the doping concentration range of the N-type doped charge storage layer 104 is 1E15 - 1E16 cm -3 , with a thickness less than 3 microns; the doping concentration range of the P-well 105 is 1E16 - 1E18 cm -3 , with a thickness less than 5 microns; the doping concentration range of the P-type heavily doped contact region 106 is 1E18 - 1E20 cm -3 , the doping concentration range of the N-type heavily doped contact region 107 is 1E18 - 1E20 cm -3 .

[0091] In some embodiments, forming the semiconductor layer 1 includes the following steps:

[0092] (1) As Figure 2 shown, provide an N-type heavily doped SiC substrate 3, epitaxially grow the P-type heavily doped SiC collector region layer 101 on the N-type heavily doped SiC substrate 3, epitaxially grow the N-type lightly doped SiC buffer layer 102 on the P-type heavily doped SiC collector region layer 101, and epitaxially grow the N-type doped SiC drift layer 103 on the N-type lightly doped SiC buffer layer 102;

[0093] (2) As Figure 3 shown, perform N-type ion (including but not limited to phosphorus ions) implantation on the upper surface layer of the N-type doped SiC drift layer 103 to obtain the N-type doped charge storage layer 104;

[0094] (3) As Figure 4 shown, perform P-type ion (including but not limited to boron ions) implantation on the upper surface layer of the N-type doped charge storage layer 104 to obtain the P-well 105;

[0095] (4) As Figure 5 shown, perform P-type ion implantation on a preset region of the upper surface layer of the P-well 105 to obtain the P-type heavily doped contact region 106;

[0096] (5) As Figure 6 shown, perform N-type ion implantation on a preset region of the upper surface layer of the P-well 105 to obtain the N-type heavily doped contact region 107.

[0097] Thus far, the semiconductor layer 1 located on the N-type heavily doped SiC substrate 3 is fabricated, wherein the N-type heavily doped SiC substrate 3 will be removed before the subsequent formation of the collector metal layer, such that the collector metal layer is formed on the back surface of the P-type heavily doped SiC collector region layer 3.

[0098] Please refer to again Figure 7 and perform the step S2: Form a gate trench 2 in the semiconductor layer 1 by dry etching, wet etching or other suitable methods. The gate trench 2 opens from the top surface of the semiconductor layer 1 on the side of the N-type heavily doped contact region 107 away from the P-type heavily doped contact region 106 and extends downward into the charge storage layer 104.

[0099] Specifically, the width of the gate trench 2 and the specific position of the bottom surface of the gate trench 2 in the charge storage layer 104 can be adjusted according to the electrical requirements of the actual device, and the protection scope of the present invention should not be overly limited here.

[0100] Please refer to again Figure 8 and perform the step S3: Form a gate dielectric layer 4 on the inner wall of the gate trench 2.

[0101] As an example, a thermal oxide layer is formed on the inner wall of the gate trench 2 by thermal oxidation to serve as the gate dielectric layer 4, and the thickness range of the gate dielectric layer 4 is 40-60 nanometers.

[0102] Please refer to again Figure 9 and perform the step S4: Form a heterojunction trench 5 on the side of the gate trench 2 away from the N-type heavily doped contact region 107. The heterojunction trench 5 opens from the top surface of the semiconductor layer 1 and extends downward. One side surface of the heterojunction trench 5 exposes the gate dielectric layer 4, and the bottom surface of the heterojunction trench 5 is higher than the bottom surface of the gate trench 2.

[0103] As an example, the bottom surface of the heterojunction trench 5 is located in the P-well 105, and the depth of the heterojunction trench 5 is less than 2 micrometers.

[0104] Please refer to again Figure 10 and perform the step S5: Form a polysilicon layer, which includes a gate polysilicon 6 in the gate trench 2 and a heterojunction polysilicon 7 in the heterojunction trench 5. The junction between the heterojunction polysilicon 7 and the semiconductor layer 1 forms a polysilicon-SiC heterojunction;.

[0105] Specifically, the purpose of introducing the heterojunction polysilicon 7 in the front structure of the SiC IGBT device in the present invention is to form a polysilicon-SiC heterojunction. Please refer to Figure 11 which shows the energy band diagram of the polysilicon-SiC heterojunction. Since the band gaps of polysilicon and SiC are relatively large, on the SiC side, the energy band bends downward to form a relatively large potential barrier, as Figure 11As shown by the solid line, the downward-bent barrier inhibits holes from flowing out of the device through the emitter. To maintain electrical neutrality, holes induce electrons, enhancing the conductivity modulation effect and reducing the on-state voltage drop. Meanwhile, when the device switches from on to off, the drain voltage further rises, and the voltage is applied across the heterojunction, flattening the bent energy band, as Figure 11 shown by the dashed line. Since the valence band of polysilicon is higher than that of SiC, holes can flow into the polysilicon and finally flow out of the device through the emitter, inhibiting the formation of the tail current and enabling the device to turn off quickly. That is, adopting the solution of the present invention can achieve the improvement of the turn-off characteristics while reducing the forward on-state voltage drop of the device. The subsequent steps of the preparation method of the SiC IGBT device of the present invention will be described in detail below.

[0106] Please refer to Figure 12 , and perform the step S6: form a protective layer 8 on the top surface of the gate polysilicon 6.

[0107] As an example, the protective layer 8 can be selected from a silicon oxide layer or other suitable material layers, and its thickness can be set according to actual needs, which is not specifically limited in the present invention.

[0108] As an example, a silicon oxide layer can be deposited on the semiconductor layer 1 first, and then lithography and etching are performed to pattern the silicon oxide layer to obtain the protective layer 8, protecting the gate polysilicon 6.

[0109] Please refer to Figure 13 , and perform the step S7: form an emitter metal layer 9 on the semiconductor layer 1 by sputtering or other suitable methods, and the emitter metal layer 9 covers the heterojunction polysilicon 7 and the protective layer 8.

[0110] Specifically, the emitter metal layer 9 also covers the P-type heavily doped contact region 106 and the N-type heavily doped contact region 107 to be electrically connected to the P-type heavily doped contact region 106 and the N-type heavily doped contact region 107.

[0111] As an example, the emitter metal layer 9 includes but is not limited to one or more of a Ni layer, a Ti layer, and an Al layer.

[0112] Please refer to Figure 14 , and perform the step S8: form a collector metal layer 10 on the back surface of the semiconductor layer 1 by sputtering or other suitable methods.

[0113] As an example, before forming the collector metal layer 10, the N-type heavily doped SiC substrate 3 on the back surface of the semiconductor layer 1 is removed by chemical mechanical polishing or other suitable methods, so that the collector metal layer 10 is formed on the back surface of the P-type heavily doped SiC collector region layer 101.

[0114] As an example, the collector metal layer includes, but is not limited to, one or more of a Ti layer and an Al layer.

[0115] Thus, a SiC IGBT device is fabricated. The preparation method of the SiC IGBT device of the present invention introduces a polysilicon-SiC heterojunction on the front side of the device by a simple method, which can reduce the forward conduction voltage drop of the device while improving the turn-off characteristics.

[0116] Embodiment 2

[0117] The present invention also provides a SiC IGBT device, which can be fabricated by using the preparation method of the SiC IGBT device described in Embodiment 1 or other suitable methods.

[0118] As an example, please refer to Figure 14 , which shows a cross-sectional structure schematic diagram of the SiC IGBT device in some embodiments, including a semiconductor layer 1, a gate trench 2, a gate dielectric layer 4, a heterojunction trench 5, a polysilicon layer, a protective layer 8, an emitter metal layer 9, and a collector metal layer 10. Among them, the material of the semiconductor layer 1 includes SiC; the gate trench 2 is located in the semiconductor layer 1, and the gate trench 2 opens from the top surface of the semiconductor layer 1 and extends downward; the gate dielectric layer 4 is located on the inner wall of the gate trench 2; the heterojunction trench 5 is located on one side of the gate trench 2, the heterojunction trench 5 opens from the top surface of the semiconductor layer 1 and extends downward, one side surface of the heterojunction trench 5 exposes the gate dielectric layer 4, and the bottom surface of the heterojunction trench 5 is higher than the bottom surface of the gate trench 2; the polysilicon layer includes gate polysilicon 6 located in the gate trench 2 and heterojunction polysilicon 7 located in the heterojunction trench 5, and the junction between the heterojunction polysilicon 7 and the semiconductor layer 1 forms a polysilicon-SiC heterojunction; the protective layer 8 is located on the top surface of the gate polysilicon 6; the emitter metal layer 9 is located on the semiconductor layer 1 and covers the heterojunction polysilicon 7 and the protective layer 8; the collector metal layer 10 is located on the back surface of the semiconductor layer 1.

[0119] As an example, the semiconductor layer 1 includes a P-type heavily doped SiC collector region layer 101, an N-type lightly doped SiC buffer layer 102, an N-type doped SiC drift layer 103, an N-type doped charge storage layer 104, and a P well 105, which are sequentially arranged from bottom to top. A preset region on the upper surface of the P well 105 is provided with a P-type heavily doped contact region 106 and an N-type heavily doped contact region 107. The side surface of the P-type heavily doped contact region 106 is adjacent to the side surface of the N-type heavily doped contact region 107. The gate trench 2 is located on one side of the N-type heavily doped contact region 107 and is adjacent to the N-type heavily doped contact region 107. The bottom surface of the gate trench 2 is located in the charge storage layer 104. The heterojunction trench 5 is located on the side of the gate trench 2 away from the N-type heavily doped contact region 107. The bottom surface of the heterojunction trench 5 is located in the P well 105. The emitter metal layer 9 also covers the P-type heavily doped contact region 106 and the N-type heavily doped contact region 107. The collector metal layer 10 is located on the back surface of the P-type heavily doped SiC collector region layer 3.

[0120] Due to the introduction of a polysilicon-SiC heterojunction on the front side of the SiC IGBT device of the present invention, it not only has a lower forward conduction voltage drop of the device but also has better turn-off characteristics.

[0121] In summary, the SiC IGBT device and its manufacturing method of the present invention can achieve the improvement of the turn-off characteristics while reducing the forward conduction voltage drop of the device. Among them, a heterojunction polysilicon is introduced into the front structure of the SiC IGBT device. The junction between the heterojunction polysilicon and the semiconductor layer forms a polysilicon-SiC heterojunction. Due to the relatively large band gaps of the two, on the SiC side, the energy band bends downward to form a relatively large potential barrier. The downward-bent potential barrier inhibits holes from flowing out of the device through the emitter. To maintain electrical neutrality, holes induce electrons, enhancing the conductance modulation effect and reducing the conduction voltage drop. At the same time, when the device switches from on to off, the drain voltage further rises, and the voltage is applied to the heterojunction. The bent energy band becomes flat. Since the valence band of polysilicon is higher than that of SiC, holes can flow into the polysilicon and finally flow out of the device through the emitter, inhibiting the formation of the tail current, and the device can be quickly turned off. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0122] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a SiC IGBT device, characterized in that, It includes the following steps: Provide a semiconductor layer, the material of the semiconductor layer includes SiC; Form a gate trench in the semiconductor layer, the gate trench opens from the top surface of the semiconductor layer and extends downward; Form a gate dielectric layer on the inner wall of the gate trench; Form a heterojunction trench on one side of the gate trench, the heterojunction trench opens from the top surface of the semiconductor layer and extends downward, one side surface of the heterojunction trench exposes the gate dielectric layer, and the bottom surface of the heterojunction trench is higher than the bottom surface of the gate trench; Form a polysilicon layer, the polysilicon layer includes gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, and the junction between the heterojunction polysilicon and the semiconductor layer constitutes a polysilicon-SiC heterojunction; Form a protective layer on the top surface of the gate polysilicon; Form an emitter metal layer on the semiconductor layer, the emitter metal layer covers the heterojunction polysilicon and the protective layer; Form a collector metal layer on the back surface of the semiconductor layer.

2. The manufacturing method of the SiC IGBT device according to claim 1, characterized in that: The semiconductor layer includes a P-type heavily doped SiC collector region layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P well arranged in sequence from bottom to top. A P-type heavily doped contact region and an N-type heavily doped contact region are provided in a preset area on the upper surface layer of the P well. The side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region. The gate trench is located on one side of the N-type heavily doped contact region and is adjacent to the N-type heavily doped contact region. The bottom surface of the gate trench is located in the charge storage layer. The heterojunction trench is located on the side of the gate trench away from the N-type heavily doped contact region, and the bottom surface of the heterojunction trench is located in the P well. The emitter metal layer also covers the P-type heavily doped contact region and the N-type heavily doped contact region.

3. The manufacturing method of the SiC IGBT device according to claim 2, characterized in that, Forming the semiconductor layer includes the following steps: Provide an N-type heavily doped SiC substrate, and epitaxially grow the P-type heavily doped SiC collector region layer on the N-type heavily doped SiC substrate; Epitaxially grow the N-type lightly doped SiC buffer layer on the P-type heavily doped SiC collector region layer; Epitaxially grow the N-type doped SiC drift layer on the N-type lightly doped SiC buffer layer; Perform ion implantation on the upper surface layer of the N-type doped SiC drift layer to obtain the N-type doped charge storage layer; perform ion implantation on the upper surface layer of the N-type doped charge storage layer to obtain the P well Perform ion implantation on a preset area on the upper surface layer of the P well to obtain the P-type heavily doped contact region and the N-type heavily doped contact region; Wherein, before forming the collector metal layer, it further includes the step of removing the N-type heavily doped SiC substrate, and the collector metal layer is formed on the back surface of the P-type heavily doped SiC collector region layer.

4. The manufacturing method of the SiC IGBT device according to claim 2, wherein: The doping concentration range of the P-type heavily doped SiC collector region layer is 1E18 - 1E20 cm -3 , and the thickness is less than 5 microns; the doping concentration range of the N-type lightly doped SiC buffer layer is 1E15 - 1E16 cm -3 , and the thickness is less than 3 microns; the doping concentration range of the N-type doped SiC drift layer is 1E14 - 1E15 cm -3 , and the thickness is less than 200 microns; the doping concentration range of the N-type doped charge storage layer is 1E15 - 1E16 cm -3 , and the thickness is less than 3 microns; the doping concentration range of the P-well is 1E16 - 1E18 cm -3 , and the thickness is less than 5 microns; the doping concentration range of the P-type heavily doped contact region is 1E18 - 1E20 cm -3 , and the doping concentration range of the N-type heavily doped contact region is 1E18 - 1E20 cm -3 .

5. The manufacturing method of the SiC IGBT device according to claim 1, characterized in that: The gate dielectric layer includes a thermal silicon oxide layer, and the thickness range of the gate dielectric layer is 40 - 60 nanometers.

6. The manufacturing method of the SiC IGBT device according to claim 1, characterized in that: The depth of the heterojunction trench is less than 2 micrometers.

7. The manufacturing method of the SiC IGBT device according to claim 1, characterized in that: The protective layer includes a silicon oxide layer.

8. The manufacturing method of the SiC IGBT device according to claim 1, characterized in that: The emitter metal layer includes one or more of a Ni layer, a Ti layer, and an Al layer, and the collector metal layer includes one or more of a Ti layer and an Al layer.

9. A SiC IGBT device, characterized in that, Comprising: A semiconductor layer, the material of the semiconductor layer including SiC; A gate trench, located in the semiconductor layer, the gate trench opening from the top surface of the semiconductor layer and extending downward; A gate dielectric layer, located on the inner wall of the gate trench; A heterojunction trench, located on one side of the gate trench, the heterojunction trench opening from the top surface of the semiconductor layer and extending downward, one side surface of the heterojunction trench exposing the gate dielectric layer, and the bottom surface of the heterojunction trench being higher than the bottom surface of the gate trench; A polysilicon layer, including gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, the junction between the heterojunction polysilicon and the semiconductor layer forming a polysilicon-SiC heterojunction; A protective layer, located on the top surface of the gate polysilicon; An emitter metal layer, located on the semiconductor layer, the emitter metal layer covering the heterojunction polysilicon and the protective layer; A collector metal layer, located on the back surface of the semiconductor layer.

10. The SiC IGBT device according to claim 9, wherein: The semiconductor layer includes a P-type heavily doped SiC collector region layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P well arranged in sequence from bottom to top. A P-type heavily doped contact region and an N-type heavily doped contact region are provided in a preset area on the upper surface layer of the P well. The side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region. The gate trench is located on one side of the N-type heavily doped contact region and is adjacent to the N-type heavily doped contact region. The bottom surface of the gate trench is located in the charge storage layer. The heterojunction trench is located on the side of the gate trench away from the N-type heavily doped contact region, and the bottom surface of the heterojunction trench is located in the P well. The emitter metal layer also covers the P-type heavily doped contact region and the N-type heavily doped contact region. The collector metal layer is located on the back surface of the P-type heavily doped SiC collector region layer.

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