Phototransistor for simulating neural synapse, preparation method and multispectral weight updating circuit

Abstract

The invention discloses a phototransistor for simulating neural synapses, a preparation method and a multispectral weight updating circuit, and belongs to the technical field of photoelectric synapse devices. The photoelectric transistor is composed of a gate bottom electrode, a gate dielectric layer, a metal oxide film layer, a quantum dot-PMMA blending layer and source and drain electrodes, an active layer of the device is reconstructed into an oxide / quantum dot / PMMA heterojunction system, the light response of the device is enhanced through the programmable photoelectric characteristic of quantum dots, and the spectral response range of the device is widened; based on a heterojunction charge capture effect and a double-electric-layer ion-electron coupling effect, the long-term synaptic plasticity of the device is greatly improved, so that the device can accurately simulate various memory behaviors related to biomimetic synapses, including generation of current after excitatory synapses, conversion from short-term plasticity to long-term plasticity and the like; a multispectral weight updating circuit built based on the device can realize dynamic weight regulation and control by using all-optical signals, simulates a self-organization reconstruction process of a neural circuit in a human neural network, and has important application prospects in the fields of bionic visual perception and neural morphology calculation.

Description

Technical Field

[0001] The present invention belongs to the technical field of optoelectronic synaptic devices, and specifically relates to a phototransistor for simulating neural synapses. The specific preparation method of this phototransistor is disclosed, and based on this, an all-optical regulated multi-spectral weight update circuit is built to achieve symmetric long-term plasticity (LTP / LTD) of synaptic weights. Background Art

[0002] In recent years, neuromorphic computing has shown great potential in simulating the efficient parallel information processing and low-power consumption characteristics of the human brain, and has become an important research direction for breaking through the bottleneck of the traditional von Neumann architecture. Developing new synaptic biomimetic devices, such as memristors, phase change memories, ferroelectric transistors, etc., is one of the hardware ways to achieve the memory storage of the human brain.

[0003] The regulation of synaptic plasticity is the key to simulating the functions of biological synapses. Synaptic plasticity mainly includes short-term synaptic plasticity (STP) and long-term synaptic plasticity (LTP), which are considered to be the biological basis at the cellular level of learning and memory activities. LTP plays a very important role in the memory function and neural connections of the brain. It is extremely necessary to prepare corresponding device structures to simulate the long-term plasticity of synapses. Compared with traditional memristors and phase change memories, synaptic transistors have the characteristics of low power consumption, high integration, and similarity to biological neural architectures. Moreover, due to their three-terminal structure, transistors have obvious advantages in that signals can be synchronously transmitted during the learning process.

[0004] The phototransistor can dynamically adjust the channel conductance through photo-generated carriers, and its response characteristics have an inherent similarity with the weight modulation behavior of biological synapses. For example, optical pulses can simulate the release of neurotransmitters, inducing STP or LTP of the device conductance, thereby realizing light-controlled synaptic plasticity. Among them, metal oxide semiconductor (such as IGZO) thin film transistors have the possibility of becoming photosensitive neural synaptic devices due to their high carrier mobility, low preparation temperature, and excellent optoelectronic response characteristics. However, problems such as the relatively large bandgap of the oxide material itself, the absorption wavelength of the corresponding light generally concentrated in the ultraviolet band, low intrinsic light absorption efficiency, and limited response speed limit its application in high-sensitivity synaptic devices.

[0005] To make up for the deficiencies of oxide semiconductors themselves, those skilled in the art have tried to address the corresponding problems by constructing heterojunctions with quantum dots (QDs) that have a wide absorption spectral range in combination with oxide semiconductor materials to expand the light absorption range of a single oxide. Because quantum dots have size-dependent tunable bandgaps, they can break through the wide bandgap limitations of oxide semiconductors (such as IZO, IGZO, etc.), are expected to broaden the light response range of devices to the visible-near infrared spectrum, and the high absorption coefficient and multi-exciton effect of quantum dots can significantly enhance the photocurrent response of phototransistors. Constructing a quantum dot / oxide semiconductor heterojunction can effectively suppress the recombination of photo-generated electrons and holes and improve the separation efficiency of photo-generated carriers.

[0006] Chinese Patent CN 111554770 A discloses a three-terminal thin-film transistor, which is a thin-film transistor channel composed of a traditional metal oxide compounded with a quantum dot material. The quantum dots transfer the generated photo-generated carriers to the oxide part to play a role, enabling the thin-film transistor to generate an obvious postsynaptic current not only in response to ultraviolet light but even to visible light stimulation, broadening the response spectrum of the photosensitive synapse. Moreover, after the light is removed, the current value slowly drops to the initial value, that is, it has a persistent photoconductivity effect.

[0007] However, although this device has achieved memory behaviors related to biological bionic synapses such as long-range plasticity and short-range plasticity, this patent does not mention its ability to update weights using all-optical signals to simulate the reorganization of the human neural network to form new neural circuits, thereby affecting the relevant content of behavior and cognitive function processes. Because to achieve dynamic simulation of LTP / LTD, it is necessary to comprehensively regulate it in combination with its working mechanism and the key characteristics of biological synaptic plasticity. Specifically, the photosensitive transistor needs to integrate an optical / electrical dual-regulation module to achieve the temporal coupling of presynaptic (optical input) and postsynaptic (electrical output) signals, reproduce the dynamic characteristics of spike-timing-dependent plasticity (STDP), and the duration, input specificity, and non-linear response characteristics of long-term potentiation / depression of the photosensitive synaptic transistor should conform to biological benchmarks. Therefore, simulating the dynamic synaptic plasticity of long-term potentiation (LTP) and long-term depression (LTD) remains one of the core challenges in the hardware implementation of artificial neural networks, and its complexity is reflected in multiple aspects such as biological mechanism reproduction, hardware material selection, and algorithm adaptation.

[0008] In addition, existing photosensitive synaptic transistors mainly rely on electrical pulse regulation alone, or optoelectronic combination to change synaptic weights. There are few circuit platforms that use all-optical means to update weights. If a bionic synaptic device with all-optical regulation for multi-spectral perception can be constructed and a circuit platform that uses all-optical means to update weights can be successfully built, it will have broad application prospects in the fields of bionic vision systems and neuromorphic computing. Summary of the Invention

[0009] In view of the above problems, the present invention aims to provide a photoelectric transistor simulating a neural synapse and discloses its preparation method. After reconstructing the active layer of the device into an oxide / quantum dot / PMMA heterojunction system, the light response of the device is enhanced, the spectral response range of the device is broadened, and the long-term plasticity of the device is greatly improved. By applying light signals of different wavelengths to the device, the synaptic bionic function can be simulated, the excitatory postsynaptic current (EPSC) of a neural synapse can be realized, and the transformation from short-term synaptic plasticity (STP) to long-term synaptic plasticity (LTP) can be achieved; on this basis, the multi-spectral weight update circuit built can realize dynamic weight regulation using all-optical signals and can simulate the self-organizing reconstruction process of neural circuits in the human neural network.

[0010] To achieve the above object, the technical solution adopted by the present invention is as follows: A photoelectric transistor simulating a neural synapse, characterized in that it includes a gate bottom electrode, a gate dielectric layer, a metal oxide film layer, a quantum dot-PMMA blend layer, and source and drain electrodes arranged in sequence from bottom to top; the spectral response range of the photoelectric transistor is 200nm to 850nm, and it exhibits a wavelength-dependent postsynaptic current response characteristic. Different band light pulse stimulations can trigger different EPSC amplitudes, and after the light stimulation is removed, the EPSC decays over time. This stimulus intensity-duration co-coding mechanism successfully reproduces the long-term plasticity (LTP) characteristics of biological synapses.

[0011] Further, the gate dielectric layer material is porous SiO2 with a thickness of 100 to 150nm; the metal oxide is one or more of indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO), and the thickness of the oxide semiconductor layer is 20 to 50nm; the quantum dot is any one of PbS, CdS, CdSe, and GaN, and the thickness of the quantum dot-PMMA blend layer is 20 to 50nm; the material of the source electrode or the drain electrode is any one or more of Al, Au, Cu, and Ti, and the thickness of the source and drain electrodes is 50 to 300nm.

[0012] The preparation method of the above photoelectric transistor simulating a neural synapse is as follows:

[0013] 1) Pretreat the gate bottom electrode material;

[0014] 2) Prepare the gate dielectric layer on the surface of the gate bottom electrode;

[0015] 3) Prepare the metal oxide thin film on the surface of the gate dielectric layer;

[0016] 4) Prepare the quantum dot-PMMA mixed solution;

[0017] 5) Spin-coat, print, or cast a quantum dot-PMMA mixed solution on the metal oxide thin film, and anneal it to obtain an oxide / quantum dot / PMMA heterojunction semiconductor layer;

[0018] 6) Fabricate source and drain electrodes above the heterojunction semiconductor layer by vacuum evaporation.

[0019] Further, in step 3), the preparation method of the metal oxide thin film includes chemical vapor deposition process, magnetron sputtering deposition process, or hydrothermal synthesis process; preferably, when the metal oxide thin film is prepared by magnetron sputtering, the pressure is 0.5-0.8 Pa and the sputtering power is 60-80 W.

[0020] Further, in step 4), the specific process of preparing the quantum dot-PMMA mixed solution is as follows: first, spin the quantum dot solution in the dark, mix PMMA and benzyl alcohol in a mass ratio of 1:10-20, and heat at 80°C-100°C for 24 h-48 h; mix the PMMA solution and the quantum dot solution in a mass ratio of 1:1-3, and spin in the dark to form a quantum dot-PMMA mixed solution.

[0021] Further, in step 5), when using the spin-coating process, the spin-coating speed is 1000-4000 rpm, and the spin-coating time is 30-90 s; the annealing temperature is 60-100°C and the annealing time is 30-60 min.

[0022] Based on the above optoelectronic transistor simulating a neural synapse with broad spectral response characteristics and greatly enhanced long-term plasticity, this application uses two such optoelectronic transistors (denoted as device a and device b) to build a multi-spectral weight update circuit: connect transistors a and b in series, and the probe contacts the source, drain, and gate of the device, ground the source of device a, apply fixed voltages at the gates of the two devices and the drain of device b to turn off the transistors, and apply corresponding optical signals in the form of pulses at device a or b to selectively regulate the conductance voltage division, that is, to selectively enhance or suppress the weight, and realize the long-term potentiation (LTP) and long-term depression (LTD) plasticity of the simulated synaptic efficacy.

[0023] Further, the specific design of the weight enhancement circuit is as follows: the probe contacts the source, drain, and gate of devices a and b, ground the source of device a, apply a fixed voltage V ds at the gates of devices a and b, gs turn off the transistors, and the connection point of the drain of device a and the source of device b is V out ; apply an optical signal in the form of a pulse at device a. Under the stimulation of the optical pulse, the conductance G a of device a increases, the voltage division of device a becomes larger, and V out of the postsynaptic response becomes larger, realizing the enhancement of the synaptic weight.

[0024] Further, the specific design of the weight suppression circuit is as follows: The probe contacts the source, drain, and gate of devices a and b, grounding the source of device a and applying a fixed voltage V at the drain of device b. ds A fixed voltage V is applied to the gates of devices a and b. gs This turns off the transistor. The connection point between the drain of device a and the source of device b is V. out An optical signal is applied to device b in the form of a pulse. Under the stimulation of the optical pulse, the conductance G of device b b increases, the voltage division of device b increases, and the V of the postsynaptic response out decreases, achieving the suppression of synaptic weight.

[0025] The beneficial effects of the present invention are as follows:

[0026] 1. In this application, a single oxide semiconductor (such as IGZO, IZO, etc.) layer is modified with quantum dots, and the active layer of the device is reconstructed into an oxide / quantum dot / PMMA heterojunction system. This structure utilizes the programmable optoelectronic properties of quantum dots (precise bandgap regulation induced by the quantum confinement effect), breaking through the inherent narrow spectral response limitation of a single oxide semiconductor. It not only enhances the optical response of the device but also broadens the spectral response range of the device, achieving wide spectral coverage from ultraviolet to near-infrared. The synaptic plasticity gain in the visible light band is particularly significant, providing an innovative hardware architecture for a highly sensitive bionic vision perception system.

[0027] 2. Based on the heterostructure modified with quantum dots, a novel optoelectronic synaptic transistor has been successfully developed in this application. Through the charge trapping effect of the quantum dot / semiconductor heterojunction, the recombination time of photo-generated carriers is significantly extended, enabling the device to continuously maintain the current state even after the optical stimulation is removed, thereby greatly enhancing the long-term plasticity of the device. This characteristic enables it to accurately simulate various memory behaviors related to bionic synapses, including the generation of excitatory postsynaptic current (EPSC) and the dynamic transformation process from short-term synaptic plasticity (STP) to long-term synaptic plasticity (LTP), etc.

[0028] 3. By broadening the spectral response range of the transistor, this application helps to build a multi-spectral weight update circuit. The entire circuit can be regarded as the series connection of two separate devices. By applying optical pulse stimulation to different transistor devices, the weights can be selectively enhanced / suppressed, that is, it can achieve dynamic weight regulation using all-optical signals and can simulate the self-organizing reconstruction process of neural circuits in the human neural network. This mechanism based on optically controlled synaptic plasticity can further map the dynamic regulation characteristics of behavior and cognitive functions in the biological nervous system, helping to ultimately achieve a high-fidelity simulation of synaptic bionic functions.

[0029] 4. Compared with traditional synaptic weight regulation methods based on electrical regulation or optoelectronic hybrid modes, the present application innovatively constructs an all-optical multi-wavelength weight regulation platform. This technology realizes synaptic weight update through the synergistic effect of multi-spectral optical signals, not only overcoming the inherent limitations of electrical signal interference and wavelength dependence, but also laying a hardware foundation for the development of multi-spectral neuromorphic vision systems (such as retina-like convolutional neural networks (CNNs)), showing great application potential in the fields of bionic visual perception and neuromorphic computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is the preparation flow chart of the optoelectronic transistor simulating a neural synapse;

[0031] Figure 2 is the structural schematic diagram of the optoelectronic transistor simulating a neural synapse prepared in Example 1;

[0032] Figure 3 is the electrical characteristic diagram of the optoelectronic transistor simulating a neural synapse prepared in Example 1. Among them, subfigure a is the output characteristic curve diagram, and subfigure b is the transfer characteristic curve diagram;

[0033] Figure 4 is the ultraviolet-visible-near-infrared absorption spectrum of IGZO and IGZO / quantum dot / PMMA films;

[0034] Figure 5 is the schematic curve diagram of the EPSC behavior of the optoelectronic transistor simulating a neural synapse prepared in Example 1 after light pulse stimulation. Subfigure a is the schematic curve diagram of the EPSC behavior after being stimulated by light with a wavelength of 405 nm for 0.2 s, and subfigure b is the schematic curve diagram of the EPSC behavior after being stimulated by light with a wavelength of 405 nm for 2 s;

[0035] Figure 6 is the schematic curve diagram of the EPSC behavior of the optoelectronic transistor simulating a neural synapse prepared in Example 1 after being stimulated by light pulses of different wavelengths. Subfigure a is the schematic curve diagram of the EPSC behavior after being stimulated by a 405 nm light pulse, subfigure b is the schematic curve diagram of the EPSC behavior after being stimulated by a 532 nm light pulse, and subfigure c is the schematic curve diagram of the EPSC behavior after being stimulated by a 655 nm light pulse;

[0036] Figure 7 is the energy band diagram of the optoelectronic transistor simulating a neural synapse prepared in Example 1. Subfigure a is the energy band diagram when the gate voltage is positive (VG>0), and subfigure b is the energy band diagram when the gate voltage is negative (VG<0);

[0037] Figure 8 Among them, subfigures a and b are the weight update circuit diagrams for realizing light enhancement and light inhibition based on the optoelectronic transistor prepared in Example 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] To enable those of ordinary skill in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0039] Embodiment 1

[0040] This embodiment discloses a photoelectric transistor simulating a neural synapse, and the preparation process refers to Figure 1 , and the specific preparation steps are as follows:

[0041] 1) Pretreatment of the gate bottom electrode: Using highly doped P-type silicon material (P ++ Si) as the gate bottom electrode, first ultrasonically clean the Si-based substrate in absolute ethanol and deionized water for 10 min to 20 min respectively, repeat three times, and dry the water stains on the surface of the Si wafer with a nitrogen gun and then heat-treat for 5 min to 10 min.

[0042] 2) Preparation of the gate dielectric layer (ion gate): Using SiH4 / N2 and N2O as reaction gases, deposit a porous SiO2 thin film with a thickness of about 120 nm on the cleaned gate bottom electrode by plasma-enhanced chemical vapor deposition (PECVD) technology, with a deposition time of 7 min and a deposition temperature of 150 °C.

[0043] 3) Preparation of the oxide film layer: At room temperature, use radio frequency sputtering of magnetron sputtering to sputter a 30 nm IGZO thin film under the conditions of 0.5 pa and 60 W.

[0044] 4) Preparation of the CdS quantum dot-PMMA mixed solution: Spin the CdS quantum dot solution (with n-octane as the solvent and a concentration of 10 mg / mL) in the dark (rotation speed of 900 rpm) for 1 min; mix polymethyl methacrylate (PMMA) and benzyl alcohol (BA) at a mass ratio of 1:20 and heat at 80 °C for 36 h to fully mix and dissolve; mix the PMMA solution and the CdS quantum dot solution at a mass ratio of 1:1 and spin in the dark at a speed of 900 rpm for 30 min to prepare the CdS quantum dot-PMMA mixed solution.

[0045] 5) Preparation of the CdS-PMMA blend layer: In a glove box, spin-coat the prepared CdS-PMMA solution on the IGZO thin film according to the spin-coating parameters of 3000 rpm / 60 s, and anneal at 80 °C for 30 min to obtain a 30 nm thick CdS-PMMA blend layer.

[0046] Doping PMMA with quantum dots has a certain encapsulation effect on the quantum dots, which can improve the stability of the quantum dots. In addition, the presence of PMMA can increase the defect pores around the quantum dots, and these pores can capture photo-generated carriers, thereby prolonging the carrier lifetime, contributing to the formation of long-range plastic current, which is crucial for simulating the long-term memory function of biological synapses.

[0047] 6) Preparation of source and drain electrodes: Deposit the source and drain electrodes through a mask. Put the metal particles and the device covered with the mask into the evaporation coater. With the combined action of the mechanical pump and the molecular pump, evacuate the inside of the evaporation coater to 5×10 -4 Pa. At this time, the evaporation boat starts to work. Adjust the power control knob to gradually increase the evaporation power. When the boat is bright and the evaporation rate is stable, open the sample baffle to start preparing the Al source and drain electrodes with a thickness of 100 nm; after evaporation is completed, slowly reduce the power to 0, cool the cavity for 20 min to 40 min, fill in nitrogen and open the cavity, take out the finished product, and scrape the edge of the device to expose the bottom gate electrode for testing.

[0048] Figure 2 The structure diagram of the phototransistor prepared based on the above steps is as follows. From bottom to top, it is the P ++ Si gate bottom electrode, porous SiO2 ion gate, IGZO / CdS / PMMA heterojunction semiconductor layer, and metal source and drain electrodes.

[0049] In this embodiment, the PECVD technology is used to prepare the gate dielectric layer. The low-temperature deposition process promotes the formation of a loose microstructure of the SiO2 electrolyte film. This porous feature allows H + ions to migrate along the Si-O bond network. Under the drive of an external electric field, the ions gradually accumulate at the SiO2 electrolyte / Al electrode interface, resulting in a huge double-layer capacitance, enabling the transistor to operate at a low voltage (≤4V).

[0050] As Figure 3 shown, the device electrical property characterization shows that: the output characteristic curve graph ( Figure 3 sub-figure a) presents typical n-type channel transistor characteristics and good ohmic contact. At V ds = 3V and V gs = 4V, a maximum saturation current of 81 μA can be observed; observing its transfer characteristic curve ( Figure 3 sub-figure b), an obvious counterclockwise hysteresis phenomenon can be seen. This phenomenon verifies the double-layer effect of H + ions in the SiO2 electrolyte film, providing experimental evidence for the porous structure of the dielectric layer.

[0051] After comparing the ultraviolet-visible-near-infrared absorption spectra of the IGZO thin film and the IGZO / quantum dot / PMMA thin film, it can be found that ( Figure 4):Due to the synergistic effect of quantum dots and PMMA, the heterojunction structure exhibits broadband absorption characteristics in the range of 200 nm - 850 nm. This composite structure not only extends the absorption bandwidth of the IGZO semiconductor layer to the near-infrared region, but also significantly enhances the spectral response intensity in the ultraviolet band compared to the original IGZO phototransistor.

[0052] The synaptic function simulated by the device exhibits synaptic plasticity, which refers to the variability of the synaptic connection strength between neurons, and the excitatory postsynaptic current (EPSC) can represent synaptic plasticity. Refer to Figure 5 In subfigures a and b of the neutron diagram, it can be seen that the phototransistors prepared in this embodiment exhibit different light response characteristics under light stimulation at a wavelength of 405 nm with different stimulation durations (0.2 s and 2 s). After removing the light stimulation, the decay processes of EPSC caused by the two different irradiation times show obvious differences, indicating the dynamic transition of the device from short-term plasticity to long-term plasticity.

[0053] Observe again Figure 6 It can be found that the phototransistors prepared in this embodiment all produce obvious light responses after being stimulated by 405 nm, 532 nm, and 655 nm light pulses respectively. When the light stimulation is removed, the current remains for a long time. The EPSC of this photonic synaptic transistor is generated by the accumulation of photo-generated carriers at the conductive channel and the ion gate interface. When the light pulse is removed, the EPSC decays over time, further proving its long-term plasticity.

[0054] According to the accumulation and depletion of free electrons at the IGZO / ion gate interface, the energy band bending diagram of the device is as Figure 7 shown. The energy band diagram shows the carrier transport behavior in the IGZO / quantum dot / PMMA channel under different gate voltages. When the gate voltage is positive (V G >0), positive ions will accumulate at the ion gate / IGZO interface. Due to the double-layer coupling effect, the free electrons in the IGZO / quantum dot / PMMA channel layer are attracted to the interface between the ion gate and IGZO, and thus a relatively high conductance value can be observed. On the contrary (V G <0), the free electrons in the IGZO / quantum dot / PMMA channel layer are repelled, and the device maintains a relatively low conductance value. Therefore, the carrier transport characteristics of this photonic synaptic device can be synergistically controlled by double-layer modulation.

[0055] The synaptic function of the phototransistor is simulated using Keysight B1500A. Compared with a transistor with a common gate dielectric layer, porous silica as the ion gate allows Figure 2 the transistor with this structure to operate at a relatively low voltage, which is also the preferred choice for synaptic simulation. Measuring the transfer characteristics of the transistor, due to the ion gating effect, under forward and backward gate voltages (Vgs ) It shows typical hysteresis between scans.

[0056] Application Example

[0057] This application example proposes a novel neuromorphic circuit based on all-optical signals to achieve weight update. Through reasonable wiring, it realizes multi-spectral synaptic weight update with long-term potentiation (LTP) and long-term depression (LTD) plasticity of analog synaptic efficacy.

[0058] Reference Figure 8 , for the long-term potentiation (LTP) and long-term depression (LTD) plasticity circuits of synaptic efficacy, two transistor devices prepared in Example 1 need to be connected in series. The two devices are respectively denoted as device a and device b. Ground the source of device a and apply a fixed voltage V at the drain of device b ds , apply a fixed voltage V to the gates of devices a and b gs Turn off the transistor. The connection point between the drain of device a and the source of device b is V out .

[0059] Weight Enhancement Circuit Reference Figure 8 Subfigure a, specifically: The probe contacts the source, drain, and gate of devices a and b. Ground the source of device a and apply a fixed source-drain voltage V ds (V in ), apply a fixed gate voltage V to the gates of devices a and b gs Turn off the transistor and regulate the conductance only relying on optical signals. The connection point between the drain of device a and the source of device b is V out , and its voltage is determined by the voltage division of devices a and b. The weight enhancement mechanism is: Apply a certain optical signal in the form of a pulse at device a to represent visual information. Under the stimulation of the optical pulse, the photo-generated carriers in device a increase, and the conductance G a of device a increases, and the equivalent resistance R a = 1 / G a decreases. Since V out = V ds * (R b / R a + R b ) = V ds * (G a / G a + G b ), the voltage division of device a becomes larger, and the V out of the postsynaptic response becomes larger, realizing the enhancement of synaptic weight.

[0060] Weight Inhibition Circuit Reference Figure 8 Subfigure b, specifically: The probe contacts the source, drain, and gate of devices a and b. Ground the source of device a and apply a fixed source-drain voltage V ds; Apply a fixed gate voltage V to the gates of devices a and b gs Turn off the transistor. The connection point between the drain of device a and the source of device b is V out , and its voltage is determined by the voltage division of devices a and b. The weight inhibition mechanism is as follows: Apply a certain optical signal in the form of a pulse to device b. Under the stimulation of the optical pulse, the conductance G of the right device b b increases, and the equivalent resistance R b = 1 / G b decreases. Based on V out = V ds *(G a / G a +G b ), the voltage division of the right device b increases, and the V of the postsynaptic response out decreases, thus realizing the inhibition of synaptic weight.

[0061] Since the phototransistor prepared in Example 1 has a wide spectral response characteristic, the response range is extended from the ultraviolet band to the near-infrared band, and the response can be achieved without external electrical writing. Therefore, devices a and b can respond to optical signals of different bands (such as red, green, and blue light) respectively under the condition of no external electrical writing, realizing the separation of multi-spectral input.

[0062] It can also be known from the above content that for the constructed LTP and LTD plasticity circuits, stimulating device a can achieve weight enhancement, and stimulating device b can achieve weight inhibition. Therefore, by selectively enhancing / inhibiting weights with different wavelength optical signals, color channel separation can be theoretically achieved. For example, stimulating device a with red light can enhance the weight of red features, while stimulating device b with blue light can achieve the effect of inhibiting the weight of background noise, realizing dynamic weight allocation.

[0063] Therefore, if different color optical signals are mapped to the enhancement / inhibition of synaptic weights, and multiple synaptic weights are simultaneously regulated by multi-spectral optical signals to accelerate color feature extraction, the response of the cone cells of the retina to the RGB channels can be simulated, and the robustness of color recognition can be improved.

[0064] In summary, the series optical-controlled synaptic circuit proposed in this application example realizes the bidirectional update of synaptic weights driven by all-optical through selective regulation of conductance voltage division by optical pulses and by broadening the spectral response range of the device to construct a multi-spectral weight update circuit. That is, this application integrates the pulse coding information of the inhibition and enhancement dual channels and uses all-optical regulation to achieve the symmetric long-term plasticity (LTP / LTD) of synaptic weights. This mechanism provides a hardware basis for multi-spectral neuromorphic vision systems (such as retina-like CNN), and the efficiency and accuracy of color recognition can be further improved in the future through material optimization and system integration.

[0065] The basic principles, main features and advantages of the present invention have been shown and described above. However, the above are only specific embodiments of the present invention, and the technical features of the present invention are not limited thereto. Any other embodiments obtained by those skilled in the art without departing from the technical solution of the present invention should be covered within the scope of the present invention.

Claims

1. A phototransistor simulating a synapse, characterized in that: It includes a gate bottom electrode, a gate dielectric layer, a metal oxide film layer, a quantum dot-PMMA blended layer and a source-drain electrode arranged in sequence from bottom to top; The spectral response range of the phototransistor is 200nm to 850nm, and it exhibits wavelength-dependent postsynaptic current response characteristics. Light pulse stimulation in different bands can trigger differentiated EPSC amplitudes, and after the light stimulation is removed, the EPSC decays over time. This stimulus intensity-duration co-coding mechanism successfully reproduces the long-term plasticity characteristics of biological synapses.

2. The phototransistor simulating a neural synapse according to claim 1, characterized in that: The gate bottom electrode material is P ++ Si; The gate dielectric layer is made of porous SiO2 with a thickness of 100 to 150 nm. The metal oxide is one or more of indium gallium zinc oxide and indium zinc oxide, and the thickness of the oxide semiconductor layer is 20 to 50 nm; The quantum dots are any one of PbS, CdS, CdSe, and GaN, and the thickness of the quantum dot-PMMA blended layer is 20 to 50 nm; The material of the source electrode or the drain electrode is any one or more of Al, Au, Cu or Ti, and the thickness of the source and drain electrodes is 50 to 300 nm.

3. The method for preparing a phototransistor simulating a neural synapse according to any one of claims 1 to 2, characterized in that: The steps include: 1) Pre-treating the gate bottom electrode material; 2) preparing a gate dielectric layer on the surface of the gate bottom electrode; 3) preparing a metal oxide film on the surface of the gate dielectric layer; 4) preparing a quantum dot-PMMA mixed solution; 5) spin coating, printing or casting a quantum dot-PMMA mixed solution on the metal oxide film, and annealing to obtain an oxide / quantum dot / PMMA heterojunction semiconductor layer; 6) A source-drain electrode is fabricated on the heterojunction semiconductor layer by vacuum evaporation.

4. The method for preparing a phototransistor simulating a neural synapse according to claim 3, characterized in that: In step 3), the preparation method of the metal oxide film includes a chemical vapor deposition process, a magnetron sputtering deposition process or a hydrothermal synthesis process; When the metal oxide film is prepared by magnetron sputtering, the pressure is 0.5-0.8 Pa and the sputtering power is 60-80 W.

5. The method for preparing a phototransistor simulating a neural synapse according to claim 3, characterized in that: In step 4), the specific process of preparing the quantum dot-PMMA mixed solution is: first spin the quantum dot solution in the dark, mix PMMA and benzyl alcohol in a mass ratio of 1:10 to 20, and heat at 80°C to 100°C for 24h to 48h; mix the PMMA solution and the quantum dot solution in a mass ratio of 1:1 to 3, spin in the dark, and form a quantum dot-PMMA mixed solution.

6. The method for preparing a phototransistor simulating a neural synapse according to claim 3, characterized in that: In step 5), when the spin coating process is adopted, the spin coating speed is 1000-4000 rpm, and the spin coating time is 30-90 s; the annealing temperature is 60-100° C., and the annealing time is 30-60 min.

7. A multi-spectral weight updating circuit, characterized in that: It is constructed based on the phototransistor simulating neural synapses described in any one of the two claims 1-2; The two transistors a and b are connected in series, and the probes are in contact with the source, drain and gate of the devices. The source of device a is grounded, and fixed voltages are applied to the gates of the two devices and the drain of device b to turn off the transistors. The corresponding light signals are applied in the form of pulses at device a or b to selectively regulate the conductance voltage divider, which can selectively enhance or inhibit the weight, thereby realizing long-term enhancement and inhibitory plasticity that simulates synaptic efficacy.

8. A multi-spectral weight updating circuit as claimed in claim 7, characterized in that: The design of the weight enhancement circuit is as follows: the probe contacts the source, drain and gate of devices a and b, the source of device a is grounded, and a fixed voltage V is applied to the drain of device b. ds , apply a fixed voltage V to the gates of devices a and b gs To turn off the transistor, the drain of device a and the source of device b are connected at V out ; A light signal is applied in the form of a pulse at device a. Under the stimulation of the light pulse, the conductance G of device a a increases, the voltage of device a increases, and the postsynaptic response V out becomes larger, thus achieving the enhancement of synaptic weight.

9. A multi-spectral weight updating circuit as claimed in claim 7, characterized in that: The design of the weight suppression circuit is as follows: the probe contacts the source, drain and gate of devices a and b, the source of device a is grounded, and a fixed voltage V is applied to the drain of device b. ds ; Apply a fixed voltage V to the gates of devices a and b gs To turn off the transistor, the drain of device a and the source of device b are connected at V out ; A light signal is applied in the form of a pulse at device b. Under the stimulation of the light pulse, the conductance G of device b b increases, the voltage of device b increases, and the V out Decrease, thus achieving the inhibition of synaptic weight.

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