Circuit and method for linearization of switch for isolating high-speed data driver from audio signal amplifier

Abstract

The system includes a plug shared by high speed data and analog audio transmissions. One or more switches may be included to isolate the high speed data driver from the audio signal amplifier. A gate drive circuit may be used to turn the switches on and off, and to provide linearization during the on-state of the switches. The linearization may be achieved at least in part by applying an absolute value waveform as a component of the gate drive signal.

Description

Technical Field

[0001] This application relates to linearization circuits, and more particularly to the linearized operation of switches on an audio signal line. Background Art

[0002] Wireless communication devices are typically small form factor devices within small form factor devices (such as tablet devices). Due to the smaller configuration of such devices, it is particularly meaningful to use the device space economically. In this regard, it may be desirable to convert the audio path on a wireless communication device (e.g., to a headset or speaker) from a 3.5 millimeter (mm) jack to a Universal Serial Bus (USB) Type-C (USB-C) port connector, as the USB-C port connector is more versatile (e.g., sending audio, exchanging USB data, exchanging battery charger data, etc.).

[0003] Due to the additional functionality of providing audio over USB-C, the differential transmit data lines DP / DN associated with the host USB-C circuit are loaded with many components, such as switch devices that couple the differential transmit lines DP / DN to the audio circuit, an application processor (AP), a battery charger circuit, an electrostatic discharge (ESD) device, traces, flexible connectors, and other circuits. In some systems, the audio signal amplifier is served by the same pins as the high-speed data driver in the AP. The audio signal amplifier is expected to have a high level of capacitive load, so there is a need in the art for circuits and techniques for isolating the AP from the capacitive load when sending high-speed data. Summary of the Invention

[0004] In a specific embodiment, a wireless communication device includes: an application processor; a first audio signal amplifier; a multiplexing circuit configured to couple the application processor and the first audio signal amplifier to a set of wires; a data and audio plug coupled to the set of wires; a first switch disposed between the first audio signal amplifier and the application processor; and a first gate drive circuit coupled to the gate of the first switch, the first gate drive circuit including a first absolute value circuit.

[0005] In another specific implementation, a method for operating a wireless communication device is described. The wireless communication device has a first metal-oxide semiconductor (MOSFET) switch implemented between a first audio signal amplifier and an application processor. The method includes: isolating the first audio signal amplifier from the application processor, including applying a first gate control signal to the first MOSFET switch at a first voltage level, the first gate control signal turning off the first MOSFET switch; and linearizing the first MOSFET switch, including applying the first gate control signal to the first MOSFET switch at a second voltage level during the on state of the first MOSFET switch, where linearizing the first MOSFET switch includes generating a first absolute value waveform from a first signal, and the first gate control signal includes the first absolute value waveform.

[0006] In another specific implementation, a wireless communication device includes: components for running an operating system; components for amplifying an analog audio signal; components for coupling the components for running the operating system and the components for amplifying the analog audio signal to a set of wires; a data and audio plug coupled to the set of wires; a first transistor coupled between the components for running the operating system and the components for amplifying the analog audio signal; and components for linearizing the operation of the first transistor, the components including components for generating a gate control signal from a full-wave rectified signal.

[0007] In yet another specific implementation, a wireless communication device includes: an application processor; a pair of audio signal amplifiers corresponding to a first audio channel and a second audio channel; a decoder / encoder (codec) chip having a multiplexing circuit configured to couple the application processor and the pair of audio signal amplifiers to a set of wires; a plug coupled to the set of wires; a first switch coupled between the application processor and the first audio channel; and a first gate drive circuit having an output coupled to the gate of the first switch, the first gate drive circuit configured to generate a first gate control signal including a first absolute value waveform.

[0008] These advantages and additional advantages can be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram illustrating an example wireless device including a gate drive circuit according to one specific implementation.

[0010] Figure 2 Illustrated is a specific implementation for use in a device (such asFigure 1 An example architecture for multiplexing an audio signal, a high-speed data signal, and charging in a device).

[0011] Figure 3 Illustrates an example architecture consistent with a Figure 2 specific implementation, in the form of a schematic diagram.

[0012] Figure 4 Illustrates an example architecture according to a specific implementation.

[0013] Figures 5 to 6 Illustrates an example gate drive circuit operating in a current domain, which can be used in a Figure 4 specific implementation.

[0014] Figure 7 Illustrates an example architecture for implementing a Figure 4 specific implementation in an analog voltage domain, for an absolute value function.

[0015] Figure 8 Illustrates an example architecture for implementing a Figure 4 specific implementation in a digital voltage domain, for an absolute value function.

[0016] Figure 9 Illustrates a flowchart of an example method that can be performed by a Figure 2 example architecture.

[0017] The specific implementations of the present disclosure and their advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Description

[0018] In one example, a wireless device includes a Universal Serial Bus (USB) Type-C (USB-C) socket for charging, for high-speed data, and for analog audio signals. For example, the device may omit a 3.5 mm audio jack to support using the USB-C socket to physically attach a headset or earbuds. The advantage of such devices is that they can use a single chip for USB-C and audio, thus saving area inside the device's enclosure.

[0019] However, the capacitive load attributable to the audio signal amplifier may pose a threat to the distortion of high-speed data signals from the USB-C data driver. This is especially true when the audio signal amplifier and the USB-C data driver share a common pin on a decoder / encoder (codec) chip. One solution includes placing a relatively large metal-oxide-semiconductor field-effect transistor (MOSFET) switch in line with the audio signal amplifier to allow the audio signal amplifier to be isolated from the USB-C data driver during high-speed data transmission. The solution may also include turning on the MOSFET switch during the transmission of the analog audio signal. The relatively large size of the MOSFET switch can give the MOSFET switch a lower on-state resistance at the cost of a higher capacitance.

[0020] A potential problem with using a relatively large MOSFET switch is that the switch itself may cause a capacitive load and thus cause distortion of the high-speed data signal. Thus, there may be a trade-off between the audio signal amplifier as a parasitic capacitive load and the MOSFET switch as a parasitic capacitive load on the USB-C data driver path.

[0021] Various embodiments include linearization circuitry to keep the on-state resistance of the MOSFET switch within an acceptable range during normal operation to reduce the total harmonic distortion (THD) of the analog audio signal. Such embodiments may allow a relatively large MOSFET switch to be used for effective high-speed data isolation with little or no THD loss to the analog audio signal.

[0022] In one example, a wireless communication device includes an application processor and an audio signal amplifier coupled to a set of wires via a multiplexing circuit. A data and audio plug is coupled to the set of wires.

[0023] A switch (such as a MOSFET transistor) is disposed between the first audio signal amplifier and the application processor. The switch is operable to isolate the application processor from the audio signal amplifier during high-speed data transmission from the application processor and is also operable to electrically couple the audio signal amplifier to the data and audio plug during analog audio transmission.

[0024] Linearization can be achieved by using a gate drive circuit. The gate drive circuit may have an output coupled to the gate of the switch. The gate drive circuit may include a first absolute value circuit that generates a first absolute value waveform. The first absolute value circuit may generate the first absolute value waveform by applying an absolute value function to a first waveform. The first waveform may include a digital waveform, an audio signal, a common-mode voltage, or any other suitable waveform. The first gate control signal from the first gate drive circuit includes the first absolute value waveform and may also include other components such as a direct current (DC) voltage, a common-mode voltage, etc.

[0025] One example embodiment includes an analog circuit operating in a current domain. Another example embodiment includes an analog circuit operating in a voltage domain. Yet another example embodiment includes a digital circuit operating in a voltage domain.

[0026] Some advantages of embodiments are high performance. Specifically, a gate control voltage can provide a more constant on-state resistance of a transistor during audio signal transmission. A more constant on-state resistance can result in a higher THD value and higher user satisfaction.

[0027] Of course, the above examples are given for a single audio channel. Some embodiments may include multiple (e.g., two) audio channels, and the two audio channels may have a switch and a gate drive circuit for driving the switch. Such embodiments are described in more detail below.

[0028] Figure 1 An example device 100 in which aspects of the present disclosure may be implemented is illustrated. Device 100 may be a battery-powered device such as a cellular phone, a handheld device, a wireless device, a laptop computer, a tablet computer, a smart phone, a wearable device, etc.

[0029] Device 100 may include a processor 104 that controls the operation of device 100. Processor 104 may also be referred to as a central processing unit (CPU). A memory 106 that may include both a read-only memory (ROM) and a random access memory (RAM) provides instructions and data to processor 104. A portion of memory 106 may also include a non-volatile random access memory (NVRAM). Processor 104 generally performs logical and arithmetic operations based on program instructions stored within memory 106.

[0030] In some aspects, device 100 may further include a housing 108 that may include a transmitter 110 and a receiver 112 to allow for data transmission and reception between device 100 and a remote location. For some aspects, transmitter 110 and receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached to or otherwise coupled to housing 108 and electrically connected to transceiver 114. Device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0031] Device 100 may also include a signal detector 118 that may be used to detect and quantify the signal level received by transceiver 114. Signal detector 118 may detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density and other signal parameters. Device 100 may also include a digital signal processor (DSP) 120 for processing the signals.

[0032] Device 100 may also include a battery 122 for powering the various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of device 100. The PMIC 124 may perform various functions for the device, such as direct current (DC) - to - DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In some aspects, the PMIC 124 may include a battery charging circuit (e.g., a primary - secondary battery charging circuit) or other switched - mode power supplies. The various components of device 100 may be coupled together via a bus system 126, which may include, in addition to a data bus, a power bus, a control signal bus, and / or a status signal bus.

[0033] For some aspects, device 100 may have an input / output (I / O) module 128 for receiving and / or outputting data and / or power. In some aspects, the I / O module 128 may include a connector 130, such as a USB Type - A (USB - A) socket or a USB - C socket. The pins of the connector 130 may be routed via the bus system 126 and / or signal lines of the I / O module 128 to the processor 104 and / or the PMIC 124, and at least some of these signal lines may include over - voltage protection circuits. Also, as described herein, the I / O module 128 may include a decoder - encoder (codec) chip, which includes an audio signal path and drivers and other hardware components to facilitate audio passing through the connector 130.

[0034] Figure 2 is an illustration of an example hardware architecture 200, which provides more details on how some parts of device 100 may be implemented. For example, architecture 200 includes an application processor 210, which may include some or all of the functions of processor 104 and DSP 120. In some examples, the application processor 210 may be a system - on - a - chip (SOC) that includes multiple processor cores, a digital signal processor (DSP), memory, etc. For example, one or more of the processor cores may run an operating system with a kernel that provides functions for, e.g., controlling a multiplexing circuit 235 and a gate - drive circuit 236. Architecture 200 also includes a charger integrated circuit 220, which may include some or all of the functions of PMIC 124.

[0035] The codec chip 230 may provide some or all of the functions of the I / O module 128 and may also include a connector 130 for physically docking with the USB-C plug 250. In this example, the plug 250 is a USB-C plug, but the scope of the specific implementation may include any suitable plug, whether or not it conforms to the standard. The codec chip 230 interfaces with both the audio signal path and the USB data path. For example, the codec chip 230 receives high-speed data from the USB-C plug 250 on the DN and DP data lines. The codec chip 230 can then route this high-speed data to the application processor 210.

[0036] Additionally, the codec chip includes audio signal amplifiers 231, 232 for the right and left channels, respectively. The analog audio signal can be output to the USB-C plug 250 for use with, for example, wired headphones. It is also worth noting that the USB-C plug 250 can be used for charging such that DC power can be provided from the USB-C plug 250 to the charger IC 220.

[0037] To facilitate sharing the connection, the codec chip 230 includes a multiplexing circuit 235, which is illustrated as a plurality of switches in Figure 2 . For example, when an audio signal is being sent from the audio signal amplifiers 231, 232 to the USB-C plug 250, the switches can be turned on to create a circuit path from the audio signal amplifiers 231, 232 to the USB-C plug 250, while other switches can be turned off to isolate the application processor 210 from the audio signal path and also isolate the charger IC 220 from the audio signal path. Similarly, when the application processor 210 is using the USB-C plug 250 to send and receive digital data via the DP and DN pins, the charger IC 220 and the audio signal amplifiers 231, 232 can be isolated from the USB-C plug 250 via the multiplexing circuit 235. Moreover, when the charger IC 220 is receiving DC power via the DN and DP pins of the USB-C plug 250, the multiplexing circuit 235 can create an electrical connection from the charger IC 220 to the USB-C plug 250 while isolating the application processor 210 and the audio signal amplifiers 231, 232 from the DC charging power. The multiplexing circuit 235 can be controlled, for example, by the application processor 210 or some other suitable hardware or software logic within the architecture 200.

[0038] The multiplexing circuit 235 may include transistors M1 and M2, which are disposed between the audio signal amplifiers 231, 232 and the application processor 210. First, looking at transistor M1, when the application processor 210 transmits and receives high-speed data via the USB-C plug 250, this transistor isolates the audio signal amplifier 231 from the application processor 210. Similarly, transistor M2 isolates the audio signal amplifier 232 from the application processor 210 in the same manner. Transistors M1 and M2 may be turned on to create a circuit path on a set of wires DPR and DNL for the transmission of analog audio signals.

[0039] The gate drive circuits 236a and 236b drive the gates of transistors M1 and M2 to create an off state during high-speed data transmission and a linearized on state during the transmission of analog audio signals. As described below, the gate drive circuits 236a and 236b may include circuitry operable to generate an absolute value (ABS) waveform that, to some extent, maintains the on-state resistance of transistors M1 and M2 within an acceptable range.

[0040] Figure 3 An example of Figure 2 is shown in the schematic diagram of the example architecture 300 consistent with the specific implementation. Figure 3 An example of the relationship between the right audio channel and the application processor is shown, including the placement of transistor M1. It should be understood that the same relationship exists between the left audio channel and the application processor, including the placement of transistor M2.

[0041] The audio signal amplifier 231 receives an analog audio signal from the DAC 325 and provides a gain level to the analog audio signal sufficient to cause the audio signal to be applied to a transducer (such as a speaker in a headset). In this example, the transducer is represented by the headset load impedance 330. The DAC 325 receives the digital audio signal Vhph_dac[n], converts the digital audio signal to a pre-amplified audio signal, and provides the pre-amplified audio signal to the input of the audio signal amplifier 231. During the transmission of the analog audio signal, transistor M1 is in the on state, creating a headset signal path. During the on state, the gate drive circuit 236a provides a gate control signal to transistor M1 to keep transistor M1 in the on state and provide linearization to transistor M1. During the off state, the gate drive circuit 236a provides a gate control signal to turn off transistor M1, such as by generating a negative gate-source voltage.

[0042] In the various specific implementations described herein, at least for the purposes of a particular application, transistor M1 is large enough to isolate the USB-C driver 310 from the audio signal amplifier 231. Additionally, the gate drive circuit 236a operates to provide a gate control signal to the gate of transistor M1, where the gate control signal includes a linearization component. The linearization component of the gate control signal can reduce or eliminate distortion that would otherwise be attributable to transistor M1.

[0043] The gate drive circuit 236b and transistor M2 operate in the same or a similar manner. Specifically, transistor M2 isolates the audio signal amplifier 232 from the USB-C driver 310 during high-speed data transmission, and transistor M2 forms a headphone signal path from the audio signal amplifier 232 to the headphone load impedance 330 during audio signal transmission. The gate drive circuit 236b provides a gate control signal to transistor M2 to turn transistor M2 on or off, and maintains the resistance of transistor M2 constant or nearly constant during the on state.

[0044] Figure 4 is an illustration of an example architecture 400 according to a particular implementation of the present disclosure. The example architecture 400 focuses on the right audio channel, but it should be understood that these principles apply equally to the left audio channel. Specifically, architecture 400 illustrates techniques for linearizing transistor M1 on the right audio channel, and the principles discussed with respect to architecture 400 also apply to linearizing transistor M2 on the left audio channel.

[0045] The gate drive circuit (e.g., gate drive circuit 236a) in architecture 400 includes an absolute value circuit 401, gain elements 402 and 403, and an adder 404. The audio signal amplifier 231 is coupled to the source of transistor M1, which in this particular implementation is shown as an n-channel metal oxide semiconductor (NMOS) transistor. The audio signal output is labeled Vhph_out, and the audio signal is an alternating current (AC) audio signal. The signal output at the drain of transistor M1 is Vload, and Vload can be applied to a transducer via the USB-C plug 250.

[0046] Architecture 400 includes an arrangement of resistors R1 and R2 that are coupled from the source to the drain to provide a common-mode voltage Vm. Specifically, resistor R1 is coupled to the source of transistor M1, and resistor R2 is coupled to the drain of transistor M1. In this example, the common-mode voltage Vm is applied to the body terminal of transistor M1. Vm is equal to 0.5*(Vhph_out + Vload).

[0047] The common-mode voltage Vm is a waveform derived from the audio signal output (Vhph_out), and this common-mode voltage is applied to the input of the gain element 402. In this example, the gain element 402 may include an operational amplifier, a transistor, or other components suitable for providing a gain of 0.5. Additionally, the specific value of the gain of the gain element 402 may be set at any appropriate level for a given application. The gain element 402 reduces the input voltage swing at the absolute value circuit 401 to remain within the linear range of the absolute value circuit 401. The output of the gain element 402 is 0.5*Vm, and it is received by the input of the absolute value circuit 401. In this example, the absolute value circuit 401 acts as a full-wave rectifier, as described in more detail below with respect to Figures 5 to 7 More detailed description.

[0048] The gain element 403 can be calibrated to compensate for known process variations. In some examples, the gain element 403 may be combined with the gain element 402 or may be separate. The output of the gain element 403 is 0.5*Kcomp*ABS(Vm), where ABS(Vm) represents the result of applying the absolute value function to the common-mode voltage Vm.

[0049] The adder 404 receives the output of the gain element 403, the common-mode voltage, and the DC voltage offset Vconst. In this example, Vcont is a DC voltage component that is set at a high enough level to turn on the transistor M1. Both the output of the gain element 403 and the common-mode voltage Vm are AC components.

[0050] The gate control signal Vg is output from the adder 404, and it is equal to 0.5*Kcomp*ABS(Vm)+Vm+Vconst. The absolute value component (ABS(Vm)) of Vg is used to linearize the operation of the transistor M1. Specifically, during the on state of the transistor M1, the DC component of Vg keeps the transistor M1 on, and the amplitude of ABS(vm) changes as the amplitude of the audio signal output Vhph_out changes, thereby adjusting the gate-source voltage of M1 to remain relatively constant and keeping the on-state resistance relatively constant and within a specified range.

[0051] The absolute value component of Vg has been simulated and tested and is shown to significantly reduce the second-order intermodulation distortion at the headphone load impedance 330. An advantage of some specific implementations is that the reduced second-order intermodulation distortion can further reduce the third-order intermodulation distortion, where the third-order intermodulation distortion is associated with a reduction in audio quality. Therefore, specific implementations that linearize the operation of the transistor M1 can experience reduced third-order intermodulation distortion and provide higher audio quality.

[0052] Figure 5 Illustrated can be in Figure 4An example gate drive circuit 500 used in a specific implementation. The components of the gate drive circuit 500 include those that implement the functions of the gain components 402, 403, the adder 404, and the absolute value circuit 401. The output of the gate drive circuit 500 is Vg, which can be applied to the gate of a transistor (such as transistor M1 or, when implemented on the left audio channel, applied to transistor M2).

[0053] The common mode voltage Vm is received at the gain element 402, and the output of the gain element 402 is a gain-adjusted version of Vm, which is a sinusoidal waveform 510 having a positive part and a negative part. The operational amplifiers 501, 503 are coupled in parallel, and both receive the gain-adjusted version of Vm. The operational amplifier 501 is powered by VDD (positive power supply), while the operational amplifier 503 is powered by the inverted power supply -VDD.

[0054] The operational amplifier 501 can be arranged as a voltage follower and, more specifically, as a half-wave rectifier. This is illustrated in more detail with respect to Figure 6 where the operational amplifier 501 is coupled to node A through its non-inverting input. The inverting input is coupled to node B in a feedback loop. The diode D3 is set between the output of the operational amplifier 501 and node B. The voltage at node B is the positive half-wave rectified waveform Vpos_shft. In other words, Vpos_shft represents the positive half of the waveform at node A.

[0055] The operational amplifier 503 provides the negative half of the waveform at node A. Figure 6 The operational amplifier 503 is illustrated in more detail. Node A is coupled to the input resistor Ri, and the diode D1 is coupled between the resistor Ri and Rf. The cathode of the diode D1, the resistor Ri, and the resistor Rf are all coupled to the inverting input of the operational amplifier 503. The non-inverting input of the operational amplifier 503 is coupled to ground. The output of the operational amplifier 503 is coupled to the anode of the diode D1 and to the cathode of the diode D2. The anode of the diode D2 is coupled to node C. The operational amplifier 503 is arranged as an inverting half-wave rectifier. The voltage at node C is the negative half-wave rectified waveform Vneg_shft.

[0056] The operational amplifier 501 is coupled to the transconductance amplifier 502, and the operational amplifier 503 is coupled to the transconductance amplifier 504. The transconductance amplifier 502 receives the positive half of the waveform, and the transconductance amplifier 504 receives the negative half of the waveform. The transconductance amplifier 502 generates Ipos, which is the positive half of the waveform in the current domain. The transconductance amplifier 504 generates Ineg, which is the negative half of the waveform in the current domain. Although in Figure 5Although not explicitly shown in the figure, in appropriate cases, a compensation gain may be included within transconductance amplifiers 502 and 504.

[0057] Currents Ipos and Ineg are respectively output from transconductance amplifiers 502 and 504. Iconst is a DC current, which corresponds to Figure 4 Vconst in lift The resistor R is placed at node D and coupled to the common-mode voltage Vm. Currents Ipos, Ineg, and Iconst are added at node D. The placement of the resistor R lift at node D provides a voltage equal to Vg, which in this example is equal to Vm + Iconst * Rlift + ABS(Vm) * k.

[0058] Figure 7 Illustrates an example architecture 700 for implementing Figure 4 the absolute value function in a specific implementation. Architecture 700 includes an absolute value circuit 701 that receives the common-mode voltage Vm waveform 702. Again, the common-mode voltage is an AC waveform 702 having a positive part of its period and a negative part of its period, as illustrated by waveform 702. Although not explicitly shown in Figure 7 the figure, some specific implementations may include a gain element, such as gain element 402, to limit the input range of the absolute value circuit 701.

[0059] In Figure 7 the example, the absolute value circuit 701 can be implemented using any suitable hardware. For example, in some specific implementations, any full-wave rectifier known now or developed later that is suitable for a given application can be used. The output of the absolute value circuit 701 is the absolute value waveform 703, which is also referred to as Vhph_abs.

[0060] The absolute value waveform 703 is input to the gain element 403, and the output of the gain element 403 is provided to the adder 704. The adder 704 receives the DC voltage Vconst, the common-mode voltage Vm, and the output of the gain element 403. In this example, the gate voltage Vg is equal to ABS(Vm) * Kcomp + Vconst + Vm.

[0061] Similar to Figures 4 to 6 the specific implementation of Figure 7 the principle can be adapted to the left audio channel by using the common-mode voltage of M2 and applying its corresponding Vg to the gate of M2.

[0062] Figure 8 Illustrates an example architecture 800 according to one specific implementation. Architecture 800 includes voltage rectification in the digital domain. The digital audio signal Vhph_dac[n] (as Figure 3As shown, it can be individually transmitted to the absolute value digital filter 801 and transmitted in parallel to the DAC 325 (not shown). The digital filter 801 can be appropriately implemented using hardware and / or software. The digital filter 801 applies a digital function to generate a digital signal 810 representing the audio signal that has undergone rectification. The digital signal 810 is received by the DAC 802, which outputs an analog signal 811. In this example, the analog signal 811 is a rectified version of Vhph_out.

[0063] The analog signal 811 can be further appropriately adjusted in gain up or down by the gain element 803. The gain element 803 is illustrated as an adjustable gain element, and any one of the gain elements 402, 403, 803 can be adjustable if suitable for a given application. The adder 804 receives the output from the gain element 803, the common mode voltage Vm, and the DC offset Vconst. The gate control voltage Vg is equal to ABS(Vhph_out)*Kcomp + Vconst + Vm.

[0064] The architecture 800 can be implemented within the architecture 400, with some changes made to the architecture 400. For example, the architecture 400 can be modified such that the common mode voltage Vm is not applied to the gain element 402. More precisely, the gain element 402 can be eliminated, and the absolute value circuit 401 can be implemented using the ABS digital filter 801 and the DAC 802. Digital domain linearization can also be performed on the transistors M2 and the audio signal amplifier 232 on the left audio channel.

[0065] Various embodiments can include advantages over other solutions. For example, the linearization circuits and techniques described herein can operate to reduce the range of on-state resistance fluctuations during the transmission of the analog audio signal within the transistors M1 and M2. For example, experiments and simulations have shown that the range of on-state resistance can be reduced by approximately one order of magnitude relative to the range of on-state resistance of a system that uses the non-rectified version of Vhph_out in the gate control signal. In other words, the linearization circuits and techniques can cause the on-state resistance of the transistors M1 and M2 to remain substantially constant during normal operation, thereby providing enhanced total harmonic distortion (THD) performance. Various embodiments can include additional components downstream of the transistors M1 and M2, where those downstream components are expected to increase the amount of THD. However, reducing the THD at the transistors M1 and M2 can result in a reduction in the total THD at those downstream components. The reduced total THD can result in higher audio fidelity and higher user satisfaction.

[0066] Now reference will be made to Figure 9The flowchart shown discusses an example method for operating a wireless communication device having a first MOSFET switch implemented between a first audio signal amplifier and an application processor. Method 900 may be performed by a hardware architecture such as Figure 2 illustrated, since the hardware architecture receives and transmits audio signals on a transmit line. For example, the hardware architecture may include one or more high-speed data transmit lines (e.g., DPR and DNL) configured to transmit audio signals and coupled to a multiplexing circuit (e.g., multiplexing circuit 235) and an audio signal amplifier (e.g., audio signal amplifiers 231, 232). The first MOSFET switch may be disposed between the audio signal amplifier and the application processor to isolate the application processor from the audio signal amplifier during high-speed data transmission. The actions of method 900 may be performed under the control of logic, such as may be implemented in the core of application processor 210 or under the control of other suitable computing circuitry.

[0067] The method includes, at action 910, isolating the first audio signal amplifier from the application processor. Action 910 may include applying a first gate control signal to the first MOSFET switch at a first voltage level that turns off the first MOSFET switch. For example, gate drive circuit 236a may output a low voltage to transistor M1, thereby turning off transistor M1 and isolating application processor 210 from the capacitive load attributable to audio signal amplifier 231.

[0068] Similarly, action 910 may include isolating other audio signal amplifiers, such as isolating audio signal amplifier 232 from application processor 210 by applying a low voltage to the gate of transistor M2 by the action of gate drive circuit 236b.

[0069] The method includes, at action 920, linearizing the first MOSFET switch, including applying a first gate control signal to the first MOSFET switch at a second voltage level during the on state of the first MOSFET switch. Examples of action 920 include Figure 2 gate drive circuit 236a applying a gate control signal to transistor M1, where the gate control signal includes a DC voltage (Vdc) sufficient to turn on transistor M1 and an AC component (ABS(Vm) or ABS(Vhph_out)) that linearizes the operation of transistor M1 during the on state.

[0070] Consistent with Figures 3 to 8 an example, the AC component may be generated at least in part by applying an absolute value function to a waveform derived from the output of the audio signal amplifier (e.g., Vm) or to a digital audio signal.

[0071] The method includes: at operation 930, similarly linearizing other MOSFET switches. For example, on the left audio channel, transistor M2 can be linearized in the same manner, such as by applying an absolute value function to a waveform derived from the output of an audio signal amplifier or from a digital audio signal, and then applying a gate control signal to the gate of M2. The gate control signal can include the absolute value waveform.

[0072] When those transistors M1 and M2 are turned on and when a set of wires DPR, DNL conduct an analog audio signal from the audio signal amplifier, operations 920 - 930 can be performed. Thus, the resistance of transistors M1, M2 can remain approximately constant within the range of the audio signal.

[0073] At operation 940, the MOSFET switches are returned to the off state. For example, the corresponding gate drive circuit can apply the gate control signal to those transistors at a voltage level sufficient to cause a negative gate - source voltage at transistors M1, M2. Operation 940 can be performed when a set of wires DPR, DNL are not used to conduct an analog audio signal from the audio signal amplifier.

[0074] The scope of the specific implementation is not limited to the series of operations described with respect to Figure 9 Rather, operations 910 - 940 can be appropriately repeated depending on when the wired audio capability is used or not used.

[0075] As those skilled in the art will understand so far and depending on the particular application at hand, many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of using the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific implementations illustrated and described herein (since they are only some examples of the present disclosure), but should be fully equivalent to the appended claims below and their functional equivalents.

[0076] The specific implementation examples are described in the following numbered clauses:

[0077] 1. A wireless communication device, the wireless communication device comprising:

[0078] An application processor;

[0079] A first audio signal amplifier;

[0080] A multiplexing circuit configured to couple the application processor and the first audio signal amplifier to a set of wires;

[0081] A data and audio plug coupled to the set of wires;

[0082] A first switch, the first switch being disposed between the first audio signal amplifier and the application processor; and

[0083] A first gate driver circuit, the first gate driver circuit being coupled to the gate of the first switch, the first gate driver circuit including a first absolute value circuit.

[0084] 2. The wireless communication device according to clause 1, wherein the first gate driver circuit is configured to generate a first absolute value waveform by applying an absolute value function to a first waveform derived from an audio signal output of the first audio signal amplifier, wherein a first gate control signal from the first gate driver circuit includes the first absolute value waveform, and wherein the first waveform derived from the audio signal output of the first audio signal amplifier includes a common mode voltage between the source and the drain of the first switch.

[0085] 3. The wireless communication device according to clause 2, wherein the first gate driver circuit includes:

[0086] An adder, the adder being configured to receive the common mode voltage, the first absolute value waveform, and a direct current (DC) voltage, and output the first gate control signal to the gate of the first switch.

[0087] 4. The wireless communication device according to any one of clauses 1 to 2, wherein the first audio signal amplifier corresponds to a first audio channel, and wherein the wireless communication device further includes:

[0088] A second audio signal amplifier, the second audio signal amplifier corresponding to a second audio channel;

[0089] A second switch, the second switch being disposed between the second audio signal amplifier and the application processor; and

[0090] A second gate driver circuit, the second gate driver circuit being coupled to the gate of the second switch, the second gate driver circuit including a second absolute value circuit, and the second absolute value circuit being configured to generate a second absolute value waveform by applying the absolute value function to a second waveform derived from an audio signal output of the second audio signal amplifier, wherein a second gate control signal from the second gate driver circuit includes the second absolute value waveform.

[0091] 5. The wireless communication device according to any one of clauses 1 to 4, wherein the first gate driver circuit includes:

[0092] A first operational amplifier powered by a first power supply;

[0093] A first transconductance amplifier coupled to the first operational amplifier;

[0094] A second operational amplifier powered by an inverting power supply;

[0095] A second transconductance amplifier coupled to the second operational amplifier; and

[0096] An adder coupled to the first transconductance amplifier and the second transconductance amplifier, wherein the adder is coupled to the gate of the first switch.

[0097] 6. The wireless communication device according to clause 5, wherein the first operational amplifier is configured as a first voltage follower, and wherein the second operational amplifier is configured as a second voltage follower.

[0098] 7. The wireless communication device according to clause 5, wherein the first transconductance amplifier and the second transconductance amplifier are coupled in parallel to the adder, and wherein the adder includes a direct current (DC) current source and a resistor coupled to the common-mode voltage between the source and the drain of the first switch.

[0099] 8. The wireless communication device according to clause 5, wherein the first operational amplifier is configured as a half-wave rectifier, and wherein the second operational amplifier is configured as an inverting half-wave rectifier.

[0100] 9. The wireless communication device according to any one of clauses 1 to 8, wherein the first absolute value circuit is coupled to the common-mode voltage between the source and the drain of the first switch, and wherein the first gate driver circuit includes:

[0101] A full-wave rectifier coupled to the common-mode voltage;

[0102] An adder coupled to the full-wave rectifier, the adder being further coupled to a direct current (DC) voltage and the common-mode voltage, wherein the output of the adder is coupled to the gate of the first switch.

[0103] 10. The wireless communication device according to clause 9, wherein the full-wave rectifier includes an analog voltage full-wave rectifier.

[0104] 11. The wireless communication device according to any one of clauses 1 to 10, wherein the first audio signal amplifier, the multiplexing circuit, and the first switch are implemented on a decoder / encoder (codec) chip.

[0105] 12. The wireless communication device according to any one of clauses 1 to 11, wherein the data and audio plug includes a universal serial bus (USB) plug.

[0106] 13. The wireless communication device according to any one of clauses 1 to 12, wherein the wireless communication device further comprises:

[0107] A decoder codec chip, the decoder codec chip comprising the set of wires, the first audio signal amplifier, and the multiplexing circuit, and wherein the first switch is included in the multiplexing circuit.

[0108] 14. A method for operating a wireless communication device having a first metal oxide semiconductor (MOSFET) switch implemented between a first audio signal amplifier and an application processor, the method comprising:

[0109] Isolating the first audio signal amplifier from the application processor, including applying a first gate control signal at a first voltage level to the first MOSFET switch, the first gate control signal turning off the first MOSFET switch; and

[0110] Linearizing the first MOSFET switch, including applying the first gate control signal at a second voltage level to the first MOSFET switch during an on state of the first MOSFET switch, wherein linearizing the first MOSFET switch includes generating a first absolute value waveform from a first signal, and wherein the first gate control signal includes the first absolute value waveform.

[0111] 15. The method according to clause 14, wherein generating the first absolute value waveform comprises:

[0112] Generating a half-wave rectified positive signal from the first signal;

[0113] Generating a half-wave rectified negative signal from the first signal;

[0114] Converting the half-wave rectified positive signal to a first current;

[0115] Converting the half-wave rectified negative signal to a second current; and

[0116] Adding the first current and the second current to a direct current (DC) current.

[0117] 16. The method according to any one of clauses 14 to 15, wherein generating the first absolute value waveform is performed in an analog voltage domain, and wherein the first absolute value waveform is added to a direct current (DC) voltage and an absolute value voltage.

[0118] 17. The method according to any one of clauses 14 to 16, wherein the first signal includes a digital audio signal, and wherein generating the first absolute value waveform is performed in a digital voltage domain, including inputting the digital audio signal into a digital filter, wherein the digital filter performs an absolute value function.

[0119] 18. The method according to any one of clauses 14 to 17, wherein the first signal includes a common-mode voltage between a source and a drain of the first MOSFET switch.

[0120] 19. The method according to any one of clauses 14 to 18, wherein the first MOSFET switch corresponds to a first audio channel, and the method further includes: linearizing a second MOSFET switch corresponding to a second audio channel.

[0121] 20. A wireless communication device, the wireless communication device comprising:

[0122] Components for running an operating system;

[0123] Components for amplifying an analog audio signal;

[0124] Components for coupling the components for running the operating system and the components for amplifying the analog audio signal to a set of wires;

[0125] A data and audio plug, the data and audio plug being coupled to the set of wires;

[0126] A first transistor, the first transistor being coupled between the components for running the operating system and the components for amplifying the analog audio signal; and

[0127] Components for linearizing the operation of the first transistor, the components including components for generating a gate control signal from a full-wave rectified signal.

[0128] 21. The wireless communication device according to clause 20, wherein the data and audio plug includes a Universal Serial Bus (USB) plug.

[0129] 22. The wireless communication device according to any one of clauses 20 to 21, the wireless communication device further comprising:

[0130] A decoder - codec chip, the decoder - codec chip including the set of wires, the components for amplifying the analog audio signal, and the components for coupling, and wherein the first transistor is disposed on the codec chip.

[0131] 23. The wireless communication device according to any one of clauses 20 to 22, wherein the component for generating the gate control signal includes:

[0132] A first half-wave rectifier coupled to a first transconductance amplifier; and

[0133] A second half-wave rectifier coupled to a second transconductance amplifier.

[0134] 24. The wireless communication device according to any one of clauses 20 to 23, wherein the component for generating the gate control signal includes:

[0135] A digital filter and a digital-to-analog converter (DAC) configured to generate the full-wave rectified signal from a digital audio signal.

[0136] 25. The wireless communication device according to any one of clauses 20 to 24, wherein the component for generating the gate control signal includes:

[0137] A component for generating the full-wave rectified signal from the common-mode voltage of the first transistor in an analog-digital domain.

[0138] 26. A wireless communication device, the wireless communication device comprising:

[0139] An application processor;

[0140] A pair of audio signal amplifiers corresponding to a first audio channel and a second audio channel;

[0141] A decoder / encoder (codec) chip having a multiplexing circuit configured to couple the application processor and the pair of audio signal amplifiers to a set of wires;

[0142] A plug coupled to the set of wires;

[0143] A first switch coupled between the application processor and the first audio channel; and

[0144] A first gate drive circuit having an output coupled to the gate of the first switch, the first gate drive circuit being configured to generate a first gate control signal including a first absolute value waveform.

[0145] 27. The wireless communication device according to clause 26, wherein the first switch is disposed on the codec chip.

[0146] 28. The wireless communication device according to any one of clauses 26 to 27, wherein the wireless communication device further comprises:

[0147] a second switch coupled between the application processor and the second audio channel; and

[0148] a second gate drive circuit having an output coupled to the gate of the second switch, the second gate drive circuit being configured to generate a second gate control signal from a second absolute value waveform.

[0149] 29. The wireless communication device according to any one of clauses 26 to 28, wherein the first gate drive circuit comprises:

[0150] a first operational amplifier (op amp) powered by a first power supply;

[0151] a first transconductance amplifier coupled to the first op amp;

[0152] a second op amp powered by an inverted power supply;

[0153] a second transconductance amplifier coupled to the second op amp; and

[0154] an adder coupled to the first transconductance amplifier and the second transconductance amplifier, wherein the adder is coupled to the gate of the first switch.

[0155] 30. The wireless communication device according to clause 29, wherein the first absolute value waveform comprises a full-wave rectified version of the common-mode voltage of the first switch.

Claims

1. A wireless communication device, the wireless communication device comprising: An application processor; A first audio signal amplifier; A multiplexing circuit configured to couple the application processor and the first audio signal amplifier to a set of wires; A data and audio plug coupled to the set of wires; A first switch disposed between the first audio signal amplifier and the application processor; And A first gate drive circuit coupled to the gate of the first switch, the first gate drive circuit including a first absolute value circuit.

2. The wireless communication device according to claim 1, wherein the first gate drive circuit is configured to generate a first absolute value waveform by applying an absolute value function to a first waveform derived from an audio signal output of the first audio signal amplifier, wherein a first gate control signal from the first gate drive circuit includes the first absolute value waveform, and wherein the first waveform derived from the audio signal output of the first audio signal amplifier includes a common mode voltage between the source and drain of the first switch.

3. The wireless communication device according to claim 2, wherein the first gate drive circuit includes: An adder configured to receive the common mode voltage, the first absolute value waveform, and a direct current (DC) voltage, and output the first gate control signal to the gate of the first switch.

4. The wireless communication device according to claim 2, wherein the first audio signal amplifier corresponds to a first audio channel, and wherein the wireless communication device further includes: A second audio signal amplifier corresponding to a second audio channel; A second switch disposed between the second audio signal amplifier and the application processor; And A second gate drive circuit coupled to the gate of the second switch, the second gate drive circuit including a second absolute value circuit configured to generate a second absolute value waveform by applying the absolute value function to a second waveform derived from an audio signal output of the second audio signal amplifier, wherein a second gate control signal from the second gate drive circuit includes the second absolute value waveform.

5. The wireless communication device according to claim 1, wherein the first gate drive circuit includes: A first operational amplifier powered by a first power supply; A first transconductance amplifier coupled to the first operational amplifier; A second operational amplifier powered by an inverted power supply; A second transconductance amplifier coupled to the second operational amplifier; And An adder coupled to the first transconductance amplifier and the second transconductance amplifier, wherein the adder is coupled to the gate of the first switch.

6. The wireless communication device according to claim 5, wherein the first operational amplifier is configured as a first voltage follower, and wherein the second operational amplifier is configured as a second voltage follower.

7. The wireless communication device according to claim 5, wherein the first transconductance amplifier and the second transconductance amplifier are coupled in parallel to the adder, and wherein the adder includes a direct current (DC) current source and a resistor coupled to a common-mode voltage between a source and a drain of the first switch.

8. The wireless communication device according to claim 5, wherein the first operational amplifier is configured as a half-wave rectifier, and wherein the second operational amplifier is configured as an inverting half-wave rectifier.

9. The wireless communication device according to claim 1, wherein the first absolute value circuit is coupled to a common-mode voltage between a source and a drain of the first switch, and wherein the first gate drive circuit includes: a full-wave rectifier coupled to the common-mode voltage; an adder coupled to the full-wave rectifier, the adder being further coupled to a DC voltage and the common-mode voltage, wherein an output of the adder is coupled to the gate of the first switch.

10. The wireless communication device according to claim 9, wherein the full-wave rectifier includes an analog voltage full-wave rectifier.

11. The wireless communication device according to claim 1, wherein the first audio signal amplifier, the multiplexing circuit, and the first switch are implemented on a decoder / encoder (codec) chip.

12. The wireless communication device according to claim 1, wherein the data and audio plug includes a universal serial bus (USB) plug.

13. The wireless communication device according to claim 1, the wireless communication device further comprising: a decoder / encoder (codec) chip, the decoder / encoder (codec) chip including the set of wires, the first audio signal amplifier, and the multiplexing circuit, and wherein the first switch is included in the multiplexing circuit.

14. A method for operating a wireless communication device having a first metal-oxide-semiconductor (MOSFET) switch implemented between a first audio signal amplifier and an application processor, the method comprising: isolating the first audio signal amplifier from the application processor, including applying a first gate control signal to the first MOSFET switch at a first voltage level, the first gate control signal turning off the first MOSFET switch; and linearizing the first MOSFET switch, including applying the first gate control signal to the first MOSFET switch at a second voltage level during an on state of the first MOSFET switch, wherein linearizing the first MOSFET switch includes generating a first absolute value waveform from a first signal, and wherein the first gate control signal includes the first absolute value waveform.

15. The method according to claim 14, wherein generating the first absolute value waveform includes: generating a half-wave rectified positive signal from the first signal; generating a half-wave rectified negative signal from the first signal; converting the half-wave rectified positive signal to a first current; converting the half-wave rectified negative signal to a second current; and Add the first current and the second current to a direct current (DC) current.

16. The method according to claim 14, wherein generating the first absolute value waveform is performed in an analog voltage domain, and wherein the first absolute value waveform is added to a direct current (DC) voltage and an absolute value voltage.

17. The method according to claim 14, wherein the first signal includes a digital audio signal, and wherein generating the first absolute value waveform is performed in a digital voltage domain, including inputting the digital audio signal into a digital filter, wherein the digital filter performs an absolute value function.

18. The method according to claim 14, wherein the first signal includes a common mode voltage between the source and the drain of the first MOSFET switch.

19. The method according to claim 14, wherein the first MOSFET switch corresponds to a first audio channel, and the method further comprises: Linearize a second MOSFET switch corresponding to a second audio channel.

20. A wireless communication device, the wireless communication device comprising: Components for running an operating system; Components for amplifying an analog audio signal; Components for coupling the components for running the operating system and the components for amplifying the analog audio signal to a set of wires; A data and audio plug, the data and audio plug being coupled to the set of wires; A first transistor, the first transistor being coupled between the components for running the operating system and the components for amplifying the analog audio signal; And Components for linearizing the operation of the first transistor, the components including components for generating a gate control signal from a full-wave rectified signal.

21. The wireless communication device according to claim 20, wherein the data and audio plug includes a universal serial bus (USB) plug.

22. The wireless communication device according to claim 20, the wireless communication device further comprising: A decoder decoder (codec) chip, the decoder decoder (codec) chip including the set of wires, the components for amplifying the analog audio signal, and the components for coupling, and wherein the first transistor is disposed on the codec chip.

23. The wireless communication device according to claim 20, wherein the components for generating the gate control signal include: A first half-wave rectifier, the first half-wave rectifier being coupled to a first transconductance amplifier; And A second half-wave rectifier, the second half-wave rectifier being coupled to a second transconductance amplifier.

24. The wireless communication device according to claim 20, wherein the components for generating the gate control signal include: A digital filter and a digital-to-analog converter (DAC) configured to generate the full-wave rectified signal from a digital audio signal.

25. The wireless communication device according to claim 20, wherein the components for generating the gate control signal include: Components for generating the full-wave rectified signal from a common mode voltage of the first transistor in an analog-digital domain.

26. A wireless communication device, the wireless communication device comprising: An application processor; A pair of audio signal amplifiers corresponding to a first audio channel and a second audio channel; A decoder / encoder (codec) chip, the decoder / encoder (codec) chip having a multiplexing circuit configured to couple the application processor and the pair of audio signal amplifiers to a set of wires; A plug coupled to the set of wires; A first switch coupled between the application processor and the first audio channel; And A first gate drive circuit having an output coupled to the gate of the first switch, the first gate drive circuit configured to generate a first gate control signal including a first absolute value waveform.

27. The wireless communication device according to claim 26, wherein the first switch is disposed on the codec chip.

28. The wireless communication device according to claim 26, the wireless communication device further comprising: A second switch coupled between the application processor and the second audio channel; And A second gate drive circuit having an output coupled to the gate of the second switch, the second gate drive circuit configured to generate a second gate control signal from a second absolute value waveform.

29. The wireless communication device according to claim 26, wherein the first gate drive circuit comprises: A first operational amplifier (op amp) powered by a first power supply; A first transconductance amplifier coupled to the first op amp; A second op amp powered by an inverted power supply; A second transconductance amplifier coupled to the second op amp; And An adder coupled to the first transconductance amplifier and the second transconductance amplifier, wherein the adder is coupled to the gate of the first switch.

30. The wireless communication device according to claim 29, wherein the first absolute value waveform comprises a full-wave rectified version of the common-mode voltage of the first switch.

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