A SOC state estimation system and estimation method used in a BMS

Abstract

The application discloses a SOC state estimation system and estimation method used in a BMS, which comprises a current signal conditioning circuit, a voltage detection circuit and a SOC estimation module; the input end of the current signal conditioning circuit is connected with the positive pole of a battery pack; the input end of the voltage detection circuit is connected with the positive pole and the negative pole of the battery pack respectively; the voltage detection circuit is used for obtaining the open circuit voltage VOC of the battery pack and is connected with the data sampling port of the SOC estimation module; the current signal conditioning circuit is used for detecting the current of the battery pack and is connected with the data sampling port of the SOC estimation module; the SOC estimation module is used for calculating the initial value SOC0 of the battery pack during work according to the pre-stored battery model and the open circuit voltage VOC, and is used for calculating the SOC value of the battery at any time according to the current and the ampere-hour integral method. The SOC detection of the battery is realized by combining the open circuit voltage method and the ampere-hour integral method, and the application has the advantages of simplicity, practicality and accurate result.

Description

Technical Field

[0001] The present invention relates to the field of power batteries, and in particular to BMS current detection and state estimation. Background Art

[0002] In the field of power batteries, battery management systems (BMS) play a vital role in ensuring the safe and efficient operation of batteries. Among them, accurately estimating the battery's state of charge (SOC) is one of the core functions of BMS. However, existing SOC estimation methods have many shortcomings. On the one hand, some methods have difficulty achieving high-precision measurements when measuring the initial state of the battery, resulting in inaccurate initial SOC values, which in turn affects the accuracy of SOC estimation throughout the subsequent battery operation. On the other hand, when detecting battery charge and discharge currents, traditional current detection circuits are often complex and costly, and are unable to automatically adjust detection parameters according to the size of the battery current, resulting in inaccurate detected current signals, ultimately affecting the accuracy of SOC estimation. In addition, due to the inability to achieve integrated detection of charging mode current and discharge mode current, the efficiency and accuracy of SOC estimation under different operating conditions are low, making it difficult to meet the requirements of modern power batteries for high safety, long life and efficient operation. Summary of the Invention

[0003] The present invention aims to provide a BMS current conditioning circuit and state-of-charge (SOC) estimation method. This method combines the open-circuit voltage method with the ampere-hour integration method to accurately detect SOC. This method optimizes the current conditioning circuit to achieve integrated charge and discharge detection, reducing costs and improving reliability. This method allows for rapid and accurate SOC estimation under various operating conditions, improving battery life and safety.

[0004] The technical solution provided by the present invention is as follows: a SOC state estimation system for a BMS, comprising a current signal conditioning circuit, a voltage detection circuit and an SOC estimation module; the input end of the current signal conditioning circuit is connected to the positive electrode of the battery pack; the input end of the voltage detection circuit is connected to the positive and negative electrodes of the battery pack respectively; the voltage detection circuit is used to obtain the open circuit voltage VOC of the battery pack and is connected to the data sampling port of the SOC estimation module; the current signal conditioning circuit is used to detect the current i B , and connected to the data sampling port of the SOC estimation module; the SOC estimation module calculates the initial value SOC0 of the battery pack when it is working based on the pre-stored battery model and the open circuit voltage VOC, and on the other hand, based on the current i B Calculate the SOC value of the battery at any time using the ampere-hour integration method;

[0005] The current signal conditioning circuit includes a current-to-voltage module, a DC bias circuit, and a CT matching resistor control module; the current-to-voltage module consists of a current transformer (CT), a parallel controllable matching resistor network, and a TVS protection circuit, and is used to convert the battery loop current into a proportional voltage signal; the DC bias circuit consists of an operational amplifier (OP) and an equivalent resistor network, receives the voltage signal output by the current-to-voltage module, and outputs a positive unipolar voltage after applying a reference bias; the CT matching resistor control module includes a voltage comparator array, a logic gate circuit, and a bidirectional shift register group, which monitors the voltage amplitude output by the DC bias circuit in real time and stabilizes the output voltage within the measurement range of the ADC range by dynamically switching the parallel branches of the controllable matching resistor network.

[0006] The above-mentioned SOC state estimation system for BMS, the current-to-voltage module includes a current transformer CT, a matching resistor R1, a matching resistor R2, a matching resistor R3, a matching resistor R4, a dual N-channel MOS transistor M1, a dual N-channel MOS transistor M2, a dual N-channel MOS transistor M3, a dual N-channel MOS transistor M4 and a bidirectional TVS transistor D1; the input side of the current transformer CT receives the current i of the battery pack B One end of the output side of the current transformer CT is respectively connected to one end of a matching resistor R1, one end of a matching resistor R2, one end of a matching resistor R3, one end of a matching resistor R4, and one end of a bidirectional TVS transistor D1; the other end of the matching resistor R1 is connected to one end pin of a dual N-channel MOS transistor M1, and the other end pin of the dual N-channel MOS transistor M1 is grounded; the other end of the matching resistor R2 is connected to one end pin of a dual N-channel MOS transistor M2, and the other end pin of the dual N-channel MOS transistor M2 is grounded; the other end of the matching resistor R3 is connected to one end pin of a dual N-channel MOS transistor M3, and the other end pin of the dual N-channel MOS transistor M3 is grounded; the other end of the matching resistor R4 is connected to one end pin of a dual N-channel MOS transistor M4, and the other end pin of the dual N-channel MOS transistor M4 is grounded; the other end of the bidirectional TVS transistor D1 is grounded; the dual N-channel MOS transistors M1, M2, M3, and M4 are also connected to a CT matching resistor control module.

[0007] The aforementioned SOC state estimation system for BMS, the DC bias circuit includes an operational amplifier OP, four resistors R5, R6, R7 and R8 with the same resistance value; the non-inverting input terminal of the operational amplifier OP is respectively connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected to the output end of the current-to-voltage module, and the other end of the resistor R6 is connected to a 2.5V reference voltage; the inverting input terminal of the operational amplifier OP is connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the other end of the resistor R8 is connected to the output end of the operational amplifier OP.

[0008] The aforementioned SOC state estimation system for BMS, the CT matching resistance control module includes a voltage comparator CP1, a voltage comparator CP2, a voltage comparator CP3, a voltage comparator CP4, an OR gate OR1, an OR gate OR2, an OR gate OR3, an OR gate OR4, an OR gate OR5, an OR gate OR6, a bidirectional shift register U1 and a bidirectional shift register U2; the non-inverting input terminal of the voltage comparator CP1, the inverting input terminal of the voltage comparator CP2, the inverting input terminal of the voltage comparator CP3 and the non-inverting input terminal of the voltage comparator CP4 are respectively connected to the output terminal of the operational amplifier OP; the voltage comparator The inverting input of CP1 is connected to a 3V reference voltage, and the output of the voltage comparator CP1 is respectively connected to an input of the OR gate OR1 and the S0 pin of the bidirectional shift register U1; the non-inverting input of the voltage comparator CP2 is connected to a 2.6V reference voltage, and the output of the voltage comparator CP2 is respectively connected to the other input of the OR gate OR1 and the S1 pin of the bidirectional shift register U1; the output of the OR gate OR1 is connected to the CP pin of the bidirectional shift register U1; the non-inverting input of the voltage comparator CP3 is connected to a 2V reference voltage, and the output of the voltage comparator CP3 is respectively connected to an input of the OR gate OR2. The inverting input of the voltage comparator CP4 is connected to the 2.4V reference voltage, and the output of the voltage comparator CP4 is respectively connected to the other input of the OR gate OR2 and the S1 pin of the bidirectional shift register U2; the output of the OR gate OR2 is connected to the CP pin of the bidirectional shift register U2; the two inputs of the OR gate OR3 are respectively connected to the Q0 pin of the bidirectional shift register U1 and the Q4 pin of the bidirectional shift register U2, and the output of the OR gate OR3 is connected to the signal receiving end of the dual N-channel MOS tube M4; the two inputs of the OR gate OR4 are respectively connected to the Q0 pin of the bidirectional shift register U1 and the Q4 pin of the bidirectional shift register U2, and the output of the OR gate OR3 is connected to the signal receiving end of the dual N-channel MOS tube M4; The two input ends of the OR gate OR5 are respectively connected to the Q2 pin of the bidirectional shift register U1 and the Q6 pin of the bidirectional shift register U2, and the output end of the OR gate OR5 is connected to the signal receiving end of the dual N-channel MOS transistor M2; the two input ends of the OR gate OR6 are respectively connected to the Q3 pin of the bidirectional shift register U1 and the Q7 pin of the bidirectional shift register U2, and the output end of the OR gate OR6 is connected to the signal receiving end of the dual N-channel MOS transistor M1.

[0009] The aforementioned estimation method for the SOC state estimation system in the BMS includes the following steps:

[0010] Step 1: When the battery starts working, the SOC estimation module obtains the open circuit voltage VOC of the battery pack and calculates the battery SOC value based on the pre-stored battery model and VOC data, and uses it as the initial value SOC0;

[0011] Step 2: After the battery starts working, the current signal conditioning circuit realizes a wide range of current i by adaptive resistor switching. B The SOC estimation module then calculates the current i B The SOC value of the battery at any time is calculated using the ampere-hour integration method.

[0012] The aforementioned estimation method for the SOC state estimation system in the BMS, the specific process of calculating the SOC value of the battery at any time is as follows:

[0013] Step 2.1: Obtain the driving signal state values ​​of the dual N-channel MOS transistors M1, M2, M3, and M4 in the current conditioning circuit, and then determine the equivalent matching resistance value R of the current transformer CT in the current-to-voltage module. CT ;

[0014] Step 2.2, obtain the value of the output signal v1 of the operational amplifier OP in the current conditioning circuit, according to v B =v1-2.5 to get the output signal v of the current-to-voltage module B The value of

[0015] Step 2.3: Based on the current transformer CT current attenuation coefficient K CT and CT equivalent matching resistance R CT , calculate the battery current i B =v B / K CT R CT ;

[0016] Step 2.4: Use the ampere-hour integration method to calculate the increment of SOC at time k, that is, calculate ΔSOC k =i B (k)T value; where k is the calculation time of the increment, T is the interval time of the increment calculation, and the corresponding time t at the k moment k =kT;

[0017] Step 2.5, BMS based on SOC k =SOC k-1 +i B (k)T calculates the SOC value at time k, where: k ≥ 1.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] 1. Before the battery pack is put into operation, the present invention calculates the initial state of the battery each time it is operated by measuring the open-circuit voltage of the battery pack. After the operation starts, the charge and discharge current of the battery pack is measured with high precision and time is integrated to obtain the change in the battery state, thereby calculating the state value of the battery at any time during operation. Therefore, the present invention realizes battery SOC detection by combining the open-circuit voltage method and the ampere-hour integration method, which has the advantages of simplicity, practicality and accurate results.

[0020] 2. The current conditioning circuit of the present invention can adjust the current according to the battery current i B The value of the CT is automatically adjusted to ensure that the matching resistance of the B The converted voltage signal v B The current conditioning circuit of the present invention achieves integrated detection of charging mode current and discharge mode current, with advantages such as simple and reliable structure and low cost. In addition, based on the integrated detection of charge and discharge current, the BMS can achieve rapid and accurate estimation of SOC in charging mode, discharge mode and charge and discharge conditions, thereby improving battery life and safe operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the connection of the system of the present invention;

[0022] Figure 2 is a current conditioning circuit diagram of the present invention; DETAILED DESCRIPTION

[0023] The present invention will be further described below with reference to the embodiments and drawings, but they are not intended to limit the present invention.

[0024] Example: A SOC state estimation system for a BMS, such as Figure 1 As shown, it includes a current signal conditioning circuit, a voltage detection circuit and an SOC estimation module; the input end of the current signal conditioning circuit is connected to the positive electrode of the battery pack; the input end of the voltage detection circuit is connected to the positive and negative electrodes of the battery pack respectively; the voltage detection circuit is used to obtain the open circuit voltage VOC of the battery pack and is connected to the data sampling port of the SOC estimation module; the current signal conditioning circuit is used to detect the current i B , and connected to the data sampling port of the SOC estimation module; the SOC estimation module calculates the initial value SOC0 of the battery pack when it is working based on the pre-stored battery model and the open circuit voltage VOC, and on the other hand, based on the current i BThe SOC value of the battery at any time is calculated using the ampere-hour integration method. In this embodiment, the voltage detection circuit is a conventional circuit. Its principle is to proportionally attenuate the voltage of the high-voltage battery pack to a safe range through a voltage divider network. After signal conditioning (differential amplification, filtering) and isolation processing, it is converted into a digital signal by a high-precision ADC for use by the SOC estimation module. It belongs to conventional technical means well known and mastered by those skilled in the art, so it will not be described in detail here. In this embodiment, the SOC estimation module is integrated into the BMS main control circuit board, including an STM32F4 series microcontroller, a current / voltage signal input interface and a memory. The microcontroller collects the conditioned current signal through the built-in ADC, and executes the ampere-hour integration algorithm stored in the Flash to update the SOC value in real time.

[0025] The current signal conditioning circuit includes a current-to-voltage module, a DC bias circuit, and a CT matching resistor control module; the current-to-voltage module consists of a current transformer (CT), a parallel controllable matching resistor network, and a TVS protection circuit, and is used to convert the battery loop current into a proportional voltage signal; the DC bias circuit consists of an operational amplifier (OP) and an equivalent resistor network, receives the voltage signal output by the current-to-voltage module, and outputs a positive unipolar voltage after applying a 2.5V reference bias; the CT matching resistor control module includes a voltage comparator array, a logic gate circuit, and a bidirectional shift register group, which monitors the voltage amplitude output by the DC bias circuit in real time and stabilizes the output voltage within the measurement range of the ADC range by dynamically switching the parallel branches of the controllable matching resistor network.

[0026] In this embodiment, the current-to-voltage module includes a current transformer CT, a matching resistor R1, a matching resistor R2, a matching resistor R3, a matching resistor R4, a dual N-channel MOS transistor M1, a dual N-channel MOS transistor M2, a dual N-channel MOS transistor M3, a dual N-channel MOS transistor M4, and a bidirectional TVS transistor D1; the model of the dual N-channel MOS transistor M1, the dual N-channel MOS transistor M2, the dual N-channel MOS transistor M3, and the dual N-channel MOS transistor M4 are all 8205A; the input side of the current transformer CT receives the current i of the battery pack BOne end of the output side of the current transformer CT is respectively connected to one end of a matching resistor R1, one end of a matching resistor R2, one end of a matching resistor R3, one end of a matching resistor R4, and one end of a bidirectional TVS transistor D1; the other end of the matching resistor R1 is connected to one end pin of a dual N-channel MOS transistor M1, and the other end pin of the dual N-channel MOS transistor M1 is grounded; the other end of the matching resistor R2 is connected to one end pin of a dual N-channel MOS transistor M2, and the other end pin of the dual N-channel MOS transistor M2 is grounded; the other end of the matching resistor R3 is connected to one end pin of a dual N-channel MOS transistor M3, and the other end pin of the dual N-channel MOS transistor M3 is grounded; the other end of the matching resistor R4 is connected to one end pin of a dual N-channel MOS transistor M4, and the other end pin of the dual N-channel MOS transistor M4 is grounded; the other end of the bidirectional TVS transistor D1 is grounded; the dual N-channel MOS transistors M1, M2, M3, and M4 are also connected to a CT matching resistor control module. Among them, CT is a through-type current transformer, and its current attenuation coefficient K CT Meet K CT =N / 1, that is, the current of the CT output coil is the input current i B 1 / N of; M1 is the control switch of R1, M2 is the control switch of R2, M3 is the control switch of R3, and M4 is the control switch of R4. M1, M2, M3 and M4 are controlled by the output signals X1, X2, X3 and X4 of the CT matching resistance control module, which are used to match different resistances when the battery current is different, and adjust the battery charge and discharge current i B The matching resistor on the secondary side of the CT is converted into a suitable voltage signal v B , ensure that v B In a reasonable size. D1 realizes the voltage signal v B Perform amplitude limiting to protect CT and signal conditioning circuits. B with i B Satisfies the following formula:

[0027] v B =K CT R CT i B ;

[0028] Where: R CT is the equivalent matching resistance of the secondary output coil of the CT, satisfying:

[0029]

[0030] The DC bias circuit includes an operational amplifier OP, four resistors with the same resistance value, namely R5, R6, R7 and R8; the non-inverting input terminal of the operational amplifier OP is connected to one end of the resistor R5 and one end of the resistor R6 respectively, the other end of the resistor R5 is connected to the output end of the current-to-voltage module, and the other end of the resistor R6 is connected to a 2.5V reference voltage; the inverting input terminal of the operational amplifier OP is connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the other end of the resistor R8 is connected to the output end of the operational amplifier OP. According to electrical engineering knowledge, v1 and v B satisfy:

[0031] v1=2.5+v B .

[0032] The CT matching resistance control module includes a voltage comparator CP1, a voltage comparator CP2, a voltage comparator CP3, a voltage comparator CP4, an OR gate OR1, an OR gate OR2, an OR gate OR3, an OR gate OR4, an OR gate OR5, an OR gate OR6, a bidirectional shift register U1 and a bidirectional shift register U2; the non-inverting input terminal of the voltage comparator CP1, the inverting input terminal of the voltage comparator CP2, the inverting input terminal of the voltage comparator CP3 and the non-inverting input terminal of the voltage comparator CP4 are respectively connected to the output terminal of the operational amplifier OP; the inverting input terminal of the voltage comparator CP1 is connected to the 3V reference The output end of the voltage comparator CP1 is connected to an input end of the OR gate OR1 and the S0 pin of the bidirectional shift register U1; the non-inverting input end of the voltage comparator CP2 is connected to the 2.6V reference voltage, and the output end of the voltage comparator CP2 is connected to the other input end of the OR gate OR1 and the S1 pin of the bidirectional shift register U1; the output end of the OR gate OR1 is connected to the CP pin of the bidirectional shift register U1; the non-inverting input end of the voltage comparator CP3 is connected to the 2V reference voltage, and the output end of the voltage comparator CP3 is connected to an input end of the OR gate OR2 and the S1 pin of the bidirectional shift register U1. The inverting input of the voltage comparator CP4 is connected to the S0 pin of the bidirectional shift register U2; the inverting input of the voltage comparator CP4 is connected to the 2.4V reference voltage, and the output of the voltage comparator CP4 is respectively connected to the other input of the OR gate OR2 and the S1 pin of the bidirectional shift register U2; the output of the OR gate OR2 is connected to the CP pin of the bidirectional shift register U2; the two inputs of the OR gate OR3 are respectively connected to the Q0 pin of the bidirectional shift register U1 and the Q4 pin of the bidirectional shift register U2, and the output of the OR gate OR3 is connected to the signal receiving end of the dual N-channel MOS transistor M4; the two inputs of the OR gate OR4 are respectively connected to the bidirectional shift register The Q1 pin of the bit register U1 is connected to the Q5 pin of the bidirectional shift register U2, and the output end of the OR gate OR4 is connected to the signal receiving end of the dual N-channel MOS transistor M3; the two input ends of the OR gate OR5 are respectively connected to the Q2 pin of the bidirectional shift register U1 and the Q6 pin of the bidirectional shift register U2, and the output end of the OR gate OR5 is connected to the signal receiving end of the dual N-channel MOS transistor M2; the two input ends of the OR gate OR6 are respectively connected to the Q3 pin of the bidirectional shift register U1 and the Q7 pin of the bidirectional shift register U2, and the output end of the OR gate OR6 is connected to the signal receiving end of the dual N-channel MOS transistor M1. CP1 compares v1 with 3V to obtain the output signal v2, CP2 compares v1 with 2.6V to obtain the output signal v3, CP3 compares v1 with 2.4V to obtain the output signal v4, and CP4 compares v1 with 2V to obtain the output signal v5; G1 performs an OR operation on v2 and v3 to obtain the output signal v P+ ; G2 performs an OR operation on v4 and v5 to obtain the output signal v P-; U1's shift mode control terminals S1 and S0 are connected to v2 and v3 respectively, which are used to set whether U1 shifts left or right. U1's shift clock pulse terminal CP is connected to v P+ Connect the data input terminals D3, D2, D1, D0 and left shift data DSL of U1 to GND, and the reset terminal of U1 to The right shift data DSR is connected to VCC, and the output signals of U1's output terminals Q0, Q1, Q2, and Q3 are connected to the input terminals of OR3, OR4, OR5, and OR6 respectively; the shift mode control terminals S1 and S0 of U2 are connected to v4 and v5 respectively to set whether U2 shifts left or right. The shift clock pulse terminal CP of U2 is connected to v P- Connect the data input terminals D3, D2, D1, D0 and left shift data DSL of U2 to GND, and the reset terminal of U2 to The right-shifted data DSR is connected to VCC, and the output signals of U2's output terminals Q4, Q5, Q6, and Q7 are connected to the other input terminals of OR3, OR4, OR5, and OR6 respectively; OR3 performs an OR operation on Q0 and Q4 to obtain the drive signal X4 for M4; OR4 performs an OR operation on Q1 and Q5 to obtain the drive signal X3 for M3; OR5 performs an OR operation on Q2 and Q6 to obtain the drive signal X2 for M2; OR6 performs an OR operation on Q3 and Q7 to obtain the drive signal X1 for M1. CP1, CP2, OR1, and U1 in the CT matching resistor control module form the CT matching resistor control function in the charging mode, CP3, CP4, OR2, and U2 form the CT matching resistor control function in the discharge mode, and OR3, OR4, OR5, and OR6 realize the drive of the CT matching resistor control switches M1, M2, M3, and M4. The working principle is as follows:

[0033] In charging mode: CT output voltage v B The value of the voltage signal v1 at the OP output terminal is greater than 2.5V. B When the voltage v1 increases to a value greater than 3V, the output signal v2 of the voltage comparator CP1 changes from low level to high level, the output signal v3 of the voltage comparator CP2 remains at a low level, and the level state of the mode control terminal S1S0 of the bidirectional shift register U1 changes from 00 to 01, and U1 works in the right shift mode. p+ Connected to the CP terminal of U1, so v p+ It will delay the time jump a little bit more than v2. B When v1 is increased to be greater than 3V, S1S0 first changes from 00 to 01, setting U1 to right shift mode; then, the output signal v p+Generate a rising edge, the high level is shifted right to the output terminal Q0 of the bidirectional shift register U1, and Q1, Q2, and Q3 are shifted right one position in turn, and then a new 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit to reduce the conversion resistance when the current increases, ensuring i B Converted into a voltage signal of appropriate size v B As the conversion resistance decreases, v1 drops rapidly and becomes less than 3V, and the output signal v2 of CP1 changes from high level to low level. At the same time, by properly selecting the values ​​of R1, R2, R3, and R4, it can be ensured that the value of v1 drops rapidly is greater than 2.6V. Therefore, the level state of the mode control terminal S1S0 of the bidirectional shift register U1 changes from 01 to 00, and is in the hold mode. After this, if the current i B When v1 is increased further and becomes greater than 3V again, the high level is shifted right to the output terminal Q0 of the bidirectional shift register U1, and Q1, Q2, and Q3 are shifted right one position in turn. Then, another 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit, so that the conversion resistance is reduced when the current increases, ensuring that i B Converted into a voltage signal of appropriate size v B According to this principle, by analogy, when the current i B When it increases to make v1 greater than 3V, the high level will be shifted right one position in Q3, Q2, Q1, and Q0, and the corresponding 8205A tube will be turned on, and the CT matching resistance value will be reduced, and then v B with i B The magnification is reduced to ensure that v B The above process is repeated until the states of Q3, Q2, Q1, and Q0 become 1111, and v B with i B The magnification is the smallest, corresponding to i B Works in the maximum range. Similarly, when the current i B When v1 is reduced to less than 2.6V, the output signal v3 of the voltage comparator CP2 changes from low level to high level, the output signal v2 of the voltage comparator CP1 remains at a low level, and the level state of the mode control terminal S1S0 of the bidirectional shift register U1 changes from 00 to 10, and U1 works in the left shift mode. p+ Connected to the CP terminal of U1, so v p+ It will delay the time jump a little bit more than v3. B When v1 is reduced to less than 2.6V, S1S0 first changes from 00 to 10, setting U1 to left shift mode; then, the output signal v p+Generate a rising edge, the low level is shifted left to the output terminal Q3 of the bidirectional shift register U1, and Q2, Q1, and Q0 are shifted left one position in turn, and then the 8205A is turned off and the corresponding matching resistor is disconnected, so that the conversion resistance is increased when the current decreases, ensuring i B Converted into a voltage signal of appropriate size v B As the conversion resistance increases, v1 increases rapidly and exceeds 2.6V, and the output signal v3 of CP2 changes from high level to low level. At the same time, by properly selecting the values ​​of R1, R2, R3, and R4, it can be ensured that the value of v1 that increases rapidly is less than 3V. Therefore, the level state of the mode control terminal S1S0 of the bidirectional shift register U1 changes from 10 to 00, and is in the hold mode. After this, if the current i B When v1 is reduced further and becomes less than 2.6V again, the low level is shifted to the output terminal Q3 of the bidirectional shift register U1, and Q2, Q1, and Q0 are shifted to the left one position in turn, and then one 8205A is turned off and the corresponding matching resistor is disconnected, so that the conversion resistance is increased when the current decreases, ensuring that i B Converted into a voltage signal of appropriate size v B According to this principle, by analogy, when the current i B When it decreases to make v1 less than 2.6V, the low level is shifted left one position in Q3, Q2, Q1, and Q0, and the corresponding 8205A tube is turned off, and the CT matching resistance value is increased, and then v B with i B The magnification is increased, ensuring that v B The above process is repeated until the states of Q3, Q2, Q1, and Q0 become 0001, and v B with i B The magnification is the largest, corresponding to i B Minimum range.

[0034] In discharge mode: battery current i B In the reverse direction, the corresponding CT output voltage v B Less than zero, the value of the voltage signal v1 at the output of OP1 is less than 2.5V. B When the voltage increases to the point where v1 is less than 2V, the output signal v4 of the voltage comparator CP3 changes from low level to high level, the output signal v5 of the voltage comparator CP4 remains at a low level, and the level state of the mode control terminal S1S0 of the bidirectional shift register U2 changes from 00 to 01, and U2 works in the right shift mode. p- Connected to the CP terminal of U2, so v p- It will delay the time jump a little bit more than v4. BWhen it increases to the point where v1 is less than 2V, S1S0 first changes from 00 to 01, setting U2 to right shift mode; then, the output signal v of OR2 p- Generate a rising edge, the high level is shifted right to the output terminal Q4 of the bidirectional shift register U2, and Q5, Q6, and Q7 are shifted right one position in turn, and then a new 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit to reduce the conversion resistance when the current increases, ensuring i B Converted into a voltage signal of appropriate size v B As the conversion resistance decreases, v1 increases rapidly and becomes greater than 2V, and the output signal v4 of CP3 changes from high level to low level. At the same time, by properly selecting the values ​​of R1, R2, R3, and R4, v1 can be guaranteed to be less than 2.4V. Therefore, the level state of the mode control terminal S1S0 of the bidirectional shift register U2 changes from 01 to 00, and it is in the hold mode. After this, if the current i B When v1 is further increased to be less than 2V again, the high level is shifted right to the output terminal Q4 of the bidirectional shift register U2, and Q5, Q6, and Q7 are shifted right one position in turn. Then, another 8205A is turned on, and the corresponding matching resistor is connected in parallel to the circuit to reduce the conversion resistance when the current increases, ensuring that i B Converted into a voltage signal of appropriate size v B According to this principle, by analogy, when the current i B When it increases to make v1 less than 2V, the high level will be shifted right one position in Q7, Q6, Q5, and Q4, and the corresponding 8205A tube will be turned on, and the CT matching resistance value will be reduced, and then v B with i B The magnification is reduced to ensure that v B The above process is repeated until the states of Q7, Q6, Q5, and Q4 become 1111, and v B with i B The magnification is the smallest, corresponding to i B Works in the maximum range. Similarly, when the current i B When v1 is reduced to a value greater than 2.4V, the output signal v5 of the voltage comparator CP4 changes from low level to high level, the output signal v4 of the voltage comparator CP3 remains at a low level, and the level state of the mode control terminal S1S0 of the bidirectional shift register U2 changes from 00 to 10, and U2 works in the left shift mode. p- Connected to the CP terminal of U2, so v p- It will delay the time jump a little bit more than v5. BWhen v1 is reduced to be greater than 2.4V, S1S0 first changes from 00 to 10, setting U2 to left shift mode; then, the output signal v p- Generate a rising edge, the low level is shifted left to the output terminal Q7 of the bidirectional shift register U2, and Q6, Q5, and Q4 are shifted left one position in turn, and then the 8205A is turned off and the corresponding matching resistor is disconnected, so that the conversion resistance is increased when the current decreases, ensuring i B Converted into a suitable voltage signal v B As the conversion resistance increases, v1 decreases rapidly and becomes less than 2.4V, and the output signal v5 of CP4 changes from high level to low level. At the same time, by properly selecting the values ​​of R1, R2, R3, and R4, v1 can be guaranteed to be greater than 2V. Therefore, the level state of the mode control terminal S1S0 of the bidirectional shift register U2 changes from 10 to 00, and is in the hold mode. After this, if the current i B When v1 is further reduced to be greater than 2.4V again, the low level is shifted left to the output terminal Q7 of the bidirectional shift register U2, and Q6, Q5, and Q4 are shifted left one position in turn, and then one 8205A is turned off and turned on, and the corresponding matching resistor is disconnected, so that the conversion resistance is increased when the current decreases, ensuring that i B Converted into a suitable voltage signal v B According to this principle, by analogy, when the current i B When it decreases to make v1 greater than 2.4V, the low level is shifted left by one position in Q7, Q6, Q5, and Q4, and the corresponding 8205A tube is turned off, and the CT matching resistance value is increased, and then v B with i B The magnification is increased, ensuring that v B The above process is repeated until the states of Q7, Q6, Q5, and Q4 become 0001, and v B with i B The magnification is the largest, corresponding to i B Minimum range.

[0035] Based on the attached Figure 1 and Figure 2 The voltage detection circuit and current signal conditioning circuit shown in the figure are Figure 1 The main control chip in the SOC estimation module can obtain the open circuit voltage value VOC of the battery after it is at rest and the charge and discharge current value i during operation in real time. B , and then the SOC value of the battery at any time can be obtained. Therefore, the implementation principle and steps of SOC state estimation are as follows:

[0036] Step 1: When the battery starts working, the SOC estimation module obtains the open circuit voltage VOC of the battery pack and calculates the battery SOC value based on the pre-stored battery model and VOC data, and uses it as the initial value SOC0;

[0037] In this step, the pre-stored battery model is usually in the form of an open circuit voltage (VOC)-SOC mapping table combined with capacity parameters, for example:

[0038] Lithium battery model parameter table

[0039] SOC (%) VOC(V) Capacity(Ah) 100 4.20 200 90 4.15 200 80 4.10 200 ... ... ... 20 3.60 200 10 3.40 200 0 3.00 200

[0040] Model application logic:

[0041] Initial SOC calculation: After the battery is at rest, measure the VOC (e.g., 3.85V) and look up the corresponding SOC value (e.g., 65%).

[0042] The model establishes a monotonic correspondence between VOC and SOC through experimental data. It is applicable to common battery types such as lithium iron phosphate and ternary lithium, and has the advantages of fast table lookup speed and low computational complexity.

[0043] Step 2: After the battery starts working, the current signal conditioning circuit realizes a wide range of current i by adaptive resistor switching. B The SOC estimation module then calculates the current i B The SOC value of the battery at any time is calculated using the ampere-hour integration method.

[0044] The specific process of calculating the SOC value of the battery at any time is as follows:

[0045] Step 2.1: Obtain the driving signal state values ​​of the dual N-channel MOS transistors M1, M2, M3, and M4 in the current conditioning circuit, and then determine the equivalent matching resistance value R of the current transformer CT in the current-to-voltage module. CT ;

[0046] Step 2.2, obtain the value of the output signal v1 of the operational amplifier OP in the current conditioning circuit, according to v B =v1-2.5 to get the output signal v of the current-to-voltage module B The value of

[0047] Step 2.3: Based on the current transformer CT current attenuation coefficient K CT and CT equivalent matching resistance R CT , calculate the battery current i B =v B / K CT R CT ;

[0048] Step 2.4: Use the ampere-hour integration method to calculate the increment of SOC at time k, that is, calculate ΔSOC k =i B (k)T value; where k is the calculation time of the increment, T is the interval time of the increment calculation, and the corresponding time t at the k moment k =kT;

[0049] Step 2.5, BMS based on SOC k =SOC k-1 +i B (k)T calculates the SOC value at time k, where: k ≥ 1.

[0050] In summary, the present invention realizes battery SOC detection by combining the open circuit voltage method and the ampere-hour integration method, which has the advantages of being simple, practical and accurate.

Claims

1. A SOC state estimation system for a BMS, characterized by: The system includes a current signal conditioning circuit, a voltage detection circuit and an SOC estimation module; the input end of the current signal conditioning circuit is connected to the positive electrode of the battery pack; the input end of the voltage detection circuit is connected to the positive and negative electrodes of the battery pack respectively; the voltage detection circuit is used to obtain the open circuit voltage VOC of the battery pack and is connected to the data sampling port of the SOC estimation module; the current signal conditioning circuit is used to detect the current of the battery pack , and connected to the data sampling port of the SOC estimation module; The SOC estimation module calculates the initial value SOC0 of the battery pack during operation based on a pre-stored battery model and open-circuit voltage VOC, and calculates the SOC value of the battery at any time based on the current and ampere-hour integration method. Before the battery pack is operated, the initial state of the battery at each operation is calculated by measuring the open-circuit voltage of the battery pack. After operation begins, the battery pack's charge and discharge current is measured with high precision and integrated over time to obtain the change in the battery state, thereby calculating the state value of the battery at any time during operation. The current signal conditioning circuit includes a current-to-voltage module, a DC bias circuit, and a CT matching resistance control module; The current-to-voltage module consists of a current transformer (CT), a parallel controllable matching resistor network, and a TVS protection circuit, and is used to convert the battery loop current into a proportional voltage signal. The DC bias circuit consists of an operational amplifier (OP) and an equivalent resistor network, which receives the voltage signal output by the current-to-voltage module and outputs a positive unipolar voltage after applying a reference bias. The CT matching resistor control module includes a voltage comparator array, a logic gate circuit, and a bidirectional shift register group. It monitors the voltage amplitude output by the DC bias circuit in real time and stabilizes the output voltage within the measurement range of the ADC by dynamically switching the parallel branches of the controllable matching resistor network. The current conditioning circuit is based on the battery current The value of the CT is automatically adjusted to ensure the matching resistance of the Converted voltage signal In the appropriate voltage range; The current-to-voltage module includes a current transformer CT, a matching resistor R1, a matching resistor R2, a matching resistor R3, a matching resistor R4, a dual N-channel MOS transistor M1, a dual N-channel MOS transistor M2, a dual N-channel MOS transistor M3, a dual N-channel MOS transistor M4 and a bidirectional TVS transistor D1; the input side of the current transformer CT receives the current of the battery pack One end of the output side of the current transformer CT is respectively connected to one end of a matching resistor R1, one end of a matching resistor R2, one end of a matching resistor R3, one end of a matching resistor R4, and one end of a bidirectional TVS transistor D1; the other end of the matching resistor R1 is connected to one end pin of a dual N-channel MOS transistor M1, and the other end pin of the dual N-channel MOS transistor M1 is grounded; the other end of the matching resistor R2 is connected to one end pin of a dual N-channel MOS transistor M2, and the other end pin of the dual N-channel MOS transistor M2 is grounded; the other end of the matching resistor R3 is connected to one end pin of a dual N-channel MOS transistor M3, and the other end pin of the dual N-channel MOS transistor M3 is grounded; the other end of the matching resistor R4 is connected to one end pin of a dual N-channel MOS transistor M4, and the other end pin of the dual N-channel MOS transistor M4 is grounded; the other end of the bidirectional TVS transistor D1 is grounded; the dual N-channel MOS transistors M1, M2, M3, and M4 are also connected to a CT matching resistor control module.

2. The SOC state estimation system for a BMS according to claim 1, characterized in that: The DC bias circuit includes an operational amplifier OP, four resistors with the same resistance value, namely R5, R6, R7 and R8; the non-inverting input terminal of the operational amplifier OP is respectively connected to one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected to the output end of the current-to-voltage module, and the other end of the resistor R6 is connected to a 2.5V reference voltage; the inverting input terminal of the operational amplifier OP is connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is grounded, and the other end of the resistor R8 is connected to the output end of the operational amplifier OP.

3. The SOC state estimation system for a BMS according to claim 2, characterized in that: The CT matching resistance control module includes a voltage comparator CP1, a voltage comparator CP2, a voltage comparator CP3, a voltage comparator CP4, an OR gate OR1, an OR gate OR2, an OR gate OR3, an OR gate OR4, an OR gate OR5, an OR gate OR6, a bidirectional shift register U1 and a bidirectional shift register U2; the non-inverting input terminal of the voltage comparator CP1, the inverting input terminal of the voltage comparator CP2, the inverting input terminal of the voltage comparator CP3 and the non-inverting input terminal of the voltage comparator CP4 are respectively connected to the output terminal of the operational amplifier OP; the inverting input terminal of the voltage comparator CP1 is connected to the 3V reference The output end of the voltage comparator CP1 is connected to an input end of the OR gate OR1 and the S0 pin of the bidirectional shift register U1; the non-inverting input end of the voltage comparator CP2 is connected to the 2.6V reference voltage, and the output end of the voltage comparator CP2 is connected to the other input end of the OR gate OR1 and the S1 pin of the bidirectional shift register U1; the output end of the OR gate OR1 is connected to the CP pin of the bidirectional shift register U1; the non-inverting input end of the voltage comparator CP3 is connected to the 2V reference voltage, and the output end of the voltage comparator CP3 is connected to an input end of the OR gate OR2 and the S1 pin of the bidirectional shift register U1. The inverting input of the voltage comparator CP4 is connected to the S0 pin of the bidirectional shift register U2; the inverting input of the voltage comparator CP4 is connected to the 2.4V reference voltage, and the output of the voltage comparator CP4 is respectively connected to the other input of the OR gate OR2 and the S1 pin of the bidirectional shift register U2; the output of the OR gate OR2 is connected to the CP pin of the bidirectional shift register U2; the two inputs of the OR gate OR3 are respectively connected to the Q0 pin of the bidirectional shift register U1 and the Q4 pin of the bidirectional shift register U2, and the output of the OR gate OR3 is connected to the signal receiving end of the dual N-channel MOS transistor M4; the two inputs of the OR gate OR4 are respectively connected to the bidirectional shift register The Q1 pin of the bit register U1 is connected to the Q5 pin of the bidirectional shift register U2, and the output end of the OR gate OR4 is connected to the signal receiving end of the dual N-channel MOS transistor M3; the two input ends of the OR gate OR5 are respectively connected to the Q2 pin of the bidirectional shift register U1 and the Q6 pin of the bidirectional shift register U2, and the output end of the OR gate OR5 is connected to the signal receiving end of the dual N-channel MOS transistor M2; the two input ends of the OR gate OR6 are respectively connected to the Q3 pin of the bidirectional shift register U1 and the Q7 pin of the bidirectional shift register U2, and the output end of the OR gate OR6 is connected to the signal receiving end of the dual N-channel MOS transistor M1.

4. The SOC state estimation method for a BMS according to any one of claims 1 to 3, characterized in that: The steps include: Step 1: When the battery starts working, the SOC estimation module obtains the open circuit voltage VOC of the battery pack and calculates the battery SOC value based on the pre-stored battery model and VOC data, and uses it as the initial value SOC0; Step 2: After the battery starts working, the current signal conditioning circuit realizes a wide range of current through adaptive resistance switching The SOC estimation module then calculates the current The SOC value of the battery at any time is calculated using the ampere-hour integration method.

5. The SOC state estimation method for a BMS according to claim 4, characterized in that: The specific process of calculating the SOC value of the battery at any time is as follows: Step 2.1: Obtain the driving signal state values ​​of the dual N-channel MOS transistors M1, M2, M3, and M4 in the current conditioning circuit, and then determine the equivalent matching resistance value of the current transformer CT in the current-to-voltage module. ; Step 2.2: Get the output signal of the operational amplifier OP in the current conditioning circuit The value of Get the output signal of the current-to-voltage module The value of Step 2.3: Based on the current attenuation coefficient of the current transformer CT and CT equivalent matching resistance , calculate the battery current ; Step 2.4: Use the ampere-hour integration method to calculate the increment of SOC at time k, that is, calculate ; where: is the calculation time of the increment, The interval time for incremental calculation, the corresponding time at moment k ; Step 2.5, BMS basis Calculate the SOC value at time k, where: .

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