Time synchronization testing of cascaded radar transceiver chips

Abstract

A radar system employs self-testing to determine time synchronization of cascaded radar transceiver integrated circuits (ICs) used in a motor vehicle in the radar system. In order to efficiently detect information in an environment, the radar system periodically performs self-test operations by transmitting a trigger signal to at least one follower radar transceiver IC. In addition, the guide radar transceiver IC generates a chirp signal at a set frequency and transmits this chirp signal. In response to receiving the trigger signal, the at least one follower radar transceiver IC receives the chirp signal transmitted from the guide and generates its own local chirp signal at the set frequency, but also includes a frequency offset. The received signal is then down-converted to an intermediate frequency (IF) signal using the local chirp signal. The IF signal is filtered, analog-to-digital converted, and processed to determine a beat frequency. The beat frequency is compared to the frequency offset to determine a level of synchronization between the director radar transceiver IC and the at least one follower radar transceiver IC.

Description

Technical Field

[0001] Relates to radar. Background Art

[0002] The radar system of a motor vehicle frequently performs self-tests to determine the operating status and meet functional safety standards. The functional safety standards include the operation of the hardware and / or software of the motor vehicle, such as a radar system operating within a normal range. During the self-test, one or more radar transceiver chips of the radar system are inspected for errors that prevent the safe operation of the motor vehicle. The connection of multiple radar transceiver chips includes a leader radar transceiver IC and one or more follower radar transceiver ICs. To ensure the safe operation of the motor vehicle, the leader radar transceiver IC sends a trigger signal to check the time synchronization between the leader radar transceiver IC and the follower radar transceiver IC by using a chirp signal. In response to the trigger signal, the follower radar transceiver IC sends a loopback signal to the leader radar transceiver IC to check the timing between the loopback signal and the chirp signal. However, in order to adopt the loopback signal, additional wiring is added between the leader radar transceiver IC and the follower radar transceiver IC. Summary of the Invention

[0003] Provided is a method, characterized by including: sending, by a first radar transceiver integrated circuit (IC), a trigger signal; in response to receiving the trigger signal, generating and sending, by the first radar transceiver IC, a chirp signal having a set frequency; in response to receiving the trigger signal from the first radar transceiver IC, receiving the chirp signal, and generating, by at least one second radar transceiver IC, a local chirp signal, the local chirp signal being parameterized by the sum of the set frequency and a frequency offset to down-convert the received chirp signal into an intermediate frequency (IF) signal; and determining the synchronization level between the first radar transceiver IC and the at least one second radar transceiver IC based on comparing a beat frequency with the frequency offset.

[0004] In one or more embodiments, generating the local chirp signal includes generating the frequency offset within a frequency range between a high-pass filter cut-off frequency and a low-pass filter cut-off frequency.

[0005] In one or more embodiments, the at least one second radar transceiver IC marks a functional safety error in response to the beat frequency exceeding the frequency range.

[0006] In one or more embodiments, generating the local chirp signal includes: generating, by a frequency synthesizer of the at least one second radar transceiver IC, the local chirp signal.

[0007] In one or more embodiments, generating the local chirp signal by the frequency synthesizer is performed during a test mode.

[0008] In one or more embodiments, the beat frequency includes the difference between the chirp signal received by the at least one second radar transceiver IC and the local chirp signal.

[0009] In one or more embodiments, comparing the beat frequency with the frequency offset includes: determining the signal strength of the received chirp signal; and in response to the signal strength exceeding a power threshold, determining the beat frequency for comparison with the frequency offset.

[0010] In one or more embodiments, generating the local chirp signal occurs simultaneously with the generation and transmission of the chirp signal.

[0011] There is also provided a radar system, characterized by comprising: at least one second radar transceiver integrated circuit (IC), configured to receive a chirp signal transmitted from a first radar transceiver IC and generate a local chirp signal parameterized by a set frequency and a frequency offset in response to a trigger signal received from the first radar transceiver IC, to test the synchronization level between the first radar transceiver IC and the at least one second radar transceiver IC based on comparing the beat frequency with the frequency offset.

[0012] In one or more embodiments, the at least one second radar transceiver IC is further configured to: generate the frequency offset within a frequency range between a high-pass filter cut-off frequency and a low-pass filter cut-off frequency.

[0013] In one or more embodiments, the at least one second radar transceiver IC is further configured to: mark a functional safety error in response to the beat frequency exceeding the frequency range.

[0014] In one or more embodiments, the at least one second radar transceiver IC is further configured to: generate the local chirp signal by a frequency synthesizer.

[0015] In one or more embodiments, the at least one second radar transceiver IC is further configured to: generate the local chirp signal by the frequency synthesizer during a test mode.

[0016] In one or more embodiments, the at least one second radar transceiver IC is further configured to: determine the beat frequency based on the difference between the received chirp signal and the local chirp signal.

[0017] In one or more embodiments, the at least one second radar transceiver IC is further configured to: determine a signal strength of the received chirp signal; and in response to the signal strength exceeding a power threshold, determine the beat frequency for comparison with the frequency offset.

[0018] In one or more embodiments, the first radar transceiver IC is cascaded with the at least one second radar transceiver IC.

[0019] A method is provided, comprising: sending, by a first radar transceiver integrated circuit (IC), a trigger signal; generating and sending a chirp signal based on a set frequency and determined by a first synthesizer of the first radar transceiver IC; receiving, by a plurality of second radar transceiver ICs, the chirp signal, and in response to receiving the trigger signal from the first radar transceiver IC, generating, by a second synthesizer of each of the plurality of second radar transceiver ICs, a local chirp signal based on the set frequency and a frequency offset; and marking a functional error in response to the beat frequency being different from the frequency offset.

[0020] In one or more embodiments, the trigger signal is sent before or after normal operation of the first radar transceiver IC and the plurality of second radar transceiver ICs.

[0021] In one or more embodiments, further comprising: down-converting the chirp signal to an intermediate frequency (IF) signal using the local chirp signal.

[0022] In one or more embodiments, marking a functional error includes: comparing the beat frequency at each of the plurality of second radar transceiver ICs with the frequency offset to determine a difference between the beat frequency and the frequency offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present disclosure can be better understood by reference to the accompanying drawings, and the numerous features and advantages thereof will be apparent to those skilled in the art. Like reference numerals are used in the different figures to indicate similar or identical items.

[0024] Figure 1 is a block diagram of a radar system that, according to some embodiments, implements a leader radar transceiver IC that sends a trigger signal to a plurality of follower radar transceiver ICs.

[0025] Figure 2 is a block diagram of a part of a radar system that, according to some embodiments, implements a leader radar transceiver IC cascaded with follower radar transceiver ICs.

[0026] Figure 3A graph of the frequency range of the offset frequency according to some embodiments.

[0027] Figure 4 A graph of performing a test mode during the transmission of a trigger signal according to some embodiments.

[0028] Figure 5 A flowchart of a method for testing signal strength and time synchronization between a leader radar transceiver IC and a follower radar transceiver IC according to some embodiments.

[0029] Figure 6 A flowchart of a method for testing time synchronization between a leader radar transceiver IC and a follower radar transceiver IC according to some embodiments. Detailed Description

[0030] Figure 1-6 Systems and techniques for time synchronization of cascaded radar transceiver integrated circuits (ICs) used in motor vehicles in a radar system are shown. For simplicity in manufacturing, radar transceiver ICs typically include a relatively small number (e.g., four) of antennas to transmit and / or receive signals. To overcome the limited number of antennas and improve the detection capabilities of the radar system, the radar transceiver ICs are cascaded (i.e., connected to each other, where one IC acts as a leader and the other ICs act as followers) to increase the number of antennas for transmitting and / or receiving signals. For example, a leader radar transceiver IC in a radar system of a motor vehicle transmits a chirp signal, and each radar transceiver IC (both leader and followers) listens for the return of the at least one signal after the at least one signal bounces or reflects off an object, a person, or another vehicle. After receiving the at least one signal, the leader transceiver IC transmits information about the object (e.g., distance, speed, or other information) for further processing by the control system of the motor vehicle. The data detected by the radar system in the environment provides a visualization of the environment for the motor vehicle, which serves as a safety measure.

[0031] The radar system provides input data for the control system of a motor vehicle during autonomous driving. Additionally, the radar system supports the functional safety of the motor vehicle and is specifically used by the motor vehicle to mitigate hazards in the environment by warning passengers in the motor vehicle or sending a warning to a remote device (e.g., a computing device, a telephone, a tablet computer) using a communication system. To effectively detect information in the environment and provide such functional safety, the radar system periodically performs a self-diagnostic operation by transmitting a trigger signal to the at least one follower radar transceiver IC in response to an event, which in some embodiments includes the initiation of the trigger signal, a timer within the IC, software, etc. Additionally, the leader radar transceiver IC generates a chirp signal at a set frequency and transmits this chirp signal. In response to receiving the trigger signal, the at least one follower radar transceiver IC receives the chirp signal sent from the leader and generates its own local chirp signal at the set frequency, but also includes a frequency offset. The received signal is then down-converted to an intermediate frequency (IF) signal using the local chirp signal. The IF signal is filtered, analog-to-digital converted (A / D converted), and processed to determine the beat frequency.

[0032] The beat frequency is compared with the frequency offset to determine the synchronization level between the leader radar transceiver IC and the at least one follower radar transceiver IC. If the beat frequency matches the frequency offset, the leader radar transceiver IC and the at least one follower radar transceiver IC are confirmed to be time-synchronized. However, if the beat frequency does not match the frequency offset, the leader radar transceiver IC and the at least one follower radar transceiver IC are asynchronous at that time. Thus, by measuring the beat frequency, the synchronization between the leader radar transceiver IC and the at least one follower radar transceiver IC is determined. Additionally, through the application of the frequency offset, time synchronization is tested without adding additional hardware to the radar system. And, using the techniques herein, the loopback path (i.e., the wiring connection between input / output (I / O) ports) used in conventional cascaded radar transceiver ICs is not required.

[0033] In a conventional cascaded radar transceiver IC, the at least one follower radar transceiver IC has a synthesizer (i.e., a local oscillator or LO) that is deactivated such that the follower radar transceiver IC does not generate its own chirp signal. In contrast, using the techniques described herein, the synthesizer of the at least one follower radar transceiver IC is enabled. The leader radar transceiver IC transmits a trigger signal to the at least one follower radar transceiver IC to start operation. At the same time, the leader radar transceiver IC generates a chirp signal using its own synthesizer. Subsequently, the at least one follower radar transceiver IC applies a frequency offset to the set frequency using its own synthesizer to generate a chirp signal.

[0034] By applying a frequency offset to a chirp signal using a synthesizer of the at least one follower radar transceiver IC, the time synchronization of the radar ICs of a radar system can be tested. To provide an acceptable safety margin, it is desirable for the radar system to be operable for the vast majority of the time (e.g., more than 99%) during which a motor vehicle is in operation, as the motor vehicle receives information from the radar system to visualize and identify hazards in the environment. Additionally, the radar system is employed by a control system during autonomous driving. To identify the operating state of the radar system, a master radar transceiver IC transmits a trigger signal to the at least one follower radar transceiver IC. However, due to various reasons, the responsiveness of the at least one follower radar transceiver IC is uncertain. For example, the motor vehicle is operating in a noisy environment while in motion (i.e., driving), which affects the reception of the trigger signal by the at least one follower. Additionally, in some cases, the at least one follower radar transceiver IC has faulty hardware (e.g., an antenna) that blocks or delays the reception of the trigger signal. In any of the foregoing scenarios, the at least one follower radar transceiver IC is affected, which impacts the reception of the trigger signal. The blocking and / or delaying of the reception of the trigger signal correspondingly blocks and / or delays operations on the at least one follower radar transceiver IC. In some cases, the at least one follower radar transceiver IC is prematurely triggered due to electromagnetic interference, which results in premature operation of the at least one follower radar transceiver IC. Consequently, the synchronization between the master radar transceiver IC and the at least one follower radar transceiver IC is affected. Therefore, poor synchronization between the master radar transceiver IC and the at least one follower radar transceiver IC prevents the proper combination of data of the detected environment, and the radar system cannot be relied upon. Thus, testing the time synchronization between the master radar transceiver IC and the at least one follower radar transceiver IC improves the identification of the reliability of the radar system.

[0035] Figure 1FIG. 0 shows a block diagram of a radar system 100 showing a master radar transceiver IC 102 (i.e., a radar sensor) according to some embodiments, the master radar transceiver IC 102 sending a trigger signal 108 to a plurality of slave radar transceiver ICs 104 and 106 (i.e., radar sensors). In the depicted example, radar system 100 includes master radar transceiver IC 102 and slave radar transceiver ICs 104 and 106. It should be understood that in some embodiments, there is only a single slave radar transceiver IC, such as slave radar transceiver IC 104 or 106. However, in some embodiments, there are more than two slave radar transceiver ICs 104 and 106. In various embodiments, radar system 100 is connected to a motor vehicle (not shown) to provide environmental data around the motor vehicle. In other words, radar system 100 is part of a motor vehicle to detect the environment around the motor vehicle. For example, radar system 100 is used to detect objects, people, other motor vehicles, etc.

[0036] In various embodiments, master radar transceiver IC 102 is connected to slave radar transceiver ICs 104 and 106. Specifically, master radar transceiver IC 102 is cascaded with slave radar transceiver ICs 104 and 106. In other words, master radar transceiver IC 102 is directly connected or linked to slave radar transceiver ICs 104 and 106, for example by connecting one or more output ports of master radar transceiver IC 102 to one or more input ports of slave radar transceiver ICs 104 and 106. By cascading master radar transceiver IC 102 with slave radar transceiver ICs 104 and 106, the detection ability of radar system 100 to detect data in the environment is improved due to the increased number of radar sensors for sending and / or receiving data. To control the operation of master radar transceiver IC 102 and slave radar transceiver ICs 104 and 106, master radar transceiver IC 102 transmits trigger signal 108 to slave radar transceiver ICs 104 and 106 via a dedicated line (i.e., a direct connection) in response to an event. For example, in some embodiments, the event includes the initiation of trigger signal 108, a timer within the IC, software, an input received by master radar transceiver IC 102 from an external control device (e.g., a computer, a terminal, a phone), etc. In other words, master radar transceiver IC 102 uses trigger signal 108 as a start signal or command to slave radar transceiver ICs 104 and 106 to start additional operations. In addition, slave radar transceiver ICs 104 and 106 start the same operations as master radar transceiver IC 102 in response to trigger signal 108, such as test or normal radar detection, as will be described in more detail below.

[0037] In the depicted example, each of the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 includes a mode switch 110. It should be understood that although the mode switch 110 is shown as part of the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106, in some embodiments, all or a part of the mode switch 110 is a separate component and / or is separated from the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106. In various embodiments, the mode switch 110 is used to control operations on the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106. The leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 perform normal detection of the environment around the motor vehicle in response to receiving a trigger signal 108 and the mode switch 110 being set to a first setting (e.g., normal detection mode). Additionally, the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 perform a self-test or self-diagnosis in response to receiving the trigger signal 108 and the mode switch 110 being set to a second setting (e.g., test mode, built-in self-test or BIST). The self-test or test mode ensures the operation of the follower radar transceiver ICs 104 and 106 relative to the leader radar transceiver IC 102. Specifically, the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 select the test mode via the mode switch 110. The test mode is used to determine the successful and / or timely receipt of the trigger signal 108 by the follower radar transceiver ICs 104 and 106. The successful and / or timely receipt of the trigger signal by the follower radar transceiver ICs 104 and 106 enables the successful and / or timely operation of the follower radar transceiver ICs 104 and 106. In addition, the successful and / or timely receipt of the trigger signal 108 by the follower radar transceiver ICs 104 and 106 indicates time-synchronized operation between the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106. To operate within the safety margins established by the manufacturer and / or the motor vehicle industry, the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 use the test mode to ensure the receipt of the trigger signal 108 in a time-synchronized manner. The safety margin includes functional safety, which is a standard for motor vehicle components determined by the manufacturer and / or the motor vehicle industry to operate under certain conditions to ensure the safety of the motor vehicle. By way of illustration, the motor vehicle operates (i.e., drives) on roads and / or other locations that subject the motor vehicle to external factors (e.g., unexpected movement (e.g., rocking, bouncing), wind noise, noise from the environment, etc.). The external factors affect the receipt of the trigger signal 108 by the follower radar transceiver ICs 104 and 106, which prevents and / or delays the receipt of the trigger signal 108.The prevention and / or delay of the reception of the trigger signal 108 thus prevents and / or delays the response of the follower radar transceiver ICs 104 and 106. As a result, the radar system 100 is affected, and inaccurate detection of the radar system 100 occurs. Accordingly, based on the foregoing example scenario, the functional safety of the radar system 100 is affected because it does not provide accurate data for use in a motor vehicle.

[0038] During the test mode, the leader radar transceiver IC 102 issues a trigger signal 108, which is received by the follower radar transceiver ICs 104 and 106. After a predefined time period, the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 are started simultaneously. The leader radar transceiver IC 102 generates a chirp signal at a set frequency (denoted herein as f CS,Leader ). It should be noted that the chirp signal is characterized by a frequency (fCS), a duration T, and a bandwidth B. The chirp slope is derived as K f = B / T. Additionally, in response to receiving the chirp signal, the follower radar transceiver ICs 104 and 106 generate their own local chirp signals. The local chirp signals are parameterized by the sum of the set frequency (f CS,Leader ) and the frequency offset (Δf Nominal ), which is defined as f CS,Follower = f CS,Leader + Δf Nominal . The follower radar transceiver ICs 104 and 106 receive the chirp signal from the leader transceiver IC 102 and down-convert it to an IF signal using the local chirp signal. The follower radar transceiver ICs 104 and 106 filter and convert the resulting IF signal (e.g., A / D conversion) to determine the beat frequency (i.e., the frequency difference between the received chirp signal and the local chirp signal used for down-conversion). The follower radar transceiver ICs 104 and 106 compare the beat frequency with the frequency offset to determine the synchronization level between the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 such that the beat frequency is within a certain frequency range relative to the frequency offset. Specifically, the difference between the beat frequency and the frequency offset is calculated by each of the follower radar transceiver ICs 104 and 106 to identify whether the beat frequency is within the frequency range. For example, the follower radar transceiver IC 104 and the follower radar transceiver IC 106 individually and separately confirm time synchronization or “in sync” with the leader radar transceiver IC 102 in response to the beat frequency matching the frequency offset within the frequency range, which is expressed as f Beat = Δf Nominal ± f thresholdThus, the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 are identified as time-synchronized during any round of the test mode. Alternatively, the follower radar transceiver IC 104 and the follower radar transceiver IC 106 individually and separately confirm time-asynchrony or “asynchronous” with the leader radar transceiver IC 102 in response to the beat frequency exceeding the frequency range (i.e., exceeding the synchronization threshold) and thus being frequency-offset mismatched during any round of the test mode. All of the above processes occur simultaneously within a single chirp period (i.e., during the transmission of the chirp signal from the leader radar transceiver IC 102). In the case where the follower radar transceiver ICs 104 and 106 experience any time delay (Δt L2F ), the down-converted received signal (i.e., the IF signal) is expressed as f Beat = Δf Nominal + Δt L2F * K f . It should be understood that the foregoing examples have been described for ease of understanding, and the reverse situation is also possible. In other words, during the first round of the test mode, the leader radar transceiver IC 102 is time-asynchronous with the follower radar transceiver ICs 104 and 106, and during the second round of the test mode, the leader radar transceiver IC 102 is time-synchronized with the follower radar transceiver ICs 104 and 106.

[0039] As described above, the radar system 100 needs to operate safely in function. Therefore, in order to ensure functional safety, the periodic and repeated testing of synchronization between the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 identifies errors and / or delays in the radar system 100. The test mode selected at the leader radar transceiver IC 102 is executed before normal radar sensor operation or after normal radar sensor operation (i.e., normal detection mode). These aforementioned example scenarios identify poor functional safety (i.e., functional safety that does not meet the minimum safety standards for safe motor vehicle operation), and the radar system 100 cannot detect correct information in the environment. In other words, the follower radar transceiver ICs 104 and 106 operate asynchronously with the leader radar transceiver IC 102 time, so that any data detected in the environment is inaccurate. To illustrate, at time T0, the leader radar transceiver IC 102 detects an external vehicle at position A after receiving the chirp signal, while at time T1 and / or T2, at least one of the follower radar transceiver ICs 104 and 106 detects the external vehicle at position B after receiving the local chirp signal, which does not accurately reflect the position of the external vehicle because the data detected by the leader radar transceiver IC 102 is different from the data detected by the follower radar transceiver ICs 104 and 106.

[0040] In various embodiments, the leader radar transceiver IC 102 includes a plurality of transmitter antennas 112 and a plurality of receiver antennas 113. Similarly, in various embodiments, the follower radar transceiver IC 104 includes a plurality of transmitter antennas 114 and a plurality of receiver antennas 115. Finally, in various embodiments, the follower radar transceiver IC 106 includes a plurality of transmitter antennas 116 and a plurality of receiver antennas 117. In the depicted example, each of the plurality of transmitter antennas 112, 114, 116 and each of the plurality of receiver antennas 113, 115, 117 are shown as a single antenna. However, it should be understood that the plurality of transmitter antennas 112, 114, 116 and the plurality of receiver antennas 113, 115, 117 are each more than a single antenna. With respect to Figure 1 For ease of description and understanding, the plurality of transmitter antennas 112, 114, 116 and the plurality of receiver antennas 113, 115, 117 depict a single antenna. In addition, the plurality of transmitter antennas 114 and 116 on the follower radar transceiver ICs 104 and 106 are deactivated. In the depicted example, the leader radar transceiver IC 102 transmits a trigger signal 108 to the follower radar transceiver ICs 104 and 106, respectively.

[0041] Figure 2A block diagram showing a portion of a radar system 200 implementing a leader radar transceiver IC 102 cascaded with a follower radar transceiver IC 104 according to some embodiments. The radar system 200 may implement aspects of the radar system 100 described in reference Figure 1 or be implemented by aspects of the radar system 100 described in reference Figure 1 In the depicted example, the plurality of transmitter antennas 112 includes transmitter antenna 112-1 and transmitter antenna 112-2. The plurality of receiver antennas 113 includes receiver antenna 113-1 and receiver antenna 113-2. In various embodiments, the leader radar transceiver IC 102 includes a timing engine 220, and the follower radar transceiver IC 104 includes a timing engine 222. The timing engine 220 is used by the leader radar transceiver IC 102 for local timing control and to ensure timing synchronization with the follower radar transceiver IC 104. In addition, the timing engine 220 starts the generation of a chirp signal. The timing engine 220 transmits a trigger signal 108 to the timing engine 222 such that all components within the follower radar transceiver IC 104 operate simultaneously with all components in the leader radar transceiver IC 102. Additionally, the follower radar transceiver IC 104 uses the timing engine 222 to start generating a chirp signal with a frequency offset that is time-synchronized in response to a trigger signal received during a test mode.

[0042] In various embodiments, the leader radar transceiver IC 102 further includes a synthesizer 224, and the follower radar transceiver IC 104 further includes a synthesizer 226. It should be understood that although the synthesizer 226 is discussed with respect to the follower radar transceiver IC 104, every other follower radar transceiver IC including the follower radar transceiver IC 106 includes a synthesizer that operates similarly to the synthesizer 226 described herein. The synthesizer 224 is used by the leader radar transceiver IC 102 to generate a chirp signal with a set frequency. Additionally, the follower radar transceiver IC 104 uses the synthesizer 226 to generate a local chirp signal that includes a set frequency and a frequency offset. The synthesizer 226 operates in time synchronization with the timing engine 222. Further, the frequency synthesizer 226 is connected via a frequency multiplier to the plurality of transmitter antennas 114 and a plurality of mixers (i.e., mixer / downconverters) 228. Thus, the synthesizer 226 generates a local chirp signal that is parameterized with a set frequency and a frequency offset.

[0043] In various embodiments, both the leader radar transceiver IC 102 and the follower radar transceiver IC 104 include additional components. For example, the leader radar transceiver IC 102 and the follower radar transceiver IC 104 include a system clock, multiple amplifiers, multiple high-pass filters, multiple low-pass filters, multiple band-pass filters, multiple analog-to-digital converters (ADCs), and a processing unit. The system clock is used to control the timing of all components and thus synchronize the operation of each component on the leader radar transceiver IC 102 or the follower radar transceiver IC 104. The amplifiers increase or enhance the strength of the signals transmitted by the multiple transmitter antennas 112 or received by the multiple receiver antennas 113, 115. The mixer 228 acts as a multiplier for two input signals, which in some embodiments results in signals having the sum and difference of the original frequencies. The high-pass filter removes low-frequency signals resulting from self-interference (i.e., the transmitted signal from the transmitter antenna that is received by the receiver antenna during transmission and is not based on the return of the signal from the target of interest). On the other hand, the low-pass filter is used for anti-aliasing (i.e., attenuation of signals having frequencies exceeding the limit of the sampling theorem) to pass the signal to the ADC unit. The band-pass filter is a combination of a high-pass filter and a low-pass filter and thus provides a frequency range between the high-pass filter frequency and the low-pass filter frequency. In other words, the frequency range of the band-pass filter is determined by the high-pass filter cut-off frequency and the low-pass filter cut-off frequency. Additionally, the band-pass filter is parameterized using the cut-off frequencies according to the conventional processing requirements of the radar system 100. The ADC converts the analog signal to a digital signal. Finally, the processing unit (e.g., a controller, a microcontroller, a computer processing unit (CPU)) is used to perform post-processing on the digitized signal, for example, using a fast Fourier transform (FFT) on the ADC-converted signal to extract the beat frequency.

[0044] Figure 3 FIG. 300 shows a graph depicting the characteristics of a band-pass filter according to some embodiments. In the depicted example, FIG. 300 shows the frequency offset of the frequency range having BIST report time synchronization or “in-sync”. The frequency range is given by ±f thresholdIndication. In various embodiments, the follower radar transceiver ICs 104 and 106 use a frequency offset based on the bandpass filter cut-off frequency. Specifically, the synthesizer 226 uses the frequency offset between the high-pass filter cut-off frequency and the low-pass filter cut-off frequency. As discussed above, in response to the follower radar transceiver ICs 104 and 106 receiving the trigger signal 108 that is time-synchronized with the leader radar transceiver IC 102, the beat frequency is determined to match the offset frequency. Thus, in the time-synchronization example, the beat frequency filter matches the known offset frequency. However, in the time-asynchrony example, there are two failure cases. First, asynchrony caused by a large time offset between the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and / or 106. In the first case, the beat frequency determined by the bandpass filter exceeds the high-pass filter cut-off frequency or the low-pass filter cut-off frequency. Additionally, the received signal is overly attenuated such that the signal strength is insufficient for reliable frequency measurement. Accordingly, the signal strength will be determined, and in response to the signal strength exceeding a power threshold, the beat frequency is determined for comparison with the offset frequency. Correspondingly, the trigger signal 108 is blocked and / or delayed between the transmission and reception of the follower radar transceiver ICs 104 and 106. Second, asynchrony due to a small time offset occurs, where f Beat > = f HP and f Beat <= f LP . In this case, the signal strength is high enough for reliable frequency measurement. The asynchrony is detected by comparing the beat frequency with the offset frequency. Specifically, the asynchrony is detected when the beat frequency is different from the offset frequency.

[0045] Figure 4Figure 400 shows a graph of performing a test mode during the transmission of a trigger signal 108 according to some embodiments. In the depicted example, a test mode Tsync test 401 is initiated in response to the transmission of the trigger signal 108. For example, the master radar transceiver IC 102 transmits the trigger signal 108 to the slave radar transceiver ICs 104 and 106 in response to an event. Subsequently, in response to confirming time synchronization during the test mode, the master radar transceiver IC 102 and the slave radar transceiver ICs 104 and 106 operate in the normal detection mode radar Proc 403. Alternatively and / or additionally, the radar Proc 403 is performed in response to the transmission of the trigger signal 108 from the master radar transceiver IC 102 to the slave radar transceiver ICs 104 and 106. Subsequently, the master radar transceiver IC 102 and the slave radar transceiver ICs 104 and 106 operate in the Tsync test 401 to determine time synchronization. Thus, in a first sequence, the Tsync test 401 occurs before the radar Proc 403. In a second sequence different from the first sequence, the Tsync test 401 occurs after the radar Proc 403. The order of the sequence is determined by the mode switch 110.

[0046] Figure 5 Figure 500 is a flowchart showing a method for testing signal strength and time synchronization between a master radar transceiver IC 102 and slave radar transceiver ICs 104 and 106 according to some embodiments. With respect to Figure 1An example implementation of the radar system 100 will be used to describe the method 500. At block 502, the leader radar transceiver IC 102 transmits a trigger signal 108 to the follower radar transceiver ICs 104 and 106 in response to an event. In other words, the leader radar transceiver IC 102 uses the trigger signal 108 as a start signal to the follower radar transceiver ICs 104 and 106 to initiate additional operations. In addition, the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 execute a test mode in response to the trigger signal 108. At block 504, the leader radar transceiver IC 102 begins to generate and transmit a chirp signal at a set frequency. At block 506, in response to receiving the trigger signal 108 and operating simultaneously with block 504, the follower radar transceiver ICs 104 and 106 begin to generate their local chirp signals based on the sum of the set frequency and the frequency offset. The follower radar transceiver ICs 104 and 106 receive the chirp signal from the leader radar transceiver IC 102 and down-convert it to an IF signal using the local chirp signal. Also, the follower radar transceiver ICs 104 and 106 filter and perform A / D conversion on the down-converted signal. In addition, the follower radar transceiver ICs 104 and 106 perform post-processing by filtering and performing A / D conversion on the IF signal.

[0047] At block 508, the follower radar transceiver ICs 104 and 106 calculate the signal strength of the down-converted and filtered signal such that the signal strength is above a power specific threshold and the beat frequency can then be reliably calculated. At block 510, the follower radar transceiver ICs 104 and 106 determine whether the signal strength is above the power threshold. If the signal strength does not exceed the power threshold, the signal strength is too low and a functional error is flagged at block 520.

[0048] At block 512, the follower radar transceiver ICs 104 and 106 measure the beat frequency. At block 514, the follower radar transceiver ICs 104 and 106 determine whether the difference between the measured beat frequency and the frequency offset exceeds a certain frequency threshold (i.e., f threshold)。At block 516, the follower radar transceiver ICs 104 and 106 compare the difference in beat frequencies with a frequency threshold. At block 518, the follower radar transceiver ICs 104 and 106 identify whether the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 are time asynchronous in response to the beat frequency not matching the frequency offset. At block 520, the follower radar transceiver ICs 104 and 106 flag a functional error in response to the beat frequency exceeding the frequency threshold. Accordingly, the radar system 100 is functionally unsafe because the radar system 100 has inaccurate detections due to asynchronous operation between the leader radar transceiver 102 and the follower radar transceiver ICs 104 and 106. At block 522, the follower radar transceiver ICs 104 and 106 confirm time synchronization in response to the beat frequency matching the frequency offset.

[0049] Figure 6 is a flowchart of a method 600 for testing time synchronization between a leader radar transceiver IC 10 and follower radar transceiver ICs 104 and 106 according to some embodiments. Method 600 is described with respect to Figure 1 an example implementation of the radar system 100. At block 602, the leader radar transceiver IC 102 transmits a trigger signal 108 to the follower radar transceiver ICs 104 and 106 in response to an event. In other words, the leader radar transceiver IC 102 uses the trigger signal 108 as a start signal to the follower radar transceiver ICs 104 and 106 to initiate additional operations. Further, the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 execute a test mode in response to the trigger signal 108. At block 604, the leader radar transceiver IC 102 begins generating and transmitting a chirp signal at a set frequency. At block 606, in response to receiving the trigger signal 108 and operating concurrently with block 604, the follower radar transceiver ICs 104 and 106 begin generating their local chirp signals based on the sum of the set frequency and the frequency offset. The follower radar transceiver ICs 104 and 106 receive the chirp signal from the leader radar transceiver IC 102 and down-convert it to an IF signal using the local chirp signal. Also, the follower radar transceiver ICs 104 and 106 filter and perform A / D conversion on the down-converted signal. Further, the follower radar transceiver ICs 104 and 106 perform post-processing by filtering and performing A / D conversion on the IF signal.

[0050] At block 608, the follower radar transceiver ICs 104 and 106 calculate the beat frequency from the IF signal using an FFT. At block 610, the follower radar transceiver ICs 104 and 106 check that the signal strength is high enough and that the beat frequency is within the frequency threshold. At block 612, the follower radar transceiver ICs 104 and 106 identify whether the leader radar transceiver IC 102 and the follower radar transceiver ICs 104 and 106 are time asynchronous in response to the beat frequency not matching the frequency offset. At block 614, the follower radar transceiver ICs 104 and 106 flag a functional error in response to the beat frequency exceeding the frequency threshold. Accordingly, the radar system 100 is functionally unsafe because the radar system 100 has inaccurate detections due to asynchronous operation between the leader radar transceiver 102 and the follower radar transceiver ICs 104 and 106. At block 616, the follower radar transceiver ICs 104 and 106 confirm time synchronization in response to the beat frequency matching the frequency offset.

[0051] In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a disk or optical storage device, a solid-state storage device such as flash memory, a cache, a random access memory (RAM), or other one or more non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats that can be interpreted or otherwise executed by one or more processors.

[0052] A computer-readable storage medium can include any storage medium or combination of storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but are not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-ray disc), magnetic media (e.g., floppy disk, magnetic tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS)-based storage media. The computer-readable storage medium can be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to the computing system (e.g., magnetic hard drive), removably attached to the computing system (e.g., optical disc or universal serial bus (USB)-based flash memory), or coupled to the computer system via a wired or wireless network (e.g., network-attached storage (NAS)).

[0053] It should be noted that not all activities or elements described in the above general description are required, a portion of a particular activity or apparatus may not be required, and one or more additional activities other than those described may be performed, or one or more additional elements other than those described may be included. Moreover, the order in which the activities are listed is not necessarily the order in which they are performed. Also, concepts have been described with reference to specific embodiments. However, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.

[0054] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature that may cause any benefit, advantage, or solution to occur or become more apparent should not be construed as a critical, required, or essential feature of any or all of the claims. Additionally, the specific embodiments disclosed above are illustrative only, as the disclosed subject matter can be modified and practiced in different but equivalent manners, which will be apparent to those of ordinary skill in the art who have benefited from the teachings herein. Except for the limitations described in the appended claims, no limitations are intended with respect to the details of the construction or design shown herein. It is, therefore, evident that the specific embodiments disclosed above can be altered or modified, and all such variations are considered to be within the scope of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the appended claims.

Claims

1. A method, characterized in that include: The first radar transceiver integrated circuit IC sends a trigger signal; In response to receiving the trigger signal, generating and transmitting a chirp signal having a set frequency by the first radar transceiver IC; In response to receiving the trigger signal from the first radar transceiver IC, receiving the chirp signal, and generating a local chirp signal by at least one second radar transceiver IC, the local chirp signal being parameterized by the sum of the set frequency and the frequency offset to down-convert the received chirp signal into an intermediate frequency (IF) signal; and A synchronization level of the first radar transceiver IC and the at least one second radar transceiver IC is determined based on comparing the beat frequency to the frequency offset.

2. The method according to claim 1, characterized in that Generating the local chirp signal includes generating the frequency deviation within a frequency range between a high pass filter cutoff frequency and a low pass filter cutoff frequency.

3. The method according to claim 2, characterized in that The at least one second radar transceiver IC flags a functional safety fault in response to the beat frequency exceeding the frequency range.

4. The method according to claim 1, characterized in that: Generating the local chirp signal comprises: The local chirp signal is generated by a frequency synthesizer of the at least one second radar transceiver IC.

5. The method according to claim 4, characterized in that Generating the local chirp signal by the frequency synthesizer is performed during a test mode.

6. The method according to claim 1, characterized in that The beat frequency comprises a difference between the chirp signal received by the at least one second radar transceiver IC and the local chirp signal.

7. The method according to claim 6, characterized in that Comparing the beat frequency with the frequency deviation comprises: determining a signal strength of the received chirp signal; and In response to the signal strength exceeding a power threshold, the beat frequency is determined for comparison with the frequency offset.

8. The method according to claim 1, characterized in that Generating the local chirp signal occurs simultaneously with generating and transmitting the chirp signal.

9. A radar system, characterized in that: include: at least one second radar transceiver integrated circuit IC configured to receive the chirp signal transmitted from the first radar transceiver IC and generate a local chirp signal parameterized by a set frequency and a frequency offset in response to receiving a trigger signal from the first radar transceiver IC to test a synchronization level of the first radar transceiver IC with the at least one second radar transceiver IC based on comparing a beat frequency with the frequency offset.

10. A method, characterized in that include: The first radar transceiver integrated circuit IC sends a trigger signal; generating and transmitting a chirp signal based on a set frequency and determined by a first synthesizer of the first radar transceiver IC; receiving the chirp signal by a plurality of second radar transceiver ICs, and generating a local chirp signal based on the set frequency and frequency offset using a second synthesizer of each of the plurality of second radar transceiver ICs in response to receiving the trigger signal from the first radar transceiver IC; and A functional error is flagged in response to the beat frequency being different from the frequency deviation.

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