Solid state disk, information processing apparatus, and control method

Abstract

The invention relates to a solid state disk, an information processing apparatus and a control method. The purpose of the present invention is to reduce power consumption and suppress performance degradation caused by temperature rise. The solid state disk is connectable to an information processing device, and is provided with: a non-volatile memory that can be electrically rewritten; and a memory controller that accepts a processing command to the non-volatile memory and executes a process corresponding to the processing command, and that executes a process corresponding to the processing command on the basis of a value of a QD (Queue Depth: Queue Depth) indicating the number of processing commands issued at a time by the information processing apparatus. A first processing mode in which the processing capability of the nonvolatile memory is high and a second processing mode in which the processing capability is lower than that of the first processing mode are switched.

Description

Technical Field

[0001] The present invention relates to a solid-state drive, an information processing device, and a control method. Background Art

[0002] In recent years, in information processing devices such as personal computers (PCs), devices equipped with SSDs (solid-state drives) have been spreading. In such information processing devices, there are known devices that use a PCIe (Peripheral Component Interconnect-Express) bus for connecting an SSD in order to speed up data transfer (for example, refer to Patent Document 1).

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2023-32086.

[0004] However, in the conventional information processing devices and SSDs as described above, as the data transfer of the SSD speeds up, there is a tendency for power consumption to increase regardless of the processing load. Therefore, in the conventional information processing devices and SSDs, there are cases where the operation of the information processing device is restricted due to a temperature rise. Summary of the Invention

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide a solid-state drive, an information processing device, and a control method that can reduce power consumption and suppress a decrease in performance caused by a temperature rise.

[0006] In order to solve the above problems, one aspect of the present invention is a solid-state drive that can be connected to an information processing device, including: a non-volatile memory that can be electrically rewritten; and a memory controller that receives a processing command for the non-volatile memory and executes a process corresponding to the processing command, and switches between a first processing mode with a higher processing ability for the non-volatile memory and a second processing mode with a lower processing ability than the first processing mode according to a QD (Queue Depth) value indicating the number of the processing commands issued by the information processing device at one time.

[0007] In addition, in one aspect of the present invention, in the above-mentioned solid-state drive, it can be connected to the above-mentioned information processing device via a PCIe (Peripheral Component Interconnect-Express) bus. The memory controller, upon receiving a notification indicating that the processing command has been stored in the buffer storage unit provided in the information processing device, checks the buffer storage unit. When the QD value is equal to or greater than a specified threshold, it switches to the first processing mode; when the QD value is less than the specified threshold, it switches to the second processing mode.

[0008] In addition, in one aspect of the present invention, in the above-mentioned solid-state drive, in the second processing mode, the memory controller changes to a mode where the transmission speed of the PCIe bus is lower than that in the first processing mode, and in the first processing mode, it changes to a mode where the transmission speed of the PCIe bus is higher than that in the second processing mode.

[0009] In addition, in one aspect of the present invention, in the above-mentioned solid-state drive, the memory controller can perform parallel processing of the above-mentioned processing commands through multiple threads. When at least one of the QD values corresponding to the multiple threads stored in the buffer storage unit is equal to or greater than the specified threshold, it switches to the first processing mode.

[0010] In addition, one aspect of the present invention is an information processing device incorporating the above-mentioned solid-state drive.

[0011] In addition, one aspect of the present invention is an information processing device, comprising: a solid-state drive having a non-volatile memory capable of electrical rewriting and a memory controller that receives a processing command for the non-volatile memory and executes processing corresponding to the processing command; and a main control unit that issues the processing command. The main control unit causes the solid-state drive to switch between a first processing mode with higher processing ability for the non-volatile memory and a second processing mode with lower processing ability than the first processing mode according to the QD (Queue Depth) value indicating the number of the above-mentioned processing commands issued to the solid-state drive at one time.

[0012] In addition, one aspect of the present invention is a control method, which is a control method for a solid-state drive (SSD) that can be connected to an information processing device. The SSD includes a non-volatile memory that can be electrically rewritten and a memory controller that accepts processing commands for the non-volatile memory and executes processing corresponding to the processing commands. The control method includes: a processing step in which the memory controller switches between a first processing mode with higher processing ability for the non-volatile memory and a second processing mode with lower processing ability than the first processing mode according to the value of QD (Queue Depth) indicating the number of the processing commands issued by the information processing device at one time.

[0013] According to the above aspect of the present invention, power consumption can be reduced, and a decrease in performance caused by a temperature rise can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. is an example showing a main hardware configuration of the information processing device and the SSD according to the present embodiment.

[0015] Figure 2 FIG. is a functional block diagram showing an example of the functional configuration of the information processing device according to the present embodiment.

[0016] Figure 3 FIG. is an example showing the power state and power consumption of the SSD according to the present embodiment.

[0017] Figure 4 FIG. is a diagram showing the relationship between the mode of the PCIe bus and the transmission speed.

[0018] Figure 5 FIG. is an example showing command processing for the SSD in the information processing device according to the present embodiment.

[0019] Figure 6 FIG. is a flowchart showing an example of mode switching processing of the SSD according to the present embodiment.

[0020] Figure 7 FIG. is a flowchart showing an example of temperature control processing of the SSD according to the present embodiment.

[0021] Figure 8 FIG. is a diagram showing the effects of the information processing device and the SSD according to the present embodiment.

[0022] Figure 9 FIG. is a functional block diagram showing the functional configuration of the information processing device according to a modification example of the present embodiment.

[0023] REFERENCE MARK DESCRIPTION

[0024] 1, 1a... Information processing device, 10... Main control unit, 11... CPU, 12... Main memory, 13... Video subsystem, 14... Display unit, 21... Chipset, 22... BIOS memory, 31... Embedded controller (EC), 32... Input unit, 33... Power supply circuit, 40, 40a... SSD, 41... Flash memory, 42... Memory controller, 43... Temperature sensor, 50... Storage unit, 51... Command buffer storage unit, 101... AP processing unit, 102... SSD device driver unit, 103, 422... Mode switching unit, 410... SSD storage unit, 411... Management information storage unit, 412... Mode information storage unit, 413... Data storage unit, 421... Command processing unit, 423... Temperature control unit. Detailed implementation

[0025] Hereinafter, a solid-state drive, an information processing device, and a control method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0026] Figure 1 It is a diagram showing an example of the main hardware configuration of the information processing device 1 and the SSD 40 according to the first embodiment.

[0027] As Figure 1 shown, the information processing device 1 is, for example, a notebook personal computer, and includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40. Here, the information processing device 1 is, for example, a notebook personal computer (notebook PC).

[0028] The CPU (Central Processing Unit) 11 executes various arithmetic processes through program control and controls the entire information processing device 1.

[0029] The main memory 12 is a writable memory that is used as a read-in area for the execution program of the CPU 11 or as a work area for writing processing data of the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. The execution program includes an OS (operating system), various driver programs for hardware operations on peripheral device groups, various services / utilities, application programs, and the like.

[0030] The video subsystem 13 is a subsystem for implementing functions related to image display and includes a video controller. The video controller processes the rendering commands from the CPU 11, writes the processed rendering information to the video memory, reads the rendering information from the video memory, and outputs it as rendering data (display data) to the display unit 14.

[0031] The display unit 14 is, for example, a liquid crystal display, and displays a display screen based on the rendering data (display data) output from the video subsystem 13.

[0032] The chipset 21 includes controllers such as USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus (PCIe), and LPC (Low Pin Count) bus, and connects multiple devices. Figure 1 Among them, as an example of the devices, the BIOS memory 22 and the SSD 40 are connected to the chipset 21.

[0033] Among them, in the present embodiment, the CPU 11 and the chipset 21 correspond to the main control unit 10.

[0034] The BIOS (Basic Input Output System) memory 22 is constituted by a non-volatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM (flash memory) that can be electrically rewritten. The BIOS memory 22 stores system firmware for controlling the BIOS, the embedded controller 31, and the like.

[0035] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing device 1. In addition, the embedded controller 31 has a power management function for controlling the power circuit 33. Furthermore, the embedded controller 31 is composed of a CPU, ROM, RAM, etc. (not shown), and has multi-channel A / D input terminals, D / A output terminals, a timer, and digital input / output terminals. For example, an input unit 32 and a power circuit 33 are connected to the embedded controller 31 via these input / output terminals, and the embedded controller 31 controls their operations.

[0036] The input unit 32 is, for example, an input device such as a keyboard or a pointing device such as a touchpad.

[0037] The power circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, an AC / DC adapter, etc., and converts, for example, the DC voltage supplied from an external power source via the AC / DC adapter or from a storage battery into a plurality of voltages required for the operation of the information processing device 1. In addition, the power circuit 33 supplies power to each part of the information processing device 1 based on the control from the embedded controller 31.

[0038] The SSD (Solid State Drive) 40 is a memory drive device having a rewritable non-volatile memory, and stores an OS, various driver programs, various service / utilities, application programs, and various data. The information processing device 1 performs various information processes using the data stored in the SSD 40. The SSD 40 is connected to the chipset 21, for example, via a Serial ATA or PCI-Express bus.

[0039] In addition, in the present embodiment, it is assumed that the SSD 40 is connected via a PCI-Express bus (PCIe bus).

[0040] In addition, the SSD 40 includes a plurality of flash memories 41 and a memory controller 42.

[0041] The flash memory 41 is, for example, a NAND flash memory. The flash memory 41 includes, for example, a storage cell of a floating gate type, a storage cell of a charge trapping type that stores data by trapping electrons in a charge trapping layer without a floating gate, and the like. In addition, the storage cells of the flash memory 41 are multi-bit cells that store multiple bits of data in one storage cell, and are, for example, MLC (Multiple Level Cell), TLC (Triple Level Cell), and QLC (Quad Level Cell). Here, a multi-bit cell is a storage cell that can perform storage equivalent to multiple bits in one storage cell by setting write thresholds for multiple data.

[0042] The temperature sensor 43 is a sensor for detecting the internal temperature of the SSD 40. The temperature sensor 43 outputs a detection value for temperature detection to the memory controller 42.

[0043] The memory controller 42 is, for example, a processor including a CPU, a ROM, a RAM, etc. (not shown), and comprehensively controls the SSD 40. The SSD controller 42 performs, for example, control processing of a host interface (host I / F) with the chipset 21, control processing of a memory interface (memory I / F) with the flash memory 41, data management processing of the flash memory 41, and the like.

[0044] In addition, the memory controller 42 detects the temperature of the SSD 40 based on the detection value detected by the temperature sensor 43, and controls so that the detected temperature does not exceed a specified threshold temperature. For example, if the memory controller 42 detects that the temperature reaches the specified threshold temperature, it restricts the operation of the SSD 40 to lower the temperature of the SSD 40.

[0045] In addition, the memory controller 42 has a performance mode (first processing mode) with a relatively high processing capacity and an ECO (Ecology) mode (second processing mode) with a relatively low processing capacity compared to the performance mode, and switches between the performance mode and the ECO mode according to the value of QD (Queue Depth). In addition, details of the process of switching the processing mode according to the value of QD will be described later.

[0046] Next, with reference to Figure 2 , the functional configuration of the information processing apparatus 1 of the present embodiment will be described.

[0047] Figure 2 It is a functional block diagram showing an example of the functional configuration of the information processing apparatus 1 of the present embodiment.

[0048] As Figure 2 shown, the information processing apparatus 1 includes a main control unit 10, an SSD 40, and a storage unit 50.

[0049] Among them, the main control unit 10 and the SSD 40 are connected through a PCIe bus.

[0050] The storage unit 50 is, for example, a storage unit implemented by the main memory 12, and stores various information used by the information processing device 1. The storage unit 50 includes a command buffer storage unit 51.

[0051] The command buffer storage unit 51 (an example of a buffer storage unit) is, for example, a storage unit implemented by the main memory 12, and stores processing commands for the SSD 40. The command buffer storage unit 51 can store multiple processing commands with the number of processing commands issued by the information processing device 1 to the SSD 40 at one time as QD. The command buffer storage unit 51 stores the processing commands in correspondence with the data. In addition, the command buffer storage unit 51 stores QD for multiple threads respectively. The SSD 40 performs parallel processing for multiple threads respectively.

[0052] In addition, the processing commands of the SSD 40 are commands for performing various processes such as reading and writing data of the SSD 40. The processing commands are temporarily stored in the command buffer storage unit 51 and executed by being read out to the SSD 40.

[0053] The main control unit 10 is a functional unit implemented by executing a program stored in the main memory 12 by the CPU 11 and the chipset 21, and performs various processes based on the OS. The main control unit 10, for example, performs various processes based on the data stored in the SSD 40. The main control unit 10 includes an AP processing unit 101 and an SSD device driver unit 102.

[0054] The AP processing unit 101 is a functional unit that processes application programs executed on the OS. The AP processing unit 101, for example, accesses the SSD 40 and reads and writes data. The AP processing unit 101 accesses the SSD 40 via the SSD device driver unit 102 described later.

[0055] The SSD device driver unit 102 is a functional unit that implements a device driver for accessing the SSD 40. The SSD device driver unit 102 stores the processing commands in the command buffer storage unit 51 according to the access to the SSD 40, and then notifies the SSD 40 that the processing commands have been stored in the command buffer storage unit 51.

[0056] The SSD device driver unit 102, for example, when the processing command is a read command, acquires the read data from the SSD 40 and outputs it to the OS or the application program.

[0057] The SSD 40 includes a memory controller 42, a temperature sensor 43, and an SSD storage unit 410.

[0058] The SSD storage unit 410 is a storage unit implemented by, for example, the flash memory 41 of the SSD 40, and includes a management information storage unit 411, a mode information storage unit 412, and a data storage unit 413.

[0059] The management information storage unit 411 is a storage unit implemented by, for example, the flash memory 41, and stores the management information of the SSD 40. The management information storage unit 411 stores, for example, the conversion table information of the physical address and the logical address (e.g., LBA: Logical Block Addressing: logical block addressing (logical location information)) of the flash memory 41, the management information of the free area and the used area of the flash memory 41, and the like.

[0060] The mode information storage unit 412 is a storage unit implemented by, for example, the flash memory 41, and stores information indicating processing modes such as a performance mode and an ECO mode, and a power state. In addition, as Figure 3 shown, the SSD 40 of the present embodiment has a power state.

[0061] Figure 3 is a diagram showing an example of the power state and power consumption of the SSD 40 of the present embodiment.

[0062] As Figure 3 shown, the power state of the SSD 40 includes PS01 - Perf, PS0 - Eco, PS1, PS2, PS3, and PS4.

[0063] PS01 - Perf and PS0 - Eco are power states in which normal processing of the SSD 40 can be performed. PS01 - Perf corresponds to the performance mode, and PS0 - Eco corresponds to the ECO mode.

[0064] In addition, PS1 and PS2 are states in which a part of the functions of the SSD 40 are restricted, and thermal throttling for restricting the functions is used so that the temperature does not exceed a specified threshold temperature.

[0065] In addition, PS3 and PS4 are standby states, and are states changed according to a processing command from the information processing device 1 or a timeout of the SSD 40.

[0066] Returning again to Figure 2 the description, the data storage unit 413 is a storage unit implemented by, for example, the flash memory 41, and stores various data. The data storage unit 413 stores, for example, various data of the information processing device 1, programs of the OS and applications, and the like.

[0067] The memory controller 42 includes a command processing unit 421, a mode switching unit 422, and a temperature control unit 423.

[0068] The command processing unit 421 obtains a processing command from the command buffer storage unit 51 according to a notification from the SSD device driver unit 102 of the main control unit 10, and executes the processing of the SSD 40 corresponding to the processing command. The command processing unit 421 executes processing such as writing data to the SSD storage unit 410 and reading data from the SSD storage unit 410 according to the processing command.

[0069] The mode switching unit 422 switches between a performance mode (first processing mode) with high processing ability for the flash memory 41 and an ECO mode (second processing mode) with lower processing ability than the performance mode according to the value of QD. Here, QD represents the number of processing commands of the SSD 40 issued by the information processing apparatus 1 (main control unit 10) at one time.

[0070] For example, when the value of QD is equal to or greater than a specified threshold (for example, two or more), the mode switching unit 422 switches to the performance mode. When switching to the performance mode, the mode switching unit 422 causes the mode information storage unit 412 to store the mode information indicating the performance mode, and sets the PCIe bus to PCIe Gen4 with the highest transmission speed.

[0071] In addition, for example, when the value of QD is less than the specified threshold (for example, less than 2), the mode switching unit 422 switches to the ECO mode. When switching to the ECO mode, the mode switching unit 422 causes the mode information storage unit 412 to store the mode information indicating the ECO mode, and sets the PCIe bus to PCIe Gen3 with a lower transmission speed than the performance mode. Here, refer to Figure 4 for an explanation of the transmission speed of the PCIe bus.

[0072] Figure 4 is a diagram showing the relationship between the mode of the PCIe bus and the transmission speed.

[0073] As Figure 4 shown, the PCIe bus has four Gens (generations), and the larger the number of Gens, the faster the transmission speed. For example, in PCIe Gen4, the maximum transmission speed is 16 Gbps (gigabits per second), and the sequential read speed in the SSD 40 is 4000 MB / s (megabytes per second).

[0074] In addition, for example, in PCIe Gen3, the maximum transmission speed is 8 Gbps, and the sequential read speed in the SSD 40 is 3300 MB / s. In addition, for example, in PCIe Gen2, the maximum transmission speed is 4 Gbps, and the sequential read speed in the SSD 40 is 1600 MB / s. In addition, for example, in PCIe Gen1, the maximum transmission speed is 2 Gbps, and the sequential read speed in the SSD 40 is 800 MB / s.

[0075] In addition, in the present embodiment, as an example, the mode switching unit 422 uses PCIe Gen4 (16 Gbps) in the performance mode and uses PCIe Gen3 (8 Gbps) in the ECO mode.

[0076] In addition, when there are multiple threads in the buffer storage unit 51, the mode switching unit 422 switches to the performance mode when at least one of the QD values corresponding to the multiple threads is equal to or greater than a specified threshold value (for example, two or more). In addition, when there are multiple threads in the buffer storage unit 51, the mode switching unit 422 switches to the ECO mode when the QD values of all the threads are smaller than the specified threshold value (for example, smaller than two).

[0077] The temperature control unit 423 uses the temperature sensor 43 to detect the internal temperature of the SSD 40 and controls the SSD 40 so that the detected temperature does not exceed a specified threshold temperature. For example, if the detected temperature reaches the specified threshold temperature, the temperature control unit 423 restricts the operation of the SSD 40 to lower the temperature of the SSD 40. Specifically, when the temperature reaches the specified threshold temperature, the temperature control unit 423 changes the power state from PS01 - Perf or PS0 - Eco to PS1 or PS2. In addition, PS1 or PS2 is a state in which a part of the functions of the SSD 40 is restricted, for example, a state in which the clock signal is stopped or the frequency is reduced.

[0078] Next, with reference to the drawings, the operations of the information processing apparatus 1 and the SSD 40 according to the present embodiment will be described.

[0079] Figure 5 This is a diagram showing an example of command processing for the SSD 40 in the information processing apparatus 1 according to the present embodiment.

[0080] As shown in Figure 5 When accessing the SSD 40, the SSD device driver unit 102 first sends a command and data to the command buffer storage unit 51 (step S11). The SSD device driver unit 102 expands the processing for the SSD 40 into commands (processing commands) and stores each command and data (for example, write data, etc.) in the command buffer storage unit 51.

[0081] In addition, multiple commands (processing commands) can be executed at once as QD. In the Figure 5 example shown, four processing commands (QD value is "4") are stored in thread A, and two processing commands (QD value is "2") are stored in thread B.

[0082] Next, the SSD device driver unit 102 notifies the memory controller 42 of the SSD 40 of the storage of the command (step S12). The SSD device driver unit 102 notifies (command notification) the memory controller 42 that the command buffer storage unit 51 stores (stores) the processing command.

[0083] Next, the memory controller 42 acquires the command and data from the command buffer storage unit 51 (step S13). The command processing unit 421 of the memory controller 42 acquires the processing command and data from the command buffer storage unit 51 according to the notification.

[0084] Next, the memory controller 42 executes command processing (step S14). The command processing unit 421 executes command processing according to the processing command acquired from the command buffer storage unit 51.

[0085] Next, refer to Figure 6 and the mode switching process of the SSD 40 will be described.

[0086] Figure 6 is a flowchart showing an example of the mode switching process of the SSD 40 of the present embodiment.

[0087] As Figure 6 shown, the memory controller 42 of the SSD 40 first determines whether a command notification has been received (step S101). The mode switching unit 422 of the memory controller 42 determines whether the command notification shown in step S12 of the above Figure 5 has been received. When the mode switching unit 422 has received the command notification (step S101: Yes), the process proceeds to step S102. In addition, when the mode switching unit 422 has not received the command notification (step S101: No), the process returns to step S101.

[0088] In step S102, the mode switching unit 422 confirms the QD of the command buffer storage unit 51.

[0089] Next, the mode switching unit 422 determines whether the QD is N or more (step S103). Here, N is a specified threshold value, for example, "2". When the QD is N or more (for example, the value of the QD is 2 or more) (step S103: Yes), the mode switching unit 422 causes the process to proceed to step S104. In addition, when the QD is less than N (the value of the QD is less than 2) (step S103: No), the mode switching unit 422 causes the process to proceed to step S107.

[0090] In step S104, the mode switching unit 422 sets the SSD 40 to the performance mode. The mode switching unit 422 causes the mode information storage unit 412 to store the mode information indicating the performance mode, and sets the setting of the PCIe bus to PCIe Gen4 with the highest transfer speed.

[0091] Next, the command processing unit 421 of the memory controller 42 performs command processing (step S105). That is, the command processing unit 421 performs command processing through the performance mode (PCIe Gen4).

[0092] Next, the memory controller 42 maintains the period specified by the performance mode (constant period) (step S106). After the processing in step S106, the memory controller 42 returns the processing to step S101.

[0093] In addition, in step S107, the mode switching unit 422 sets the SSD 40 to the ECO mode. The mode switching unit 422 causes the mode information storage unit 412 to store the mode information indicating the ECO mode, and sets the setting of the PCIe bus to PCIe Gen3 with a transfer speed lower than that of the performance mode.

[0094] Next, the command processing unit 421 of the memory controller 42 performs command processing (step S108). That is, the command processing unit 421 performs command processing through the ECO mode (PCIe Gen3). After the processing in step S108, the memory controller 42 returns the processing to step S101.

[0095] Next, the temperature control processing of the SSD 40 according to the present embodiment will be described.

[0096] Figure 7 It is a flowchart showing an example of the temperature control processing of the SSD 40 according to the present embodiment.

[0097] As Figure 7 shown, the memory controller 42 of the SSD 40 first determines whether the temperature of the SSD 40 is above the threshold temperature (step S201). The temperature control unit 423 of the memory controller 42 uses the temperature sensor 43 to detect the internal temperature of the SSD 40 and determines whether the detected temperature is above the threshold temperature. When the detected temperature is above the threshold temperature (step S201: Yes), the temperature control unit 423 causes the processing to proceed to step S202. In addition, when the detected temperature is lower than the threshold temperature (step S201: No), the temperature control unit 423 causes the processing to proceed to step S203.

[0098] In step S202, the temperature control unit 423 changes the power state to PS1 or PS2. The temperature control unit 423 causes the mode information storage unit 412 to store mode information indicating PS1 or PS2 and restricts a part of the operations. After the processing of step S202, the temperature control unit 423 returns the processing to step S201.

[0099] In addition, in step S203, the temperature control unit 423 changes the power state to PS0 (PS01 - Perf or PS0 - Eco). The temperature control unit 423 causes the mode information storage unit 412 to store mode information indicating PS0 (performance mode or ECO mode) and releases the restriction of the operations. After the processing of step S203, the temperature control unit 423 returns the processing to step S201.

[0100] Next, with reference to Figure 8 , the effects of the information processing apparatus 1 and the SSD 40 of the present embodiment will be described.

[0101] In Figure 8 , the horizontal axis of the graph is time, and the vertical axis represents the temperature and performance of the SSD 40.

[0102] Figure 8 The waveform W1 shown in

[0103] represents the temperature change in the conventional SSD. In addition, the waveform W2 represents the performance in the conventional SSD. In addition, the waveform W3 represents the temperature change in the SSD 40 of the present embodiment. In addition, the waveform W4 represents the performance in the SSD 40 of the present embodiment.

[0104] As shown by the waveform W1, in the conventional SSD, the setting is fixed to PCIe Gen4, and the base temperature is the temperature Tm1. In this state, if continuous operations are performed, at time T1, the threshold temperature Tmth is reached, and for example, it is changed to PS2 or PS3. As a result, the temperature of the conventional SSD decreases. In addition, as shown by the waveform W2, in the conventional SSD, after time T1, the performance also decreases.

[0105] On the other hand, in the SSD 40 of the present embodiment, as shown by the waveform W3, since the performance mode and the ECO mode are switched, the base temperature is the temperature Tm2. That is, the temperature Tm2 is a value lower than the temperature Tm1 by the temperature difference ΔTmp. In this case, if the SSD 40 performs continuous operations, at a time T2 later than time T1, the threshold temperature Tmth is reached, and for example, it is changed to PS2 or PS3.

[0106] Thus, in the SSD 40 of the present embodiment, the period until the threshold temperature Tmth is reached can be extended, and the period of higher performance can be extended.

[0107] As described above, the SSD 40 (solid state drive) of the present embodiment is an SSD that can be connected to the information processing apparatus 1, and includes a flash memory 41 (non-volatile memory) and a memory controller 42. The flash memory 41 is a non-volatile memory that can be electrically rewritten. The memory controller 42 receives a processing command for the flash memory 41 and executes processing corresponding to the processing command. In addition, the memory controller 42 switches between a performance mode (first processing mode) with a higher processing ability for the flash memory 41 and an ECO mode (second processing mode) with a lower processing ability than the performance mode according to the value of QD. Here, QD represents the number of processing commands issued by the information processing apparatus 1 at one time.

[0108] Accordingly, the SSD 40 of the present embodiment can reduce power consumption by reducing the processing ability using the ECO mode, and thus can suppress an increase in the temperature of the SSD 40. That is, the SSD 40 of the present embodiment can reduce power consumption and suppress a decrease in performance caused by a temperature increase.

[0109] In addition, in the present embodiment, the SSD 40 can be connected to the information processing apparatus 1 via the PCIe bus. The memory controller 42 confirms the command buffer storage unit 51 (buffer storage unit) according to the reception of a notification indicating that a processing command is stored in the command buffer storage unit 51 provided in the information processing apparatus 1. The SSD 40 switches to the performance mode when the value of QD is equal to or greater than a specified threshold (for example, two or more), and switches to the ECO mode when the value of QD is less than the specified threshold (for example, two).

[0110] Accordingly, the SSD 40 of the present embodiment can cope with additional processing with a margin by switching to the performance mode when the value of QD is equal to or greater than a specified threshold (for example, two or more). In addition, the SSD 40 of the present embodiment can reduce power consumption by switching to the ECO mode when the value of QD is less than the specified threshold (for example, two). Thus, the SSD 40 of the present embodiment can suppress a decrease in performance while reducing power consumption.

[0111] In addition, in the present embodiment, the memory controller 42 changes to a mode (PCIe Gen3 setting mode) in which the transmission speed of the PCIe bus is lower than that in the performance mode (PCIe Gen4 setting mode) in the ECO mode. In addition, the memory controller 42 changes to a mode (PCIe Gen4 setting mode) in which the transmission speed of the PCIe bus is higher than that in the ECO mode (PCIe Gen3 setting mode) in the performance mode.

[0112] Thus, as Figure 3 and Figure 4 shown, by becoming the ECO mode (a setting mode of PCIe Gen3), the SSD 40 of the present embodiment can easily reduce power consumption. In addition, as shown by the waveforms W3 and W4 of Figure 8 , since the SSD 40 of the present embodiment reduces power consumption, it reduces the base temperature (temperature Tm2), can extend the period until the threshold temperature is reached, and can maintain high performance.

[0113] In addition, in the present embodiment, the memory controller 42 can perform parallel processing of processing commands through multiple threads. When at least one of the QD values corresponding to the multiple threads stored in the command buffer storage unit 51 is equal to or greater than a specified threshold value, it switches to the performance mode.

[0114] Thus, the SSD 40 of the present embodiment can suppress a decrease in performance while reducing power consumption corresponding to multiple threads.

[0115] In addition, the information processing apparatus 1 of the present embodiment incorporates the above-described SSD 40.

[0116] Thus, the information processing apparatus 1 of the present embodiment exhibits the same effects as the above-described SSD 40, can reduce power consumption, and can suppress a decrease in performance caused by a temperature rise.

[0117] In addition, the control method of the present embodiment is a control method of the SSD 40 that can be connected to the information processing apparatus 1. The SSD 40 includes a flash memory 41 that can be electrically rewritten and a memory controller 42 that receives a processing command for the flash memory 41 and executes processing corresponding to the processing command. The above control method includes a processing step. In the processing step, the memory controller 42 switches between a performance mode with a higher processing ability for the flash memory 41 and an ECO mode with a lower processing ability than the performance mode according to the QD value indicating the number of processing commands issued by the information processing apparatus 1 at one time.

[0118] Thus, the control method of the present embodiment exhibits the same effects as the above-described SSD 40 and the information processing apparatus 1, can reduce power consumption, and can suppress a decrease in performance caused by a temperature rise.

[0119] Next, with reference to Figure 9 , a modification of the present embodiment will be described. In the above-described present embodiment, an example in which the SSD 40 includes a mode switching unit 422 and switches between the performance mode and the ECO mode has been described, but the switching may be performed by the main control unit 10 of the information processing apparatus 1. Here, with reference to Figure 9, a modification example in which the main control unit 10 switches between the performance mode and the ECO mode will be described.

[0120] Figure 9 It is a functional block diagram showing the functional configuration of the information processing device 1a which is a modification example of the present embodiment.

[0121] As Figure 9 shown, the information processing device 1a includes a main control unit 10a, an SSD 40a, and a storage unit 50.

[0122] In addition, in Figure 9 the same components as those of the above Figure 2 are given the same reference numerals, and their descriptions are omitted.

[0123] The main control unit 10a is a functional unit implemented by the CPU 11 and the chipset 21 executing the program stored in the main memory 12, and performs various processes based on the OS. The main control unit 10a performs various processes based on the data stored in the SSD 40, for example. The main control unit 10a includes an AP processing unit 101, an SSD device driver unit 102, and a mode switching unit 103.

[0124] The mode switching unit 103 switches the SSD 40a to a performance mode (first processing mode) with higher processing ability for the SSD 40a and an ECO mode (second processing mode) with lower processing ability than the performance mode according to the value of QD.

[0125] For example, when the value of QD is equal to or greater than a specified threshold (for example, 2 or more), the mode switching unit 103 sends a request for mode switching to the SSD 40a and switches to the performance mode.

[0126] In addition, for example, when the value of QD is less than the specified threshold (for example, less than 2), the mode switching unit 103 sends a request for mode switching to the SSD 40a and switches to the ECO mode.

[0127] The SSD 40a includes a memory controller 42a and an SSD storage unit 410.

[0128] The memory controller 42a includes a command processing unit 421 and a temperature control unit 423. When the memory controller 42a receives a request to switch to the performance mode from the mode switching unit 103, it causes the mode information storage unit 412 to store the mode information indicating the performance mode, and sets the PCIe bus setting to the highest transmission speed PCIe Gen4.

[0129] In addition, when the memory controller 42a receives a request to switch to the ECO mode from the mode switching unit 103, it causes the mode information storage unit 412 to store mode information indicating the ECO mode, and sets the PCIe bus setting to PCIe Gen3.

[0130] As described above, the information processing device 1a according to the modification example of the present embodiment includes the SSD 40a and the main control unit 10a. The SSD 40a includes a flash memory 41 that can be electrically rewritten, and a memory controller 42 that receives a processing command for the flash memory 41 and executes a process corresponding to the processing command. The main control unit 10a is a main control unit that issues a processing command, and switches between a performance mode with a higher processing ability for the flash memory 41 and an ECO mode with a lower processing ability than the performance mode according to the QD value indicating the number of processing commands issued to the SSD40 at one time.

[0131] Accordingly, the information processing device 1a according to the modification example of the present embodiment exhibits the same effects as the above-described SSD 40 and information processing device 1, and can reduce power consumption and suppress a decrease in performance caused by a temperature rise.

[0132] In this way, the information processing device 1a may also include a part or all of the functions of the mode switching unit 422 in which the main control unit 10 includes the SSD 40.

[0133] Furthermore, the present invention is not limited to the above-described embodiments, and can be modified without departing from the gist of the present invention.

[0134] For example, in the above-described embodiment, an example in which the information processing device 1 is a notebook personal computer (mobile computer) has been described, but the present invention is not limited thereto. For example, it may also be other information processing devices such as a desktop personal computer or a tablet terminal device.

[0135] In addition, in the above-described embodiment, an example in which the performance mode and the ECO mode are set to modes with different transmission speeds of the PCIe bus and switched has been described, but the present invention is not limited thereto. It may also be a mode that restricts the processing ability of the SSD 40 (40a).

[0136] In addition, in the above-described embodiment, an example in which the setting mode of PCIe Gen4 and the setting mode of PCIe Gen3 are switched when switching between the performance mode and the ECO mode has been described, but the present invention is not limited thereto. For example, the setting mode of PCIe Gen4 and the setting mode of PCIe Gen2 may be switched, or the setting mode of PCIe Gen3 and the setting mode of PCIe Gen2 may be switched. That is, as long as the above Figure 4For the setting of two of the four transfer speeds shown, other combinations are also possible.

[0137] In addition, in the above-described embodiment, a configuration example of a personal computer-based information processing apparatus 1 (1a) including an embedded controller 31 has been described. However, the present invention is not limited thereto, and the information processing apparatus 1 may be configured not to include the embedded controller 31. Further, the OS of the information processing apparatus 1 is not limited to Windows (registered trademark), and may be applied to other OSs such as Android (registered trademark) and iOS (registered trademark), for example.

[0138] In addition, in the above-described embodiment, an example in which the information processing apparatus 1 (1a) and the SSD 40 (40a) are connected via a PCIe bus has been described. However, the present invention is not limited thereto, and in the case where a bus faster than the PCIe bus is newly implemented, another bus may be used.

[0139] In addition, each configuration included in the above-described information processing apparatus 1 (1a) and the SSD 40 (40a) may have a computer system inside. Then, by recording a program for implementing the functions of each configuration included in the above-described information processing apparatus 1 (1a) and the SSD 40 (40a) on a computer-readable recording medium, and causing the computer system to read and execute the program recorded on the recording medium, the processing in each configuration included in the above-described information processing apparatus 1 (1a) and the SSD 40 (40a) is performed. Here, "causing the computer system to read and execute the program recorded on the recording medium" includes installing the program in the computer system. The "computer system" as used herein includes hardware such as an OS and peripheral devices.

[0140] In addition, the "computer system" may include a plurality of computer devices connected via a network including communication lines such as the Internet, a WAN, a LAN, and a dedicated line. Further, the "computer-readable recording medium" refers to a storage device such as a floppy disk, an optical disk, a ROM, a CD-ROM, or the like, which is a removable medium, or a hard disk built in the computer system. Thus, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

[0141] In addition, the recording medium also includes an internal or external recording medium that can be accessed from a distribution server for distributing the program. Further, the program may be divided into multiple parts, downloaded at different timings, and then merged in each component provided in the information processing device 1 (1a) and the SSD 40 (40a). The distribution servers for distributing the divided programs are different. Also, the "computer-readable recording medium" includes a recording medium that holds the program for a certain period of time, such as a volatile memory (RAM) inside a computer system of a server or a client when the program is transmitted via a network. Additionally, the above program may be a program that implements a part of the above functions. Also, it may be a program that can implement the above functions through combination with a program already recorded in the computer system, that is, a so-called differential file (differential program).

[0142] In addition, the above functions may be implemented in part or in whole as an integrated circuit such as an LSI (Large Scale Integration). Each of the above functions may be processorized independently, or part or all of them may be integrated and processorized. Further, the method of integrating into an integrated circuit is not limited to LSI and may be implemented by a dedicated circuit or a general-purpose processor. Also, in the case where an integrated circuit technology that replaces LSI appears due to the development of semiconductor technology, an integrated circuit based on that technology may be used.

Claims

1. A solid state hard disk is a solid state hard disk that can be connected to an information processing device, wherein: have: Non-volatile memory capable of being electrically rewritten; and A memory controller is a memory controller that accepts processing commands for the above-mentioned non-volatile memory and executes processing corresponding to the above-mentioned processing commands. The memory controller switches between a first processing mode with higher processing capability for the above-mentioned non-volatile memory and a second processing mode with lower processing capability than the above-mentioned first processing mode according to the value of QD (Queue Depth) representing the number of the above-mentioned processing commands issued by the above-mentioned information processing device at one time.

2. The solid state drive according to claim 1, wherein: Able to be connected to the above-mentioned information processing device via a PCIe (Peripheral Component Interconnect-Express) bus, The memory controller confirms the buffer storage unit upon receipt of a notification indicating that the processing command is stored in the buffer storage unit of the information processing device, switches to the first processing mode when the value of the QD is greater than a prescribed threshold, and switches to the second processing mode when the value of the QD is less than the prescribed threshold.

3. The solid state drive according to claim 2, wherein: The memory controller changes the transmission speed of the PCIe bus to a mode lower than that of the first processing mode in the second processing mode, and changes the transmission speed of the PCIe bus to a mode higher than that of the second processing mode in the first processing mode.

4. The solid state drive according to claim 3, wherein: The memory controller is capable of processing the processing commands in parallel through multiple threads, and switching to the first processing mode when at least one of the QD values ​​corresponding to the multiple threads stored in the buffer storage unit is above the specified threshold.

5. An information processing device, wherein: A solid state hard disk having any one of claims 1 to 4 built therein.

6. An information processing device, wherein: have: A solid state drive comprising an electrically rewritable nonvolatile memory and a memory controller for receiving a processing command to the nonvolatile memory and executing a process corresponding to the processing command; and The main control unit is the main control unit that issues the above-mentioned processing commands. The main control unit switches the above-mentioned solid-state hard disk between a first processing mode with higher processing capability for the above-mentioned non-volatile memory and a second processing mode with lower processing capability than the above-mentioned first processing mode according to the value of QD (Queue Depth) representing the number of the above-mentioned processing commands issued to the above-mentioned solid-state hard disk at one time.

7. A control method for a solid state hard disk that can be connected to an information processing device, the solid state hard disk comprising an electrically rewritable non-volatile memory and a memory controller that receives a processing command to the non-volatile memory and executes a process corresponding to the processing command, wherein: The control method comprises: The memory controller switches the processing steps between a first processing mode having higher processing capability for the nonvolatile memory and a second processing mode having lower processing capability than the first processing mode according to a value of QD (Queue Depth) indicating the number of processing commands issued at one time by the information processing device.

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