A data processing method, device, storage medium and electronic device

Abstract

Embodiments of the present disclosure provide a data processing method, apparatus, storage medium, and electronic device, relating to the field of computer technologies. The method is applied to a solid-state drive, and the method includes: in response to a write request, obtaining first information of the solid-state drive, where the first information characterizes a working mode of the solid-state drive; performing a write operation according to the working mode and the write request; wherein, the processing priorities of garbage collection and the write request are different under different working modes; and the triggering conditions of different working modes are different. In this way, garbage collection and write requests are processed through different working modes to improve the processing mechanism of garbage collection and reduce the average latency of IO operations.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method, device, storage medium, and electronic device. Background Art

[0002] On a mechanical hard drive, the process of writing a file is relatively simple and flexible. Because mechanical hard drives use magnetic storage technology, the magnetic head magnetizes the magnetic material on the platter, creating a magnetization pattern that corresponds to the data. Due to this characteristic of mechanical hard drives, when a user needs to write new data, if the storage location of the new data is the same as or overlaps with the old data, the new data will directly overwrite the old data.

[0003] However, in solid-state drives (SSDs), NAND flash memory (a type of non-volatile flash memory technology) uses non-volatile storage technology, so written data cannot be directly overwritten. Each storage cell must be erased before writing data, and the erase unit is the flash block. This means that if new data is to be written to a flash block that has already been written, the valid data on that flash block must first be moved to another flash block. Once the entire flash block is completely filled with invalid data, the entire flash block must be erased. Garbage collection, based on this NAND mechanism, organizes valid data on data blocks and clears unused flash blocks to make room for new data.

[0004] The garbage collection technology currently in widespread use generally adopts a preset fixed threshold mechanism, which is based on a key condition: when the number of flash memory blocks available for allocation in the system drops below a predetermined critical value, the garbage collection process will be triggered. The main purpose of this design is to ensure that the storage system can effectively manage its limited space resources and avoid users being unable to perform data write operations due to insufficient space. Specifically, when the system detects that the number of remaining available flash memory blocks is lower than the fixed threshold, garbage collection begins to operate. By identifying and cleaning up those data blocks that are no longer needed by the system or users (i.e., "garbage" data), the occupied space is freed up and made available again for subsequent data write needs.

[0005] However, existing technologies employ a fixed threshold strategy for triggering garbage collection. Once this threshold is reached and garbage collection is initiated, under heavy input / output (IO) load, the garbage collection process inevitably increases the workload of migrating valid data and cleaning up discarded flash blocks. This additional burden can cause delays in IO read and write operations issued by the host, temporarily impairing the overall performance of the SSD. More seriously, this process can trigger unstable fluctuations in overall drive performance, known as performance jitter, which poses a challenge to smooth system operation. Summary of the Invention

[0006] The present disclosure provides a data processing method, device, storage medium and electronic device to at least solve the above technical problems existing in the prior art.

[0007] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0008] In a first aspect, an embodiment of the present disclosure provides a data processing method, which is applied to a solid-state drive and includes:

[0009] In response to a write request, obtaining first information of the solid-state hard disk, where the first information represents an operating mode of the solid-state hard disk;

[0010] Performing a write operation according to the working mode and the write request;

[0011] Among them, the processing priorities of garbage collection and the write request are different in different working modes; and the triggering conditions of different working modes are different.

[0012] In a second aspect, an embodiment of the present disclosure provides a data processing device, which is applied to an electronic device and includes:

[0013] A first processing module is configured to obtain first information of the solid-state drive in response to a write request, where the first information represents an operating mode of the solid-state drive;

[0014] A second processing module, configured to perform a write operation according to the working mode and the write request;

[0015] Among them, the processing priorities of garbage collection and the write request are different in different working modes; and the triggering conditions of different working modes are different.

[0016] In the above solution, the step of obtaining the first information of the solid state drive includes:

[0017] Determining the number of available flash memory blocks of the solid state drive;

[0018] If the number is less than a first threshold and greater than a second threshold, determining that the operating mode is the first mode;

[0019] If the number is less than a second threshold, determining that the operating mode is the second mode;

[0020] If the number is greater than a first threshold, it is determined that the working mode is the third mode.

[0021] In the above solution, if the working mode is the first mode, performing a write operation according to the working mode and the write request includes:

[0022] Obtaining first statistical data; the first statistical data includes historical input and output load conditions of each channel;

[0023] Determine an erase decision probability and a write decision probability of each flash memory chip corresponding to each channel according to the first statistical data;

[0024] A first target operation to be executed is determined according to the erase decision probability and the write decision probability, where the first target operation is an erase operation or a write operation corresponding to the write request.

[0025] In the above solution, determining the erase decision probability and the write decision probability of each flash memory chip corresponding to each channel according to the first statistical data includes:

[0026] Determine an erase decision coefficient based on the average idle time of a unit block and the average erase time of a unit block of each flash memory chip; and determine an erase decision probability based on the erase decision coefficient;

[0027] A write decision coefficient is determined based on the average idle time of a unit block and the average read and write time of a unit block of each flash memory chip; and a write decision probability is determined based on the write decision coefficient.

[0028] In the above solution, determining the first target operation to be performed based on the erase decision probability and the write decision probability includes:

[0029] If the erase decision probability is greater than a third threshold, generating a first pseudo-random number, and if the first pseudo-random number satisfies a random number condition, determining that the first target operation is an erase operation;

[0030] If the write decision probability is greater than a fourth threshold, a second pseudo-random number is generated. If the second pseudo-random number satisfies a random number condition, the first target operation is determined to be the write operation corresponding to the write request.

[0031] In the above solution, the first pseudo-random number satisfies the random number condition, including: a first evaluation value obtained by performing a remainder operation on the first pseudo-random number based on a preset rule is greater than a fifth threshold;

[0032] The second pseudo-random number satisfies a random number condition, including: a second evaluation value obtained by performing a modulo operation on the second pseudo-random number based on a preset rule is greater than a sixth threshold.

[0033] In the above solution, if the first target operation is an erase operation, the method further includes:

[0034] Acquire second statistical data; the second statistical data includes historical information related to the erase and write operations;

[0035] determining an erase benefit of at least one flash memory block based on the second statistical data;

[0036] A target flash memory block whose erase yield satisfies an erase condition is determined as the flash memory block on which an erase operation is to be performed.

[0037] In the above solution, the second statistical data includes at least one of the following information for each flash memory block:

[0038] Erasure duration;

[0039] The relationship coefficient between the number of erase and write times and time;

[0040] All data space and damaged data space;

[0041] Maximum number of erase / write cycles and number of erase / write cycles performed;

[0042] Determining an erase benefit of at least one flash memory block according to the second statistical data includes:

[0043] determining a remaining data space based on the entire data space and the damaged data space;

[0044] Determine the remaining number of erase times according to the maximum number of erase times and the number of erase times performed;

[0045] The erase benefit is determined according to the erase duration, the relationship coefficient between the erase times and time, the remaining data space, and the remaining erase times.

[0046] In the above solution, determining the target flash memory block whose erase profit satisfies the erase condition includes:

[0047] determining a flash memory block with the greatest erase benefit from at least one flash memory block to be erased;

[0048] If the erase profit of the flash memory block with the largest erase profit is positive, the flash memory block with the largest erase profit is determined as the target flash memory block.

[0049] In the above solution, if the working mode is the second mode, performing a write operation according to the working mode and the write request includes:

[0050] Determining the amount of recovered data corresponding to the garbage collection and the amount of written data corresponding to the write request;

[0051] If the amount of recovered data is greater than the amount of written data, adding the write request to an execution command queue;

[0052] If the amount of recovered data is less than or equal to the amount of written data, the write request is added to a waiting command queue.

[0053] In the above solution, if the working mode is the third mode, performing a write operation according to the working mode and the write request includes:

[0054] A write operation is performed according to the write request.

[0055] In the above solution, the solid-state hard disk includes: a controller, a flash memory chip and a channel, wherein the channel is used to connect the flash memory chip and the controller;

[0056] Each of the channels is connected to one or more flash memory chips;

[0057] Each of the flash memory chips includes: one or more flash memory blocks.

[0058] In a third aspect, an embodiment of the present disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the data processing methods described.

[0059] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute any one of the data processing methods.

[0060] The embodiments of the present disclosure have the following beneficial effects:

[0061] The data processing method, device, storage medium, and electronic device provided in the embodiments of the present disclosure are applied to obtain first information of a solid-state drive in response to a write request, wherein the first information represents the operating mode of the solid-state drive; a write operation is performed according to the operating mode and the write request; wherein the processing priorities of garbage collection and the write request are different under different operating modes; and the triggering conditions of different operating modes are different. In this way, garbage collection and I / O requests (such as write requests) are processed through different operating modes to improve the garbage collection processing mechanism and reduce the average delay of I / O operations.

[0062] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A flowchart of a data processing method provided in an embodiment of the present disclosure;

[0064] Figure 2 A schematic structural diagram of a solid-state hard disk provided in an embodiment of the present disclosure;

[0065] Figure 3 A flowchart of a processing method in an IGC mode provided in an embodiment of the present disclosure;

[0066] Figure 4 A flowchart of an erasure processing method provided by an embodiment of the present disclosure;

[0067] Figure 5 A flowchart of a method for optimizing solid-state disk IO load performance provided by an embodiment of the present disclosure;

[0068] Figure 6 A schematic diagram of the structure of an electronic device based on solid-state disk IO load performance optimization provided by an embodiment of the present disclosure;

[0069] Figure 7 A schematic structural diagram of a data processing device provided in an embodiment of the present disclosure;

[0070] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0072] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0073] If descriptions similar to "first / second" appear in the application documents, the following explanations shall be added. In the following descriptions, the terms "first / second / third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. Understandably, "first / second / third" can be interchanged in a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0075] Figure 1 A flowchart of a data processing method provided for an embodiment of the present disclosure is shown as Figure 1 shown. The method is applied to a solid-state drive, and the data processing method includes:

[0076] Step 101: In response to a write request, obtain first information of the solid-state drive, where the first information characterizes the working mode of the solid-state drive;

[0077] Step 102: Perform a write operation according to the working mode and the write request;

[0078] Among them, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different.

[0079] Here, the working mode characterizes how to process the write request and garbage collection (GC, Garbage Collection); that is, based on the working mode, the priorities of garbage collection and the write request, and whether garbage collection can be interrupted are determined.

[0080] Among them, the working mode includes at least one of the following: the first mode, the second mode, and the third mode;

[0081] The first mode characterizes an interruptible garbage collection (IGC) mode; in this mode, the garbage collection process can be interrupted by other operations (such as a write request), that is, when there is a write request, the garbage collection will pause and the write request will be processed preferentially.

[0082] The second mode is an uninterruptible garbage collection (UGC) mode; in this mode, the garbage collection will continue and cannot be interrupted by a write request, and the write request must wait until the garbage collection operation is completed before it can be executed.

[0083] The third mode represents a mode that is neither the IGC mode nor the UGC mode; in this mode, no garbage collection process is enabled, and the write request is directly executed.

[0084] Here, in different working modes, the priorities of garbage collection and write operations are different. For example, in the first mode (IGC mode), the priority of the write request is higher than that of garbage collection, while in the second mode (UGC mode), the priority of garbage collection is higher, and the write request will be delayed. In the third mode, there is no garbage collection operation, only write requests.

[0085] In the embodiments of the present disclosure, by setting two thresholds, multiple working modes are triggered. In different working modes, the solid-state drive processes write requests and garbage collection operations according to priorities, ensuring that the system can minimize the waste of storage space without affecting performance. In the IGC mode, write requests can be processed preferentially to ensure efficient read and write operations. In the UGC mode, garbage collection is executed preferentially, avoiding repeated writing to storage units, thereby extending the service life of the hard disk. Through these flexible working modes, the solid-state drive can adjust its working mode according to different load requirements, reduce latency, improve the system response speed, optimize storage performance, and enhance the user experience.

[0086] In some embodiments, the obtaining of the first information of the solid-state drive includes:

[0087] Determine the number of available flash blocks of the solid-state drive;

[0088] If the number is less than the first threshold and greater than the second threshold, determine that the working mode is the first mode;

[0089] If the number is less than the second threshold, determine that the working mode is the second mode;

[0090] If the number is greater than the first threshold, determine that the working mode is the third mode.

[0091] Here, the solid-state drive (SSD) is a storage device that stores data through flash chips.

[0092] The flash chip (NAND Flash Chip) is the storage unit inside the solid-state drive and is responsible for storing all data. The solid-state drive includes multiple flash chips, and each flash chip can contain multiple flash blocks. These flash chips adopt NAND flash technology to store binary data.

[0093] A flash block is an important part of a flash memory chip. Each flash block can contain multiple pages. A flash block can also be called a block or a data block, and it can be understood that the flash block is the underlying storage unit.

[0094] The available flash blocks can be used to represent the flash blocks that can be used to store new data. In the management of a solid-state drive, the controller of the solid-state drive can monitor which blocks are idle and unused, that is, determine the available data blocks. The number of available flash blocks is denoted as , where the first threshold is greater than the second threshold, that is, the first threshold is a high threshold, denoted as , and the second threshold is a low threshold, denoted as .

[0095] When , no processing is enabled, and the working mode is determined to be the third mode, and the write operation can be directly executed;

[0096] When , the working mode is determined to be the first mode, that is, enter the processing flow of the IGC mode;

[0097] When , the working mode is determined to be the second mode, that is, enter the processing flow of the UGC mode.

[0098] The first threshold and the second threshold are set based on experience, experiments, etc., and no specific values are limited.

[0099] In some embodiments, the method further includes:

[0100] Receiving a read request;

[0101] In response to the read request, performing the read operation corresponding to the read request.

[0102] Here, considering the unique nature of the flash memory in the solid-state drive, its reading speed is often significantly faster than the writing speed. Therefore, when the IO request is a read request, the read operation can be directly executed; if the IO request is a write request, the data processing operation is performed according to step 101 and step 102 to implement the operation corresponding to the write request.

[0103] In some embodiments, if the working mode is the first mode, according to the working mode and the write request, performing the write operation, including:

[0104] Obtaining first statistical data;

[0105] Determining the erase decision probability and write decision probability of each flash memory chip corresponding to each channel according to the first statistical data;

[0106] Determine a first target operation to be performed according to the erasure decision probability and the write decision probability, where the first target operation is an erasure operation or a write operation corresponding to the write request.

[0107] Here, the first statistical data includes the historical input / output (IO) load conditions of each channel; for example, it may include at least one of the following:

[0108] The number of write operations, duration, and data volume of each flash memory chip through each channel in the past period of time;

[0109] The number of erasure operations, duration, and data volume of each flash memory chip through each channel in the past period of time;

[0110] The usage of the free space of each flash memory chip.

[0111] It should be noted that the information for each memory chip above includes the information of each flash memory block in each memory chip, such as the free space of the flash memory block, the number of write operations, etc.

[0112] In some embodiments, determining the erasure decision probability and the write decision probability of each flash memory chip corresponding to each channel according to the first statistical data includes:

[0113] Determine an erasure decision coefficient according to the average free duration per unit block and the average erasure duration per unit block of each flash memory chip; determine the erasure decision probability according to the erasure decision coefficient;

[0114] Determine a write decision coefficient according to the average free duration per unit block and the average read / write duration per unit block of each flash memory chip; determine the write decision probability according to the write decision coefficient.

[0115] Here, the erasure decision coefficient is calculated according to the average free duration per unit block and the average erasure duration per unit block, and is used to evaluate whether the flash memory chip is suitable for being erased. This coefficient can reflect the efficiency of the erasure operation;

[0116] The erasure decision probability is used to indicate the demand and priority for erasing the flash memory chip by the current solid-state drive.

[0117] Among them, the average free duration per unit block refers to: the average duration that the flash memory block in the flash memory chip is in the free state.

[0118] The average erasure duration per unit block refers to: the average duration of the erasure operation of the flash memory block in the flash memory chip. The erasure speeds of different solid-state drives can be different, resulting in different erasure durations.

[0119] Here, the write decision coefficient is calculated based on the average read / write duration of the unit block, and is used to evaluate whether the flash memory chip is suitable for write operations. The lower the write decision coefficient, the higher the efficiency of the write operation, and the more inclined to select the flash memory chip for writing.

[0120] The write decision probability is determined based on the write decision coefficient, and reflects whether to select the current channel to perform write operations on the corresponding flash memory chip.

[0121] The average read / write duration of the unit block refers to the average duration of read / write operations of the flash blocks in the flash memory chip.

[0122] Specifically, according to the first statistical data, the erase decision probability and the write decision probability of each flash memory chip corresponding to each channel are determined (denoted as ), and the calculation process is as follows:

[0123] Step 001: Determine the erase decision coefficient (denoted as ) according to the average idle duration of the unit block and the average erase duration of each flash memory chip, as follows:

[0124] (1)

[0125] Where, is the average idle duration of the unit block. Here, the idle durations within each statistical period can be statistically counted according to the statistical period, and the average value of the idle durations of each statistical period is calculated to obtain the average idle duration of the unit block; is the average erase duration of the unit block;

[0126] As shown in Equation 1, when , is 1; otherwise is 0.

[0127] Step 002: Determine the erase decision probability according to the erase decision coefficient; as follows:

[0128] (2)

[0129] Where, is the erase decision probability, is the i-th time point; m is less than n. For example, m is 5 and n is a value greater than 5;

[0130] is the proportion of the processing mechanism judgment for the current time (i.e., from the first time point to the m-th time point as described above), is the proportion of the processing mechanism judgment for the overall time (i.e., from the first time point to the n-th time point);

[0131] Here, the processing mechanism judgment refers to: determining whether to perform an erase operation on the flash memory chip;

[0132] It can be adjusted according to the operation conditions of a specific period. For example, if the memory chip is frequently erased during a period of time, then A higher value indicates that the operations in the current time period have a greater impact on the decision.

[0133] If the write operation is continued for a long time, then The value of will gradually decrease, and adjustments based on this change will make the decision-making mechanism more stable and steady. That is, the weight of operations in the current period will be gradually reduced, and more reliance will be placed on the overall operation trend in the longer term.

[0134] Considering that in the garbage collection process, valid data needs to be read out before subsequent write operations are performed, the embodiments of the present disclosure propose to treat the read and write operations as a whole write operation for processing.

[0135] Specifically, the write decision probability of each channel is calculated according to the first statistical data ( ),include:

[0136] Step 011: Determine the write decision coefficient based on the average idle time of the unit block and the average read and write time of the unit block, as shown in the following formula:

[0137] (3)

[0138] in, To write the decision coefficient, is the average idle time of the unit block, is the average read and write time of a unit block, is the average read time per unit block, Write time for unit quick assessment, when hour, is 1; otherwise is 0.

[0139] Step 012: Determine the write decision probability based on the write decision coefficient, as follows:

[0140] (4)

[0141] in, To write the decision probability, is the i-th time point; m is less than n, for example, m is 5 and n is a value greater than 5;

[0142] is the weight of the processing mechanism judgment for the current time (i.e., from the first time point to the mth time point mentioned above), Represents the proportion of the processing mechanism judgment for the overall time (i.e., from the first time point to the nth time point);

[0143] Here, the processing mechanism judgment refers to: determining whether to perform a write operation on the flash chip;

[0144] It can be adjusted according to the operation conditions in a specific period. For example, if the memory chip performs write operations frequently within a period of time, then The value will be higher, indicating that the operation in the current period has a greater impact on the decision-making.

[0145] If it has been a write operation for a long time, then The value will gradually decrease, and the decision-making mechanism is adjusted according to this change to make it more stable. That is, gradually reduce the weight of the operation in the current period, and thus rely more on the overall operation trend in the longer term.

[0146] In some embodiments, determining the first target operation to be executed according to the erase decision probability and the write decision probability includes:

[0147] If the erase decision probability is greater than the third threshold, generate a first pseudo-random number. If the first pseudo-random number meets the random number condition, determine that the first target operation is an erase operation;

[0148] If the write decision probability is greater than the fourth threshold, generate a second pseudo-random number. If the second pseudo-random number meets the random number condition, determine that the first target operation is the write operation corresponding to the write request.

[0149] Here, the third threshold and the fourth threshold are preset thresholds for determining whether to generate a random number; the two can be the same or different.

[0150] There can be a hardware module (referred to as a pseudo-random number generation module) in the solid-state drive. If the write decision probability or the erase decision probability is greater than the corresponding threshold, call the pseudo-random number generation module to generate the corresponding first pseudo-random number or second pseudo-random number.

[0151] Here, the first pseudo-random number meets the random number condition, including: the first evaluation value obtained by performing a modulo operation on the first pseudo-random number based on a preset rule is greater than the fifth threshold;

[0152] The second pseudo-random number meets the random number condition, including: the second evaluation value obtained by performing a modulo operation on the second pseudo-random number based on a preset rule is greater than the sixth threshold.

[0153] For example, the third threshold and the fourth threshold may be the same or different. Taking the same as an example, both are 70%; the fifth threshold and the sixth threshold may be the same or different. Taking the same as an example, both are 70. Specifically, if the erasure decision probability is greater than 70%, the pseudo-random number generation module is called to generate a first pseudo-random number. When the remainder of the first pseudo-random number divided by 100 is greater than 70, an erasure operation is performed on the flash memory block in the flash memory chip on the corresponding channel. If the write decision probability is greater than 70%, the pseudo-random number generation module is called to generate a second pseudo-random number. When the remainder of the second pseudo-random number divided by 100 is greater than 70, a write operation is performed on the flash memory block in the flash memory chip on the corresponding channel.

[0154] In some embodiments, if the first target operation is an erasure operation, the method further includes:

[0155] Obtaining second statistical data;

[0156] Determining the erasure gain of at least one flash memory block according to the second statistical data;

[0157] Determining the target flash memory block whose erasure gain meets the erasure condition as the flash memory block to be subjected to the erasure operation.

[0158] Here, the second statistical data includes the historical input / output load conditions of each channel, specifically referring to the additional statistical information related to the erase / write operations, which may include: the historical erasure times of the flash memory block, the utilization of the free space of the flash memory block, the write times, and the health status of the flash memory block, etc.

[0159] The erasure gain refers to the benefits that can be brought after performing the erasure operation. For example, erasing a certain flash memory block will release a large amount of storage space, reduce the latency of subsequent writes, or help improve the overall performance of the system.

[0160] The erasure condition refers to the requirements or criteria for performing the erasure operation. By setting the erasure condition, only when the erasure gain of the flash memory block is high enough and meets the erasure condition, it will be selected as the object to perform the erasure operation.

[0161] In this way, unnecessary erasure operations can be avoided, thereby improving the efficiency of the storage device and extending its service life.

[0162] In some embodiments, the second statistical data includes at least one of the following information for each flash memory block:

[0163] Erasure duration;

[0164] The correlation coefficient between the number of erase / write operations and time;

[0165] Total data space and damaged data space;

[0166] The maximum number of erase / write cycles and the number of executed erase / write cycles;

[0167] Determine the erase gain of at least one flash memory block according to the second statistical data, including:

[0168] Determine the remaining data space according to the total data space and the damaged data space;

[0169] Determine the remaining number of erase / write cycles according to the maximum number of erase / write cycles and the number of executed erase / write cycles;

[0170] Determine the erase gain according to the erase duration, the relationship coefficient between the number of erase / write cycles and time, the remaining data space, and the remaining number of erase / write cycles.

[0171] Specifically, determine the erase gain according to the erase time, the relationship coefficient between the number of erase / write cycles and time, the remaining data space, and the remaining number of erase / write cycles, including:

[0172] Step 021: Determine the relationship coefficient between the number of erase / write cycles and time according to the number of erase / write cycles and the erase time, as follows:

[0173] (5)

[0174] ]]Where k represents the relationship coefficient between the number of erase / write cycles and time within a certain time period; is the i-th time point (i.e., the erase time); is the number of erase / write cycles at the i-th time point, represents the number of erase / write cycles at the (i + 100)-th time point, ( ) represents the change in the number of erase / write cycles from the i-th time point to the (i + 100)-th time point.

[0175] Step 022: Determine the erase gain according to the relationship coefficient between the number of erase / write cycles and time, the erase duration, the remaining data space, and the remaining number of erase / write cycles, as follows:

[0176] (6)

[0177] Where is the total data space on the flash memory block (this value is obtained based on the attributes of each flash memory block of the solid-state drive), is the damaged data space on the flash memory block (i.e., the unusable data space due to damage), which can be obtained by detecting the flash memory block; is the remaining data space;

[0178] is the maximum number of erase / write cycles of the flash memory block (this value is obtained based on the attributes of each flash memory block of the solid-state drive), The number of erase / write times of the flash memory block (i.e., the current number of erase / write times) is obtained by detecting the flash memory block; The remaining number of erase and write times; The duration of the erase operation.

[0179] In the embodiment of the present disclosure, considering the duration of erasure Afterwards, get the available If the number of flash block erase and write times exceeds , may cause problems in the entire flash memory block, and the data space on the entire flash memory block will be cleared. If you erase and write according to the relationship coefficient between the current erase and write times and time, it will cause Therefore, the sum of the two is taken as the erase benefit M, which represents the actual benefit of erasing a flash memory block.

[0180] By calculating the erase benefit, the efficiency of flash memory block usage can be maximized during erase and write operations, while minimizing data loss and extending the lifespan of the flash memory blocks. Properly scheduling erase and write operations can reduce unnecessary data loss, ensuring that erase and write operations are performed only at appropriate times and avoiding flash memory block damage caused by excessive erases. By balancing the availability of data space with the risks associated with erase and write operations, this method improves flash memory utilization, reduces the risk of premature flash memory damage, and enhances system stability and reliability. Furthermore, the erase benefit model helps optimize erase and write decisions, ensuring maximum utilization of remaining available space without exceeding the maximum number of erase and write cycles, thereby improving the long-term operational stability of the entire system.

[0181] In some embodiments, determining the target flash memory block whose erase profit satisfies the erase condition includes:

[0182] determining a flash memory block with the greatest erase benefit from at least one flash memory block to be erased;

[0183] If the erase profit of the flash memory block with the largest erase profit is positive, the flash memory block with the largest erase profit is determined as the target flash memory block.

[0184] Here, among all the flash memory blocks to be erased, a hardware module (called a search module) is used to search for the flash memory block with the largest benefit M, and only when the erasure benefit M of this flash memory block is positive will the erasure operation of this flash memory block be considered.

[0185] If the erase benefit is positive, it means that the benefit of erasing the flash memory block is positive (such as releasing available space and extending the life of the flash memory block), and the flash memory block is selected as the target for erasure.

[0186] By selecting the flash blocks with the highest erase benefit, you can ensure that the erase operation delivers the greatest benefit and avoid meaningless erasures of flash blocks. By properly selecting erase targets, you can extend the overall lifespan of the flash device, reduce unnecessary wear and tear, and ensure efficient use of storage space, thereby improving the overall system efficiency.

[0187] In some embodiments, if the operating mode is the second mode, performing a write operation according to the operating mode and the write request includes:

[0188] Determining the amount of recovered data corresponding to the garbage collection and the amount of written data corresponding to the write request;

[0189] If the amount of recovered data is greater than the amount of written data, adding the write request to an execution command queue;

[0190] If the amount of recovered data is less than or equal to the amount of written data, the write request is added to a waiting command queue.

[0191] Here, the execution command queue is a queue for storing commands to be executed.

[0192] The waiting command queue is used to store commands that cannot be executed temporarily.

[0193] It can be understood that the commands in the execution command queue can be executed directly, the commands in the waiting command queue are in a pending state, and the commands in the execution command queue are executed earlier than the commands in the waiting command queue.

[0194] The second mode is the UGC mode. Considering that both garbage collection and IO operations occupy system resources, if the consumption of both is not controlled, it may lead to waste of system resources or bottlenecks. By ensuring that the amount of data collected by garbage collection is slightly larger than the amount of data written, a serious imbalance between garbage collection and IO operations can be avoided, and the excessive resource occupation of one operation causing delays in the other operation can be avoided. Therefore, in this mode, it is necessary to ensure that the amount of data collected by garbage collection is slightly larger than the amount of data to be written by IO (that is, it does not need to be larger than a certain amount, just larger is enough). When the amount of data collected by garbage collection is larger than the amount of data to be written by IO, the IO write request is placed in the execution command queue to reduce memory pressure. At the same time, it will not cause too many IO writes to be backlogged in the waiting queue, which helps the system maintain a high response speed and throughput. When the amount of data collected by garbage collection is smaller than the amount of data to be written by IO, the IO write request is placed in the waiting command queue, that is, execution is postponed. This allows the system to have more time to process other tasks during the waiting process, thereby improving concurrent processing capabilities.

[0195] In some embodiments, if the working mode is the third mode, a write operation is performed according to the working mode and the write request, including:

[0196] Performing a write operation according to the write request.

[0197] Here, the third mode represents a mode that is neither the IGC mode nor the UGC mode; in this mode, no garbage collection process is enabled, and the write request is directly executed.

[0198] In some embodiments, the method is applied to a solid-state drive, which includes: a controller, a flash memory chip, and a channel, where the channel is used to connect the flash memory chip and the controller;

[0199] Each of the channels can be connected to one or more flash memory chips;

[0200] Each flash memory chip can include: one or more flash memory blocks.

[0201] As Figure 2 shown, Figure 2 is a structural schematic diagram of a solid-state drive provided by an embodiment of the present disclosure. The solid-state drive includes: an SSD master controller (i.e., a controller), a NAND flash memory, and a channel.

[0202] The NAND flash memory includes: a plurality of flash memory chips, Figure 1 where "CHIP0-n" in it represents the multiple flash memory chips connected by the channel. Each flash memory chip is a unit of data storage and stores actual files or information. Each flash memory chip can include: one or more flash memory blocks.

[0203] The flash memory chips on the same channel share the channel bus, that is, multiple flash memory chips on the same channel share the same channel bus, which is also sharing the data transmission path. Multiple flash memory chips can execute operation commands simultaneously, that is, within one channel, multiple flash memory chips can execute the commands issued by the SSD controller in parallel to improve the data read and write efficiency.

[0204] The method provided by the embodiment of the present disclosure takes into account that during the garbage collection process triggered by the reduction of available flash memory blocks in the solid-state drive, the system simultaneously bears the IO load, resulting in a significant increase in the average latency of IO operations due to the additional operations of garbage collection. The reason is that the data migration and block erasure operations take a long time, which further causes the additional write operations during this period to encounter latency. Through the provided data processing method, the garbage collection processing mechanism is optimized, the average latency of IO operations is significantly reduced, and at the same time, during the erasure processing, the wear leveling processing effect is further optimized by quantifying the future benefits. It shows significant advantages in controlling the average latency of IO operations and improving the overall service life of the SSD.

[0205] Figure 3 A flowchart of a processing method in the IGC mode provided by an embodiment of the present disclosure; as Figure 3 shown, the statistical module and the pseudo-random number generation module need to be called in the IGC mode; among them, the statistical module is used to count the historical IO load on each channel, and the pseudo-random number generation module is used to generate pseudo-random numbers (such as the above-mentioned first pseudo-random number and second pseudo-random number). By judging whether there is a flash chip of a channel that meets the conditions (such as Figure 1 judging the first pseudo-random number and the second pseudo-random number in the method shown), if there is, perform the corresponding erasing operation or writing operation, if not, do not perform the operation.

[0206] Figure 4 A schematic flowchart of an erasing processing method provided by an embodiment of the present disclosure; as Figure 4 shown, in the erasing processing method, the statistical module and the search module need to be called. The statistical module is used to count the historical IO load on each channel, and the search module is used to search and sort to the corresponding maximum or minimum result according to a certain value (that is, the flash block with the largest erasing gain), and is responsible for quickly locating and accessing specific storage units inside the SSD according to a specific order.

[0207] Figure 5 A schematic flowchart of a method for optimizing the IO load performance based on a solid-state drive provided by an embodiment of the present disclosure; as Figure 5 shown, the statistical module respectively counts the IO load under different channels. Due to the characteristics of the flash memory, the speed of reading data is much slower than the speed of writing data. Therefore, if the IO request sent by the host is a read request, the corresponding read operation is directly executed according to the read request;

[0208] Otherwise, if the IO request is a write request, judge the number of available flash blocks at this time , compare with the high threshold and the low threshold , and determine the operation to be executed based on the comparison result; including:

[0209] If , do not start any processing and directly execute the IO write;

[0210] If the IGC threshold is reached, that is, , enter the processing in the IGC mode according to Figure 3 ;

[0211] If the UGC threshold is reached, that is, , turn on the processing mechanism in UGC mode. In UGC mode, it is necessary to ensure that the amount of data recovered by garbage collection is slightly larger than the amount of data to be written by IO. When the amount of data recovered by garbage collection is larger than the amount of data to be written by IO, the IO write request is put into the execution command queue. When the amount of data recovered by garbage collection is smaller than the amount of data to be written by IO, the IO write request is put into the waiting command queue. In UGC mode, it is necessary to ensure that the amount of data released by garbage collection is slightly larger than the amount of data required to be written by IO operations. Specifically, if the amount of data released by garbage collection exceeds the amount of data required for IO writes, the IO write request is added to the execution command queue; conversely, if the amount of data released by garbage collection is not enough to meet the IO write requirements, the IO write request is put into the waiting command queue. Due to the reasonable settings of high thresholds and below-index and the IGC processing mechanism, UGC mode is generally rarely entered.

[0212] Figure 6 A schematic diagram of the structure of an electronic device based on solid-state disk IO load performance optimization provided by an embodiment of the present disclosure; Figure 6 As shown, the electronic device includes: a host, a solid-state drive (SSD); the solid-state drive includes:

[0213] NAND Flash Memory is memory, namely NAND flash memory;

[0214] The SSD interface unit is responsible for communicating with the host, receiving and parsing data packets and IO requests from the host.

[0215] The garbage collection module organizes the contents of flash blocks, removes useless data ("garbage"), and migrates valid data to new flash blocks, ensuring that as many free flash blocks as possible are retained. This module integrates two advanced processing mechanisms, IGC and UGC.

[0216] The erase module is used to clean up the flash memory blocks that are completely occupied by invalid data, ensuring further purification and effective utilization of storage resources.

[0217] The statistics module plays the role of data traffic monitoring, statistics and analyzes the IO load status under different channels, and provides detailed data support for system optimization.

[0218] The pseudo-random number generation module is used to generate pseudo-random numbers (such as the first pseudo-random number and the second pseudo-random number mentioned above).

[0219] The search module is used to quickly locate and access specific memory cells within the SSD according to established rules. Based on the erase processing mechanism, the search module can properly store the address value of the flash memory block with the highest ranking value in a register based on the calculated erase profit M value.

[0220] In the embodiments of the present disclosure, the process of block search is accelerated by introducing a hardware acceleration module, namely a search module. When performing an erasure operation, according to the evaluation of future benefits, the flash block with the greatest future benefit (i.e., the above-mentioned target flash block) is searched for and preferentially erased. The search module searches for the block with the maximum benefit M and only considers performing an erasure when the benefit M of the block is positive. By optimizing the erasure order of flash blocks, while ensuring efficient erasure, wear leveling is also taken into account, thus providing a strong guarantee for extending the overall service life of the SSD.

[0221] Figure 7 It is a schematic structural diagram of a data processing device provided by an embodiment of the present disclosure; as Figure 7 shown, the device is applied to a solid-state drive, and the device includes:

[0222] A first processing module, configured to obtain first information of the solid-state drive in response to a write request, where the first information characterizes the working mode of the solid-state drive;

[0223] A second processing module, configured to perform a write operation according to the working mode and the write request;

[0224] Among them, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different.

[0225] In some embodiments, the first processing module is configured to determine the number of available flash blocks of the solid-state drive;

[0226] If the number is less than a first threshold and greater than a second threshold, determine that the working mode is the first mode;

[0227] If the number is less than the second threshold, determine that the working mode is the second mode;

[0228] If the number is greater than the first threshold, determine that the working mode is the third mode.

[0229] In some embodiments, the second processing module is configured to, if the working mode is the first mode, obtain first statistical data; the first statistical data includes the historical input / output load conditions of each channel;

[0230] Determine the erasure decision probability and write decision probability of each flash chip corresponding to each channel according to the first statistical data;

[0231] Determine a first target operation to be executed according to the erasure decision probability and the write decision probability, where the first target operation is an erasure operation or a write operation corresponding to the write request.

[0232] In some embodiments, the second processing module is configured to determine an erasure decision coefficient according to the average idle duration per unit block and the average erasure duration per unit block of each flash memory chip; and determine an erasure decision probability according to the erasure decision coefficient.

[0233] Determine a write decision coefficient according to the average idle duration per unit block and the average read / write duration per unit block of each flash memory chip; and determine a write decision probability according to the write decision coefficient.

[0234] In some embodiments, if the erasure decision probability is greater than a third threshold, the second processing module is configured to generate a first pseudo-random number, and if the first pseudo-random number meets the random number condition, determine that the first target operation is an erasure operation.

[0235] If the write decision probability is greater than a fourth threshold, generate a second pseudo-random number, and if the second pseudo-random number meets the random number condition, determine that the first target operation is the write operation corresponding to the write request.

[0236] In some embodiments, the first pseudo-random number meeting the random number condition includes: a first evaluation value obtained by performing a remainder operation on the first pseudo-random number based on a preset rule is greater than a fifth threshold.

[0237] The second pseudo-random number meeting the random number condition includes: a second evaluation value obtained by performing a remainder operation on the second pseudo-random number based on a preset rule is greater than a sixth threshold.

[0238] In some embodiments, if the first target operation is an erasure operation, the second processing module is further configured to obtain second statistical data; the second statistical data includes historical information related to erasure and write operations.

[0239] Determine the erasure gain of at least one flash memory block according to the second statistical data.

[0240] Determine a target flash memory block whose erasure gain meets the erasure condition as the flash memory block to be subjected to the erasure operation.

[0241] In some embodiments, the second statistical data includes at least one of the following information of each flash memory block:

[0242] Erasure duration;

[0243] Coefficient of the relationship between the number of erase / write operations and time;

[0244] Total data space and damaged data space;

[0245] Maximum number of erase / write operations and number of executed erase / write operations;

[0246] The second processing module is configured to determine the remaining data space according to the total data space and the damaged data space.

[0247] Determine the remaining number of erase cycles based on the maximum number of erase cycles and the number of executed erase cycles;

[0248] Determine the erase benefit based on the erase duration, the relationship coefficient between the number of erase cycles and time, the remaining data space, and the remaining number of erase cycles.

[0249] In some embodiments, the second processing module is configured to determine the flash memory block with the maximum erase benefit from at least one flash memory block to be erased;

[0250] If the erase benefit of the flash memory block with the maximum erase benefit is positive, determine the flash memory block with the maximum erase benefit as the target flash memory block.

[0251] In some embodiments, the second processing module is configured to, if the working mode is the second mode, determine the amount of recycled data corresponding to garbage collection and the amount of written data corresponding to the write request;

[0252] If the amount of recycled data is greater than the amount of written data, add the write request to the execution command queue;

[0253] If the amount of recycled data is less than or equal to the amount of written data, add the write request to the waiting command queue.

[0254] In some embodiments, the second processing module is configured to, if the working mode is the third mode, perform a write operation according to the write request.

[0255] In some embodiments, the solid-state drive includes: a controller, a flash memory chip, and a channel, and the channel is used to connect the flash memory chip and the controller;

[0256] Each of the channels is connected to one or more flash memory chips;

[0257] Each of the flash memory chips includes: one or more flash memory blocks.

[0258] It can be understood that when implementing the corresponding data processing method, the data processing device provided in the above embodiments may, as needed, allocate the above processing to different program modules to complete all or part of the processing described above. In addition, the device provided in the above embodiments and the embodiments of the corresponding method belong to the same concept, and the specific implementation process is detailed in the method embodiments and will not be repeated here.

[0259] An embodiment of the present application provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes a data processing method.

[0260] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, where the executable instructions, when executed by a processor, cause the processor to execute the data processing method provided by the embodiment of the present application.

[0261] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or may be various devices including one or any combination of the above memories.

[0262] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, and may be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0263] As an example, the executable instructions may or may not correspond to a file in a file system, and may be stored as part of a file that stores other programs or data. For example, they may be stored in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program being discussed, or stored in multiple cooperating files (such as files storing one or more modules, subroutines, or code portions).

[0264] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one location, or on multiple computing devices distributed at multiple locations and interconnected by a communication network.

[0265] Figure 8 A schematic structural diagram of an electronic device provided by an embodiment of the present disclosure; as Figure 8 shown, the electronic device 80 includes: a processor 801, and a memory 802 communicatively connected to the processor 801; the memory 802 stores instructions executable by the processor 801. The instructions are executed by the processor 801 so that the processor 801 can execute:

[0266] In response to a write request, obtain first information of the solid state drive, where the first information characterizes the working mode of the solid state drive;

[0267] Execute a write operation according to the working mode and the write request;

[0268] Wherein, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different.

[0269] The electronic device provided in the above embodiment and the embodiment of the corresponding data processing method belong to the same concept. For the specific implementation process, please refer to the method embodiment, which will not be elaborated here.

[0270] In practical applications, the electronic device 80 may further include: at least one network interface 803. Each component in the electronic device 80 is coupled together through a bus system 804. It can be understood that the bus system 804 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in Figure 8 all kinds of buses are labeled as the bus system 804. Among them, the number of the processors 801 can be at least one, and the number of the memories 802 can be at least one. The network interface 803 is used for the communication between the electronic device 80 and other devices in a wired or wireless manner.

[0271] The memory 802 in the embodiment of the present disclosure is used to store various types of data to support the operation of the electronic device 80.

[0272] The methods disclosed in the above embodiments of the present disclosure can be applied to or implemented by the processor 801. The processor 801 may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above methods can be completed by the integrated logic circuit in hardware or instructions in software form in the processor 801. The above-mentioned processor 801 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 801 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the methods disclosed in the embodiments of the present disclosure, it can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, and this storage medium is located in the memory 802. The processor 801 reads the information in the memory 802 and combines its hardware to complete the steps of the foregoing data processing method.

[0273] In some embodiments, the electronic device 80 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontroller units (MCUs), microprocessors, or other electronic components for executing the foregoing methods.

[0274] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. There is no limitation herein.

[0275] In the above description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0276] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by those skilled in the art in the art of this disclosure. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0277] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0278] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0279] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data processing method, characterized in that, The method is applied to a solid-state drive, and the method includes: In response to a write request, obtain first information of the solid-state drive, where the first information characterizes the working mode of the solid-state drive; Execute a write operation according to the working mode and the write request; Among them, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different; The obtaining of the first information of the solid-state drive includes: Determine the number of available flash memory blocks of the solid-state drive; If the number is less than a first threshold and greater than a second threshold, determine that the working mode is a first mode; If the number is less than the second threshold, determine that the working mode is a second mode; If the number is greater than the first threshold, determine that the working mode is a third mode; If the working mode is the first mode, executing a write operation according to the working mode and the write request includes: Obtain first statistical data; the first statistical data includes the historical input / output load conditions of each channel; Determine the erase decision probability and write decision probability of each flash memory chip corresponding to each channel according to the first statistical data; Determine a first target operation to be executed according to the erase decision probability and the write decision probability, where the first target operation is an erase operation or a write operation corresponding to the write request.

2. The method according to claim 1, wherein Determining the erase decision probability and write decision probability of each flash memory chip corresponding to each channel according to the first statistical data includes: Determine an erase decision coefficient according to the average idle duration per unit block and the average erase duration per unit block of each flash memory chip; determine the erase decision probability according to the erase decision coefficient; Determine a write decision coefficient according to the average idle duration per unit block and the average read / write duration per unit block of each flash memory chip; determine the write decision probability according to the write decision coefficient.

3. The method according to claim 1, wherein The determining of the first target operation to be executed according to the erase decision probability and the write decision probability includes: If the erase decision probability is greater than a third threshold, generate a first pseudo-random number, and if the first pseudo-random number meets the random number condition, determine that the first target operation is an erase operation; If the write decision probability is greater than a fourth threshold, generate a second pseudo-random number, and if the second pseudo-random number meets the random number condition, determine that the first target operation is the write operation corresponding to the write request.

4. The method according to claim 3, characterized in that, The first pseudo-random number meets the random number condition, including: a first evaluation value obtained by performing a modulo operation on the first pseudo-random number based on a preset rule is greater than a fifth threshold; The second pseudo-random number meets the random number condition, including: a second evaluation value obtained by performing a modulo operation on the second pseudo-random number based on a preset rule is greater than a sixth threshold.

5. The method according to claim 1, wherein If the first target operation is an erase operation, the method further includes: Obtain second statistical data; the second statistical data includes historical information related to erase and write operations; Determine the erase gain of at least one flash memory block according to the second statistical data; Determine a target flash memory block whose erase gain meets the erase condition as the flash memory block to be subjected to the erase operation.

6. The method according to claim 5, characterized in that, The second statistical data includes at least one of the following information of each flash memory block: Erase duration; The relationship coefficient between the number of erase and write times and time; All data space and damaged data space; Maximum number of erase / write cycles and number of executed erase / write cycles; Determining the erase benefit of at least one flash memory block according to the second statistical data, including: Determining the remaining data space according to the all data space and the damaged data space; Determining the remaining number of erase / write cycles according to the maximum number of erase / write cycles and the number of executed erase / write cycles; Determining the erase benefit according to the erase duration, the relationship coefficient between the number of erase / write cycles and time, the remaining data space, and the remaining number of erase / write cycles.

7. The method according to claim 6, wherein The determining the target flash memory block whose erase benefit meets the erase condition includes: Determining the flash memory block with the maximum erase benefit from at least one flash memory block to be erased; If the erase benefit of the flash memory block with the maximum erase benefit is positive, determining the flash memory block with the maximum erase benefit as the target flash memory block.

8. The method according to claim 1, wherein If the working mode is the second mode, performing a write operation according to the working mode and the write request, including: Determining the amount of recycled data corresponding to garbage collection and the amount of write data corresponding to the write request; If the amount of recycled data is greater than the amount of write data, adding the write request to the execution command queue; If the amount of recycled data is less than or equal to the amount of write data, adding the write request to the waiting command queue.

9. The method according to claim 1, characterized in that, If the working mode is the third mode, performing a write operation according to the working mode and the write request, including: Performing a write operation according to the write request.

10. The method according to claim 1, characterized in that, The solid state drive includes: a controller, flash memory chips, and channels for connecting the flash memory chips and the controller; Each of the channels is connected to one or more flash memory chips; Each of the flash memory chips includes: one or more flash memory blocks.

11. A data processing device, characterized in that, The device is applied to a solid state drive, and the device includes: A first processing module, configured to obtain first information of the solid state drive in response to a write request, where the first information characterizes the working mode of the solid state drive; A second processing module, configured to perform a write operation according to the working mode and the write request; Wherein, the processing priorities of garbage collection and the write request are different in different working modes; the triggering conditions of different working modes are different; The first processing module is configured to determine the number of available flash memory blocks of the solid state drive; If the number is less than a first threshold and greater than a second threshold, determining that the working mode is the first mode; If the number is less than the second threshold, determining that the working mode is the second mode; If the number is greater than the first threshold, determining that the working mode is the third mode; The second processing module is configured to, if the working mode is the first mode, obtain first statistical data; the first statistical data includes the historical input / output load conditions of each channel; Determining the erase decision probability and the write decision probability of each flash memory chip corresponding to each channel according to the first statistical data; Determining a first target operation to be executed according to the erase decision probability and the write decision probability, where the first target operation is an erase operation or a write operation corresponding to the write request.

12. An electronic device, characterized in that, Including: At least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions, when executed by the at least one processor, enable the at least one processor to perform the method according to any one of claims 1 to 10.

13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are for causing a computer to perform the method according to any one of claims 1 to 10.

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