Dual basic input and output system refresh method, device, electronic equipment and medium

Abstract

The present application discloses a method, device, electronic device, and medium for refreshing a dual basic input / output system, relating to the technical field of storage systems. The method includes first upgrading the firmware of a backup memory, switching to the main memory and restarting, and then upgrading the firmware of the main memory, automatically executing a sequential upgrade to avoid missed refreshes; after the firmware upgrade of the main memory is completed, executing a watchdog register erase instruction to clear any dirty data that may exist in the EEPROM register data area to prevent it from interfering with system operation. By verifying that the dual firmware versions are the same to verify version consistency, and detecting that the watchdog erase instruction is effective to ensure that the dirty data has been cleared, the dual verification confirms that the upgrade is successful and the system status is clean, thereby eliminating performance fluctuations, stability degradation, or reliability risks caused by dirty data from the root.

Description

Technical Field

[0001] The present application relates to the technical field of storage systems, and in particular to a refresh method, device, electronic device, and medium for a dual basic input and output system. Background Art

[0002] With the rapid development of information technology, enterprise data volumes are growing exponentially, placing higher demands on the stability and reliability of unified storage systems. The Basic Input / Output System (BIOS), the underlying firmware of a computer system, has a direct impact on system availability through its refresh and recovery mechanisms. Traditional single-BIOS architectures present a single point of failure during the refresh process. A refresh failure can render the system unbootable, requiring manual recovery and severely impacting business continuity. Therefore, dual-BIOS redundancy has emerged, enhancing system fault tolerance through a primary / backup BIOS switchover mechanism.

[0003] The traditional dual BIOS upgrade process typically requires independent operations on both the primary and backup BIOSes. Due to the cumbersome steps, it's easy to miss a flash in the limited time available, impacting overall system performance and stability. Furthermore, the BIOS configuration data stored in the watchdog's Electrically Erasable Programmable Read-Only Memory (EEPROM) registers can become corrupted due to interruptions or anomalies during the upgrade process, affecting the system's ability to accurately interpret the BIOS status. Therefore, the reliability of traditional dual BIOS solutions is limited in practical applications, creating an urgent need for a more efficient and secure dual BIOS flash method. Summary of the Invention

[0004] The present application provides a dual basic input and output system refresh method, device, electronic device and medium to at least solve the problems in the related art of the dual BIOS upgrade process being cumbersome and prone to omissions, and the presence of dirty data in the watchdog EEPROM register data area, which affects system performance, stability and reliability.

[0005] The present application provides a refresh method for a dual basic input / output system, wherein the dual basic input / output system includes a main memory and a backup memory that share a physical memory chip, including:

[0006] When a refresh test item of the dual basic input and output system is triggered, detecting whether the sequence number of the currently activated memory is the first sequence number corresponding to the main memory;

[0007] If not, upgrading the second firmware corresponding to the backup memory;

[0008] Switching from the backup memory to the main memory and performing a power-off restart operation;

[0009] Upgrading the first firmware corresponding to the main memory after power failure and restart;

[0010] Executing a watchdog register erase instruction and performing a power-off restart operation; the watchdog register erase instruction is used to write a first value to the watchdog register;

[0011] When it is detected after power off and restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is a first value, it is determined that the dual basic input and output system refresh is completed.

[0012] The present application also provides a refresh device for a dual basic input / output system, wherein the dual basic input / output system includes a main memory and a backup memory that share a physical memory chip, including:

[0013] a memory detection module, configured to detect whether the sequence number of the currently activated memory is the first sequence number corresponding to the main memory when a refresh test item of the dual basic input and output system is triggered;

[0014] A second firmware upgrade module, configured to upgrade the second firmware corresponding to the backup memory if no;

[0015] A memory switching module, configured to switch from the backup memory to the main memory and perform a power-off restart operation;

[0016] A first firmware upgrade module, configured to upgrade the first firmware corresponding to the main memory after power failure and restart;

[0017] An erasing module, configured to execute a watchdog register erase instruction and perform a power-off restart operation; the watchdog register erase instruction is configured to write a first value into the watchdog register;

[0018] The verification module is configured to determine that the dual basic input and output system refresh is completed when it is detected that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is a first value after power failure and restart.

[0019] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned dual basic input and output system refresh methods when executing the computer program.

[0020] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for refreshing a dual basic input and output system are implemented.

[0021] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned dual basic input and output system refresh methods when executed by a processor.

[0022] This application first upgrades the backup memory's firmware, switches to the primary memory and reboots, then upgrades the primary memory's firmware. This automatically executes the upgrade sequence to avoid missed updates. After the primary memory's firmware upgrade is complete, the watchdog register erase instruction is executed to clear any dirty data in the EEPROM register data area, preventing it from interfering with system operation. By verifying that both firmware versions are identical to verify version consistency, and by verifying that the watchdog erase instruction has taken effect to ensure that dirty data has been cleared, this dual verification confirms that the upgrade was successful and the system is in a clean state, fundamentally eliminating performance fluctuations, stability degradation, or reliability risks caused by dirty data. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1A To unify the production and testing process diagram of the storage machine;

[0025] Figure 1B Schematic diagram of the process flow for functional testing, aging testing and inspection testing;

[0026] Figure 2 Flowchart 1 of a dual basic input / output system refresh method provided in an embodiment of the present application;

[0027] Figure 3 A logical diagram of a refresh method for a dual basic input / output system provided in an embodiment of the present application;

[0028] Figure 4 Schematic diagram of the process of refreshing the dual basic input and output system provided in the embodiment of the present application Figure 2 ;

[0029] Figure 5 Schematic diagram of the process of refreshing the dual basic input and output system provided in the embodiment of the present application Figure 3 ;

[0030] Figure 6 A schematic diagram of the structure of a refresh device for a dual basic input / output system provided in an embodiment of the present application;

[0031] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0034] In order to more clearly illustrate the embodiments of the present application, the following briefly introduces the technical terms used in the embodiments:

[0035] Unified storage is a storage system that can run and manage files and applications on a single device. Unified storage systems integrate file-based and block-based access on a single storage platform, supporting Fibre Channel-based Storage Area Networks (SANs), IP-based SANs, and Network Attached Storage (NAS). Unified storage devices typically have a single BIOS Flash chip. The BIOS is a set of programs embedded in the motherboard that performs power-on self-tests, hardware initialization, and provides the operating system with a low-level hardware control interface.

[0036] Traditional single-BIOS architectures present a single point of failure during the refresh process. A failed refresh could render the system unbootable and require manual recovery, severely impacting business continuity. Therefore, dual-BIOS redundancy has emerged, enhancing the fault tolerance of unified storage systems through a primary / backup BIOS switchover mechanism.

[0037] Unified storage machine production and testing process such as Figure 1AAs shown, it includes pre-processing, assembly line, functional testing, aging testing, inspection testing, packaging, outgoing quality control (OQC) sampling inspection, finished product warehousing and shipment. Among them, functional testing is a functional test of the assembled product to verify whether the product can achieve the intended function. If the functional test fails, it is necessary to return to the pre-processing, assembly line and other links to troubleshoot the problem; if it passes, proceed to the next step. Aging testing simulates the use scenario of the product under specific conditions such as long time and high load, and tests the stability and reliability of the product during long-term operation. Inspection testing is a comprehensive quality inspection of products that have undergone aging testing, including appearance, performance and other aspects to ensure that the product meets quality standards.

[0038] like Figure 1B The process flow for functional testing, burn-in testing, and verification testing is shown. After the unified storage machine is assembled, the front-end workstation (i.e., the functional testing station) performs firmware (FW) updates for various components, including the BIOS, baseboard management controller (BMC), and add-in cards. Field replaceable units (FRUs), vital product data (VPD), and system management BIOS (SMBIOS) information are updated. Configuration checks, health checks, and functional tests are also performed. The burn-in testing station performs alternating current (AC) and direct current (DC) testing, storage system functionality and performance testing, and stress testing of storage components, mixed stress testing, and full system stress testing. For example, the test environment includes normal temperature; a 1 / 100 sample is sampled for high-temperature burn-in, with a hothouse temperature of 5-55°C. Testing lasts 48-60 hours, with the hard drive burn-in test lasting 25 hours. Perform information inspection, storage cluster creation and testing, function testing, and creation of whole-machine snapshots at the testing station.

[0039] A Complex Programmable Logic Device (CPLD) is an integrated circuit that can be programmed to implement logical functions. It is often used in motherboards to implement hardware logic control, signal routing and other functions.

[0040] BMC is an independent management chip on the motherboard, used for monitoring hardware status (such as temperature, voltage, fan speed), remote management (such as power on and off, firmware upgrade), etc.

[0041] Electrically-Erasable Programmable Read Only Memory (EEPROM) is a non-volatile memory that can erase and rewrite data through electrical signals. It is often used to store system configuration parameters, and the data is not lost after power failure.

[0042] A watchdog is a hardware or software timer used to monitor system health. If the system isn't fed regularly, the watchdog triggers a system reboot to prevent a freeze. Once the watchdog is activated, a countdown begins, and the system must periodically feed the watchdog (resetting the timer). If the watchdog isn't fed regularly, the system is considered abnormal and a reset is triggered.

[0043] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0044] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the dual-BIOS refresh method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0045] The hardware architecture includes: dual BIOS chips, switching control circuit, system bus, and watchdog circuit.

[0046] Dual BIOS chips: The motherboard is equipped with two BIOS chips, typically a primary BIOS and a backup BIOS. These chips are typically flash memory (Flash ROM), which can be read and written at operating voltage. The data lines, address lines, and some control lines of the two chips are connected in parallel. The chip select pin determines which chip is active. When the chip select pin is low, the chip is selected for operation; when it is high, the chip is in a high-impedance state and does not operate.

[0047] Switching Control Circuit: Some motherboards use jumpers to switch the BIOS chip. By adjusting the jumper to the "RESCUEROM" position, the system boots with the backup BIOS. Other motherboards use electronic switching circuits, controlled by BIOS settings or a specific control program, eliminating the need for manual jumper operation.

[0048] System bus: The BIOS chip connects to other motherboard components, such as the CPU, memory, and southbridge chip, via the system bus. When refreshing the BIOS, data is transferred between the BIOS chip, memory, and CPU via the system bus. The CPU then executes the refresh program, writing the new firmware data from memory to the designated BIOS chip.

[0049] Watchdog Circuit: The system includes a watchdog circuit, which includes a watchdog register. This circuit monitors system operating status and can trigger actions such as a reboot if an anomaly occurs. During a dual BIOS update, a specific value (the first value) is written to the watchdog register to clear any dirty data, ensuring proper operation without affecting system performance and stability.

[0050] The software environment includes BIOS flash program, operating system support and network environment.

[0051] BIOS refresh program: A special BIOS refresh program is required, which can be run in DOS or Windows environment.

[0052] Operating system support: If flashing in a Windows environment, the operating system must provide the appropriate interfaces and permissions so that the flash program can access the BIOS chip and related system resources. Furthermore, the operating system must be able to identify and manage dual BIOS systems to ensure that conflicts or errors do not occur during the flash process.

[0053] Network environment: If you need to obtain the BIOS image file from a remote server for refresh, you also need network environment support to connect to the server through the network protocol and download the latest BIOS firmware.

[0054] An embodiment of the present application provides a dual-BIOS refresh method. The method is described in detail in conjunction with an execution flow of the dual-BIOS refresh method.

[0055] like Figure 2 As shown, Figure 2 Flowchart 1 of a dual BIOS refresh method provided in an embodiment of the present application, the method comprising the following steps S201 to S206:

[0056] S201 : When a refresh test item of a dual basic input / output system is triggered, it is detected whether the currently activated memory sequence number is the first sequence number corresponding to the main memory.

[0057] A dual Basic Input / Output System (BIOS) consists of a main memory (Flash0) and a backup memory (Flash1) that share a physical memory chip. The dual BIOS refresh test is used to verify the firmware update status of the dual BIOS. This test is part of the storage system functional test.

[0058] When the dual BIOS refresh test item is triggered, it is detected whether the currently activated memory sequence number is the first sequence number 0 corresponding to the main memory. If so, it indicates that the currently activated memory is the main memory Flash0. If not, it indicates that the currently activated memory is the backup memory Flash1, and further subsequent step S202 is executed.

[0059] In some embodiments, a memory sequence number is read from a target register, and then the sequence number is checked to see if it is the first sequence number. The target register is a register provided by the complex programmable logic device to the baseboard management controller (BMC). This means the target register is defined and maintained by the complex programmable logic device, and the BMC can read data from the target register via a bus. The address of the target register is identified as 0x69. Defining the data exchange interface using a fixed address (0x69) ensures standardized communication between the BMC and the CPLD, reducing software adaptation complexity.

[0060] Optionally, the read memory serial number is uploaded to the database to record the initial state, so as to facilitate the comparison of the previous and next serial numbers for rollback when the memory switching fails.

[0061] The above embodiment distinguishes between active and standby Flash memory by reading the Flash serial number, preventing accidental flashing. The collaboration between a complex programmable logic device and a baseboard management controller enables data exchange between the hardware layer (Flash memory) and the management layer (BMC), enabling refresh test items to monitor hardware status in real time and improving the accuracy of automated testing.

[0062] S202: If not, then upgrade the second firmware corresponding to the backup memory.

[0063] When it is detected that the backup memory is currently activated, the second firmware (Flash1_BIOS_FirmWare) corresponding to the backup memory is upgraded.

[0064] like Figure 3 As shown, Figure 3 A logic diagram of a refresh method for a dual basic input / output system provided by an embodiment of the present application: when it is detected that the backup memory Flash1 is currently activated, the second firmware corresponding to the backup memory Flash1 is upgraded.

[0065] S203: Switch from the backup memory to the main memory and perform a power-off restart operation.

[0066] like Figure 3 As shown, switch to the main memory Flash0, and then make the power-off restart (ac_cycle, AC) effective.

[0067] In some embodiments, switching from backup memory to main memory includes: executing a memory switching instruction and writing a second value to a switching control register, where the second value is named only to distinguish it from the first value written to the watchdog register. The memory cells in the EEPROM with addresses 0x2000 and 0x2002 are called switching control registers, indicating that the memory switching instruction operates on the memory cells in the EEPROM with addresses 0x2000 and 0x2002. The switching control register is used to store control parameters or status flags related to Flash switching. The address identifiers of the switching control register are 0x2000 and 0x2002. Writing the second value 0xff to the switching control register triggers the Flash switching logic, notifying the motherboard controller to prepare to switch to main memory.

[0068] Then, perform a power cycle (ac_cycle), disconnecting the device from power (power off) and then reconnecting it (power on) to allow the hardware configuration changes to take effect, ensuring consistency between the firmware and hardware. A power cycle completely cuts off the AC power, completely deenergizing the hardware, resetting the hardware registers, and resetting the hardware configuration. Without performing ac_cycle, writes to the switch control registers may not be recognized by the motherboard controller, resulting in the memory switch command and firmware flash not taking effect.

[0069] The above embodiment writes 0xff to the switch control register, operates the switch control register to switch to the main memory, and then powers off and on again to reinitialize the mainboard controller and read the latest switch control register data, ensuring that the operation is completed in one go, ensuring the synchronization of the firmware and hardware status, and avoiding the backup memory being in a half-written state due to power outages.

[0070] S204: After power is turned off and restarted, the first firmware corresponding to the main memory is upgraded.

[0071] In some embodiments, a detection is performed to determine whether the memory sequence number after powering off and restarting is the first sequence number. If so, the first firmware corresponding to the main memory is upgraded. Specifically, after powering off and restarting, the memory sequence number is read from target register 0x69, and then a detection is performed to determine whether the memory sequence number is the first sequence number 0 corresponding to the main memory. If so, the first firmware corresponding to the main memory Flash0 (Flash0_BIOS_FirmWare) is upgraded.

[0072] If it is detected that the memory sequence number after power off and restart is not the first sequence number, an error message will be generated to help engineers quickly locate the problem, such as CPLD logic error, Flash chip failure, bus communication abnormality, etc.

[0073] like Figure 3As shown, after a power cycle, the system checks whether the currently active memory is Flash0. If so, the first firmware corresponding to Flash0 is upgraded. If not, an error message is generated. This ensures that each firmware upgrade and memory switch is effective, ensuring a consistent process and reducing the uncertainty associated with manual intervention.

[0074] The above embodiment uses the currently active memory sequence as the starting point for determination, establishing a clear operation path. If the current memory is not the primary memory, the backup memory firmware is upgraded first, followed by switching to the primary memory and power cycling, and then upgrading the primary memory firmware. This sequential approach provides a clear and organized upgrade process, preventing missed upgrades due to misaligned steps. For example, during a conventional dual BIOS upgrade, a particular BIOS might be forgotten due to the complexity of the operation. This method, by clearly prioritizing each BIOS, ensures that each BIOS is upgraded, resolving the issue of a cumbersome dual BIOS upgrade process that can easily lead to missed upgrades.

[0075] S205: Execute the watchdog register erase instruction and perform a power-off restart operation.

[0076] like Figure 3 As shown, after upgrading the first firmware corresponding to the main memory Flash0, the EEPROM is cleared and AC takes effect.

[0077] The watchdog register erase instruction is used to write a first value into the watchdog register. The watchdog register has addresses 0x2000 to 0x2007. The memory cells at addresses 0x2000 to 0x2007 in the EEPROM are called watchdog registers, indicating that the watchdog register erase instruction operates on the memory cells at addresses 0x2000 to 0x2007 in the EEPROM.

[0078] In some embodiments, when executing a watchdog register erase instruction, the original values ​​of watchdog registers 0x2000-0x2007 are first cleared, and then a first value 0xff is written to watchdog registers 0x2000-0x2007. This can be understood as erasing the counts at watchdog register addresses 0x2000-0x2007 and resetting them to 0xff. A power cycle (ac_cycle) is then executed, enabling the first firmware flash and the watchdog register erase instruction to take effect.

[0079] In the above embodiment, executing the watchdog register erase instruction and writing a first value to the watchdog register directly clears any dirty data. For example, during long-term operation of the device, the watchdog register may record erroneous or invalid count information. Writing a specific value can restore the watchdog register to its initial or normal state.

[0080] In some embodiments, a check is performed to determine whether a watchdog register erase instruction is executed at the end of the watchdog countdown; if not, a dual BIOS system reset is triggered. The watchdog countdown can be 10 seconds. This means that after a power outage and restart, the first firmware corresponding to the memory must be updated and the watchdog register erase instruction executed within 10 seconds. If this is not completed within 10 seconds, a dual BIOS system reset is triggered.

[0081] S206 : When it is detected after power-off and restart that the first firmware and the second firmware are of the same version and the value of the watchdog register is the first value, determine that the dual BIOS refresh is completed.

[0082] like Figure 3 As shown, after powering off and restarting, the BIOS version is checked and the EEPROM is checked. Specifically, the versions of the first and second firmware are checked to see if they are the same, and the values ​​of the watchdog registers 0x2000-0x2007 are checked to see if they are the first value 0xff. If both of these conditions are met, the dual BIOS refresh test is considered complete.

[0083] Optionally, the first and second firmware versions are checked to see if they are identical to the firmware versions issued during the R&D phase of the production process. If they are identical, the dual BIOS firmware is successfully flashed. By verifying the identity of the two firmware versions, the upgrade is confirmed, creating a closed-loop operation and reducing the risk of missed flashes through process design.

[0084] If the values ​​of the watchdog registers 0x2000 to 0x2007 are not the first value 0xff, it means that the erase was unsuccessful or there is a hardware problem, triggering the error reporting process to prevent dirty data from remaining and affecting subsequent operations.

[0085] The above embodiment verifies the success of the upgrade by checking whether the dual BIOS versions are correct. It also verifies the success of the erase operation by determining whether the watchdog EEPROM addresses 0x2000-0x2007 are 0xff. After a power cycle, the watchdog register value is checked to see if it is the first value written. If it is, the erase operation is successful and the watchdog register data area is free of dirty data. This ensures the normal operation of the system's subsequent watchdog-based monitoring and management functions, thereby improving system performance, stability, and reliability. This enables automated quality inspection, reduces manual intervention, and improves testing efficiency.

[0086] In summary, the embodiments of the present application provide a flashing method for a dual BIOS system. This method first upgrades the backup memory's firmware, switches to the primary memory and reboots, and then upgrades the primary memory's firmware. This method automatically executes sequential upgrades to avoid missed updates. After the primary memory's firmware upgrade is complete, a watchdog register erase instruction is executed to clear any dirty data that may exist in the EEPROM register data area, preventing it from interfering with system operation. By verifying that both firmware versions are the same to verify version consistency and ensuring that dirty data has been cleared by checking that the watchdog erase instruction has taken effect, this dual verification confirms that the upgrade was successful and the system is in a clean state, fundamentally eliminating performance fluctuations, stability degradation, or reliability risks caused by dirty data.

[0087] like Figure 4 As shown, Figure 4 Schematic diagram of the process of refreshing the dual basic input and output system provided in the embodiment of the present application Figure 2 The method includes the following steps S401 to S406:

[0088] S401: If it is detected that the serial number of the currently activated memory is the first serial number corresponding to the main memory, then the first firmware corresponding to the main memory is upgraded.

[0089] After step S201, it is detected that the currently activated memory serial number is the first serial number 0 corresponding to the main memory, indicating that the currently activated memory is the main memory Flash0, and the first firmware (Flash0_BIOS_FirmWare) corresponding to the main memory is upgraded. Figure 3 As shown, it is detected whether the currently activated main memory Flash0 is, and if so, the first firmware corresponding to the main memory Flash0 is upgraded.

[0090] S402: Switch from the main memory to the backup memory and perform a power-off restart operation.

[0091] like Figure 3 As shown, the system switches to the backup memory Flash1 and then AC takes effect.

[0092] In some embodiments, switching from primary memory to backup memory includes executing a memory switch instruction, writing a third value 0x33 to the switch control register 0x2000, triggering the flash switch logic to notify the motherboard controller to prepare to switch to backup memory Flash 1. Then, performing a power cycle (ac_cycle) to enable firmware burning to the primary memory and the backup memory switch to take effect.

[0093] S403: After power is turned off and restarted, the second firmware corresponding to the backup memory is upgraded.

[0094] In some embodiments, a check is performed to determine whether the memory sequence number after powering off and restarting is the second sequence number. If so, the second firmware corresponding to the backup memory is upgraded. Specifically, after powering off and restarting, the memory sequence number is read from the target register, and then a check is performed to determine whether the memory sequence number corresponding to the backup memory Flash1 is the second sequence number 1. If so, indicating a successful memory switch, the second firmware (Flash1_BIOS_FirmWare) corresponding to the backup memory Flash1 is upgraded.

[0095] If it is detected that the memory sequence number after power off and restart is not the second sequence number, an error message is generated. Figure 3 As shown, after power is turned off and restarted, it is detected whether the activated memory at this time is the backup memory Flash1. If so, the second firmware corresponding to the backup memory Flash1 is upgraded. If not, an error is reported.

[0096] S404: Switch from the backup memory back to the main memory.

[0097] Switching from the backup memory Flash1 back to the main memory Flash0 includes executing a memory switching instruction, writing a fourth value into a switching control register, wherein the address identifiers of the switching control register include: 0x2000 and 0x2002, and writing the fourth value 0xff into the switching control registers 0x2000 and 0x2002.

[0098] S405: Execute the watchdog register erase instruction and perform a power-off restart operation.

[0099] like Figure 3 As shown, after switching back to the main memory Flash0, the EEPROM is cleared and AC takes effect.

[0100] When executing the watchdog register erase command, the original value of the watchdog register is first cleared, and then the first value 0xff is written to the watchdog registers 0x2000 to 0x2007. Then, a power cycle (ac_cycle) is performed to enable the second firmware burning, main memory switching, and watchdog register erase command to take effect.

[0101] In some embodiments, a check is performed to determine whether a watchdog register erase instruction is executed at the end of the watchdog countdown; if not, a dual BIOS system reset is triggered. The watchdog countdown can be 10 seconds. Writing the second value 0xff to the switch control registers 0x2000 and 0x2002 and writing the first value 0xff to the watchdog registers 0x2000-0x2007 are related operations and must be completed within a preset time (10 seconds) to ensure hardware consistency and prevent register status from being interfered with by other processes due to extended operation intervals. If the operation time exceeds the preset time, a dual BIOS system reset is triggered.

[0102] S406: After power is turned off and restarted, if it is detected that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value, determine that the dual basic input and output system refresh is completed.

[0103] like Figure 3 As shown, after powering off and restarting, the BIOS version is checked and the EEPROM is checked. Specifically, the first and second firmware versions are checked to see if they are the same, and the watchdog register values ​​0x2000 to 0x2007 are checked to see if they are the same as the first value 0xff. If both conditions are met, the dual BIOS refresh test is considered complete. Optionally, the first and second firmware versions are checked to see if they are the same as the firmware versions issued during the R&D phase of the production process. If the firmware versions are the same, the dual BIOS firmware is successfully burned.

[0104] The above embodiment verifies whether the upgrade is successful by checking whether the dual BIOS versions are correct, and verifies whether the erase operation is successful by determining whether the watchdog EEPROM addresses 0x2000-0x2007 are 0xff. This achieves automated quality inspection, reduces manual intervention, and improves test efficiency.

[0105] The present invention provides a method for refreshing a dual basic input / output system. The method first upgrades the firmware of the main memory, switches to the backup memory and restarts, and then upgrades the firmware of the backup memory. This method automatically executes sequential upgrades to avoid missed updates. After the backup memory firmware upgrade is complete, the system switches back to the main memory and executes a watchdog register erase instruction to clear any dirty data that may exist in the EEPROM register data area, preventing it from interfering with system operation. By verifying that the dual firmware versions are the same to verify version consistency and detecting that the watchdog erase instruction has taken effect to ensure that the dirty data has been cleared, dual verification confirms that the upgrade is successful and the system is in a clean state, fundamentally eliminating performance fluctuations, stability degradation, or reliability risks caused by dirty data.

[0106] like Figure 5 As shown, Figure 5 A schematic diagram of a refresh method for a dual basic input / output system provided in an embodiment of the present application Figure 3 The method includes the following steps S501 to S510:

[0107] S501. Read the currently activated memory sequence number from the target register.

[0108] The target register is a register provided by the complex programmable logic device to the baseboard management controller. The memory sequence number is used to distinguish whether the dual BIOS system currently activates the main memory or the backup memory.

[0109] Exemplarily, the current memory sequence number is read from the target register 0x69.

[0110] Check whether the memory sequence number is the first sequence number of the main memory. The main memory Flash0 has the first sequence number 0. If not, it means that the current memory is a backup memory and then execute S502b.

[0111] The above steps automatically select the upgrade path by monitoring the currently active memory sequence number. This adaptive process avoids steps that may be missed due to manual intervention and ensures that both BIOSes can be upgraded in an orderly manner regardless of their initial state.

[0112] S502a: If the memory serial number is the first serial number corresponding to the main memory, then upgrade the first firmware corresponding to the main memory.

[0113] S503a: Execute a memory switching instruction to switch from the main memory to the backup memory.

[0114] Writing 0x33 to the switch control register 0x2000 switches from the main memory Flash0 to the backup memory Flash1.

[0115] S504a: Execute a power-off restart operation.

[0116] Perform a power-off restart operation (ac_cycle) to make the first firmware burning and memory switching instructions take effect.

[0117] Power off and restart after each storage switch to ensure that the firmware changes are fully effective and avoid cache data interference.

[0118] S505a: Detect whether the memory serial number after power failure and restart is the second serial number corresponding to the backup memory.

[0119] If not, it means that the memory switch failed and an error message is generated. The memory serial number is read again after the restart. This closed-loop design prevents upgrade interruptions due to state asynchrony.

[0120] S506a: If yes, then upgrade the second firmware corresponding to the backup memory.

[0121] The memory sequence number after the restart is detected to be the second sequence number 1 corresponding to the backup memory Flash1, indicating that the memory switching is successful, and then the second firmware corresponding to the backup memory Flash1 is upgraded.

[0122] S507: Switch from the backup memory back to the main memory.

[0123] Specifically, 0xff is written into the switch control registers 0x2000 and 0x2002, and then subsequent steps S508 to S510 are executed.

[0124] The above steps ensure redundancy by upgrading the two memories alternately in a dual BIOS system.

[0125] When it is detected that the currently activated memory serial number is not the first serial number 0 corresponding to the main memory Flash0, it means that the currently activated memory Flash1 of the dual BIOS system is backup memory, and step S502b is executed to upgrade the second firmware corresponding to the backup memory.

[0126] S503b: Execute the memory switching instruction to switch from the backup memory to the main memory.

[0127] Specifically, 0xff is written to the switching control registers 0x2000 and 0x2002.

[0128] S504b: Execute a power-off restart operation.

[0129] Perform a power cycle (ac_cycle) to enable the second firmware burning and memory switching instructions to take effect.

[0130] S505b: Detect whether the memory serial number after the restart is the first serial number corresponding to the main memory.

[0131] If not, it means that the memory switching fails and an error message is generated.

[0132] S506b: If yes, then upgrade the first firmware corresponding to the main memory.

[0133] The memory sequence number after the restart is detected to be the first sequence number 0 corresponding to the main memory Flash0, indicating that the memory switch is successful, and then the first firmware corresponding to the main memory Flash0 is upgraded.

[0134] After the first firmware corresponding to the main memory Flash0 is upgraded, the process continues with S508 , executing the watchdog register erase instruction.

[0135] Specifically, the original values ​​stored in the watchdog registers 0x2000 to 0x2007 are first cleared, and then 0xff is written to them. This clears the residual configuration and restores the watchdog registers to their initial state, avoiding interference from dirty data.

[0136] S509: Execute a power-off restart operation.

[0137] Here, a power-off restart operation (ac_cycle) is executed to enable the second firmware burning, memory switching instruction, and watchdog register erase instruction to take effect.

[0138] The above-mentioned watchdog register erase instruction is executed after all firmware upgrades are completed and is ensured to take effect by powering off and restarting. This avoids the watchdog from interrupting the upgrade by triggering a restart prematurely due to dirty data during the upgrade process. It also avoids the timing conflict between the erase operation and the firmware write operation, preventing dirty data from being overwritten by old data after being erased, and realizing deep coupling of the erase operation and the firmware upgrade process.

[0139] S510: Detect whether the versions of the first firmware and the second firmware are the same after the restart, and whether the value of the watchdog register is the first value.

[0140] If yes, it means the dual BIOS refresh is complete.

[0141] When the firmware versions of the primary and backup memories are consistent, the upgrade is confirmed to be complete to prevent missed updates and to verify whether the firmware is fully written during the switchover process.

[0142] The above steps complete the dual BIOS refresh test items in the functional test phase. Subsequently, other test items of the functional test can be tested, which is conducive to improving test efficiency.

[0143] The above steps ensure the reliability of the BIOS firmware upgrade process by alternately upgrading, switching, and verifying the two Flash chips, using AC operations to ensure the effectiveness of the operations, and using EEPROM cleaning and checking to ensure the reliability of the BIOS firmware upgrade process and timely detect and handle possible errors.

[0144] An embodiment of the present application provides a dual basic input / output system refresh method, which embeds the watchdog register erase into the dual BIOS refresh process, thereby preventing memory from being missed and avoiding dirty data in the watchdog register, thereby improving refresh efficiency.

[0145] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0146] The embodiment of the present application also provides a refresh device for a dual basic input and output system, such as Figure 6 As shown, the dual basic input and output system includes a main memory and a backup memory that share a physical memory chip, and the device includes:

[0147] The memory detection module 601 is used to detect whether the currently activated memory number is the first number corresponding to the main memory when the refresh test item of the dual basic input and output system is triggered;

[0148] The second firmware upgrade module 602 is configured to upgrade the second firmware corresponding to the backup memory if no;

[0149] A memory switching module 603 is used to switch from the backup memory to the main memory and perform a power-off restart operation;

[0150] A first firmware upgrade module 604 is used to upgrade the first firmware corresponding to the main memory after power failure and restart;

[0151] The erase module 605 is used to execute a watchdog register erase instruction and perform a power-off restart operation; the watchdog register erase instruction is used to write a first value into the watchdog register;

[0152] The verification module 606 is configured to determine that the dual BIOS refresh is completed when it is detected that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value after power failure and restart.

[0153] As an optional implementation provided by an embodiment of the present application, the first firmware upgrade module 604, when triggering a refresh test item of the dual basic input and output system, detects whether the currently activated memory sequence number is the first sequence number corresponding to the main memory, and if so, upgrades the first firmware corresponding to the main memory;

[0154] The memory switching module 603 is further used to switch from the main memory to the backup memory and perform a power-off restart operation;

[0155] The second firmware upgrade module 602 is further used to upgrade the second firmware corresponding to the backup memory after power failure and restart;

[0156] The memory switching module 603 is further used to switch from the backup memory back to the main memory;

[0157] The erase module 605 is used to execute the watchdog register erase instruction and perform a power-off restart operation;

[0158] The verification module 606 is configured to determine that the dual BIOS refresh is completed when it is detected that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value after power failure and restart.

[0159] As an optional implementation provided in an embodiment of the present application, the memory detection module 601 is used to: read the memory serial number from the target register, the target register is a register provided by the complex programmable logic device to the baseboard management controller; and detect whether the memory serial number is the first serial number.

[0160] As an optional implementation provided in an embodiment of the present application, the first firmware upgrade module 604 is used to: detect whether the memory serial number after power off and restart is the first serial number; if so, upgrade the first firmware corresponding to the main memory.

[0161] As an optional implementation provided in an embodiment of the present application, the first firmware upgrade module 604 is further configured to generate an error message if the memory sequence number after power failure and restart is not the first sequence number.

[0162] As an optional implementation provided in an embodiment of the present application, the erasing module 605 is specifically configured to: clear the original value of the watchdog register; and write a first value into the watchdog register.

[0163] As an optional implementation provided by an embodiment of the present application, the erasing module 605 is further configured to detect whether a watchdog register erase instruction is executed when the watchdog countdown ends; if not, a dual basic input and output system reset is triggered.

[0164] For the description of the features in the embodiment corresponding to the dual BIOS refresh device, reference can be made to the description of the embodiment corresponding to the dual BIOS refresh method, which will not be repeated here.

[0165] The embodiment of the present application also provides an electronic device, such as Figure 7 As shown, the electronic device includes a memory 701 and a processor 702. The memory 701 stores a computer program. The processor 702 is configured to run the computer program to execute the steps in any of the above-mentioned dual basic input and output system refresh method embodiments.

[0166] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned dual basic input and output system refresh method embodiments when running.

[0167] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0168] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned dual basic input and output system refresh method embodiments are implemented.

[0169] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned dual basic input and output system refresh method embodiments are implemented.

[0170] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0171] The above describes in detail the dual basic input / output system refresh method, device, electronic device, and medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is intended only to facilitate understanding of the method and core concepts of the present application. It should be noted that those skilled in the art may make various improvements and modifications to the present application without departing from the principles of the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A dual basic input and output system refresh method, characterized in that: A dual basic input and output system includes a main memory and a backup memory that share a physical memory chip, and the method includes: When a refresh test item of the dual basic input and output system is triggered, detecting whether the currently activated memory sequence number is the first sequence number corresponding to the main memory; detecting whether the currently activated memory sequence number is the first sequence number corresponding to the main memory includes: reading the memory sequence number from a target register, the target register being a register provided by a complex programmable logic device to a baseboard management controller; detecting whether the memory sequence number is the first sequence number; If not, upgrading the second firmware corresponding to the backup memory; Switching from the backup memory to the main memory and performing a power-off restart operation; Upgrading the first firmware corresponding to the main memory after power failure and restart; Executing a watchdog register erase instruction and performing a power-off restart operation; the watchdog register erase instruction is used to clear the original value of the watchdog register and write a first value to the watchdog register; When it is detected after power off and restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value, it is determined that the dual basic input and output system refresh is completed.

2. The method according to claim 1, characterized in that When the refresh test item of the dual basic input and output system is triggered, after detecting whether the currently activated memory sequence number is the first sequence number corresponding to the main memory, the method further includes: If so, upgrading the first firmware corresponding to the main memory; Switching from the main memory to the backup memory and performing a power-off restart operation; Upgrading the second firmware corresponding to the backup memory after power failure and restart; Switching from the backup memory back to the main memory; Execute the watchdog register erase instruction and perform a power-off restart operation; When it is detected after power off and restart that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is the first value, it is determined that the dual basic input and output system refresh is completed.

3. The method according to claim 1, characterized in that The step of upgrading the first firmware corresponding to the main memory after power failure and restarting includes: Detecting whether the memory serial number after power failure and restart is the first serial number; If so, the first firmware corresponding to the main memory is upgraded.

4. The method according to claim 3, characterized in that The method further includes: generating an error message if the memory sequence number after power failure and restart is not the first sequence number.

5. The method according to claim 1 or 2, characterized in that The method further comprises: Detecting whether the watchdog register erase instruction is executed when the watchdog countdown ends; If not, the dual BIOS reset is triggered.

6. A dual basic input and output system refresh device, characterized in that: A dual basic input and output system includes a main memory and a backup memory that share a physical memory chip, the device comprising: a memory detection module, configured to detect whether the sequence number of the currently activated memory is the first sequence number corresponding to the main memory when a refresh test item of the dual basic input and output system is triggered; A second firmware upgrade module, configured to upgrade the second firmware corresponding to the backup memory if no; A memory switching module, configured to switch from the backup memory to the main memory and perform a power-off restart operation; A first firmware upgrade module, configured to upgrade the first firmware corresponding to the main memory after power failure and restart; An erase module, configured to execute a watchdog register erase instruction and perform a power-off restart operation; the watchdog register erase instruction is configured to clear an original value of the watchdog register and write a first value to the watchdog register; a verification module, configured to determine that the dual basic input and output system refresh is complete when detecting, after power failure and restart, that the versions of the first firmware and the second firmware are the same and the value of the watchdog register is a first value; The memory detection module is specifically used to read the memory serial number from the target register when triggering the refresh test item of the dual basic input and output system. The target register is a register provided by the complex programmable logic device to the baseboard management controller; and detect whether the memory serial number is the first serial number.

7. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the dual basic input and output system refresh method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the refresh method of the dual basic input and output system according to any one of claims 1 to 5 are implemented.

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