Test system, method, electronic device, storage medium and product

Abstract

The present application discloses a test system, method, electronic equipment, storage medium and product, which relate to the field of test technology, including a board to be tested, an electronic equipment and a conversion device; the board to be tested is communicatively connected with the electronic equipment, and a memory disk slot is provided on the board to be tested; the electronic equipment is communicatively connected with the conversion device, and the electronic equipment is used to send debugging instructions; the conversion device is connected to the board to be tested through the memory disk slot, and the conversion device is used to convert a preset memory into a target memory disk according to the debugging instructions to test the board to be tested, and the target memory disk is a computing high-speed interconnect memory disk, which solves the technical problem that the related solutions use computing high-speed interconnect memory for testing during the production test process, and there is a high cost. By converting the preset memory into computing high-speed interconnect memory, the target memory disk is used to test the board to be tested, thereby achieving the technical effect of reducing the production test cost during production testing.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to testing systems, methods, electronic devices, storage media, and products. Background Art

[0002] In the relevant test plan, the backplane needs to use a high-speed interconnect memory disk during the production test process. However, the high-speed interconnect memory disk is expensive, and the test board needs to be constantly replaced and the memory disk needs to be constantly plugged in and out during the production test process, resulting in high production test costs. Summary of the Invention

[0003] The present application provides a test system, method, electronic device, storage medium and product to at least solve the problem of high production test costs caused by production testing based on computing high-speed interconnected memory disks in related technologies.

[0004] The present application provides a test system, comprising a board to be tested, an electronic device and a conversion device;

[0005] The board to be tested is in communication connection with the electronic device, and a memory disk slot is provided on the board to be tested;

[0006] The electronic device is in communication with the conversion device, and the electronic device is used to send a debugging instruction;

[0007] The conversion device is connected to the board to be tested through the memory disk slot. The conversion device is used to convert the preset memory into the target memory disk according to the debugging instruction to test the board to be tested. The target memory disk is a high-speed interconnected memory disk.

[0008] This application provides a testing method, which is applied to a testing system and includes:

[0009] In response to the test system forming a loop, powering on and testing the target board to be tested;

[0010] In response to the completion of the test of the target board under test, the power is turned off and the device is shut down.

[0011] The present application also provides a testing device, comprising:

[0012] The test unit is used to form a loop in response to the test system, power on and test the target board to be tested;

[0013] The power-off unit is used to power off the target board in response to the completion of the test.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned testing methods when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned testing methods are implemented.

[0016] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned testing methods when executed by a processor.

[0017] According to the present application, the test system includes a board to be tested, an electronic device and a conversion device; the board to be tested is communicatively connected to the electronic device, and a memory disk slot is provided on the board to be tested; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send debugging instructions; the conversion device is connected to the board to be tested through the memory disk slot, and the conversion device is used to convert the preset memory into a target memory disk according to the debugging instructions to test the board to be tested, and the target memory disk is a computing high-speed interconnected memory disk, which solves the technical problem that the related solutions use computing high-speed interconnected memory for testing during the production test process, and the cost is high. By converting the preset memory into computing high-speed interconnected memory and using the target memory disk to test the board to be tested, the technical effect of reducing the production test cost is achieved during production testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of the structure of a test system provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the structure of a test system provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of the structure of a test system provided in an embodiment of the present application;

[0022] Figure 4 A flow chart of a testing method provided in an embodiment of the present application;

[0023] Figure 5 A flow chart of a testing method provided in an embodiment of the present application;

[0024] Figure 6 A schematic structural diagram of a testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0027] In order to facilitate those skilled in the art to better understand the technical solutions described in the embodiments of the present disclosure, the technical terms in the embodiments of the present disclosure are explained as follows before introducing the embodiments of the present disclosure.

[0028] Compute Express Link (CXL): An open industry standard for high-bandwidth, low-latency device interconnection, it allows fast, reliable data transmission between different components within a computer system, addressing bottlenecks in high-performance computing, including memory capacity, memory bandwidth, and input / output latency. CXL also enables memory expansion and sharing, and can communicate with computing accelerators such as graphics processing units (GPUs) and field-programmable gate arrays (FPGAs), providing faster and more flexible data exchange and processing.

[0029] Complex Programmable Logic Device (CPLD): CPLD allows the functions of digital circuits to be implemented through software programming. It has high integration and flexibility and is suitable for application scenarios that require fast response time, such as signal processing and protocol conversion.

[0030] E3.S interface: E3.S is a standard form factor interface designed specifically for data centers and enterprise-level applications. It is part of the EDSFF (Enterprise & Data Center SSD Form Factor) standard and is mainly used in servers and storage devices. The E3.S interface supports NVMe2.0 and PCIe5.0 technologies.

[0031] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect various external devices such as graphics cards, solid-state drives (SSDs), network cards, etc.

[0032] Electrically Erasable Programmable Read-Only Memory (EEPROM): It is a non-volatile memory (NVM), which means that data will not be lost after power failure.

[0033] The Dual In-line Memory Module (DIMM) interface is a standard physical interface for installing and connecting Dynamic Random Access Memory (DRAM) chips. It is widely used in computer systems such as desktops, laptops, and servers.

[0034] Multi-Channel I / O Cable (MCIO): A high-speed data transmission cable used in high-performance computing environments. It supports multi-channel parallel transmission and the latest PCIe standards. It plays a vital role in modern data centers, servers, and storage systems, particularly in applications requiring high bandwidth and low latency.

[0035] Serial Peripheral Interface (SPI): SPI is a high-speed synchronous serial communication interface standard, mainly used for short-distance inter-chip communication. It uses four lines to connect a master device with multiple slave devices.

[0036] CXL is a dynamic, multiprotocol technology designed to support accelerators and memory devices. CXL provides a rich set of protocols, including PCIe-like input / output semantics (i.e., CXL.io), cache protocol semantics (i.e., CXL.cache), and memory access semantics over discrete or packet links (i.e., CXL.mem). CXL.io is required for discovery and enumeration, error reporting, point-to-point access to CXL memory, and host physical address lookups. The CXL.cache and CXL.mem protocols can be selectively implemented for specific accelerator or memory device usage models. CXL provides a low-latency, high-bandwidth path for accelerators to access the system and for the system to access memory connected to CXL devices.

[0037] CXL memory disk is a DRAM module based on the CXL interface that enables server systems to significantly expand their memory capacity and bandwidth.

[0038] The CXL backplane, like a traditional hard drive backplane, is connected to the motherboard via an MCIO cable, but it is not connected to a traditional hard drive, but a CXL memory drive.

[0039] In recent years, the development of technologies such as artificial intelligence, machine learning, and cloud computing has generated massive amounts of data. With the rise of data-driven technologies, the demand for more powerful computer hardware architectures has also arisen. To create powerful processors, more and more cores are integrated onto a single chip to meet the processing and performance demands of data-intensive applications. However, memory bandwidth and capacity have not kept pace with the growth in the number of central processing unit (CPU) cores, resulting in a gap between processor and memory performance.

[0040] Unmet demands for memory capacity and bandwidth are pushing existing memory technologies beyond their current limits. Due to the limitations of existing conventional DRAM designs, further expansion of memory capacity is difficult, necessitating the need for novel memory interface technologies. Furthermore, the rise of artificial intelligence and big data is driving the trend toward heterogeneous computing, where multiple processors of different types can process vast amounts of data in parallel.

[0041] Given this trend, it is imperative to develop next-generation interconnect technologies for heterogeneous computing and composable infrastructure to achieve efficient resource utilization.

[0042] CXL is a new open interconnect standard developed by the CXL™ Consortium. It's a high-speed, low-latency CPU-to-device interconnect technology based on the PCIe physical layer. CXL provides efficient connections between host CPUs and interconnected devices, such as accelerators and memory expansion devices. CXL memory disks and backplanes were developed for this purpose. CXL backplanes require CXL memory disks during production testing. However, CXL memory disks are expensive, and the constant need to swap boards and plug and unplug memory disks during testing makes them consumables, leading to high testing costs. Therefore, we must develop a device and method to reduce these testing costs.

[0043] CXL backplane diagnostic testing is a critical step in the production testing of devices based on the CXL architecture. Due to CXL's high bandwidth and low latency, testing typically requires high-performance CXL memory drives (such as CXL SSDs or CXL DRAM modules) to simulate real-world application scenarios and verify the backplane's signal integrity, protocol compatibility, and stability.

[0044] In the relevant testing solutions, the production testing process faces the following challenges:

[0045] First of all, CXL memory disks are expensive. As an emerging technology, CXL's related hardware has not yet been widely popularized, resulting in a high unit price of CXL memory disks, usually ranging from thousands to tens of thousands of yuan.

[0046] Secondly, frequent plugging and unplugging causes wear and tear. During production testing, each CXL backplane must be tested independently, and the CXL memory drive must be repeatedly plugged and unplugged to adapt to different test items or change the board under test. This mechanical operation can easily cause physical wear and tear on CXL connectors (such as PCIe 5.0 / 6.0 interfaces) and even damage the gold fingers or firmware of the memory drive, further shortening its service life.

[0047] Thirdly, the test efficiency is low, the manual replacement of the memory disk is time-consuming, and may introduce interference factors such as poor contact, affecting the consistency and reliability of the test.

[0048] These issues make CXL memory drives a high-value consumable in production testing, significantly increasing overall production costs. For example, if a production line tests 100 backplanes per day, the cost of CXL memory drive depreciation alone can reach hundreds of thousands of yuan per year.

[0049] According to the present application, the test system includes a board to be tested, an electronic device and a conversion device; the board to be tested is communicatively connected to the electronic device, and a memory disk slot is provided on the board to be tested; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send debugging instructions; the conversion device is connected to the board to be tested through the memory disk slot, and the conversion device is used to convert the preset memory into a target memory disk according to the debugging instructions to test the board to be tested, and the target memory disk is a computing high-speed interconnected memory disk, which solves the technical problem that the related solutions use computing high-speed interconnected memory for testing during the production test process, and the cost is high. By converting the preset memory into computing high-speed interconnected memory and using the target memory disk to test the board to be tested, the technical effect of reducing the production test cost is achieved during production testing.

[0050] This application can convert ordinary memory into a CXL interface, so that it can be connected to the CXL backplane and can work normally like a CXL memory disk. During the production test, only the gold finger interface part of the CXL memory disk is damaged. The gold finger interface part is easy to replace, which greatly reduces the production test cost.

[0051] The test system and method provided by the embodiments of the present disclosure can be applied to production testing, debugging, and verification of any device and system using a CXL memory disk.

[0052] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0053] Figure 1 A schematic diagram of the structure of a test system provided in an embodiment of the present disclosure.

[0054] like Figure 1 As shown, the system includes a board to be tested, electronic equipment and a conversion device;

[0055] The board to be tested is in communication connection with the electronic device, and a memory disk slot is provided on the board to be tested;

[0056] The electronic device is in communication with the conversion device, and the electronic device is used to send a debugging instruction;

[0057] The conversion device is connected to the board to be tested through the memory disk slot. The conversion device is used to convert the preset memory into the target memory disk according to the debugging instruction to test the board to be tested. The target memory disk is a high-speed interconnected memory disk.

[0058] In some embodiments, the board under test refers to a hardware device that requires functional verification or performance testing, typically a mainboard or backplane including a memory expansion interface.

[0059] In some embodiments, the board under test and the electronic device are communicated via an MCIO cable, supporting PCIe 5.0 signal transmission.

[0060] In some embodiments, the number of memory disk slots may be one, two, or more. This application does not limit the number of memory disk slots provided on the board to be tested.

[0061] In some embodiments, the memory disk slot is an interface for inserting a storage module (such as an SSD or CXL memory disk). Common forms include E3.S interface, U.2 interface, and M.2 interface. Among them, taking the memory disk slot as E3.S as an example, the E3.S interface is connected to the board under test through gold finger insertion to transmit CXL protocol signals.

[0062] In some embodiments, the electronic device is a main control device used to control and monitor the test process. The electronic device is usually a server or a dedicated controller. In this application, a server is taken as an example.

[0063] In some embodiments, the conversion device is used to emulate a hardware device of a specific protocol memory.

[0064] In some embodiments, the conversion device is compliant with a CXL protocol standard (eg, CXL 2.0) and supports CXL devices being identified as compliant in the server system.

[0065] In some embodiments, the preset memory refers to a data source memory pre-designated by the system, which is typically a standard Double Data Rate 5 (DDR5) synchronous dynamic random access memory (DRAM), ie, ordinary memory.

[0066] In some embodiments, the target memory disk refers to the target type to be ultimately simulated or replaced. In this application, the target memory disk is a computationally expensive interconnect memory, namely, CXL memory, which complies with the CXL.mem protocol.

[0067] In some embodiments, the default power supply is taken from the 5V pin of the E3.S interface.

[0068] In some embodiments, 5V may be converted to voltages such as 3.3V or 1.8V via a direct current to direct current conversion (DC-DC) module for use by the conversion device.

[0069] In some embodiments, the voltage is converted to 3.3V or 1.8V through a DC-DC module, thereby supporting multiple input voltage ranges and adapting to power supply environments of different platforms.

[0070] According to the present application, the test system includes a board to be tested, an electronic device and a conversion device; the board to be tested is communicatively connected to the electronic device, and a memory disk slot is provided on the board to be tested; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send debugging instructions; the conversion device is connected to the board to be tested through the memory disk slot, and the conversion device is used to convert the preset memory into a target memory disk according to the debugging instructions to test the board to be tested, and the target memory disk is a computing high-speed interconnected memory disk, which solves the technical problem that the related solutions use computing high-speed interconnected memory for testing during the production test process, and the cost is high. By converting the preset memory into computing high-speed interconnected memory and using the target memory disk to test the board to be tested, the technical effect of reducing the production test cost is achieved during production testing.

[0071] In some embodiments, the conversion device includes a target chip, a control module, a memory module, and a debugging module;

[0072] The target chip is communicatively connected to the board under test via a first preset interface;

[0073] The control module is in communication with the target chip, and the control module is used to monitor the status of the target chip, where the status of the target chip includes at least one of the temperature of the target chip and the link rate of the target chip;

[0074] The memory module is communicatively connected to the target chip via a second preset interface, and the memory module is used to store data;

[0075] The debugging module is communicatively connected to the control module. The debugging module is communicatively connected to the electronic device via a third preset interface. The debugging module is used to convert debugging instructions into serial communication signals and transmit them to the control module.

[0076] In some embodiments, the conversion device converts memory of one physical form or protocol (such as DDR5) into a memory device of another protocol standard, such as CXL memory, for verifying the function and performance of the board under test without using native CXL memory, thereby reducing the cost of production testing.

[0077] In some embodiments, the target chip implements PCIe-to-CXL protocol conversion, maps the PCIe signal of the DIMM memory to the CXL.mem protocol, and interacts with the server through the E3.S interface to control link training, data transmission, cache consistency and other functions.

[0078] In some embodiments, the control module is typically composed of a microcontroller unit (MCU), an FPGA, or a CPLD, and is responsible for monitoring the target chip status, such as temperature, voltage, link rate, etc., processing instructions from the debugging module, and coordinating communication between modules. In addition, the control module also supports remote firmware upgrades through a universal serial bus (USB) interface (without physical disassembly).

[0079] In some embodiments, the memory module is typically a standard DDR5 DIMM memory bar, which provides a data source that is converted into a target memory disk and supports high-speed access to adapt to the bandwidth requirements of the PCIe / CXL protocol.

[0080] In some embodiments, the debugging module typically uses a USB-UART bridge (such as FT232, CP210x) to receive debugging instructions sent by an electronic device (such as a server), convert the instructions into serial communication signals, such as Universal Asynchronous Receiver / Transmitter (UART), Inter-Integrated Circuit (I²C), or SPI, and transmit them to the control module. This can be used for operations such as firmware updates, log collection, status query, and real-time monitoring.

[0081] In some embodiments, the first preset interface is typically E3.S, U.2, PCIe x4 / x8, etc., which is used to achieve high-speed communication between the target chip and the board under test, supports PCIe / CXL protocol, ensures a stable data link, and is inserted into the memory disk slot of the board under test.

[0082] In some embodiments, the second preset interface is typically a DIMM interface, which supports standard DDR4 / DDR5 memory sticks, Low Power Double Data Rate (LPDDR) synchronous dynamic random access memory interfaces, etc., and is used to connect the memory module to the target chip, read and write actual memory data, and the data is sent to the target chip through the interface for protocol conversion.

[0083] In some embodiments, the memory capacity and speed are dynamically adapted to the target chip (i.e., the CXL chip), supporting a maximum single stick size of 128GB. This means that the system's hardware design supports a maximum single stick size of 128GB. This limitation depends primarily on the target chip's address bus width, the conversion device's memory controller capabilities, and whether the BIOS / firmware supports large-capacity memory mapping. The specific memory capacity may be 8GB, 16GB, 32GB, 64GB, or 128GB, depending on the CXL protocol version. Memory speed, or the data transfer speed of the memory, may be DDR5-4800, DDR5-5600, or DDR5-6400. This indicates that the system can automatically identify and adjust the target chip's operating parameters based on the capacity and speed of the currently used memory module (e.g., DDR5), ensuring compatibility with memory sticks of varying specifications.

[0084] In some embodiments, the third preset interface is typically a USB interface, a UART interface, an RS232 interface, a JTAG interface, etc. The debugging module is connected to an electronic device, such as a server, through this interface to send debugging instructions and obtain status information. It is often used in automated testing scenarios such as attention command (AT) debugging and Python script control.

[0085] In some embodiments, the conversion device further comprises a power module;

[0086] The power module is connected to the power adapter through a fourth preset interface, and the power adapter is used to supply power to the conversion device.

[0087] In some embodiments, an external 5V to 12V power adapter can be optionally connected to cope with high power consumption scenarios, such as later expansion of multiple memory stick loads.

[0088] In some embodiments, the fourth preset interface refers to a reserved physical or logical interface for connecting the power module in the conversion device and the power adapter.

[0089] In some embodiments, the type of the fourth preset interface can be USB Type-A / Type-C, a dedicated DC power interface, or a PCIe 12V power supply interface, wherein USB Type-A / Type-C is suitable for low-power scenarios, and the PCIe 12V power supply interface is suitable for high-power CXL simulation.

[0090] In some embodiments, the power module refers to a circuit module responsible for providing stable voltage and current for the entire conversion device. The module may include a DC-DC converter, a voltage stabilization circuit, a power management unit, and an input filter protection circuit. The DC-DC converter is used to step down / boost the voltage to provide the conversion device with a voltage that meets the requirements.

[0091] In some embodiments, the power adapter is an external power supply device used to convert AC power into a low-voltage DC power supply suitable for electronic devices, such as 12V, 5V, or 3.3V, thereby providing a continuous and stable power supply for the conversion device.

[0092] In some embodiments, in order to avoid the E3.S / U.2 slot of the server or motherboard from being unable to provide sufficient power to drive high-performance target chips and large-capacity memory modules, and to ensure that the conversion device can obtain sufficient power support independently of the host device (such as a server), this application uses the power module in the conversion device to connect to an external power adapter through a specific interface to ensure the stability and compatibility of the system operation.

[0093] In some embodiments, the conversion device further includes a cache module;

[0094] The cache module is in communication with the target chip, and is used to store firmware and configuration parameters of the conversion device, where the configuration parameters include at least one of a device identification and a link training mode.

[0095] In some embodiments, the cache module stores device firmware and configuration parameters, such as device ID and link training mode, for loading when the CXL chip starts.

[0096] In some embodiments, the cache module may be an EEPROM, a non-volatile memory, a ferroelectric memory, or a static random access memory with power-off protection.

[0097] In some embodiments, firmware refers to the underlying program running on the target chip, which may include a protocol stack, such as conversion logic between PCIe and CXL.mem, initialization process, error handling mechanism, and driver interface.

[0098] In some embodiments, configuration parameters refer to a set of parameters used to customize the system settings, where the device identifier is used to identify the identity information of the conversion device, and the link training mode defines the training strategy used when establishing the link, such as Gen3, Gen4, and Gen5 rate matching, default voltage / frequency settings, and user-defined flags.

[0099] In some embodiments, the number of conversion devices is determined by the number of memory disk slots on the board under test.

[0100] In some embodiments, as Figure 2 As shown, Figure 2 A schematic diagram of the structure of a test system provided in an embodiment of the present application is shown in FIG. Figure 2 In the test, install the converter to the E3.S interface of the board under test. The number of converters is closely related to the design of the board under test. For example, if the board under test supports four CXL memory disk slots, four converters need to be inserted to ensure full channel coverage.

[0101] In some embodiments, the board under test is connected to the server mainboard using an MCIO high-speed cable that supports a single-channel 32GT / s+ rate, wherein the MCIO high-speed cable complies with the Gen-Z or PCIe 5.0 standard.

[0102] In some embodiments, the test system further includes a universal serial bus hub, which is used to expand the number of third preset interfaces of the electronic device so as to simultaneously connect multiple conversion devices.

[0103] In some embodiments, a serial bus hub, i.e., a USB hub (HUB), connects the USB HUB between the server and the conversion device, expanding one USB interface into multiple interfaces so that the host can connect to multiple USB devices at the same time. The serial bus hub can be active (with power management) or passive (only signal extension).

[0104] In some embodiments, by introducing a universal serial bus hub to expand the number of USB interfaces on an electronic device, parallel debugging and control of multiple conversion devices can be supported. In this way, an electronic device that originally had only one USB interface can be connected to multiple conversion devices at the same time, thereby realizing concurrent testing of multiple devices.

[0105] In some embodiments, based on the present application, a buffer interface or an automatic switching device may be used to avoid frequent plugging and unplugging operations, extend the life of the CXL memory disk, and protect hardware resources.

[0106] In some embodiments, as Figure 3 As shown, Figure 3A structural schematic diagram of a test system provided in an embodiment of the present application includes the aforementioned board to be tested, an electronic device, and a conversion device, wherein the conversion device includes a CXL chip (target memory disk), a CPLD, a DIMM interface, a memory stick including a registered dual inline memory module (RDIMM) / unbuffered dual inline memory module (UDIMM) (preset memory), a UART module, a power supply module, an E3.S interface, a USB interface, a power supply interface, and an EEPROM. The board to be tested includes an E3.S interface, and the electronic device includes a USB interface.

[0107] In some embodiments, protocol conversion technology is used to simulate ordinary DDR5 memory sticks as CXL-compliant storage devices. Using a high-performance CXL protocol conversion chip, the memory's PCIe signals are converted to the CXL.mem protocol in real time, allowing the system to recognize it as a native CXL memory drive.

[0108] In some embodiments, the modules in the conversion device of this application utilize a separate architecture, allowing the memory stick and the conversion device to be replaced independently. If the conversion device (including the CXL chip, power module, etc.) deteriorates due to long-term testing, only the device itself needs to be replaced, while the memory stick remains usable. This significantly reduces maintenance costs and avoids the wasteful use of the entire CXL memory drive in traditional solutions. Even under the demanding conditions of 50 plug-in / plug-out cycles per day, the device lifespan can reach over two years, while the memory stick can be reused for over five years.

[0109] In some embodiments, by integrating a USB-UART bridge chip, the test system supports sending debug commands directly at the operating system level. Specifically, automated testing can be achieved through the following methods: command-line tools can be used to call the AT command set to query device status (e.g., AT+CXL_VER to obtain the firmware version); script control can also be achieved through Python scripts, such as using the PyUSB library to batch execute operations such as link training and bit error rate testing. Real-time monitoring can also be achieved, continuously collecting parameters such as temperature and voltage and recording them in a database, automatically triggering alarms when anomalies occur.

[0110] In some embodiments, the test method is applied to the aforementioned test system, such as Figure 4 As shown, Figure 4 A flow chart of a test method provided in an embodiment of the present application, the test method includes:

[0111] Step 401, in response to the test system forming a loop, powering on and testing the target board to be tested;

[0112] Step 402 : In response to the completion of the test of the target board under test, the power is turned off.

[0113] In some embodiments, the board under test is installed on the server, and its power supply and signal lines are ensured to be correctly connected. The conversion device is inserted into the memory disk slot (such as E3.S) on the board under test. An MCIO high-speed cable is used to connect the server (electronic device) and the board under test; and a USB is used to connect the server and the conversion device.

[0114] In some embodiments, powering on refers to supplying power to the server, the board under test, and the conversion device.

[0115] In some embodiments, the server detects whether the conversion device is recognized as a target ramdisk device by responding to the test system forming a loop, powering on, and testing the target board under test.

[0116] In some embodiments, after the test of the board to be tested is completed, the server saves the test results and powers off. Here, shutdown refers to turning off the electronic device, that is, the server in this application.

[0117] In some embodiments, in response to the test system forming a loop, before powering on and testing the target board under test, the test method further includes:

[0118] Get the board set to be tested, which contains multiple boards to be tested;

[0119] Based on the set of boards to be tested, a target board to be tested is determined, where the target board to be tested is a board to be tested in the set of boards to be tested.

[0120] In some embodiments, the set of boards to be tested refers to a set of multiple hardware devices that need to undergo functional verification or performance testing, where each device is called a board to be tested, and can include different models of CXL backplanes, PCIe expansion cards, and server motherboards. In this application, the set of boards to be tested is mainly based on CXL backplanes.

[0121] In some embodiments, the target board to be tested is a specific individual in the set of boards to be tested, indicating the board to be tested that is currently to be tested.

[0122] In some embodiments, as Figure 5 As shown, Figure 5 A flow chart of a testing method provided for an embodiment of the present application, specifically, the testing method includes: installing a board to be tested on a corresponding server; inserting a conversion device into each memory disk connector of a backplane; powering on the computer; executing a test program to test the board to be tested; after the test is completed, powering off the computer; if there is still a board to be tested, replacing the board to be tested and continuing the test; if there is no board to be tested, then the current batch of tests ends.

[0123] Through the present application, the testing method is applied to a testing system, which includes a board to be tested, an electronic device and a conversion device; the board to be tested is communicatively connected to the electronic device, and a memory disk slot is provided on the board to be tested; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send debugging instructions; the conversion device is connected to the board to be tested through the memory disk slot, and the conversion device is used to convert the preset memory into a target memory disk according to the debugging instructions to test the board to be tested, and the target memory disk is a computing high-speed interconnect memory disk, which solves the technical problem that the related scheme uses computing high-speed interconnect memory for testing during the production test process, and has high cost. By converting the preset memory into computing high-speed interconnect memory and using the target memory disk to test the board to be tested, the technical effect of reducing the production testing cost is achieved during production testing.

[0124] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0125] The embodiment of the present application further provides a testing device 600, Figure 6 A schematic diagram of the structure of a test device provided in an embodiment of the present disclosure is shown in FIG. Figure 6 Shown, including:

[0126] The test unit 601 is configured to power on and test the target board in response to the test system forming a loop;

[0127] The power-off unit 602 is configured to power off the target board in response to completion of the test.

[0128] Furthermore, in a possible implementation of the embodiment of the present disclosure, the testing device 500 further includes a determining unit, which is configured to:

[0129] Get the board set to be tested, which contains multiple boards to be tested;

[0130] Based on the set of boards to be tested, a target board to be tested is determined, where the target board to be tested is a board to be tested in the set of boards to be tested.

[0131] According to the present application, the test system includes a board to be tested, an electronic device and a conversion device; the board to be tested is communicatively connected to the electronic device, and a memory disk slot is provided on the board to be tested; the electronic device is communicatively connected to the conversion device, and the electronic device is used to send debugging instructions; the conversion device is connected to the board to be tested through the memory disk slot, and the conversion device is used to convert the preset memory into a target memory disk according to the debugging instructions to test the board to be tested, and the target memory disk is a computing high-speed interconnected memory disk, which solves the technical problem that the related solutions use computing high-speed interconnected memory for testing during the production test process, and the cost is high. By converting the preset memory into computing high-speed interconnected memory and using the target memory disk to test the board to be tested, the technical effect of reducing the production test cost is achieved during production testing.

[0132] For the description of the features in the embodiment corresponding to the testing device, please refer to the relevant description of the embodiment corresponding to the testing method, and no further details will be given here.

[0133] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above-mentioned test method embodiments.

[0134] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above-mentioned test method embodiments when running.

[0135] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0136] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned test method embodiments are implemented.

[0137] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned test method embodiments are implemented.

[0138] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] The above is a detailed introduction to a test system, method, electronic device, storage medium and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A testing system, characterized in that: Includes the board to be tested, electronic equipment and conversion device; The board to be tested is in communication connection with the electronic device, and a memory disk slot is provided on the board to be tested; The electronic device is communicatively connected to the conversion device, and the electronic device is used to send a debugging instruction; The conversion device is connected to the board under test through the memory disk slot. The conversion device is used to convert the preset memory into a target memory disk according to the debugging instruction to test the board under test. The preset memory is a double data rate fifth generation synchronous dynamic random access memory DDR5 memory stick, and the target memory disk is a computing high-speed interconnect memory disk. The conversion device includes a target chip, a control module, a memory module, and a debugging module. The target chip is communicatively connected to the board under test via a first preset interface, and the target chip is used to map the high-speed serial computer expansion bus standard signal of the preset memory into a computing high-speed interconnection protocol; The control module is in communication with the target chip, and is configured to monitor a status of the target chip, wherein the status of the target chip includes at least one of a temperature of the target chip and a link rate of the target chip; The memory module is communicatively connected to the target chip via a second preset interface, and the memory module is used to store data; The debugging module is communicatively connected to the control module, and the debugging module is communicatively connected to the electronic device via a third preset interface. The debugging module is used to convert the debugging instruction into a serial communication signal and transmit it to the control module.

2. The test system according to claim 1, wherein: The conversion device also includes a power supply module; The power module is communicatively connected to a power adapter via a fourth preset interface, and the power adapter is used to supply power to the conversion device.

3. The test system according to claim 1, wherein: The conversion device further includes a cache module; The cache module is in communication with the target chip, and is used to store firmware and configuration parameters of the conversion device, where the configuration parameters include at least one of a device identification and a link training mode.

4. The test system according to claim 1, wherein: The number of the conversion devices is determined by the number of the memory disk slots on the board to be tested.

5. The test system according to claim 1, wherein: The system further comprises a universal serial bus hub, which is used to expand the number of third preset interfaces of the electronic device so as to connect a plurality of the conversion devices at the same time.

6. A testing method, characterized in that: The method is applied to the test system according to any one of claims 1 to 5, and the method includes: In response to the test system forming a loop, powering on and testing the target board to be tested; In response to the completion of the test of the target board under test, power is cut off and the device is shut down.

7. The testing method according to claim 6, characterized in that: Before the test system forms a loop in response to powering on and testing the target board under test, the method further includes: Acquire a set of boards to be tested, where the set of boards to be tested includes multiple boards to be tested; The target board to be tested is determined based on the set of boards to be tested, where the target board to be tested is a board to be tested in the set of boards to be tested.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the testing method according to any one of claims 6 to 7 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the testing method according to any one of claims 6 to 7 when executed by a processor.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the testing method according to any one of claims 6 to 7 are implemented.

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