A memory power consumption test system, method and device

Abstract

The present application discloses a memory power consumption test system, method and device, which relate to the field of computer technology. A test controller with a computer rapid interconnect core, a load generator and a first board are used to build a simulation working environment of a computer rapid interconnect memory. The test controller sends a test command to the load generator, and the load generator simulates computer rapid interconnect transaction operations on the tested memory according to the test command. The test controller synchronously collects state parameters of the tested memory to calculate power consumption data when the tested memory executes computer rapid interconnect transaction operations, thereby measuring the power consumption data of the computer rapid interconnect memory when executing computer rapid interconnect transactions, realizing accurate measurement and analysis of the power consumption characteristics of the computer rapid interconnect memory under different working states, and solving the problem that traditional memory power consumption test solutions cannot accurately simulate the working scenarios of computer rapid interconnect memory and cannot obtain accurate test results.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory power consumption testing system, method and device. Background Art

[0002] With the surge in demand for memory bandwidth and capacity in data centers and high-performance computing (HPC), the Compute Express Link (CXL) protocol, a new high-speed interconnect standard that supports memory expansion and sharing, has become a key technology for addressing traditional memory bottlenecks. In computing devices, the power consumption characteristics of memory modules directly impact system energy efficiency and thermal design. However, traditional memory power consumption testing solutions are unable to accurately measure the power consumption parameters of CXL memory.

[0003] How to implement power consumption testing of computer fast interconnect memory is a technical problem that those skilled in the art need to solve. Summary of the Invention

[0004] The present invention provides a memory power consumption test system, method and device, which at least solve the problem in the related art of lacking a power consumption test solution for computer fast interconnected memory.

[0005] The present invention provides a memory power consumption test system, comprising: a test controller, a load generator and a first board;

[0006] The first board is provided with a computer rapid interconnection interface for installing the memory under test, the computer rapid interconnection interface is connected to the load generator, and the load generator is connected to the test controller;

[0007] The test controller has a computer rapid interconnect core, which is used to send test commands to the load generator and synchronously collect state parameters of the tested memory to calculate power consumption data when the tested memory performs computer rapid interconnect transaction operations;

[0008] The load generator is used to simulate the computer fast interconnect transaction operation on the tested memory according to the test command.

[0009] The present invention also provides a memory power consumption testing method, comprising:

[0010] configuring computer rapid interconnect link parameters for a memory under test of a computer rapid interconnect interface installed on the first board;

[0011] In response to a test command issued based on a computer fast interconnect core, simulating a computer fast interconnect transaction operation on the memory under test;

[0012] The state parameters of the tested memory are synchronously collected to calculate the power consumption data of the tested memory when executing the computer fast interconnection transaction operation.

[0013] The present invention also provides a memory power consumption testing device, comprising:

[0014] a configuration unit, configured to configure computer rapid interconnect link parameters for a memory under test of a computer rapid interconnect interface installed on the first board;

[0015] A test unit, configured to simulate a computer fast interconnect transaction operation on the memory under test in response to a test command issued based on a computer fast interconnect core;

[0016] The collecting unit is used for synchronously collecting the state parameters of the tested memory to calculate the power consumption data when the tested memory executes the computer fast interconnection transaction operation.

[0017] The present invention adopts a test controller with a computer rapid interconnect core, a load generator and a first board to build a simulation working environment of a computer rapid interconnect memory. The test controller sends a test command to the load generator, and the load generator simulates a computer rapid interconnect transaction operation on the tested memory according to the test command. The test controller synchronously collects state parameters of the tested memory to calculate power consumption data when the tested memory executes the computer rapid interconnect transaction operation. By simulating the computer rapid interconnect transaction operation, a test environment simulating the computer rapid interconnect memory in an actual application scenario is realized, and the state parameters of the tested memory are synchronously collected to measure the power consumption data when the computer rapid interconnect memory executes the computer rapid interconnect transaction. The power consumption characteristics of the computer rapid interconnect memory in different working states can be accurately measured and analyzed, thereby solving the problem that traditional memory power consumption test solutions cannot accurately simulate the working scenario of the computer rapid interconnect memory and cannot obtain accurate computer rapid interconnect memory power consumption test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 An architectural diagram of a memory power consumption test system provided by an embodiment of the present invention;

[0020] Figure 2 A flowchart of a memory power consumption testing method provided by an embodiment of the present invention;

[0021] Figure 3 A flowchart of another memory power consumption testing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0023] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0024] In order to enable those skilled in the art to better understand the solutions of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] Here, some key terms used in the embodiments of the present invention are explained.

[0026] Compute Express Link (CXL) is a high-speed serial protocol that leverages the physical layer and electrical specifications of the high-speed serial Peripheral Component Interconnect express (PCIe) bus to enable fast and reliable data transmission between different components within a computer system. It is designed to address bottlenecks in high-performance computing, including memory capacity, memory bandwidth, and I / O latency. CXL also enables memory expansion and sharing, and can communicate with peripherals such as computing accelerators (such as graphics processing units (GPUs) and field programmable gate arrays (FPGAs)), providing faster and more flexible data exchange and processing.

[0027] The Computer Express Interconnect protocol defines two main entities: the Computer Express Interconnect Host (CXL Host) and the Computer Express Interconnect Device (CXL Device). The CXL Host and the Computer Express Interconnect Device are connected via the PCIe bus. The CXL Host is the master device in the system responsible for initializing and managing the Computer Express Interconnect Device. It is typically the system's central processing unit (CPU), but it can also be other devices with sufficient computing power and management capabilities. The Computer Express Interconnect Device is a slave device connected to the Computer Express Interconnect Host and relies on the Computer Express Interconnect Host for initialization and configuration. The Computer Express Interconnect Device can be various types of accelerators, such as GPUs, FPGAs, AI processors, or extended memory modules.

[0028] The CRI protocol introduces three sub-protocols for interaction between CRI hosts and CRI devices:

[0029] The Computer Interconnect Express I / O Protocol (CXL.io) is used for I / O communication between devices, including configuration, control, and status reporting. The CXL.io host can use CXL.io to configure the hardware resources and operating parameters of CXL devices.

[0030] The Computer Express Interconnect Cache Coherence Protocol (CXL.cache) is used for cache coherence management, ensuring cache data consistency across devices. The Computer Express Interconnect host can coordinate cache line state updates using the CXL.cache protocol.

[0031] The Computer Interconnect Express Memory Protocol (CXL.memory) is used for memory access, allowing devices to directly access system memory or shared memory pools. Computer Interconnect Express devices can request to read or write memory data using the Computer Interconnect Express Memory Protocol.

[0032] In other words, the interconnect host is the master device of the system, responsible for initializing, configuring, and managing the entire interconnect system, including memory management and cache coherence coordination. Interconnect devices are slave devices, relying on the interconnect host for initialization and configuration, executing assigned tasks, and participating in cache coherence management.

[0033] The Computer Interconnect Express protocol defines three main device types: Type 1, Type 2, and Type 3. Each device type supports a different protocol subset and is suitable for different hardware scenarios. CXL Type 1 devices are accelerators without local memory, such as SmartNICs, FPGAs, and AI inference chips. They support the CXL.io and CXL.cache protocols, but not the CXL.mem protocol. CXL Type 2 devices are accelerators with local memory, such as GPUs and AI training chips. They support the CXL.io, CXL.cache, and CXL.mem protocols. CXL Type 3 devices are pure memory expansion devices, such as CXL memory bars, memory pools, and SSD memorized storage. They support the CXL.io and CXL.mem protocols, but not CXL.cache.

[0034] In the embodiment of the present invention, the targeted computer rapid interconnect memory can include two categories: one category is the computer rapid interconnect memory in the expansion card, and the other category is an independent computer rapid interconnect memory module.

[0035] The related technology lacks power consumption testing solutions for computer interconnect memory. Traditional memory power consumption testing solutions, such as static current measurement or simple script load simulation solutions, have many problems: Unable to simulate dynamic loads: The access mode of computer interconnect memory is bursty and multi-threaded, and traditional methods are difficult to reproduce real scenarios. Lack of protocol layer integration: The transaction layer and link layer characteristics of the computer interconnect protocol are not combined, resulting in test results that deviate from reality. Insufficient data acquisition accuracy: Relying on an external power consumption meter, it is impossible to synchronize the status of the computer interconnect host (CXL Host) and the computer interconnect device (CXL Device) in real time. Traditional memory power consumption testing solutions can only obtain physical layer power consumption data and cannot analyze the impact of computer interconnect protocol characteristics on power consumption, resulting in large test errors.

[0036] To this end, the present invention provides a memory power consumption test solution for computer rapid interconnect memory. The solution adopts a test controller with a computer rapid interconnect core, a load generator and a first board to build a simulation working environment of the computer rapid interconnect memory. The test controller sends a test command to the load generator, and the load generator simulates computer rapid interconnect transaction operations on the tested memory according to the test command. The test controller synchronously collects state parameters of the tested memory to calculate power consumption data when the tested memory executes the computer rapid interconnect transaction operations. By simulating the computer rapid interconnect transaction operations, a test environment simulating the actual application scenario of the computer rapid interconnect memory is realized, and the state parameters of the tested memory are synchronously collected to measure the power consumption data when the computer rapid interconnect memory executes the computer rapid interconnect transaction. The power consumption characteristics of the computer rapid interconnect memory in different working states are accurately measured and analyzed, thereby solving the problem that traditional memory power consumption test solutions cannot accurately simulate the working scenario of the computer rapid interconnect memory and cannot obtain accurate computer rapid interconnect memory power consumption test results.

[0037] Figure 1 This is an architectural diagram of a memory power consumption testing system provided by an embodiment of the present invention.

[0038] like Figure 1 As shown, the memory power consumption test system provided by the embodiment of the present invention may include: a test controller, a load generator 102 and a first board; the first board is provided with a computer rapid interconnection interface for installing the memory under test, the computer rapid interconnection interface is connected to the load generator 102, and the load generator is connected to the test controller; the test controller has a computer rapid interconnection core, which is used to send test commands to the load generator 102 and synchronously collect status parameters of the memory under test to calculate power consumption data when the memory under test performs computer rapid interconnection transaction operations; the load generator 102 is used to simulate computer rapid interconnection transaction operations on the memory under test according to the test commands.

[0039] In the embodiment of the present invention, the memory under test may be a computer express interconnect memory in an expansion card or a separate computer express interconnect memory module. The memory under test complies with the CXL 1.1 or CXL 2.0 specification.

[0040] Although the computer rapid interconnection protocol is based on the physical layer transmission signal of the high-speed serial computer expansion bus, it adds cache consistency protocol and memory semantic support, which significantly increases the complexity of the link layer protocol. Traditional memory power consumption test equipment is difficult to accurately simulate the actual timing relationship of protocol interaction under dynamic load, and cannot support multi-level computer rapid interconnection switches and heterogeneous accelerators, making it difficult to truly reproduce the resource allocation pressure under dynamic load.

[0041] To this end, an embodiment of the present invention uses a test controller and a load generator 102 in combination. The test controller simulates a computer interconnect host to meet the complex timing requirements of the computer interconnect protocol and implements flow-limiting interface terminal (FLIT) scheduling and link state machine management at the hardware level. The load generator 102 integrates the computer interconnect protocol and simulates computer interconnect transactions to achieve a realistic working environment of a simulated computer interconnect memory.

[0042] In this embodiment of the present invention, the test controller uses a processor equipped with a Computer Interconnect Express (CXL) IP core to simulate a CXL host environment. This supports CXL Type 1, CXL Type 2, and CXL Type 3 device emulation and transmits and receives data using the CXL protocol. The CXL IP core can be a CXL 2.0 IP core.

[0043] In an embodiment of the present invention, load generator 102 can employ a microcontroller unit (MCU) or field programmable gate array (FPGA) to generate dynamic memory access requests based on parameters set by the test controller, simulating various memory load conditions. Without load generator 102, the test controller would need to run a specific test program to simulate dynamic memory load. This would result in high power consumption by the test controller itself, masking changes in memory power consumption and leading to inaccurate test results.

[0044] In this embodiment of the present invention, the type of CXL transaction may include at least one of a CXL memory read / write (CXL.mem) transaction and a CXL cache coherence operation (CXL.cache) transaction. The load generator 102 generates a test load to simulate the data processing requirements of actual CXL memory operations.

[0045] In an embodiment of the present invention, in order to calculate the power consumption data of the tested memory, the types of state parameters of the tested memory that need to be collected may include but are not limited to current values, voltage values, power values, etc., and may also include computer fast protocol state parameters of the tested memory.

[0046] In traditional memory power consumption test schemes, external test fixtures or instruments are usually required to collect the power consumption parameters of the memory. In an embodiment of the present invention, the test controller can synchronously collect the state parameters of the memory under test while controlling the load generator 102 to simulate computer fast interconnection transactions. In some optional implementations of the embodiment of the present invention, the test controller may include a first processor 101 and a power consumption acquisition module 104; the first processor 101 has a computer fast interconnection core; the power consumption acquisition module 104 is connected to a first sensor provided on the memory under test, and the power consumption acquisition module 104 is used to read the state parameters of the memory under test collected by the first sensor.

[0047] That is, the power consumption collection module 104 may be a module integrated in the test controller, or the first processor 101 and the power consumption collection module 104 may be provided separately.

[0048] The first processor 101 is a processor with a computer fast interconnect core. The first processor 101 can be a microprocessor or a field programmable logic gate array.

[0049] Some computer high-speed interconnect memories are equipped with sensors for self-testing status parameters. If the memory under test is equipped with a sensor, the first sensor can be the sensor installed in the memory under test. If the memory under test is not equipped with a sensor, a separate first sensor can be installed to collect the status parameters of the memory under test. For example, a first sensor installed on the first mainboard 103 can be used to monitor the status parameters of the memory under test.

[0050] The first sensor can be a high-precision current sensor (such as the TI INA226). If the INA226 sensor is used, the power consumption acquisition module 104 is connected to the first sensor using, for example, a two-wire serial bus (Inter-Integrated Circuit, I2C). The power consumption acquisition module 104 writes configuration values to the INA226 sensor's configuration register to set the sampling rate, sampling mode, sampling filter period, and other parameters (the sampling rate can be set to 1kHz), and writes calibration values to the INA226 sensor's calibration register. The power consumption acquisition module 104 can calculate the bus voltage of the memory under test by reading the value of the INA226 sensor's bus voltage register; the shunt voltage of the memory under test by reading the value of the INA226 sensor's shunt voltage register; the current value of the memory under test by reading the value of the INA226 sensor's current register; and the power value of the memory under test by reading the value of the INA226 sensor's power register.

[0051] The power consumption acquisition module 104 may obtain the state parameters of the memory under test from the first sensor and transmit the obtained state parameters to the first processor 101 for processing.

[0052] In the embodiment of the present invention, the first board is used to provide a computer fast interconnect interface for installing the memory under test. A connection is established between the memory under test and the load generator 102 via a PCIe link on the first board.

[0053] The memory power consumption test system provided by the embodiment of the present invention may further include a computer express interconnect link status monitoring module, which is used to monitor the status of the PCIe link between the test system and the memory under test.

[0054] In some optional implementations of the embodiments of the present invention, the first processor 101 can be directly connected to the memory under test, and the load generator 102 is also connected to the memory under test. The first processor 101 directly accesses the memory under test to simulate the memory access mode in actual applications, so that the memory power consumption test results are closer to the actual usage scenario, and can test the correctness, delay, etc. of the read and write operations of the memory under test. The dynamic load is generated by the load generator 102. However, when the first processor 101 and the load generator 102 are both connected to the memory under test, the power consumption of the first processor 101 itself may interfere with the measurement of the power consumption of the memory under test, especially when the first processor 101 and the memory under test are working at the same time, and the coordinated work of the first processor 101 and the load generator 102 needs to be considered at the same time.

[0055] In some other optional implementations of the embodiments of the present invention, the first processor 101 may not be directly connected to the memory under test, and the load generator 102 may be independently connected to the memory under test to generate a dynamic load and measure the power consumption. In this case, the interference of the power consumption of the first processor 101 on the power consumption measurement of the memory under test can be avoided, and the accuracy of the memory power consumption measurement can be adjusted. However, the functional characteristics of the memory under test cannot be directly tested at this time, and since the access mode of the first processor 101 may be different from the access mode of the load generator 102, the power consumption test results of the memory under test may be different from the memory usage in actual use of the memory under test.

[0056] In some further optional implementations of the embodiments of the present invention, the first processor 101 and the load generator 102 may be connected to the memory under test, and the operating modes of the first processor 101 and the load generator 102 may be adjusted according to test requirements. For example, the first processor 101 may test the functional characteristics of the memory under test, while the load generator 102 may generate a dynamic load and measure the power consumption of the memory under test. In this case, a comprehensive test can be performed on the memory under test, which can test both the functional characteristics of the memory under test and the power consumption data of the memory under test, without affecting the power consumption test results of the memory under test by the power consumption of the first processor 101.

[0057] In actual applications, depending on the test requirements of the memory under test, whether only the power consumption data of the memory under test is tested or a comprehensive test of the memory under test is required, one of the three connection methods of the first processor 101, the load generator 102 and the memory under test provided in the embodiment of the present invention can be selected and a corresponding control strategy can be set.

[0058] If the load generator 102 is directly connected to the memory under test, it can be configured to perform read and write pressure on the memory under test according to the test command of the test controller, and the test controller initializes the load generator 102 and sets the working mode, access frequency, data mode and other parameters of the load generator 102. The load generator 102 generates dynamic memory access requests based on the parameters in the test command of the test controller to simulate computer fast interconnection transactions and perform read and write operations on the memory under test. The test controller or the power consumption acquisition module 104 reads the state parameters of the memory under test collected by the first sensor to calculate the power consumption data of the memory under test based on the state parameters. Thus, the load generator 102 can be used to realize the generation of dynamic loads to simulate computer fast interconnection transactions in the actual use scenario of computer fast interconnection memory. The load generator 102 can accurately control the frequency, data volume and timing of memory access, thereby improving the accuracy and reliability of the computer fast interconnection memory power consumption test.

[0059] If the load generator 102 is not directly connected to the memory under test, but the read and write operations of the memory under test are indirectly controlled through the test controller, the test controller will initialize the load generator 102 and set parameters such as the load generator 102's operating mode, access frequency, and data mode. The load generator 102 generates memory access instructions and sends them to the test controller via an interface. The test controller then performs read and write operations on the memory under test based on the received instructions. At the same time, the test controller synchronously collects the state parameters of the memory under test through the power consumption acquisition module 104 to obtain the power consumption data of the memory under test. This allows the test controller to flexibly execute various memory access instructions to meet different test requirements. However, the power consumption test accuracy of this method is not as good as directly connecting the load generator 102 to the memory under test. In actual applications, the connection method of the test controller, load generator 102, and memory under test can be determined according to the test requirements.

[0060] When using the memory power consumption test system provided by the embodiment of the present invention to test the memory under test, the memory under test is installed in the computer rapid interconnection interface of the first motherboard 103, and computer rapid interconnection support is enabled in the Basic Input / Output System (BIOS) of the first motherboard 103 (usually provided in the latest firmware or by turning on a hidden BIOS option) to ensure that the power supply of the first motherboard 103 is stable and sufficient to support all components of the test system.

[0061] For software setup, ensure that the test controller's wipe subsystem supports CRI (Computer Interconnect Express), for example, Linux kernel version 5.19 or later. The test controller should include CRI drivers and tools, such as the CRI Memory Resource Kit (CMRK), and test software for monitoring and recording the power consumption of the memory under test, such as the Intel Memory Latency Checker (MLC) or other power consumption testing tools.

[0062] After completing the above hardware and software deployment, the memory power consumption test system provided by the embodiment of the present invention can be used to experimentally simulate the dynamic load of CXL transactions, thereby simulating the bursty and multi-threaded access mode of CXL memory. By combining the transaction layer and link layer characteristics of the CXL protocol, the test results are more accurate, and the status of the CXL host and CXL device are synchronized in real time without relying on an external power consumption meter.

[0063] A memory power consumption testing system provided by an embodiment of the present invention uses a test controller with a computer rapid interconnect core, a load generator, and a first board to establish a simulated working environment for a computer rapid interconnect memory. The test controller issues a test command to the load generator 102, and the load generator 102 simulates computer rapid interconnect transaction operations on the memory under test according to the test command. The test controller synchronously collects state parameters of the memory under test to calculate power consumption data when the memory under test executes the computer rapid interconnect transaction operations. By simulating computer rapid interconnect transaction operations, a test environment simulating the actual application scenario of the computer rapid interconnect memory is realized, and the state parameters of the memory under test are synchronously collected to measure the power consumption data when the computer rapid interconnect memory executes the computer rapid interconnect transaction. This achieves accurate measurement and analysis of the power consumption characteristics of the computer rapid interconnect memory under different working states, thereby solving the problem that traditional memory power consumption testing solutions cannot accurately simulate the working scenarios of the computer rapid interconnect memory and cannot obtain accurate computer rapid interconnect memory power consumption test results.

[0064] The embodiment of the present invention continues to describe the method for analyzing power consumption data of the tested memory.

[0065] In some optional implementations of the embodiments of the present invention, the test controller can calculate the power consumption data of the tested memory based on the collected state parameters of the tested memory, and establish a correspondence between the computer fast interconnect transaction operations executed by the tested memory and the power consumption data of the tested memory.

[0066] Specifically, the test controller can maintain a data analysis platform, store and analyze power consumption and protocol logs based on a time series database (such as InfluxDB), and collect, store and analyze data from the computer fast interconnect core, load generator 102 and power consumption acquisition module 104.

[0067] The above-mentioned data analysis platform can also be implemented based on another processor. In other optional implementations of the embodiments of the present invention, the memory power consumption test system provided by the embodiments of the present invention can also include a host computer 105; the host computer 105 is used to obtain computer fast interconnection transaction operations and status parameters of the memory under test, and establish a correspondence between the execution time of the computer fast interconnection transaction operations and the timestamp of the status parameters of the memory under test of the memory under test and the power consumption data of the memory under test.

[0068] That is, the host computer 105 can also store and analyze power consumption and protocol logs based on the time series database, and collect, store and analyze data from the computer fast interconnect core, the load generator 102 and the power consumption acquisition module 104.

[0069] In an embodiment of the present invention, the host computer 105 can be connected to the first processor 101; the host computer 105 can also be used to receive the test system status parameters sent by the test controller, so as to establish a correspondence between the computer fast interconnection transaction operation executed by the tested memory and the power consumption data of the tested memory according to the test system status parameters.

[0070] In an embodiment of the present invention, the host computer 105 may also be connected to the load generator 102; the host computer 105 may also be used to receive generation data and / or statistical data of computer rapid interconnection transactions sent by the load generator 102, so as to establish a correspondence between the computer rapid interconnection transaction operations executed by the tested memory and the power consumption data of the tested memory based on the generation data and / or statistical data.

[0071] In some optional implementations of the embodiments of the present invention, the host computer 105 can be used to receive the test system status parameters sent by the test controller and the relevant data of the computer rapid interconnection transactions sent by the load generator 102, so as to establish a correspondence between the computer rapid interconnection transaction operation executed by the tested memory and the power consumption data of the tested memory based on the test system status parameters and the relevant data of the computer rapid interconnection transactions; wherein the relevant data of the computer rapid interconnection transactions includes at least one of the generation parameters of the computer rapid interconnection transactions and the statistical parameters of the computer rapid interconnection transactions.

[0072] The host computer 105 receiving the test system state parameter sent by the test controller may be the host computer 105 receiving the test system state parameter sent by the first processor 101 .

[0073] In an embodiment of the present invention, the host computer 105 establishes a correspondence between the computer rapid interconnection transaction operation executed by the tested memory and the power consumption data of the tested memory, which may include: the host computer 105 establishes a power consumption transaction association graph of the tested memory according to the type of computer rapid interconnection transaction operation executed by the tested memory and the correspondence between the state parameters of the tested memory and time.

[0074] In an embodiment of the present invention, when the test controller or host computer 105 is used to implement a data analysis platform, a power consumption transaction association model for the memory under test can be established based on the type of computer fast interconnect transaction operations executed by the memory under test and the power consumption data calculated from the synchronously collected state parameters of the memory under test. This model can identify high-power operations (such as frequent cache coherence maintenance) and generate a power consumption distribution heat map (specifically, it can be categorized by transaction type and address range). The power consumption transaction association map can be a power consumption transaction association scatter plot (with time on the X-axis and current on the Y-axis, and color distinguishing transaction types).

[0075] In an embodiment of the present invention, the host computer 105 can also be used to calculate the unit operation energy efficiency ratio of the tested memory based on the current parameters of the tested memory, the voltage parameters of the tested memory, the unit acquisition time, and the computer fast interconnection transaction operations performed by the tested memory per unit acquisition time.

[0076] In an embodiment of the present invention, when the test controller or host computer 105 is used to implement the data analysis platform, in addition to generating a power consumption distribution heat map, the energy efficiency ratio per unit operation (EPO) of the tested memory can also be calculated, which can be expressed as follows:

[0077] .

[0078] The memory power consumption test system provided by the embodiment of the present invention can also be used to optimize and verify the memory under test, so as to determine the optimal control strategy of the memory under test.

[0079] In an embodiment of the present invention, the test controller issues a test command to the load generator 102 and synchronously collects state parameters of the memory under test to calculate power consumption data when the memory under test executes a computer rapid interconnection transaction operation. This may include: the test controller performs iterative testing on the memory under test. In the current round of iterative testing, the test controller issues a corresponding test command to the load generator 102 based on the computer rapid interconnection device control parameters of the current round of iterative testing to obtain power consumption data corresponding to the computer rapid interconnection device control parameters. If the iteration end condition is not met, the computer rapid interconnection device control parameters are adjusted based on the power consumption data of the memory under test, and then the next round of iterative testing is entered.

[0080] In specific implementations, the control parameters of the memory under test can be adjusted based on the data analysis results provided by the data analysis platform, or the computer fast interconnection device strategy of the memory under test (such as the cache replacement algorithm) can be replaced, and the energy efficiency improvement strategy of the memory under test can be verified through iterative testing.

[0081] The memory power consumption test system provided by the embodiment of the present invention is applied, and the test process may include four stages:

[0082] Environment initialization: Configure computer fast interconnection link parameters (bandwidth, latency), load mode, and data collection frequency. The corresponding software implementation may include:

[0083] Configure the computer fast interconnect link parameters:

[0084] cxl_config = { / / Computer fast interconnect definition;

[0085] "link_width": "x16", / / computer fast interconnection link bandwidth;

[0086] "data_rate": "32 GT / s", / / data rate;

[0087] "latency_mode": "Low Latency" / / Latency mode: low latency;

[0088] };

[0089] Set the load mode (mixed read and write):

[0090] workload_profile = { / / Workload profile;

[0091] "read_ratio": 0.7, / / read ratio;

[0092] "write_ratio": 0.3, / / write ratio;

[0093] "burst_length": 256 --Unit: byte / / burst length;

[0094] }.

[0095] Load execution and data collection: Inject fast computer interconnect transactions (such as MemRead, MemWrite, and Snoop requests). Synchronously collect the power consumption (instantaneous current and voltage) and protocol status (transaction type, link layer retry count) of the memory under test. The corresponding software implementation may include:

[0096] Use the computer fast interconnect input and output transaction injection tool to send a memory read (MemRead) request:

[0097] Bash / / Description of computer rapid interconnection test tool;

[0098] cxl_test_tool op read addr 0x1000 len 256 repeat 1000 / / The computer fast interconnect test tool specifies the operation type as a read operation, the starting address of the read operation as 0x1000, the length of the read operation as 256 bytes, and the number of times the read operation is repeated is 1000.

[0099] Synchronously collect power consumption data and timestamp it:

[0100] power_data = ina226.read_current() / / Read instantaneous current;

[0101] log_event("CXL_READ", timestamp=time.now()) / / Record the computer fast interconnect read operation log and set the timestamp to the current time.

[0102] Data analysis: Build a power-transaction correlation model to identify high-power operations (such as frequent cache coherence maintenance). Generate a power distribution heat map (categorized by transaction type and address range).

[0103] Optimization and verification: Adjust computer fast interconnect device strategies (such as cache replacement algorithms) and iteratively test and verify energy efficiency improvements.

[0104] Specifically, when performing the test on the memory under test, the memory under test is installed on the computer rapid interconnection interface of the first mainboard 103, and the power consumption test module is connected to the power input terminal of the memory under test. The memory power consumption test system is started to ensure that the computer rapid interconnection support is correctly configured in the basic input and output system. The operating system is entered to check whether the computer rapid interconnection device can be correctly identified, and then the memory power consumption test is run, and the test software is used to perform read and write operations on the memory under test. In order to simulate the actual workload of the computer rapid interconnection transaction, the power consumption acquisition module 104 is used to synchronously collect the state parameters of the memory under test to calculate the power consumption data of the memory under test. The power consumption data of the internal test memory is collected by using the data analysis platform, and the corresponding computer rapid interconnection transactions are synchronized, and the power consumption performance of the memory under test under different workloads is analyzed, so as to optimize the control parameters or usage mode of the memory under test and determine the method to reduce the power consumption of the memory under test.

[0105] In the memory power consumption test system provided in the embodiment of the present invention, the data flows involved may include but are not limited to:

[0106] Test Controller → Load Generator 102:

[0107] Data flow: test data / control commands;

[0108] Description: The test controller sends test data or control commands to the load generator 102 to trigger load generation.

[0109] Load Generator 102 → Test Controller:

[0110] Data flow: response data / status information;

[0111] Description: After receiving test data or control commands, the load generator 102 generates corresponding response data or status information and sends it back to the test controller.

[0112] Power consumption acquisition module 104 → data analysis platform:

[0113] Data flow: power consumption data;

[0114] Description: The power consumption acquisition module 104 monitors the power consumption of the tested memory in real time and sends the power consumption data to the data analysis platform for analysis.

[0115] Test controller → data analysis platform:

[0116] Data flow: performance data / log information;

[0117] Description: The test controller may also need to send performance data or log information to the data analysis platform to more comprehensively analyze the test results.

[0118] Load generator 102 → data analysis platform:

[0119] Data flow: load generation data / statistics;

[0120] Description: The load generator 102 may also send load-generated data or statistical information to a data analysis platform for analyzing the impact of the load on system performance.

[0121] In the specific implementation, take the test of a certain model of computer fast interconnect memory expansion card as an example:

[0122] The test scenario can be 80% random read + 20% sequential write, and the pressure lasts for 10 minutes.

[0123] Result analysis:

[0124] Average power consumption: 12.3W (peak 18.7W);

[0125] High-power operation: Snoop response (35% of total power consumption).

[0126] Optimization measures: After enabling the cache prefetch policy, the energy efficiency ratio (EPO) per operation is reduced by 22%.

[0127] An embodiment of the present invention provides a memory power consumption testing method. The method is described in detail below in conjunction with the execution flow of the memory power consumption testing method.

[0128] Figure 2 A flowchart of a memory power consumption testing method provided by an embodiment of the present invention; Figure 3 A flowchart of another memory power consumption testing method provided by an embodiment of the present invention.

[0129] like Figure 2 As shown, the memory power consumption testing method provided by the embodiment of the present invention may include:

[0130] S201: configuring computer rapid interconnect link parameters for a memory under test of a computer rapid interconnect interface installed on a first board.

[0131] S202: In response to a test command issued by a computer fast interconnect core, simulate a computer fast interconnect transaction operation on the memory under test.

[0132] S203: synchronously collecting state parameters of the memory under test to calculate power consumption data when the memory under test executes a computer fast interconnect transaction operation.

[0133] like Figure 3 As shown, the memory power consumption testing method provided by the embodiment of the present invention may include:

[0134] S201: configuring computer rapid interconnect link parameters for a memory under test of a computer rapid interconnect interface installed on a first board.

[0135] S301: The computer rapid interconnect core sends corresponding test commands to the load generator according to the computer rapid interconnect device control parameters of the current round of iterative testing.

[0136] S203: synchronously collecting state parameters of the memory under test to calculate power consumption data when the memory under test executes a computer fast interconnect transaction operation.

[0137] S302: Determine whether the iteration end condition is met, if yes, proceed to S304; if not, proceed to S303.

[0138] S303: Adjust the control parameters of the computer rapid interconnect device according to the power consumption data of the tested memory, and then proceed to S301.

[0139] S304: Outputting the optimization control strategy of the tested memory.

[0140] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0141] An embodiment of the present invention also provides a memory power consumption testing device, which may include: a configuration unit, configured to configure computer rapid interconnect link parameters for a memory under test installed on a computer rapid interconnect interface of a first board; a testing unit, configured to simulate computer rapid interconnect transaction operations on the memory under test in response to a test command issued based on a computer rapid interconnect core; and a collection unit, configured to synchronously collect state parameters of the memory under test to calculate power consumption data when the memory under test executes computer rapid interconnect transaction operations.

[0142] The memory power consumption testing apparatus provided by an embodiment of the present invention may further include an optimization verification unit configured to adjust computer interconnect device control parameters based on the power consumption data of the memory under test when the test does not meet the iteration termination conditions. Accordingly, the testing unit, in response to test commands issued by the computer interconnect core, simulates computer interconnect transaction operations on the memory under test, including issuing corresponding test commands to a load generator based on the computer interconnect device control parameters for the current iteration test.

[0143] The description of the features in the embodiment corresponding to the memory power consumption testing device can be found in the relevant description of the embodiment corresponding to the memory power consumption testing method, and will not be repeated here.

[0144] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned memory power consumption test method embodiments.

[0145] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned memory power consumption testing method embodiments when running.

[0146] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0147] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned memory power consumption testing method embodiments are implemented.

[0148] An embodiment of the present invention also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned memory power consumption test method embodiments.

[0149] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0150] The above is a detailed introduction to the memory power consumption test system, method and device provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified. These improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A memory power consumption test system, characterized in that: include: Test controller, load generator and first board; The first board is provided with a computer rapid interconnection interface for installing the memory under test, the computer rapid interconnection interface is connected to the load generator, and the load generator is connected to the test controller; The test controller has a computer rapid interconnect core, which is used to send test commands to the load generator and synchronously collect state parameters of the tested memory to calculate power consumption data when the tested memory performs computer rapid interconnect transaction operations; The load generator is used to simulate the computer fast interconnect transaction operation on the tested memory according to the test command; The test controller sends a test command to the load generator and synchronously collects state parameters of the tested memory to calculate power consumption data when the tested memory performs a computer fast interconnect transaction operation, including: The test controller performs an iterative test on the memory under test. In a current round of iterative testing, the test controller issues a corresponding test command to the load generator based on the computer rapid interconnect device control parameters of the current round of iterative testing to obtain power consumption data corresponding to the computer rapid interconnect device control parameters. If an iteration end condition is not met, the test controller adjusts the computer rapid interconnect device control parameters based on the power consumption data of the memory under test before entering the next round of iterative testing. The type of the computer fast interconnect transaction operation includes at least one of a computer fast interconnect memory read / write transaction and a computer fast interconnect cache consistency operation transaction.

2. The memory power consumption test system according to claim 1, wherein: The test controller includes a first processor and a power consumption acquisition module; The first processor has the computer rapid interconnect core; The power consumption acquisition module is connected to a first sensor provided on the memory under test, and is used to read the state parameters of the memory under test acquired by the first sensor.

3. The memory power consumption test system according to claim 1, wherein: Also includes the host computer; The host computer is used to obtain the computer rapid interconnection transaction operation and the state parameters of the memory under test, and establish a correspondence between the execution of the computer rapid interconnection transaction operation by the memory under test and the power consumption data of the memory under test based on the execution time of the computer rapid interconnection transaction operation and the timestamp of the state parameters of the memory under test.

4. The memory power consumption test system according to claim 3, characterized in that: The host computer is further configured to receive the test system status parameters sent by the test controller and the relevant data of the computer rapid interconnection transaction sent by the load generator, so as to establish a correspondence between the computer rapid interconnection transaction operation executed by the tested memory and the power consumption data of the tested memory according to the test system status parameters and the relevant data of the computer rapid interconnection transaction; The data related to the computer rapid interconnection transaction includes at least one of a generation parameter of the computer rapid interconnection transaction and a statistical parameter of the computer rapid interconnection transaction.

5. The memory power consumption test system according to claim 3, characterized in that: The host computer establishes a corresponding relationship between the computer fast interconnection transaction operation executed by the tested memory and the power consumption data of the tested memory, including: The host computer establishes a power consumption transaction association graph of the tested memory according to the type of the computer rapid interconnection transaction operation executed by the tested memory and the corresponding relationship between the state parameters of the tested memory and time.

6. The memory power consumption test system according to claim 3, characterized in that: The host computer is further configured to calculate the unit operation energy efficiency ratio of the tested memory based on the current parameter of the tested memory, the voltage parameter of the tested memory, the unit acquisition time, and the computer fast interconnection transaction operation performed by the tested memory during the unit acquisition time.

7. A memory power consumption test method, characterized in that: include: configuring computer rapid interconnect link parameters for a memory under test of a computer rapid interconnect interface installed on the first board; In response to a test command issued based on a computer fast interconnect core, simulating a computer fast interconnect transaction operation on the memory under test; Synchronously collecting state parameters of the tested memory to calculate power consumption data when the tested memory executes the computer fast interconnection transaction operation; The type of the computer fast interconnect transaction operation includes at least one of a computer fast interconnect memory read / write transaction and a computer fast interconnect cache consistency operation transaction.

8. A memory power consumption test device, characterized in that: include: a configuration unit, configured to configure computer rapid interconnect link parameters for a memory under test of a computer rapid interconnect interface installed on the first board; A test unit, configured to simulate a computer fast interconnect transaction operation on the memory under test in response to a test command issued based on a computer fast interconnect core; an acquisition unit, configured to synchronously acquire state parameters of the memory under test to calculate power consumption data when the memory under test executes the computer fast interconnection transaction operation; The type of the computer fast interconnect transaction operation includes at least one of a computer fast interconnect memory read / write transaction and a computer fast interconnect cache consistency operation transaction.

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