Display device

Abstract

A display device is provided. The display device includes: a display panel including an active area in which a plurality of sub-pixels are disposed and a non-active area surrounding the active area; and a plurality of level shift circuits disposed in the active area and transmitting a mode signal to drive the plurality of sub-pixels in a first mode or a second mode, in which each of the plurality of sub-pixels includes: a first light emitting element; a first optical member that refracts light from the first light-emitting element; a second light emitting element; and a second optical member refracting light from the second light emitting element and having a different shape from the first optical member. Accordingly, a bezel region can be reduced by embedding a level shift circuit for generating a mode signal in an active region.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0196627, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of controlling a viewing angle. Background Art

[0004] With the development of technology in modern society, display devices are being used in various ways to provide information to users. Display devices are included not only in electronic billboards that simply transmit visual information in one direction, but also in various electronic devices that require higher technology to confirm user input and provide information in response to the confirmed input. Summary of the Invention

[0005] For example, a display device may be included in a vehicle to provide various types of information to the driver and passengers of the vehicle. However, the display device in the vehicle needs to appropriately display content so as not to interfere with the operation of the vehicle. For example, the display device needs to restrict the display of content that may reduce driving attention while the vehicle is in operation.

[0006] An object to be achieved by the present disclosure is to provide a display device capable of controlling a viewing angle with a minimized bezel.

[0007] An object to be achieved by a preferred embodiment of the present disclosure is to provide a display device capable of generating a mode signal using a low - voltage signal without a separate high - voltage IC.

[0008] Another object to be achieved by a preferred embodiment of the present disclosure is to provide a display device capable of selectively controlling the viewing angle in both the row direction and the column direction for multiple regions.

[0009] The objects of the present disclosure are not limited to the objects mentioned above, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of the present disclosure, a display device according to an exemplary embodiment of the present disclosure includes: a display panel including an active area in which a plurality of sub-pixels are disposed and a non-active area surrounding the active area; and a plurality of level shifter circuits (which may also be referred to as level shifters or simply "level shift") disposed in the active area and transmitting a mode signal to drive the plurality of sub-pixels in a first mode or a second mode, wherein each of the plurality of sub-pixels includes: a first light-emitting element; a first optical member that refracts light from the first light-emitting element; a second light-emitting element; and a second optical member that refracts light from the second light-emitting element and has a different shape from the first optical member. Accordingly, the viewing angle of the sub-pixel can be controlled by the first optical member and the second optical member, thereby controlling the viewing angle of the display device. In addition, by embedding a level shift for generating a mode signal in the active area, the bezel area can be reduced.

[0011] Other details of the exemplary embodiment are included in the detailed description and the drawings.

[0012] According to an exemplary embodiment of the present disclosure, by embedding a level shift for generating a mode signal in the active area, the bezel area can be reduced.

[0013] According to an exemplary embodiment of the present disclosure, by using a level shift that utilizes the same control signal as the signal for driving the sub-pixel circuit to generate a mode signal without using a separate IC, the manufacturing cost can be reduced.

[0014] According to an exemplary embodiment of the present disclosure, by disposing level shifts in a plurality of regions, the viewing angle can be selectively controlled in both the row direction and the column direction.

[0015] According to an exemplary embodiment of the present disclosure, by allowing the level shift to share signal lines with the sub-pixel circuit to minimize additional lines for driving the level shift, the line design can be prevented from becoming complicated.

[0016] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings, in which:

[0018] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 3A and Figure 3B is a waveform diagram for describing a sub-pixel circuit of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 4A and Figure 4B is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 5 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 6 is a schematic enlarged plan view of an active region of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 7 is a circuit diagram of a first level shifter of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 8 is a waveform diagram for describing a first level shifter of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 9A is a circuit diagram of a first level shifter of a display device during a first period in a wide viewing angle mode according to an exemplary embodiment of the present disclosure;

[0027] Figure 9B is a circuit diagram of a first level shifter of a display device during a second period in a wide viewing angle mode according to an exemplary embodiment of the present disclosure;

[0028] Figure 9C is a circuit diagram of a first level shifter of a display device during a third period in a wide viewing angle mode according to an exemplary embodiment of the present disclosure;

[0029] Figure 10 is a circuit diagram of a second level shifter of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 11 is a waveform diagram for describing a second level shifter of a display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 12A is a circuit diagram of a second level shifter of a display device during a first period in a narrow viewing angle mode according to an exemplary embodiment of the present disclosure;

[0032] Figure 12B is a circuit diagram of a second level shifter of a display device according to an exemplary embodiment of the present disclosure during a second period in a narrow viewing angle mode; and

[0033] Figure 12C is a circuit diagram of a second level shifter of a display device according to an exemplary embodiment of the present disclosure during a third period in a narrow viewing angle mode. DETAILED DESCRIPTION

[0034] By referring to the following exemplary embodiments described in detail together with the accompanying Figure 1 drawings, the advantages and features of the present disclosure and the methods for achieving the advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0035] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having", and "consisting of" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular form may include the plural form unless otherwise explicitly stated.

[0036] Even if not explicitly stated, components are interpreted to include a normal error range.

[0037] When using terms such as "on", "above", "below", and "next to" to describe the positional relationship between two parts, unless these terms are used together with the term "immediately" or "directly", one or more parts may be located between the two parts.

[0038] When an element or layer is provided "on" another element or layer, other layers or other elements may be directly placed on the other element or between them.

[0039] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0040] Throughout the specification, like reference numerals generally represent like elements.

[0041] For ease of description, the dimensions and thicknesses of each component shown in the drawings are illustrated, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0042] The features of the various embodiments of the present disclosure may be partially or wholly adhered or combined with each other, and may be interlocked and operated in various ways technically, and the embodiments may be executed independently or in association with each other.

[0043] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0044] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0045] As a display device 100 according to an exemplary embodiment of the present disclosure, an electroluminescent display device may be applied. As the electroluminescent display device, an organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device may be used.

[0046] Referring to Figure 1 , the display device 100 may include a display panel PN, a data driving circuit DD, a gate driving circuit GD, and a timing controller TC.

[0047] The display panel PN may generate an image to be provided to a user. For example, the display panel PN may generate and display an image to be provided to the user through pixels PX in which a plurality of sub-pixel circuits are provided.

[0048] The data driving circuit DD, the gate driving circuit GD, and the timing controller TC may provide signals for the operation of each pixel PX through signal lines. The signal lines may include, for example, data lines DL and gate lines GL.

[0049] The data lines DL may include a plurality of lines arranged in a column direction and connected to the pixels PX arranged in the column direction, and the gate lines GL may include a plurality of lines arranged in a row direction and connected to the pixels PX arranged in the row direction.

[0050] In some cases, the display device 100 may further include a power supply unit. In this case, a signal for operating the pixel PX may be provided through a power line connecting the power supply unit and the display panel PN. According to an exemplary embodiment, the power supply unit may supply power to the data driving circuit DD and the gate driving circuit GD. The data driving circuit DD and the gate driving circuit GD may be driven based on the power supplied from the power supply unit.

[0051] For example, the data driving circuit DD can apply data signals to each pixel PX through data lines DL, the gate driving circuit GD can apply gate signals to each pixel PX through gate lines GL, and the power supply unit can supply power voltage to each pixel PX through power voltage supply lines.

[0052] The timing controller TC can control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller TC can rearrange the digital video data input from the outside to match the resolution of the display panel PN, and supply the rearranged digital video data to the data driving circuit DD.

[0053] The data driving circuit DD can convert the digital video data input from the timing controller TC into analog data voltage based on data control signals, and supply the analog data voltage to a plurality of data lines DL.

[0054] The gate driving circuit GD can generate scan signals and light emission signals (or light emission control signals) based on gate control signals. The gate driving circuit GD can include a scan driver and a light emission signal driver. The scan driver can generate scan signals for driving at least one scan line connected to each pixel row in a row-by-row order, and supply the generated scan signals to the scan lines. The light emission signal driver can generate light emission signals for driving at least one light emission signal line connected to each pixel row in a row-by-row order, and supply the generated light emission signals to the light emission signal lines.

[0055] According to an exemplary embodiment, the gate driving circuit GD can be disposed on the display panel PN using an in-panel gate driver (GIP) method. For example, the gate driving circuit GD can be divided into multiple parts and respectively disposed on at least two side surfaces of the display panel PN.

[0056] The display panel PN can include an active area and a non-active area surrounding the active area.

[0057] The active area of the display panel PN can include a plurality of pixels PX arranged in a row direction and a column direction. The pixels PX can be arranged in an area where a plurality of data lines and a plurality of gate lines intersect.

[0058] One pixel PX can include a plurality of sub-pixels that emit different colors. For example, the pixel PX can use three sub-pixels to implement blue, red, and green. However, the pixel PX is not limited thereto, and in some cases, the pixel PX can also include sub-pixels that further implement a specific color (for example, white).

[0059] In the pixel PX, the area that implements blue can be referred to as a blue sub-pixel, the area that implements red can be referred to as a red sub-pixel, and the area that implements green can be referred to as a green sub-pixel.

[0060] Each of the plurality of sub-pixels may include a first light-emitting element and a second light-emitting element, and may include a first lens that refracts light from the first light-emitting element in a specific direction and a second lens that refracts light from the second light-emitting element in a specific direction. Accordingly, the first lens and the second lens may limit the viewing angle of each of the plurality of sub-pixels.

[0061] A detailed description of the first lens and the second lens will be made with reference to Figure 4A and Figure 4B below.

[0062] The non-active region may be provided along the periphery of the active region. Various components for driving the plurality of sub-pixels provided in the pixel PX may be provided in the non-active region. For example, at least a part of the gate driving circuit GD may be provided in the non-active region. The non-active region may be referred to as a border region.

[0063] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. The plurality of pixels PX may include a plurality of sub-pixels SP (see Figure 6 ) each representing a different color and sub-pixel circuits SPC corresponding to each of the plurality of sub-pixels SP.

[0064] Referring to Figure 2 , each of the plurality of sub-pixels SP (see Figure 6 ) includes a plurality of light-emitting elements ED1 and ED2, and each of the plurality of sub-pixel circuits SPC includes a driving transistor DT, first to eighth transistors T1 to T8, and a storage capacitor Cst.

[0065] The plurality of transistors DT and T1 to T8 may include at least one of amorphous silicon, polycrystalline silicon, and an oxide semiconductor such as IGZO. The first electrode or the second electrode of the transistor may be a source electrode or a drain electrode. For example, the first electrode may be a source electrode and the second electrode may be a drain electrode. As another example, the first electrode may be a drain electrode and the second electrode may be a source electrode.

[0066] At least some of the plurality of transistors included in the sub-pixel circuit SPC may be n-type transistors or p-type transistors. In the case of a p-type transistor, the low-level voltage of each driving signal is a voltage that turns on the TFT, and the high-level voltage of each driving signal may be a voltage that turns off the transistor.

[0067] Here, the low-level voltage may correspond to a preset voltage lower than the high-level voltage. For example, the low-level voltage may include a voltage falling within the range of -8V to -12V. The high-level voltage may correspond to a preset voltage higher than the low-level voltage. For example, the high-level voltage may include a voltage falling within the range of 12V to 16V. According to an exemplary embodiment, the low-level voltage may be referred to as the first voltage, and the high-level voltage may be referred to as the second voltage. In this case, the first voltage may be lower than the second voltage.

[0068] The first electrode or the second electrode of the transistor to be described below may refer to the source electrode or the drain electrode. However, the terms first electrode and second electrode are only terms used to distinguish each electrode and do not limit which corresponds to each electrode. In addition, the first electrode of each electrode may not refer to the same electrode. For example, the first electrode of the first transistor T1 may refer to the source electrode of the first transistor T1, while the first electrode of the eighth transistor T8 may refer to the drain electrode of the eighth transistor T8.

[0069] The driving transistor DT may control the driving current applied to the plurality of light-emitting elements according to the source-gate voltage Vsg. The driving transistor DT includes a source electrode connected to a high-potential driving voltage line supplied with a high-potential driving voltage VDD, a gate electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0070] The first transistor T1 may apply the data voltage Vdata from the data line DL to the first node N1. The first transistor T1 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to the first scan signal line to which the first scan signal SCAN1 is applied. The first transistor T1 may be turned on or off by the first scan signal SCAN1. Therefore, the first transistor T1 may apply the data voltage Vdata from the data line DL to the first node N1 in response to the low-level first scan signal SCAN1 as the conductive level.

[0071] The second transistor T2 may diode-connect the gate electrode and the drain electrode of the driving transistor DT. The second transistor T2 includes a drain electrode connected to the second node N2, a source electrode connected to the third node N3, and a gate electrode connected to the second scan data line to which the second scan signal SCAN2 is applied. The second transistor T2 may be turned on or off by the second scan signal SCAN2. Therefore, the second transistor T2 may diode-connect the gate electrode and the drain electrode of the driving transistor DT in response to the low-level second scan signal SCAN2 as the conductive level.

[0072] The third transistor T3 can apply a reference voltage Vref to the first node N1. The third transistor T3 includes a source electrode connected to a reference line that transmits the reference voltage Vref, a drain electrode connected to the first node N1, and a gate electrode connected to a light-emitting signal line. The third transistor T3 can be turned on or off by the light-emitting signal EM. Therefore, the third transistor T3 can transmit the reference voltage Vref to the first node N1 in response to a low-level light-emitting signal EM that is a conductive level.

[0073] When driven in a wide viewing angle mode as a first mode, the fourth transistor T4 can form a current path between the driving transistor DT and the first light-emitting element ED1. The fourth transistor T4 includes a source electrode connected to a fourth node N4, a drain electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to a first mode control line to which a first mode signal MS1 is applied. The fourth transistor T4 can be turned on or off by the first mode signal MS1. Therefore, the fourth transistor T4 forms a current path between the fourth node N4, which is the source electrode of the fourth transistor T4, and the first light-emitting element ED1 in response to a low-level first mode signal MS1 that is a conductive level. That is, the fourth transistor T4 forms a current path between the driving transistor DT and the first light-emitting element ED1 in response to a low-level first mode signal MS1. Therefore, the fourth transistor T4 can also be referred to as a first light-emitting control transistor that controls the light emission of the first light-emitting element ED1.

[0074] Here, the first mode signal MS1 is provided by a first level shifter LS1, which will be described below, and can control the driving (or light emission) of the first light-emitting element ED1 on which a first lens is provided.

[0075] The fifth transistor T5 can apply the reference voltage Vref to the anode electrode of the first light-emitting element ED1. The fifth transistor T5 includes a source electrode connected to a reference line that transmits the reference voltage Vref, a drain electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to a second scan signal line to which a second scan signal SCAN2 is applied. The fifth transistor T5 can be turned on or off by the second scan signal SCAN2. Therefore, the fifth transistor T5 can apply the reference voltage Vref to the anode electrode of the first light-emitting element ED1 in response to a low-level second scan signal SCAN2 that is a conductive level.

[0076] The sixth transistor T6 can apply a reference voltage Vref to the anode electrode of the second light-emitting element ED2. The sixth transistor T6 includes a source electrode connected to a reference line that transmits the reference voltage Vref, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second scan signal line to which a second scan signal SCAN2 is applied. The sixth transistor T6 can be turned on or off by the second scan signal SCAN2. Therefore, the sixth transistor T6 can apply the reference voltage Vref to the anode electrode of the second light-emitting element ED2 in response to the low-level second scan signal SCAN2 as a conductive level.

[0077] When driven in a narrow viewing angle mode as a second mode, the seventh transistor T7 can form a current path between the driving transistor DT and the second light-emitting element ED2. The seventh transistor T7 includes a source electrode connected to the fourth node N4, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second mode control line to which a second mode signal MS2 is applied. The seventh transistor T7 can be turned on or off by the second mode signal MS2. Therefore, the seventh transistor T7 forms a current path between the fourth node N4, which is the source electrode of the seventh transistor T7, and the second light-emitting element ED2 in response to the low-level second mode signal MS2 as a conductive level. That is, the seventh transistor T7 forms a current path between the driving transistor DT and the second light-emitting element ED2 in response to the low-level second mode signal MS2. Therefore, the seventh transistor T7 can also be referred to as a second light-emission control transistor that controls the light emission of the second light-emitting element ED2.

[0078] Here, the second mode signal MS2 is provided by a second level shifter LS2, which will be described below, and can control the driving (or light emission) of the second light-emitting element ED2 on which a second lens is provided.

[0079] The eighth transistor T8 can apply a driving current of the driving transistor DT to the fourth node N4. The eighth transistor T8 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to a light-emission signal line that transmits a light-emission signal EM. The eighth transistor T8 can be turned on or off by the light-emission signal EM. Therefore, the eighth transistor T8 can transmit the driving current to the fourth node N4 in response to the low-level light-emission signal EM as a conductive level.

[0080] The storage capacitor Cst includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst is connected to the first transistor T1. The storage capacitor Cst can store a specific voltage and keep the voltage of the gate electrode of the driving transistor DT constant when the light-emitting element emits light.

[0081] The first light-emitting element ED1 can be connected to a fourth transistor T4 that is turned on or off by a first mode signal MS1. The second light-emitting element ED2 can be connected to a seventh transistor T7 that is turned on or off by a second mode signal MS2.

[0082] In this case, the first light-emitting element ED1 or the second light-emitting element ED2 can be connected to other components of the sub-pixel circuit SPC, such as the driving transistor DT, according to the mode. The mode can be specified by a user input or determined when a pre-specified condition is met. For example, when a pre-specified first condition is met, the first light-emitting element ED1 can emit light based on the fact that the first mode signal MS1 is supplied. When a pre-specified second condition is met, the second light-emitting element ED2 can emit light based on the fact that the second mode signal MS2 is supplied. The first condition can include pre-specified conditions for driving in the first mode. The second condition can include pre-specified conditions for driving in the second mode.

[0083] When the first mode signal MS1 is input as a low value, the sub-pixel circuit can operate in the first mode. When the second mode signal MS2 is input as a low value, the sub-pixel circuit can operate in the second mode. In this case, the first mode can be a wide viewing angle mode, and the second mode can be a narrow viewing angle mode.

[0084] Specifically, the first light-emitting element ED1 emits light in the wide viewing angle mode as the first mode. As Figure 4A shown, a semi-cylindrical first lens 161 is provided on the first light-emitting element ED1, so a wide viewing angle mode can be achieved. The first light-emitting element ED1 includes an anode electrode connected to the fourth transistor T4 and a cathode electrode connected to a low potential power line to which a low potential power supply VSS is applied. The first light-emitting element ED1 receives the driving current of the driving transistor DT through the turned-on fourth transistor T4 when in the wide viewing angle mode. Therefore, when driven in the wide viewing angle mode, the first light-emitting element ED1 can receive the driving current to emit light.

[0085] The second light-emitting element ED2 emits light in the narrow viewing angle mode. As Figure 4BAs shown, the hemispherical second lens 162 is disposed on the second light-emitting element ED2, so that a narrow viewing angle mode can be achieved. The second light-emitting element ED2 includes an anode electrode connected to the seventh transistor T7 and a cathode electrode connected to the low-potential power line. The second light-emitting element ED2 receives the driving current of the driving transistor DT through the turned-on seventh transistor T7 when in the narrow viewing angle mode. Therefore, when driven in the narrow viewing angle mode, the second light-emitting element ED2 can receive the driving current to emit light.

[0086] Figure 3A and Figure 3B are waveform diagrams for describing a sub-pixel circuit of a display device according to an exemplary embodiment of the present disclosure. Specifically, Figure 3A is a waveform diagram for describing a sub-pixel circuit for implementing a wide viewing angle mode as a first mode, while Figure 3B is a waveform diagram for describing a sub-pixel circuit for implementing a narrow viewing angle mode as a second mode.

[0087] Referring together to Figures 2 to 3B , in the wide viewing angle mode, only the first light-emitting element ED1 can emit light, while in the narrow viewing angle mode, only the second light-emitting element ED2 can emit light. In the wide viewing angle mode, the second mode signal MS2 for controlling the light emission of the second light-emitting element ED2 can be output only at a high level as an off level, so that only the first light-emitting element ED1 emits light, while in the narrow viewing angle mode, the first mode signal MS1 for controlling the light emission of the first light-emitting element ED1 can be output only at a high level as an off level, so that only the second light-emitting element ED2 emits light.

[0088] Specifically, referring to Figure 2 and Figure 3A to view the wide viewing angle mode, a low-level second scan signal SCAN2, a low-level first mode signal MS1, and a low-level light emission signal EM are output during an initial period Ti. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be turned on by the low-level second scan signal SCAN2, the fourth transistor T4 can be turned on by the low-level first mode signal MS1, and the third transistor T3 and the eighth transistor T8 can be turned on by the low-level light emission signal EM.

[0089] The first node N1 can be initialized to the reference voltage Vref through the turned-on third transistor T3. The voltage of the anode electrode of the first light-emitting element ED1 can be initialized to the reference voltage Vref through the turned-on fifth transistor T5, and the voltage of the anode electrode of the second light-emitting element ED2 can be initialized to the reference voltage Vref through the turned-on sixth transistor T6. The driving transistor DT is diode-connected through the turned-on second transistor T2, and the gate electrode and the drain electrode of the driving transistor DT are short-circuited, so the driving transistor DT operates like a diode. The reference voltage Vref transmitted to the anode electrode side of the first light-emitting element ED1 through the turned-on fifth transistor T5 is transmitted to the third node N3 and the second node N2 through the turned-on fourth transistor T4 and the eighth transistor T8, so the fourth node N4, the third node N3, and the second node N2 can also be initialized to the reference voltage Vref.

[0090] Next, during the sampling period Ts, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 can be output, and a high-level first mode signal MS1 can be output. A high-level light-emitting signal EM is output, so the third transistor T3 can be turned off. At the same time, the first transistor T1 is turned on through the low-level first scan signal SCAN1, so the data voltage Vdata can be transmitted to the first node N1. The driving transistor DT is diode-connected through the turned-on second transistor T2, and the difference voltage between the high-potential power supply voltage and the threshold voltage can be sampled and supplied to the second node N2.

[0091] During the holding period Th, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can all be turned off. However, even if the first transistor T1 is turned off, the data voltage Vdata input in the previous sampling period Ts can be held by the storage capacitor Cst.

[0092] Finally, during the light-emitting period Te, a low-level first mode signal MS1 and a light-emitting signal EM are output, and a high-level second mode signal MS2 is output. The reference voltage Vref is applied to the first node N1 through the third transistor T3 turned on by the low-level light-emitting signal EM, and the voltage of the first node N1 can be the difference voltage between the reference voltage Vref and the data voltage Vdata. This voltage change can also be reflected in the second node N2. The gate-source voltage Vgs of the driving transistor DT can be set to the value Vdata - Vref + Vth obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the threshold voltage Vth to control the driving current.

[0093] The drive current is supplied from the drive transistor DT to the first light-emitting element ED1 through the turned-on fourth transistor T4 and eighth transistor T8, so that the first light-emitting element ED1 can emit light. However, the second mode signal MS2 is output at a high level. Therefore, the seventh transistor T7 is turned off, and thus the drive current does not transfer from the drive transistor DT to the second light-emitting element ED2. Therefore, in the wide viewing angle mode, the drive current is only applied to the first light-emitting element ED1, so that only the first light-emitting element ED1 can emit light.

[0094] Referring to Figure 2 and Figure 3B Looking at the narrow viewing angle mode, except that the first mode signal MS1 and the second mode signal MS2 are output in reverse, the sub-pixel circuit SPC can be driven in substantially the same manner as in the wide viewing angle mode. That is, during the light-emitting period Te when the second light-emitting element ED2 emits light, the first mode signal MS1 can be output only at a high level as the turn-off level, while the second mode signal MS2 can be output at a low level as the turn-on level.

[0095] Specifically, during the initial period Ti, the first scan signal SCAN1 is output at a high level, and the second scan signal SCAN2 is output at a low level. The first mode signal MS1 is output at a high level, and the second mode signal MS2 and the emission signal EM are output at low levels. Therefore, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be turned on by the second scan signal SCAN2, the seventh transistor T7 can be turned on by the second mode signal MS2, and the third transistor T3 and the eighth transistor T8 can be turned on by the emission signal EM.

[0096] The first node N1 can be initialized to the reference voltage Vref through the third transistor T3 turned on by the emission signal EM, and the anode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2 can be initialized to the reference voltage Vref through each of the fifth transistor T5 and the sixth transistor T6 turned on by the second scan signal SCAN2. The drive transistor DT is diode-connected through the turned-on second transistor T2 and operates like a diode. Finally, the reference voltage Vref transmitted to the anode electrode side of the second light-emitting element ED2 through the turned-on sixth transistor T6 is transmitted to the fourth node N4, the third node N3, and the second node N2 through the turned-on seventh transistor T7, so that the third node N3 and the second node N2 can also be initialized to the reference voltage Vref.

[0097] Next, during the sampling period Ts, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 can be output, and a second mode signal MS2 and a light emission signal EM can be output from a low level to a high level. Since the high-level light emission signal EM is output, the third transistor T3 can be turned off, and the first transistor T1 is turned on by the low-level first scan signal SCAN1, so that the data voltage Vdata can be transmitted to the first node N1. The driving transistor DT is diode-connected through the turned-on second transistor T2, and the differential voltage between the high-potential power supply voltage and the threshold voltage can be sampled and supplied to the second node N2.

[0098] During the holding period Th, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can all be turned off. However, even if the first transistor T1 is turned off, the data voltage Vdata input during the previous sampling period Ts can be held by the storage capacitor Cst.

[0099] Finally, during the light emission period Te, a low-level second mode signal MS2 and a light emission signal EM are output, and a high-level first mode signal MS1 is output. The reference voltage Vref is applied to the first node N1 through the third transistor T3 turned on by the low-level light emission signal EM, and the voltage of the first node N1 can be the differential voltage between the reference voltage Vref and the data voltage Vdata. This voltage change can also be reflected in the second node N2. The gate-source voltage Vgs of the driving transistor DT can be set to a value Vdata-Vref+Vth obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the threshold voltage Vth to control the driving current.

[0100] The driving current is supplied from the driving transistor DT to the second light emitting element ED2 through the turned-on seventh transistor T7, so that the second light emitting element ED2 can emit light. However, since the first mode signal MS1 is output at a high level, the fourth transistor T4 is turned off, so that the driving current does not transfer from the driving transistor DT to the first light emitting element ED1. Therefore, in the narrow viewing angle mode, the driving current is only applied to the second light emitting element ED2, so that only the second light emitting element ED2 can emit light.

[0101] Figure 4A and Figure 4B are cross-sectional views of a display device according to an exemplary embodiment of the present disclosure. Specifically, Figure 4A shows a sub-pixel in which a first lens 161 is provided, and Figure 4B shows a sub-pixel in which a second lens 162 is provided.

[0102] Reference Figure 4A and Figure 4B According to Figure 4A and Figure 4B , the display device 100 according to an exemplary embodiment of the present disclosure includes a substrate 110, a buffer film 111, a gate insulating film 112, an interlayer insulating film 113, a lower protective film 114, an outer coating 115, a first transistor Tr1, a second transistor Tr2, a first light-emitting element ED1, a second light-emitting element ED2, a first lens 161, a second lens 162, a lens protective film 170, and a packaging member 180.

[0103] The substrate 110 may include an insulating material. The substrate 110 may include a transparent material. For example, the substrate 110 may include glass or plastic.

[0104] The buffer film 111 may be disposed on the substrate 110. The buffer film 111 may include an insulating material. For example, the buffer film 111 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer film 111 may have a multilayer structure. For example, the buffer film 111 may have a stacked structure of a film formed of silicon nitride (SiNx) and a film formed of silicon oxide (SiOx).

[0105] The buffer film 111 may be located between the substrate 110 and the driving part of each pixel PX. The buffer film 111 may prevent contamination by the substrate 110 during the formation of the driving part. For example, the top surface of the substrate 110 facing the driving part of each pixel PX may be covered by the buffer film 111. The driving part of each pixel PX may be located on the buffer film 111.

[0106] The gate insulating film 112 may be disposed on the buffer film 111. The gate insulating film 112 may include an insulating material. For example, the gate insulating film 112 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating film 112 may include a material having a high dielectric constant. For example, the gate insulating film 112 may include a high-K material such as hafnium oxide (HfO). The gate insulating film 112 may have a multilayer structure.

[0107] The gate insulating film 112 may extend between the semiconductor layers 121 and 131 and the gate electrodes 122 and 132 of the transistors Tr1 and Tr2. For example, the gate electrodes of the driving transistor DT and the switching transistor ST may be insulated from the semiconductor layers of the driving transistor DT and the switching transistor ST through the gate insulating film 112. The gate insulating film 112 may cover the semiconductor layer of each pixel PX. The gate electrodes of the driving transistor DT and the switching transistor ST may be located on the gate insulating film 112.

[0108] The interlayer insulating film 113 may be disposed on the gate insulating film 112. The interlayer insulating film 113 may include an insulating material. For example, the interlayer insulating film 113 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The interlayer insulating film 113 may extend between the gate electrode and the source electrode and between the gate electrode and the drain electrode of each of the driving transistor DT and the switching transistor. For example, the source electrode and the drain electrode of each of the driving transistor DT and the switching transistor may be insulated from the gate electrode by the interlayer insulating film 113. The interlayer insulating film 113 may cover the gate electrode of each of the driving transistor DT and the switching transistor. The source electrode and the drain electrode of each pixel PX may be located on the interlayer insulating film 113. The gate insulating film 112 and the interlayer insulating film 113 may expose the source region and the drain region of each semiconductor pattern located within each pixel PX.

[0109] The lower protective film 114 may be disposed on the interlayer insulating film 113. The lower protective film 114 may include an insulating material. For example, the lower protective film 114 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower protective film 114 may prevent damage to the driving unit due to external moisture and impact. The lower protective film 114 may extend along the surface of the driving transistor DT and the switching transistor ST facing the substrate 110. The lower protective film 114 may contact the interlayer insulating film 113 outside the driving unit located within each pixel PX.

[0110] The outer coating 115 may be disposed on the lower protective film 114. The outer coating 115 may include an insulating material. The outer coating 115 may include a material different from that of the lower protective film 114. For example, the outer coating 115 may include an organic insulating material. The outer coating 115 may remove the step caused by the driving unit of each pixel PX. For example, the top surface of the outer coating 115 facing the device substrate 110 may be a flat surface.

[0111] The first transistor Tr1 and the second transistor Tr2 may be disposed on the substrate 110. The first transistor Tr1 may be electrically connected between the drain electrode of the driving transistor DT and the first lower electrode 141 of the first light-emitting element ED1. The second transistor Tr2 may be electrically connected between the drain electrode of the driving transistor DT and the second lower electrode 151 of the second light-emitting element ED2.

[0112] The first transistor Tr1 may include a first semiconductor layer 121, a first gate electrode 122, a first source electrode 123, and a first drain electrode 124. The first transistor Tr1 may have the same structure as the switching transistor and the driving transistor DT. For example, the first semiconductor layer 121 may be located between the buffer film 111 and the gate insulating film 112, and the first gate electrode 122 may be located between the gate insulating film 112 and the interlayer insulating film 113. The first source electrode 123 and the first drain electrode 124 may be located between the interlayer insulating film 113 and the lower protective film 114. The first gate electrode 122 may overlap with the channel region of the first semiconductor layer 121. The first source electrode 123 may be electrically connected to the source region of the first semiconductor layer 121. The first drain electrode 124 may be electrically connected to the drain region of the first semiconductor layer 121.

[0113] The second transistor Tr2 may include a second semiconductor layer 131, a second gate electrode 132, a second source electrode 133, and a second drain electrode 134. For example, the second semiconductor layer 131 may be on the same layer as the first semiconductor layer 121, the second gate electrode 132 may be on the same layer as the first gate electrode 122, and the second source electrode 133 and the second drain electrode 134 may be on the same layer as the first source electrode 123 and the first drain electrode 124.

[0114] The first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX may be disposed on the outer coating 115 of the corresponding pixel PX.

[0115] The first light-emitting element ED1 may emit light representing a specific color. For example, the first light-emitting element ED1 may include a first lower electrode 141, a first light-emitting layer 142, and a first upper electrode 143 sequentially stacked on the substrate 110.

[0116] The first lower electrode 141 may include a conductive material. The first lower electrode 141 may include a material having a high reflectivity. For example, the first lower electrode 141 may include metals such as aluminum (Al) and silver (Ag). The first lower electrode 141 may have a multilayer structure. For example, the first lower electrode 141 may have the following structure: a reflective electrode formed of a metal is located between transparent electrodes formed of a transparent conductive material such as ITO and IZO. The first lower electrode 141 may be electrically connected to the first drain electrode 124 (or the first source electrode 123) of the first transistor Tr1 through a contact hole penetrating the lower protective film 114 and the outer coating 115.

[0117] The first light-emitting layer 142 may generate light having a brightness corresponding to the voltage difference between the first lower electrode 141 and the first upper electrode 143. For example, the first light-emitting layer 142 may include a light-emitting material layer (EML) containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material.

[0118] The first light-emitting layer 142 may have a multi-layer structure. For example, the first light-emitting layer 142 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0119] The first upper electrode 143 may include a conductive material. The first upper electrode 143 may include a material different from that of the first lower electrode 141. The transmittance of the first upper electrode 143 may be higher than that of the first lower electrode 141. For example, the first upper electrode 143 may be a transparent electrode formed of a transparent conductive material such as ITO and IZO. Accordingly, in the display device according to an exemplary embodiment of the present disclosure, the light generated by the first light-emitting layer 142 may be emitted through the first upper electrode 143.

[0120] The second light-emitting element ED2 may have the same structure as the first light-emitting element ED1. For example, the second light-emitting element ED2 may include a second lower electrode 151, a second light-emitting layer 152, and a second upper electrode 153 sequentially stacked on the substrate 110.

[0121] The second lower electrode 151 may correspond to the first lower electrode 141, the second light-emitting layer 152 may correspond to the first light-emitting layer 142, and the second upper electrode 153 may correspond to the first upper electrode 143. For example, the second lower electrode 151 may be formed in the same structure as the first lower electrode 141 for the second light-emitting element ED2, which is the same for the second light-emitting layer 152 and the second upper electrode 153. For example, the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to have the same structure. However, the present disclosure is not limited thereto, and in some cases, at least some configurations of the first light-emitting element ED1 and the second light-emitting element ED2 may be formed differently.

[0122] In an exemplary embodiment, the second light-emitting layer 152 may be spaced apart from the first light-emitting layer 142. Accordingly, in the display device according to an exemplary embodiment of the present disclosure, light emission due to leakage current may be prevented.

[0123] According to an exemplary embodiment of the present disclosure, in the display device, according to a user selection or a pre-specified condition, light may be generated from only one of the first light-emitting layer 142 and the second light-emitting layer 152.

[0124] The second lower electrode 151 of each pixel PX may be spaced apart from the first lower electrode 141 of the corresponding pixel PX. For example, a bank insulating film 116 may be disposed between the first lower electrode 141 and the second lower electrode 151 of each pixel PX. The bank insulating film 116 may include an insulating material. For example, the bank insulating film 116 may include an organic insulating material. The bank insulating film 116 may include a material different from that of the outer coating 115.

[0125] The second lower electrode 151 of each pixel PX may be insulated from the first lower electrode 141 of the corresponding pixel PX through the bank insulating film 116. For example, the bank insulating film 116 may cover the edges of the first lower electrode 141 and the second lower electrode 151 located within each pixel PX. Therefore, in the display device, an image from the first lens region of each pixel PX where the first light-emitting element ED1 is located or an image from the second lens region of each pixel PX where the second light-emitting element ED2 is located may be provided to the user.

[0126] The first light-emitting layer 142 and the first upper electrode 143 of the first light-emitting element ED1 located within each pixel PX may be stacked on a partial region of the corresponding first lower electrode 141 exposed by the bank insulating film 116. The second light-emitting layer 152 and the second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX may be stacked on a partial region of the corresponding second lower electrode 151 exposed by the bank insulating film 116. For example, the bank insulating film 116 may distinguish a first light-emitting region that emits light from the first light-emitting element ED1 and a second light-emitting region that emits light from the second light-emitting element ED2 within each pixel PX. The size of the second light-emitting region divided within each pixel PX may be smaller than the size of the first light-emitting region.

[0127] The second upper electrode 153 of each pixel PX may be electrically connected to the first upper electrode 143 of the corresponding pixel PX. For example, the voltage applied to the second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX may be the same as the voltage applied to the first upper electrode 143 of the first light-emitting element ED1 located within the corresponding pixel PX. The second upper electrode 153 of each pixel PX may include the same material as the first upper electrode 143 of the corresponding pixel PX. For example, the second upper electrode 153 of each pixel PX may be formed simultaneously with the first upper electrode 143 of the corresponding pixel PX. The second upper electrode 153 of each pixel PX may extend onto the bank insulating film 116 and directly contact the first upper electrode 143 of the corresponding pixel PX. The brightness of the first lens region and the brightness of the second lens region within each pixel PX may be controlled by the driving current generated in the corresponding pixel PX.

[0128] The encapsulation member 180 may be located on the first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX. The encapsulation member 180 may prevent damage to the light-emitting elements ED1 and ED2 due to external moisture and impact. The encapsulation member 180 may have a multi-layer structure. For example, the encapsulation member 180 may include a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 stacked in sequence, but is not limited thereto. The first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 may include an insulating material. The second encapsulation layer 182 may include a material different from that of the first encapsulation layer 181 and the third encapsulation layer 183. For example, the first encapsulation layer 181 and the third encapsulation layer 183 are inorganic encapsulation layers including an inorganic insulating material, while the second encapsulation layer 182 may include an organic encapsulation layer including an organic insulating material. Accordingly, damage to the light-emitting elements ED1 and ED2 of the display device by external moisture and impact can be more effectively prevented.

[0129] The first lens 161 and the second lens 162 may be located on the encapsulation member 180 of each pixel PX. Meanwhile, the term "lens" used in the present disclosure is used for convenience of description and may be defined as an optical member other than a lens as long as it can be used to refract light.

[0130] The first lens 161 may be disposed on the first light-emitting element ED1. The light generated by the first light-emitting element ED1 of each pixel PX may be emitted through the first lens 161 of the corresponding pixel PX. The first lens 161 may have a shape in which light is not restricted in at least one direction. For example, the planar shape of the first lens 161 located within each pixel PX may have a strip shape extending in the first direction.

[0131] In this case, the traveling direction of the light emitted from the first lens region of the pixel PX may not be limited to the first direction. For example, the content (or image) provided through the first lens region of the pixel PX may be shared with people around the user and adjacent to the user in the first direction. In the case of providing content through the first lens region, a mode of providing content within a first viewing angle range wider than a second viewing angle range provided by the second lens region may be referred to as a wide viewing angle mode as a first mode.

[0132] The second lens 162 may be disposed on the second light-emitting element ED2. The light generated by the second light-emitting element ED2 of each pixel PX may be emitted through the second lens 162 of the corresponding pixel PX. The second lens 162 may limit the traveling direction of the transmitted light to the first direction and / or the second direction. For example, the planar shape of the second lens 162 located within the pixel PX may have a circular shape. In this case, the traveling direction of the light emitted from the second lens region of the pixel PX may be limited to the first direction and the second direction. For example, the content provided by the second lens region of the pixel PX may not be shared with people around the user. In the case of providing content through the second lens region, a mode of providing content within a second viewing angle range narrower than the first viewing angle range provided by the first lens region may be referred to as a narrow viewing angle mode as the second mode.

[0133] The first light-emitting region of each pixel PX may have a shape corresponding to the first lens 161 of the corresponding pixel PX. For example, the planar shape of the first light-emitting region of each pixel PX may have a strip shape extending in the first direction. The first lens 161 may have a size larger than the first light-emitting region of the corresponding pixel PX. Therefore, the efficiency of the light emitted from the first light-emitting region of the pixel PX can be improved.

[0134] The second light-emitting region of each pixel PX may have a shape corresponding to the second lens 162 of the corresponding pixel PX. For example, the planar shape of the second light-emitting region of each pixel PX may have a circular shape. The second lens 162 may have a size larger than the second light-emitting region of the corresponding pixel PX. Therefore, the efficiency of the light emitted from the second light-emitting region of the pixel PX can be improved.

[0135] In an exemplary embodiment, the lens protection film 170 may be located on the first lens 161 and the second lens 162 of the pixel PX. The lens protection film 170 may include an insulating material. For example, the lens protection film 170 may include an organic insulating material. The refractive index of the lens protection film 170 may be less than the refractive indices of the first lens 161 and the second lens 162 located within each pixel PX. Therefore, in the display device according to the exemplary embodiment of the present disclosure, due to the difference in refractive index of the lens protection film 170, the light passing through the first lens 161 and the second lens 162 of each pixel PX is not reflected toward the substrate 110.

[0136] Figure 5 is a plan view of a display device according to an exemplary embodiment of the present disclosure. For ease of description, Figure 5 only the display panel PN, the plurality of flexible films (chip on film (COF)), and the plurality of printed circuit boards (PCBs) among the various components of the display device 100 are shown.

[0137] Refer toFigure 5 , the display device 100 includes a plurality of flexible printed circuits (COF), a plurality of printed circuit boards (PCB), and a display panel PN.

[0138] The plurality of flexible printed circuits (COF) may be disposed at one end of the display panel PN. The plurality of flexible printed circuits (COF) are films on which various components are disposed on a flexible base film to supply signals to a plurality of pixels PX and a driving circuit, and may be electrically connected to the display panel PN. For example, the plurality of flexible printed circuits (COF) may supply a power voltage, a data voltage Vdata, etc. to the plurality of pixels PX and the driving circuit.

[0139] Meanwhile, a driver IC such as a data driver IC may be disposed on the plurality of flexible printed circuits (COF). The driver IC is a component that processes data for displaying an image and driving signals for processing the data. According to the mounting method, the driver IC may be set in a chip on glass (COG), chip on film (COF), tape carrier package (TCP) method, etc. However, for ease of description, it has been described as the chip on film method of mounting the driver IC on the plurality of flexible printed circuits (COF), but the present disclosure is not limited thereto. In addition, the driver IC may be integrated with a timing controller and be set as a single chip.

[0140] Meanwhile, a plurality of mode control units for controlling driving in a wide viewing angle mode and a narrow viewing angle mode may be disposed in the driver IC. The mode control unit may provide signals for controlling the mode of a plurality of sub-pixels SP to the plurality of sub-pixels SP. The plurality of mode control units may provide a first mode selection signal for controlling a first mode through a first mode selection signal line MCSL1. In addition, a second mode selection signal for controlling a second mode may be provided through a second mode selection signal line MCSL2. The mode control unit may be defined as a component included in the timing controller TC, or may be defined as a component separated from the timing controller TC.

[0141] Each of the plurality of printed circuit boards (PCB) is electrically connected to the plurality of flexible printed circuits (COF). The plurality of printed circuit boards (PCB) are components that supply signals to the driver IC. The plurality of printed circuit boards (PCB) may have various components configured to supply various signals such as driving signals and data signals to the driver IC.

[0142] The display panel PN may include an active area AA and a non-active area NA surrounding the active area AA. The active area AA of the display panel PN includes a plurality of areas a divided in the row direction. The plurality of areas a may be areas of pixels PX to which the same mode signal is applied. Meanwhile, Figure 5 It is shown that the active area AA is divided into 12 areas a extending in the column direction, but is not limited thereto.

[0143] The display panel PN may include a first mode selection signal line MCSL1 and a second mode selection signal line MCSL2 that extend side by side in a row or column direction in a plurality of regions a. The first mode selection signal line MCSL1 and the second mode selection signal line MCSL2 may each be connected to a mode control unit and transmit a first mode selection signal and a second mode selection signal to the plurality of regions a. The first mode selection signal transmitted by the first mode selection signal line MCSL1 and the second mode selection signal transmitted by the second mode selection signal line MCSL2 may each be output as a first mode signal MS1 and a second mode signal MS2, the voltages of which are changed by a level shift described later. Accordingly, the first mode selection signal line MCSL1 may be referred to as a wide viewing angle mode selection signal line, and the second mode selection signal line MCSL2 may be referred to as a narrow viewing angle mode selection signal line. Meanwhile, Figure 5 FIG. shows a plurality of first mode selection signal lines MCSL1 and a plurality of second mode selection signal lines MCSL2 extending in a column direction in a plurality of regions a, but is not limited thereto, and may extend in a row direction.

[0144] Figure 6 is a schematic enlarged plan view of an active area of a display device according to an exemplary embodiment of the present disclosure. Figure 6 FIG. shows Figure 5 a part of one of the plurality of regions a in FIG., for example, a region corresponding to a total of 12 pixels PX from PX1 to PX12.

[0145] Referring to Figure 6, a level shifter LS that supplies a mode signal to a plurality of sub-pixels SP is disposed in the active region AA. The level shifter LS can supply mode signals MS1 and MS2 to the plurality of sub-pixels SP, and the mode signals MS1 and MS2 control the driving mode of the display panel PN such that the plurality of sub-pixels SP are driven in a first mode or a second mode. Specifically, the level shifter LS can change the output voltages of a first mode selection signal and a second mode selection signal. For example, the level shifter LS can change a low voltage (e.g., 1.8V or 3.3V as a logic voltage) output from the mode control unit to a high voltage (e.g., a value within the range of VGL (-9.0V) to VGH (15.0V)). That is, the level shifter LS can provide a first mode signal or a second mode signal by changing the output voltages of the first mode selection signal and the second mode selection signal provided by the mode control unit. For example, the level shifter LS includes a first level shifter LS1 that provides the first mode signal MS1 and a second level shifter LS2 that provides the second mode signal MS2. Therefore, the first level shifter LS1 can be referred to as a wide viewing angle mode level shifter because it provides the first mode signal MS1 that controls the driving mode in the wide viewing angle mode, and the second level shifter LS2 can also be referred to as a narrow viewing angle mode level shifter because it provides the second mode signal MS2 that controls the driving mode in the narrow viewing angle mode.

[0146] The first level shifter LS1 and the second level shifter LS2 can be disposed one by one for each of the plurality of regions a. That is, the first level shifter LS1 and the second level shifter LS2 can each transmit a mode signal for each of the plurality of regions a. For example, the first level shifter LS1 and the second level shifter LS2 can each be configured to have the same number as the plurality of regions a, and can be disposed one by one for each of the plurality of regions a.

[0147] The plurality of regions a include pixels PX and non-pixel regions NPX. The pixel PX includes a plurality of sub-pixels SP. The non-pixel region NPX can be disposed between adjacent pixels PX. The non-pixel region NPX can be referred to as a region where no sub-pixel SP is disposed.

[0148] The first level shifter LS1 and the second level shifter LS2 are disposed between adjacent pixels PX. For example, when one region a includes 12 pixels PX, the first level shifter LS1 and the second level shifter LS2 can be disposed at an interval of 6 pixels PX. At the same time, Figure 6 It is shown that three pixels PX are disposed in the same row and two pixels PX are disposed in the same column, but this is only shown as an example, and the present disclosure is not limited thereto.

[0149] Meanwhile, the first level shifter LS1 and the second level shifter LS2 can each be disposed in a non-pixel region NPX between the pixels PX. However, the present disclosure is not limited thereto, and when a region a includes three or more pixels PX, the first level shifter LS1 and the second level shifter LS2 can each be disposed in two of the plurality of adjacent pixels PX.

[0150] Figure 7 is a circuit diagram of a first level shifter of a display device according to an exemplary embodiment of the present disclosure.

[0151] Referring to Figure 7 , the first level shifter LS1 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eleventh capacitor C11, and a twelfth capacitor C12.

[0152] Meanwhile, as described above, the first level shifter LS1 is disposed in the active region AA, and thus, signal lines can be shared with a plurality of sub-pixel circuits SPC. That is, the first level shifter LS1 can share the first scan signal line, the second scan signal line, and the light emission signal line with the sub-pixel circuit SPC.

[0153] The eleventh transistor T11 to the seventeenth transistor T17 can be p-type thin film transistors. In the case of a p-type thin film transistor, the low-level voltage of each driving signal is the voltage that turns on the TFT, and the high-level voltage of each driving signal can be the voltage that turns off the TFT.

[0154] The eleventh transistor T11 includes a gate electrode connected to the first scan signal line, a source electrode connected to the second mode selection signal line, and a drain electrode connected to an eleventh node N11 that is a first electrode of the eleventh capacitor C11. Therefore, the eleventh transistor T11 can be turned on or off by the first scan signal SCAN1 to transmit the second mode selection signal MCS2 to the eleventh node N11 that is a first electrode of the eleventh capacitor C11.

[0155] The twelfth transistor T12 includes a gate electrode connected to the first scan signal line, a source electrode connected to the first mode selection signal line, and a drain electrode connected to a twelfth node N12 that is a second electrode of the eleventh capacitor C11. Therefore, the twelfth transistor T12 can be turned on or off by the first scan signal SCAN1 to transmit the first mode selection signal MCS1 to the twelfth node N12 that is a second electrode of the eleventh capacitor C11.

[0156] The thirteenth transistor T13 includes a gate electrode connected to the second scan signal line, a source electrode connected to the second mode selection signal line, and a drain electrode connected to the thirteenth node N13 which is the first electrode of the twelfth capacitor C12. Therefore, the thirteenth transistor T13 can be turned on or off by the second scan signal SCAN2 to transmit the second mode selection signal MCS2 to the thirteenth node N13 which is the first electrode of the twelfth capacitor C12.

[0157] The fourteenth transistor T14 includes a gate electrode connected to the first scan signal line, a source electrode connected to the first mode selection signal line, and a drain electrode connected to the fourteenth node N14 which is the second electrode of the twelfth capacitor C12. Therefore, the fourteenth transistor T14 can be turned on or off by the first scan signal SCAN1 to transmit the first mode selection signal MCS1 to the fourteenth node N14 which is the second electrode of the twelfth capacitor C12.

[0158] The fifteenth transistor T15 includes a gate electrode connected to the second scan signal line, a source electrode connected to the first mode selection signal line, and a drain electrode connected to the fifteenth node N15. Therefore, the fifteenth transistor T15 can be turned on or off by the second scan signal SCAN2 to transmit the first mode selection signal MCS1 to the fourteenth node N14 which is the second electrode of the twelfth capacitor C12.

[0159] The sixteenth transistor T16 includes a gate electrode connected to the light emission signal line, a source electrode connected to the reference line for transmitting the reference voltage Vref, and a drain electrode connected to the fifteenth node N15. Therefore, the sixteenth transistor T16 is turned on or off by the light emission signal EM to transmit the reference voltage Vref to the fourteenth node N14 which is the second electrode of the twelfth capacitor C12.

[0160] The seventeenth transistor T17 includes a gate electrode connected to the light emission signal line, a source electrode connected to the eleventh node N11 which is the first electrode of the eleventh capacitor C11, and a drain electrode connected to a plurality of sub-pixels SP. Therefore, the seventeenth transistor T17 is turned on or off by the light emission signal EM to transmit the first mode signal MS1 to the plurality of sub-pixels SP.

[0161] The eleventh capacitor C11 includes a first electrode connected to the eleventh node N11 and a second electrode connected to the twelfth node N12. The twelfth capacitor C12 includes a first electrode connected to the thirteenth node N13 and a second electrode connected to the fourteenth node N14. Meanwhile, the eleventh capacitor C11 and the twelfth capacitor C12 can be connected in series.

[0162] Figure 8It is a waveform diagram of a first level shifter circuit for describing a display device according to an exemplary embodiment of the present disclosure. Figure 9A It is a circuit diagram of a first level shifter of a display device according to an exemplary embodiment of the present disclosure during a first period in a wide viewing angle mode. Figure 9B It is a circuit diagram of a first level shifter of a display device according to an exemplary embodiment of the present disclosure during a second period in a wide viewing angle mode. Figure 9C It is a circuit diagram of a first level shifter of a display device according to an exemplary embodiment of the present disclosure during a third period in a wide viewing angle mode. Hereinafter, the voltage value corresponding to the first mode selection signal MCS1 may be referred to as a first voltage "V1", and the voltage value corresponding to the second mode selection signal MCA2 may be referred to as a second voltage "V2".

[0163] Refer to together Figure 8 and Figure 9A In the wide viewing angle mode, a low-level first scan signal SCAN1 and a low-level second mode selection signal MCS2 may be output during a first period TP1. Accordingly, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 may be turned on by the low-level first scan signal SCAN1.

[0164] The second voltage "V2" may be applied to the eleventh node N11 through the turned-on eleventh transistor T11. The first voltage "V1" may be applied to the twelfth node N12 through the turned-on twelfth transistor T12. The first voltage "V1" may be applied to the fourteenth node N14 through the turned-on fourteenth transistor T14.

[0165] Accordingly, during the first period TP1, the voltage of the eleventh node N11 may be "V2", and the voltages of the twelfth node N12 and the thirteenth node N13 may be "V1". In addition, the eleventh capacitor C11 may store "V2 - V1", which is the voltage difference between two electrodes, that is, the voltage difference between the eleventh node N11 and the twelfth node N12.

[0166] Next, refer to together Figure 8 and Figure 9B A low-level second scan signal SCAN2 and a low-level second mode selection signal MCS2 may be output during a second period TP2. Accordingly, the thirteenth transistor T13 and the fifteenth transistor T15 may be turned on by the low-level second scan signal SCAN2.

[0167] The second voltage "V2" may be applied to the thirteenth node N13 through the turned-on thirteenth transistor T13. The first voltage "V1" may be applied to the fifteenth node N15 through the turned-on fifteenth transistor T15.

[0168] In this case, since the twelfth node N12 and the thirteenth node N13 have the same voltage, the voltage of the twelfth node N12 can be "V2". In addition, the voltage of the eleventh node N11 is a value obtained by adding the voltage "V2 - V1" stored in the eleventh capacitor C11 to the voltage "V2" of the twelfth node N12. Therefore, the voltage of the eleventh node N11 can be "V2+(V2 - V1)". In addition, since the fourteenth node N14 and the fifteenth node N15 have the same voltage, the voltage of the fourteenth node N14 can be "V1". In addition, the twelfth capacitor C12 can store "V2 - V1", which is the voltage difference between the two electrodes, that is, the voltage difference between the thirteenth node N13 and the fourteenth node N14.

[0169] Finally, referring together to Figure 8 and Figure 9C , the low-level light-emitting signal EM and the low-level first mode selection signal MCS1 can be output during the third time period TP3. Therefore, the sixteenth transistor T16 and the seventeenth transistor T17 can be turned on by the low-level light-emitting signal EM.

[0170] The reference voltage Vref can be applied to the fifteenth node N15 through the turned-on sixteenth transistor T16. The first mode signal MS1 can be output to the plurality of sub-pixels SP through the turned-on seventeenth transistor T17.

[0171] In this case, since the fourteenth node N14 and the fifteenth node N15 have the same voltage, the voltage of the fourteenth node N14 can be "Vref". In addition, the voltage of the thirteenth node N13 is a value obtained by adding the voltage "V2 - V1" stored in the twelfth capacitor C12 to the voltage "Vref" of the fourteenth node N14. Therefore, the voltage of the thirteenth node N13 can be "V2+(Vref - V1)". In addition, since the twelfth node N12 and the thirteenth node N13 have the same voltage, the voltage of the twelfth node N12 can be "V2+(Vref - V1)". In addition, the voltage of the eleventh node N11 is a value obtained by adding the voltage "V2 - V1" stored in the eleventh capacitor C11 to the voltage "V2+(Vref - V1)" of the twelfth node N12. Therefore, the voltage of the eleventh node N11 can be "V2+(V2 - V1)+(Vref - V1)".

[0172] In this case, the first mode signal MS1 may be output through the seventeenth transistor T17 connected to the eleventh node N11. In other words, "V2+(V2-V1)+(Vref-V1)", which is the voltage of the eleventh node N11, may be the voltage value of the first mode signal MS1, and since the low-level first mode signal MS1 is a conduction signal, the second voltage value "V2" may be set to be less than the first voltage value "V1".

[0173] Figure 10 is a circuit diagram of a second level shifter of a display device according to an exemplary embodiment of the present disclosure.

[0174] Referring to Figure 10 , the second level shifter LS2 includes a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor T27, a twenty-first capacitor C21, and a twenty-second capacitor C22.

[0175] Meanwhile, since the second level shifter LS2 is disposed in the active region AA, signal lines can be shared with a plurality of sub-pixel circuits SPC. That is, the first level shifter LS1 can share the first scan signal line, the second scan signal line, and the light-emitting signal line of the display panel with the sub-pixel circuit SPC.

[0176] The twenty-first transistor T21 to the twenty-seventh transistor T27 may be p-type thin film transistors. In the case of p-type thin film transistors, the low-level voltage of each driving signal is the voltage that turns on the TFT, and the high-level voltage of each driving signal may be the voltage that turns off the TFT.

[0177] The twenty-first transistor T21 includes a gate electrode connected to the first scan signal line, a source electrode connected to the first mode selection signal line, and a drain electrode connected to the twenty-first node N21 which is the first electrode of the twenty-first capacitor C21. Therefore, the twenty-first transistor T21 can be turned on or off by the first scan signal SCAN1 to transmit the first mode selection signal MCS1 to the twenty-first node N21 which is the first electrode of the twenty-first capacitor C21.

[0178] The twenty-second transistor T22 includes a gate electrode connected to the first scan signal line, a source electrode connected to the second mode selection signal line, and a drain electrode connected to the twenty-second node N22 which is the second electrode of the twenty-first capacitor C21. Therefore, the twenty-second transistor T22 can be turned on or off by the first scan signal SCAN1 to transmit the second mode selection signal MCS2 to the twenty-second node N22 which is the second electrode of the twenty-first capacitor C21.

[0179] The twenty-third transistor T23 includes a gate electrode connected to the second scan signal line, a source electrode connected to the first mode selection signal line, and a drain electrode connected to the twenty-third node N23 which is the first electrode of the twenty-second capacitor C22. Therefore, the twenty-third transistor T23 can be turned on or off by the second scan signal SCAN2 to transmit the first mode selection signal MCS1 to the twenty-third node N23 which is the first electrode of the twenty-second capacitor C22.

[0180] The twenty-fourth transistor T24 includes a gate electrode connected to the first scan signal line, a source electrode connected to the second mode selection signal line, and a drain electrode connected to the twenty-fourth node N24 which is the second electrode of the twenty-second capacitor C22. Therefore, the twenty-fourth transistor T24 can be turned on or off by the first scan signal SCAN1 to transmit the second mode selection signal MCS2 to the twenty-fourth node N24 which is the second electrode of the twenty-second capacitor C22.

[0181] The twenty-fifth transistor T25 includes a gate electrode connected to the second scan signal line, a source electrode connected to the second mode selection signal line, and a drain electrode connected to the twenty-fifth node N25. Therefore, the twenty-fifth transistor T25 can be turned on or off by the second scan signal SCAN2 to transmit the second mode selection signal MCS2 to the twenty-fourth node N24 which is the second electrode of the twenty-second capacitor C22.

[0182] The twenty-sixth transistor T26 includes a gate electrode connected to the light emission signal line, a source electrode connected to the reference line that transmits the reference voltage Vref, and a drain electrode connected to the twenty-fifth node N25. Therefore, the twenty-sixth transistor T26 is turned on or off by the light emission signal EM to transmit the reference voltage Vref to the twenty-fourth node N24 which is the second electrode of the twenty-second capacitor C22.

[0183] The twenty-seventh transistor T27 includes a gate electrode connected to the light emission signal line, a source electrode connected to the twenty-first node N21, and a drain electrode connected to a plurality of sub-pixels SP. Therefore, the twenty-seventh transistor T27 is turned on or off by the light emission signal EM to transmit the second mode signal MS2 to the plurality of sub-pixels SP.

[0184] The twenty-first capacitor C21 includes a first electrode connected to the twenty-first node N21 and a second electrode connected to the twenty-second node N22. The twenty-second capacitor C22 includes a first electrode connected to the twenty-third node N23 and a second electrode connected to the twenty-fourth node N24. Meanwhile, the twenty-first capacitor C21 and the twenty-second capacitor C22 can be connected in series.

[0185] Figure 11 is a waveform diagram for describing a second level shift of a display device according to an exemplary embodiment of the present disclosure. Figure 12A is a circuit diagram of a second level shift of a display device according to an exemplary embodiment of the present disclosure during a first period in a narrow viewing angle mode. Figure 12B is a circuit diagram of a second level shift of a display device according to an exemplary embodiment of the present disclosure during a second period in a narrow viewing angle mode. Figure 12C is a circuit diagram of a second level shift of a display device according to an exemplary embodiment of the present disclosure during a third period in a narrow viewing angle mode. Hereinafter, a voltage value corresponding to a first mode selection signal MCS1 may be referred to as a first voltage “V1”, and a voltage value corresponding to a second mode selection signal MCS2 may be referred to as a second voltage “V2”.

[0186] Referring to Figure 11 and Figure 12A , in the narrow viewing angle mode, a low-level first scan signal SCAN1 and a low-level first mode selection signal MCS1 may be output during a first period TP1. Accordingly, a twenty-first transistor T21, a twenty-second transistor T22, and a twenty-fourth transistor T24 may be turned on by the low-level first scan signal SCAN1.

[0187] The first voltage “V1” may be applied to a twenty-first node N21 through the turned-on twenty-first transistor T21. The second voltage “V2” may be applied to a twenty-second node N22 through the turned-on twenty-second transistor T22. The second voltage “V2” may be applied to a twenty-fourth node N24 through the turned-on twenty-fourth transistor T24.

[0188] Next, referring to Figure 11 and Figure 12B , a low-level second scan signal SCAN2 and a low-level first mode selection signal MCS1 may be output during a second period TP2. Accordingly, a twenty-third transistor T23 and a twenty-fifth transistor T25 may be turned on by the low-level second scan signal SCAN2.

[0189] The first voltage “V1” may be applied to a twenty-third node N23 through the turned-on twenty-third transistor T23. The second voltage “V2” may be applied to a twenty-fifth node N25 through the turned-on twenty-fifth transistor T25.

[0190] In this case, since the twenty-second node N22 and the twenty-third node N23 have the same voltage, the voltage of the twenty-second node N22 can be "V1". In addition, the voltage of the twenty-first node N21 is a value obtained by adding the voltage "V1 - V2" stored in the twenty-first capacitor C21 to the voltage "V1" of the twenty-second node N22. Therefore, the voltage of the twenty-first node N21 can be "V1+(V1 - V2)". In addition, since the twenty-fourth node N24 and the twenty-fifth node N25 have the same voltage, the voltage of the twenty-fourth node N24 can be "V2". In addition, the twenty-second capacitor C22 can store "V1 - V2", which is the voltage difference between two electrodes, that is, the voltage difference between the twenty-third node N23 and the twenty-fourth node N24.

[0191] Finally, referring to Figure 11 and Figure 12C , the low-level light-emitting signal EM and the low-level second mode selection signal MCS2 can be output during the third time period TP3. Therefore, the twenty-sixth transistor T26 and the twenty-seventh transistor T27 can be turned on by the low-level light-emitting signal EM.

[0192] The reference voltage Vref can be applied to the twenty-fifth node N25 through the turned-on twenty-sixth transistor T26. The second mode signal MS2 can be output through the turned-on twenty-seventh transistor T27.

[0193] In this case, since the twenty-fourth node N24 and the twenty-fifth node N25 have the same voltage, the voltage of the twenty-fourth node N24 can be "Vref". In addition, the voltage of the twenty-third node N23 is a value obtained by adding the voltage "V1 - V2" stored in the twenty-second capacitor C22 to the voltage "Vref" of the twenty-fourth node N24. Therefore, the voltage of the twenty-third node N23 can be "V1+(Vref - V2)". In addition, since the twenty-second node N22 and the twenty-third node N23 have the same voltage, the voltage of the twenty-second node N22 can be "V1+(Vref - V2)". In addition, the voltage of the twenty-first node N21 is a value obtained by adding the voltage "V1 - V2" stored in the twenty-first capacitor C21 to the voltage "V1+(Vref - V2)" of the twenty-second node N22. Therefore, the voltage of the twenty-first node N21 can be "V1+(V1 - V2)+(Vref - V2)".

[0194] In this case, the second mode signal MS2 can be output through the twenty-seventh transistor T27 connected to the twenty-first node N21. In other words, “V1+(V1-V2)+(Vref-V2)”, which is the voltage of the twenty-first node N21, can be the voltage value of the second mode signal MS2, and since the low-level second mode signal MS2 is a turn-on signal, the first voltage value “V1” can be set to be less than the second voltage value “V2”.

[0195] Meanwhile, in order to implement various viewing angles, the display device can be driven by dividing each region into a wide viewing angle mode or a narrow viewing angle mode. Generally, a control signal can be output from a mode control unit that controls the operation of the wide viewing angle mode or the narrow viewing angle mode, and can be changed to a desired voltage through level shifting and transmitted to the display panel. This is because the voltage generally output from the mode control unit is a low voltage of about 1.8V or 3.3V, while the voltage of the control signal used in the display panel is a high voltage, such as a VGH voltage of 10.0V or greater and a VGL voltage of -9.0V or less. That is, since there is a difference between the voltage output from the mode control unit and the voltage used in the display panel, a separate IC for level shifting is required to change the low control voltage to a high control voltage. In this case, due to the use of a separate IC, the manufacturing cost increases, or the bezel increases to ensure space for setting the IC for level shifting. In addition, since the output channels of one IC for level shifting are limited, one or more ICs for level shifting may be required to implement various viewing angles. In this case, there is a problem that the wire routing becomes complicated due to additional wire connections.

[0196] Therefore, in the display device 100 according to the exemplary embodiment of the present specification, the level shifter LS is provided in the active area AA. That is, since there is no need to provide a separate IC for level shifting on the flexible film (COF), the manufacturing cost can be reduced. In addition, since there is no need to ensure space in the non-active area NA for setting wires connecting the separate IC and the display panel PN, the area of the non-active area NA can be minimized. In other words, a narrow bezel can be achieved.

[0197] In addition, in the display device 100 according to an exemplary embodiment of the present disclosure, the level shifter LS may share the first scan signal line, the second scan signal line, and the light emission signal line provided on the display panel PN with the sub-pixel circuit SPC. Accordingly, an increase in the bezel due to the additional line setting may be minimized, and the design complexity due to the additional line setting may be minimized. In addition, the number of level shifters LS provided in the active area AA and the lines added to drive the level shifter LS may be minimized, and by providing the level shifter LS in the active area AA, the area to be ensured in the active area AA may also be minimized.

[0198] In addition, in the display device 100 according to an exemplary embodiment of the present disclosure, the level shifter LS includes a first level shifter LS1 that transmits the first mode signal MS1 and a second level shifter LS2 that transmits the second mode signal MS2. In this case, the first level shifter LS1 and the second level shifter LS2 are provided for each of the plurality of divided areas a of the active area AA. Accordingly, in the display device 100 according to an exemplary embodiment of the present disclosure, the wide viewing angle mode and the narrow viewing angle mode may be independently controlled for each of the plurality of areas a. That is, in the display device 100 according to an exemplary embodiment of the present disclosure, the level shifter LS may be provided for each area of the sub-pixel SP, and thus the viewing angle may be freely and selectively restricted for each of the plurality of areas. That is, in the display device 100 according to an exemplary embodiment of the present disclosure, the viewing angle may be selectively restricted by selectively and freely switching only a specific area of the screen to the wide viewing angle mode or the narrow viewing angle mode, and the driving area may be changed between the wide viewing angle mode and the narrow viewing angle mode.

[0199] An exemplary embodiment of the present disclosure may also be described as follows:

[0200] According to an aspect of the present disclosure, there is provided a display device. The display device includes: a display panel including an active area in which a plurality of sub-pixels are provided and a non-active area surrounding the active area; and a plurality of level shifters provided in the active area and transmitting mode signals to drive the plurality of sub-pixels in a first mode or a second mode. Each of the plurality of sub-pixels includes: a first light emitting element; a first optical member that refracts light from the first light emitting element; a second light emitting element; and a second optical member that refracts light from the second light emitting element and has a shape different from that of the first optical member.

[0201] Multiple voltage level shifters may include: multiple first voltage level shifters that transmit a first mode signal and multiple second voltage level shifters that transmit a second mode signal. The active region may include multiple regions divided in a row or column direction. The multiple first voltage level shifters and the multiple second voltage level shifters may be respectively arranged one by one for each of the multiple regions.

[0202] The multiple voltage level shifters transmit mode signals for each of the multiple regions.

[0203] The multiple sub-pixels may include multiple sub-pixel circuits. The first voltage level shifter and the second voltage level shifter may share signal lines with the multiple sub-pixel circuits.

[0204] The display panel may include a first scan signal line, a second scan signal line, and a light-emitting signal line. Each of the multiple sub-pixel circuits may include: a driving transistor; a first transistor that applies a data voltage to a capacitor; a second transistor that diode-connects the gate electrode and the drain electrode of the driving transistor; a third transistor that applies a reference voltage to the capacitor; a fourth transistor that forms a current path between the driving transistor and a first light-emitting element; a fifth transistor that applies a reference voltage to the anode electrode of the first light-emitting element; a sixth transistor that applies a reference voltage to the anode electrode of a second light-emitting element; a seventh transistor that forms a current path between the driving transistor and the second light-emitting element; and an eighth transistor that connects the driving transistor, the fourth transistor, and the seventh transistor.

[0205] In the first mode, the fourth transistor may be turned on and the seventh transistor may be turned off. In the second mode, the fourth transistor may be turned off and the seventh transistor may be turned on.

[0206] The first voltage level shifter circuit may include a first capacitor; a second capacitor connected in series with the first capacitor; a first transistor connected to the first scan signal line and transmitting a second mode selection signal to a first electrode of the first capacitor; a second transistor connected to the first scan signal line and transmitting a first mode selection signal to a second electrode of the first capacitor; a third transistor connected to the second scan signal line and transmitting a second mode selection signal to a first electrode of the second capacitor; a fourth transistor connected to the first scan signal line and transmitting a first mode selection signal to a second electrode of the second capacitor; a fifth transistor connected to the second scan signal line and transmitting a first mode selection signal to the second electrode of the second capacitor; a sixth transistor connected to the light-emitting signal line and transmitting a reference voltage to the second electrode of the second capacitor; and a seventh transistor connected to the light-emitting signal line and outputting a first mode signal.

[0207] The first level shift circuit can be driven separately for a first period, a second period, and a third period. During the first period, the first scan signal and the second mode selection signal can be conduction signals. During the second period, the second scan signal and the second mode selection signal can be conduction signals. During the third period, the light emission signal and the first mode selection signal can be conduction signals.

[0208] The second level shift circuit may include: a first transistor connected to the first scan signal line and transmitting the first mode selection signal to a first electrode of a first capacitor; a second transistor connected to the first scan signal line and transmitting the second mode selection signal to a second electrode of the first capacitor; a third transistor connected to the second scan signal line and transmitting the first mode selection signal to a first electrode of a second capacitor; a fourth transistor connected to the first scan signal line and transmitting the second mode selection signal to a second electrode of the second capacitor; a fifth transistor connected to the second scan signal line and transmitting the second mode selection signal to the second electrode of the second capacitor; a sixth transistor connected to the light emission signal line and transmitting a reference voltage to the second electrode of the second capacitor; and a seventh transistor connected to the light emission signal line and outputting a second mode signal.

[0209] The second level shift circuit can be driven separately for a first period, a second period, and a third period. During the first period, the first scan signal and the first mode selection signal can be conduction signals. During the second period, the second scan signal and the first mode selection signal can be conduction signals. During the third period, the light emission signal and the second mode selection signal can be conduction signals.

[0210] The display device may further include a plurality of mode control units provided in non-active regions. The display panel may include: a first mode selection signal line extending in a row or column direction in a plurality of regions and connected to the mode control unit to transmit first mode selection information to a plurality of sub-pixels; and a second mode selection signal line extending in a row or column direction in a plurality of regions and connected to the mode control unit to transmit a second mode selection signal to a plurality of sub-pixels.

[0211] The display panel may include a driving transistor and first to eighth transistors. Each of the plurality of sub-pixels may be driven respectively for an initial period, a sampling period, a holding period, and a light-emitting period. During the initial period, the voltage of the gate electrode of the driving transistor is initialized. During the sampling period, the threshold voltage of the driving transistor is sampled. The anode electrodes of the first light-emitting element and the second light-emitting element are respectively initialized. During the holding period, the first to eighth transistors are turned off. During the light-emitting period, a driving current is applied to each of the first light-emitting element and the second light-emitting element so that each of the first light-emitting element and the second light-emitting element emits light.

[0212] In the first mode, the first light-emitting element emits light, and the light from the first light-emitting element may be output at a viewing angle restricted in a first direction and a second direction by a first optical member. In the second mode, the second light-emitting element emits light, and the light from the second light-emitting element may be output at a viewing angle restricted only in the first direction by a second optical member.

[0213] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising an active area in which a plurality of sub-pixels are arranged and an inactive area surrounding the active area; as well as a plurality of level shift circuits disposed in the active region and transmitting a mode signal to drive the plurality of sub-pixels in a first mode or a second mode, Wherein, each sub-pixel of the plurality of sub-pixels comprises: a first light emitting element; a first optical member that refracts light from the first light emitting element; a second light emitting element; and A second optical member that refracts light from the second light emitting element and has a shape different from that of the first optical member.

2. The display device according to claim 1, wherein: The plurality of level shifting circuits include: a plurality of first level shift circuits for transmitting first mode signals; and a plurality of second level shift circuits for transmitting second mode signals, and Wherein, the active area includes: a plurality of areas divided in a row or column direction; and The plurality of first level shift circuits and the plurality of second level shift circuits are each provided one by one for each of the plurality of regions.

3. The display device according to claim 2, wherein: The plurality of first level shift circuits and the plurality of second level shift circuits transmit a corresponding mode signal for each of the plurality of regions.

4. The display device according to claim 2, wherein: For the plurality of sub-pixels, a plurality of sub-pixel circuits are provided, and The first level shift circuit and the second level shift circuit share a signal line with the plurality of sub-pixel circuits.

5. The display device according to claim 4, wherein: The display panel includes a first scanning signal line, a second scanning signal line and a light emitting signal line, and Each of the plurality of sub-pixel circuits comprises: Driver transistor; a first transistor that applies a data voltage to the capacitor; a second transistor having a diode connected to the gate electrode and the drain electrode of the driving transistor; a third transistor that applies a reference voltage to the capacitor; a fourth transistor forming a current path between the driving transistor and the first light emitting element; a fifth transistor that applies the reference voltage to the anode electrode of the first light emitting element; a sixth transistor that applies the reference voltage to an anode electrode of the second light emitting element; a seventh transistor forming a current path between the driving transistor and the second light emitting element; and An eighth transistor is connected to the driving transistor, the fourth transistor and the seventh transistor.

6. The display device according to claim 5, wherein: In the first mode, the fourth transistor is turned on and the seventh transistor is turned off, and In the second mode, the fourth transistor is turned off and the seventh transistor is turned on.

7. The display device according to claim 5, wherein: The first level shift circuit comprises: a first capacitor; a second capacitor connected in series with the first capacitor; a first transistor connected to the first scan signal line and transmitting a second mode selection signal to a first electrode of the first capacitor; a second transistor connected to the first scan signal line and transmitting a first mode selection signal to a second electrode of the first capacitor; a third transistor connected to the second scan signal line and transmitting the second mode selection signal to the first electrode of the second capacitor; a fourth transistor connected to the first scan signal line and transmitting the first mode selection signal to the second electrode of the second capacitor; a fifth transistor connected to the second scan signal line and transmitting the first mode selection signal to the second electrode of the second capacitor; a sixth transistor connected to the light emitting signal line and transmitting the reference voltage to the second electrode of the second capacitor; and A seventh transistor is connected to the light emitting signal line and outputs the first mode signal.

8. The display device according to claim 7, wherein: The first level shift circuit is driven into a first period, a second period and a third period respectively, During the first period, the first scan signal and the second mode selection signal are on signals, During the second period, the second scan signal and the second mode selection signal are the on signals, and During the third period, the light emitting signal and the first mode selection signal are the turn-on signals.

9. The display device according to claim 5, wherein: The second level shift circuit comprises: a first transistor connected to the first scan signal line and transmitting a first mode selection signal to a first electrode of a first capacitor; a second transistor connected to the first scan signal line and transmitting a second mode selection signal to a second electrode of the first capacitor; a third transistor connected to the second scan signal line and transmitting the first mode selection signal to the first electrode of the second capacitor; a fourth transistor connected to the first scan signal line and transmitting the second mode selection signal to the second electrode of the second capacitor; a fifth transistor connected to the second scan signal line and transmitting the second mode selection signal to the second electrode of the second capacitor; a sixth transistor connected to the light emitting signal line and transmitting the reference voltage to the second electrode of the second capacitor; and A seventh transistor is connected to the light emitting signal line and outputs the second mode signal.

10. The display device according to claim 9, wherein: The second level shift circuit is driven into a first period, a second period and a third period respectively, During the first period, the first scan signal and the first mode selection signal are on signals, During the second period, the second scan signal and the first mode selection signal are the on signals, and During the third period, the light emitting signal and the second mode selection signal are the turn-on signals.

11. The display device according to claim 2, further comprising: a plurality of mode control units disposed in the inactive region, Wherein, the display panel comprises: a first mode selection signal line extending in a row or column direction in the plurality of regions and connected to the mode control unit to transmit a first mode selection signal to the plurality of sub-pixels; and The second mode selection signal lines extend in the row or column direction in the plurality of regions and are connected to the mode control unit to transmit a second mode selection signal to the plurality of sub-pixels.

12. The display device according to claim 1, wherein: The display panel includes a driving transistor and first to eighth transistors, Each of the plurality of sub-pixels is driven into an initial period, a sampling period, a holding period, and a light emitting period, respectively. During the initial period, the voltage of the gate electrode of the driving transistor is initialized, and the anode electrode of the first light emitting element and the anode electrode of the second light emitting element are respectively initialized, During the sampling period, sampling the threshold voltage of the driving transistor, During the holding period, the first to eighth transistors are turned off, and During the light emission period, a driving current is applied to each of the first light emitting element and the second light emitting element, so that each of the first light emitting element and the second light emitting element emits light.

13. The display device according to claim 1, wherein: In the first mode, the first light emitting element emits light, and the light from the first light emitting element is output at a viewing angle limited in a first direction and a second direction by the first optical member, and In the second mode, the second light emitting element emits light, and the light from the second light emitting element is output at a viewing angle limited only in the first direction by the second optical member.

14. The display device according to claim 2, wherein: The plurality of first level shift circuits and the plurality of second level shift circuits are each configured in the same number as the plurality of regions.

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