Pixel circuit and display device

Abstract

The invention discloses a pixel circuit and a display device. The display device may include a plurality of sub-pixels, wherein each of the plurality of sub-pixels includes: a light emitting element; a driving transistor configured to operate the light emitting element by receiving a data voltage; and a switching transistor configured to apply the data voltage to a gate of the driving transistor, in which the light emitting element includes a cathode and an anode, in which the anode is connected to a source of the driving transistor, in which the cathode is electrically connected to a low-potential voltage supply line, and in which the anode is electrically connected to the gate of the driving transistor. Wherein the low potential voltage supply line supplies a low potential voltage to the light emitting element, and wherein an intermediate electrode line across the storage capacitor of the plurality of sub-pixels constitutes a first parasitic capacitor with a gate electrode of the driving transistor and constitutes a second parasitic capacitor with a source electrode of the driving transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0195717, filed on December 28, 2023, which is hereby incorporated by reference in its entirety into this application. Technical field

[0003] The present invention relates to a display device. Background art

[0004] With the official entry into the information age, the display field for visually presenting electrical information signals has developed rapidly. Therefore, various display devices with thin thickness, light weight, and excellent performance such as low power consumption have been developed. Examples of display devices may include liquid crystal display (LCD) devices, organic light - emitting display (OLED) devices, etc.

[0005] A display device may include a driving circuit, such as: a data driver configured to provide a data signal to a display panel having a pixel array on which a display image is disposed and to a data line disposed on the display panel; a gate driver configured to sequentially provide a gate signal to gate lines disposed in a display area; and a timing controller configured to control the data driver and the gate driver. Summary of the invention

[0006] One object to be achieved by the present invention is to provide a display device that reduces the channel length increased due to the demand for low - current operation.

[0007] The object of the present invention is not limited to the above object, and other objects not mentioned above can be clearly understood by those of ordinary skill in the art according to the following description.

[0008] To achieve the above object, a display device according to an embodiment of the present invention may include a plurality of sub - pixels, wherein each of the plurality of sub - pixels includes: a light - emitting element; a driving transistor configured to operate the light - emitting element by receiving a data voltage; and a switching transistor configured to apply the data voltage to the gate of the driving transistor, wherein the light - emitting element includes a cathode and an anode, the anode is connected to the source of the driving transistor, the cathode is electrically connected to a low - potential voltage supply line, wherein the low - potential voltage supply line provides a low - potential voltage to the light - emitting element, and wherein an intermediate electrode line of a storage capacitor across the plurality of sub - pixels forms a first parasitic capacitor with the gate of the driving transistor and a second parasitic capacitor with the source of the driving transistor.

[0009] A pixel circuit according to an embodiment of the present invention may include: a light-emitting element; a driving transistor configured to operate the light-emitting element by receiving a data voltage; and a switching transistor configured to apply the data voltage to a gate of the driving transistor, wherein the light-emitting element includes a cathode and an anode, wherein the anode is connected to a source of the driving transistor, wherein the cathode is connected to a low-potential voltage supply line, wherein the low-potential voltage supply line supplies a low-potential voltage to the light-emitting element, and wherein an intermediate electrode line across a storage capacitor and the gate of the driving transistor form a first parasitic capacitor and form a second parasitic capacitor with the source of the driving transistor.

[0010] Other specific details of the exemplary embodiments are included in the detailed description and the drawings.

[0011] According to the present invention, the channel length increased due to the requirement for low-current operation can be reduced, whereby the low-gray-scale FOS (front of screen) quality can be improved.

[0012] In addition, according to the present invention, a separate capacitor for causing a boosting loss in the storage capacitor can be formed, which can cause low-current operation and reduce the requirement for increasing the channel length of the driving transistor.

[0013] The effects according to the present invention are not limited to those illustrated above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features, and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. In the drawings:

[0015] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention;

[0016] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention;

[0017] Figure 3 is a view schematically illustrating a planar structure of a display device according to an embodiment of the present invention;

[0018] Figure 4 is a diagram illustrating a cross-section taken along line A-A' of a display device according to an embodiment of the present invention; Figure 3 of the display device;

[0019] Figure 5 is a circuit diagram of a sub-pixel of a display device according to another embodiment of the present invention;

[0020] Figure 6It is a circuit diagram of a sub-pixel of a display device according to another embodiment of the present invention;

[0021] Figure 7 It is a circuit diagram of a sub-pixel of a display device according to another embodiment of the present invention;

[0022] Figure 8 It is a graph illustrating the effect of propulsion loss. Detailed Embodiments

[0023] The advantages and features of the present invention and the methods for realizing these advantages and features will be clear by referring to the exemplary embodiments described below in detail together with the accompanying Figure 1 drawings. However, the present invention is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present invention and the scope of the present invention.

[0024] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present invention are only examples, and the present invention is not limited thereto. Similar reference numerals generally denote similar elements throughout the application. In addition, in the following description of the present invention, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention. Terms such as "comprising", "having", and "including" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any singular reference may include the plural, unless otherwise expressly stated.

[0025] Even if not explicitly stated, components are interpreted as including ordinary error ranges.

[0026] When describing the positional relationship between two parts using terms such as "on", "above", "below", and "after", one or more parts may be placed between these two parts, unless these terms are used together with the terms "immediately" or "directly".

[0027] When an element or layer is disposed "on" another element or layer, it may be directly on the other element or layer, or other layers or other elements may be interposed therebetween.

[0028] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the technical concept of the present invention, the first component mentioned below may be the second component.

[0029] The same reference numerals generally denote the same elements throughout the application.

[0030] For convenience of description, the dimensions and thicknesses of each component shown in the drawings are illustrated, and the present invention is not limited to the dimensions and thicknesses of the illustrated components.

[0031] The features of the embodiments of the present invention may be partially or wholly combined or combined with each other, and may be interlocked and operated in various ways technically. The embodiments may be implemented independently of each other or implemented in relation to each other.

[0032] The transistor for a display device according to an embodiment of the present invention may be implemented as either an n-channel transistor (NMOS) or a p-channel transistor (PMOS). The transistor may be implemented as an oxide semiconductor transistor having an active layer made of an oxide semiconductor or a low-temperature polycrystalline silicon (LTPS) transistor having an active layer made of low-temperature polycrystalline silicon (LTPS). The transistor may include at least a gate, a source, and a drain. The transistor may be implemented as a thin-film transistor (TFT) on a display panel. In the transistor, carriers flow from the source to the drain. Since the carriers are electrons in an n-channel transistor (NMOS), the source voltage may be lower than the drain voltage, so that electrons flow from the source to the drain. In an n-channel transistor (NMOS), current may flow from the drain to the source, and the source may be an output terminal. Since the carriers are positive holes in a p-channel transistor (PMOS), the source voltage may be higher than the drain voltage, so that positive holes flow from the source to the drain. Since positive holes flow from the source to the drain in a p-channel transistor (PMOS), current may flow from the source to the drain, and the drain may be an output terminal. Therefore, it should be noted that the source and drain of the transistor are not fixed because the source and drain may vary according to the applied voltage. The present specification has been described assuming that the transistor is an n-channel transistor (NMOS). However, the present invention is not limited thereto. A p-channel transistor may be used as the transistor. Accordingly, the circuit configuration may be changed.

[0033] The gate signal of the transistor used as a switching element may swing between a gate-on voltage and a gate-off voltage. The gate-on voltage may be set to a voltage higher than the threshold voltage Vth of the transistor. The gate-off voltage may be set to a voltage lower than the threshold voltage Vth of the transistor. The transistor may be turned on in response to the gate-on voltage. In contrast, the transistor may be turned off in response to the gate-off voltage. In the case of an n-channel transistor (NMOS), the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of a p-channel transistor (PMOS), the gate-on voltage may be a gate low voltage (VGL), and the gate-off voltage may be a gate high voltage (VGH).

[0034] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention.

[0036] Referring to Figure 1 , the display device 100 includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

[0037] The display panel 110 is a panel configured to display an image. The display panel 110 may include various circuits, lines, and light-emitting elements disposed on a substrate. The display panel 110 may include a plurality of pixels PX defined by a plurality of data lines DL and a plurality of gate lines GL that cross each other. The plurality of pixels PX are connected to the plurality of data lines DL and the plurality of gate lines GL. The display panel 110 may include a display area defined by the plurality of pixels PX and a non-display area in which various types of signal lines or various pads are formed. The display panel 110 may be implemented as a display panel 110 for various display devices such as a liquid crystal display device, an organic light-emitting display device, and an electrophoretic display device. Hereinafter, the structure of the display panel 110 that is a panel for an organic light-emitting display device will be described. However, the present invention is not limited thereto.

[0038] The timing controller 140 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock signal via a receiving circuit such as an LVDS or TMDS interface connected to a host system. Based on the input timing signals, the timing controller 140 generates timing control signals for controlling the data driver 130 and the gate driver 120.

[0039] The data driver 130 provides a data voltage DATA to a plurality of sub-pixels SP (see Figure 2 ). The data driver 130 may include a plurality of source driver integrated circuits (ICs). The plurality of source driver ICs may receive digital video data and source timing control signals from the timing controller 140. The plurality of source driver ICs may generate the data voltage DATA by converting the digital video data into a gamma voltage in response to the source timing control signals, and provide the data voltage DATA via the data lines DL of the display panel 110. The plurality of source driver ICs may be connected to the data lines DL of the display panel 110 by a chip-on-glass (COG) process or a tape automated bonding (TAB) process. In addition, the source driver ICs may be formed on the display panel 110 or a separate printed circuit board (PCB) substrate and connected to the display panel 110.

[0040] The gate driver 120 provides gate signals to a plurality of sub-pixels SP. The gate driver 120 may include a level shifter and a shift register. The level shifter may shift the level of a clock signal input from the timing controller 140 at a transistor-transistor logic (TTL) level and provide the shifted clock signal to the shift register. The shift register may be formed in a non-display area of the display panel 110 by a gate-in-panel (GIP) method. However, the present invention is not limited thereto. The shift register may include a plurality of stages configured to shift the gate signal to correspond to the clock signal and the driving signal and output the gate signal. The plurality of stages included in the shift register may sequentially output the gate signal via a plurality of output terminals.

[0041] The display panel 110 may include a plurality of sub-pixels SP. The plurality of sub-pixels SP may be sub-pixels SP that emit light beams of different colors. For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. However, the present invention is not limited thereto. The plurality of sub-pixels SP may constitute a pixel PX. A group of a plurality of sub-pixels may constitute one pixel. That is, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel may constitute a single pixel PX. The display panel 110 may include a plurality of pixels PX.

[0042] Hereinafter, with reference to Figure 2 A driving circuit for operating one sub-pixel SP will be described in more detail.

[0043] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention.

[0044] With reference to Figure 2 , the sub-pixel SP may include a switching transistor SWT, a sensing transistor SET, a driving transistor DT, and a light-emitting element EL.

[0045] The light-emitting element EL may include an anode, an organic layer, and a cathode. The organic layer may include various organic layers such as a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. The anode of the light-emitting element EL may be connected to the source electrode that is an output terminal of the driving transistor DT, and a low-potential voltage VSS may be applied to the cathode. Figure 2 It is illustrated that the light-emitting element EL is an organic light-emitting element EL. However, the present invention is not limited thereto. An inorganic light-emitting diode, that is, an LED may also be used as the light-emitting element EL.

[0046] The switching transistor SWT is a transistor for transmitting a data voltage DATA to a first node N1 corresponding to the gate of the driving transistor DT. The switching transistor SWT may include a drain connected to a data line DL, a gate connected to a gate line GL, and a source connected to the gate of the driving transistor DT. The switching transistor SWT may be turned on in response to a scan signal SCAN applied from the gate line GL and transmit the data voltage DATA provided from the data line DL to the first node N1 corresponding to the gate of the driving transistor DT.

[0047] The driving transistor DT is a transistor for operating the light-emitting element EL by supplying a driving current to the light-emitting element EL. The driving transistor DT may include a gate corresponding to the first node N1, a source corresponding to the second node N2 and an output terminal, and a drain corresponding to the third node N3 and an input terminal. The gate of the driving transistor DT may be connected to the switching transistor SWT. The drain may receive a high potential voltage VDD via a high potential voltage supply line VDDL. The source may be connected to the anode of the light-emitting element EL.

[0048] According to an embodiment of the present invention, the sub-pixel SP may include a plurality of capacitors connected to the driving transistor DT. The plurality of capacitors may include a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0049] The first capacitor C1 may be formed between the gate and the source of the driving transistor DT. Specifically, the first capacitor C1 may be connected between the first node N1 connected to the gate of the driving transistor DT and the second node N2 connected to the source of the driving transistor DT. The first capacitor C1 may be a storage capacitor located between the gate and the source of the driving transistor DT.

[0050] The second capacitor C2 may be formed between the first node N1 connected to the gate of the driving transistor DT and a fourth node N4 configured to receive a low potential voltage VSS. The fourth node N4 may be specified by an intermediate electrode line SD (see Figure 3 ). The intermediate electrode line SD may be connected to a low potential voltage supply line VSSL and serve as the fourth node N4 in the storage capacitor region.

[0051] In addition, the third capacitor C3 may be formed between the second node N2 connected to the source of the driving transistor DT and the fourth node N4 configured to receive a low potential voltage VSS.

[0052] According to an embodiment, the second capacitor C2 and the third capacitor C3 may be parasitic capacitors. One end of the second capacitor C2 and one end of the third capacitor C3 may be the intermediate electrode line SD. The other end of the second capacitor C2 may be one end of the first capacitor C1, and the other end of the third capacitor C3 may be the other end of the first capacitor C1 (seeFigure 4 )。

[0053] In the case of the display device 100, the driving transistor DT may deteriorate as the operation time of each sub-pixel SP increases. Accordingly, the inherent characteristic values of the driving transistor DT may change. In this case, the inherent characteristic values of the circuit elements may include the threshold voltage Vth of the driving transistor DT, the mobility α of the driving transistor DT, and the like. The change in the characteristic values of the circuit elements may cause a change in the luminance of the corresponding sub-pixel SP. Accordingly, the change in the characteristic values of the circuit elements may be used as the same concept as the change in the luminance of the sub-pixel SP.

[0054] In addition, the degree of change in the characteristic values between the circuit elements of each sub-pixel SP may vary according to the difference in the degree of deterioration between the circuit elements. The difference in the degree of change in the characteristic values between the circuit elements may cause a luminance deviation between the sub-pixels SP. Accordingly, the deviation in the characteristic values between the circuit elements may be used as the same concept as the luminance deviation between the sub-pixels SP. The change in the characteristic values of the circuit elements (i.e., the deviation between the changes in the luminance of the sub-pixels SP) and the characteristic values between the circuit elements (i.e., the luminance deviation between the sub-pixels SP) may cause problems such as deterioration in the luminance display accuracy of the sub-pixels SP or screen abnormalities.

[0055] A sensing function for sensing the characteristic values of the sub-pixel SP and a compensation function for compensating the characteristic values of the sub-pixel SP using the sensing result may be provided to the sub-pixel SP of the display device 100 according to an embodiment of the present invention.

[0056] Referring to Figure 2 , in addition to the switching transistor SWT, the driving transistor DT, and the light-emitting element EL, the sub-pixel SP may further include a sensing transistor SET for selectively controlling the voltage state of the source of the driving transistor DT.

[0057] The sensing transistor SET may be connected between the source of the driving transistor DT and a reference voltage line RVL configured to provide a reference voltage VREF, and the gate is connected to a gate line GL. Accordingly, the sensing transistor SET may be turned on in response to a sensing signal SENSE applied via the gate line GL, and apply the reference voltage VREF provided via the reference voltage line RVL to the source of the driving transistor DT. In addition, the sensing transistor SET may be used as one of the voltage sensing paths of the source of the driving transistor DT.

[0058] According to an embodiment, the switching transistor SWT and the sensing transistor SET of the sub-pixel SP may share a single gate line GL. That is, the switching transistor SWT and the sensing transistor SET may be connected to the same gate line GL and receive the same gate signal (e.g., a scan signal SCAN or a sense signal SENSE). However, for ease of description, the voltage applied to the gate of the switching transistor SWT is referred to as the scan signal SCAN, and the voltage applied to the gate of the sensing transistor SET is referred to as the sense signal SENSE. However, the scan signal SCAN and the sense signal SENSE applied to a single sub-pixel SP are the same signal transmitted from the same gate line GL.

[0059] According to another embodiment, the switching transistor SWT may be connected to the gate line GL, and the sensing transistor SET may be connected to a separate sensing line (not shown). The scan signal SCAN may be applied to the switching transistor SWT via the gate line GL. The sense signal SENSE may be applied to the sensing transistor SET via the sensing line.

[0060] The reference voltage VREF is applied to the source of the driving transistor DT via the sensing transistor SET. A voltage for sensing the threshold voltage Vth of the driving transistor DT or the mobility α of the driving transistor DT is detected via the reference voltage line RVL. The data driver 130 ( Figure 1 the data driver 130 in) may compensate the data voltage DATA according to the detected change amount of the threshold voltage Vth of the driving transistor DT or the detected change amount of the mobility α of the driving transistor DT.

[0061] Figure 3 is a view schematically illustrating a planar structure of a display device according to an embodiment of the present invention.

[0062] Figure 4 is a view illustrating a cross-section taken along the line Figure 3 A-A' according to an embodiment of the present invention.

[0063] Figure 3 Illustrates that one sub-pixel has a 3T3C structure, which includes a switching transistor SWT, a driving transistor DT, a sensing transistor SET, and a plurality of capacitors C1, C2, and C3. However, according to an embodiment of the present invention, transistors for supporting additional initialization operations or internal / external compensation may be further provided. In addition, Figure 3 exemplarily illustrates a planar structure of three sub-pixels. In addition, Figure 4 illustrates Figure 3 as an example, a cross-sectional structure of a plurality of capacitors C1, C2, and C3 of a display device according to an embodiment of the present invention shown in

[0064] Referring to Figure 3, in the display device according to an embodiment of the present invention, a pixel may include a plurality of sub-pixels. The plurality of sub-pixels may include a high-potential voltage supply line VDDL, a low-potential voltage supply line VSSL, a reference voltage line RVL, a gate line GL, and a data line DL. The plurality of sub-pixels may include the plurality of capacitors C1, C2, and C3, the plurality of transistors (e.g., a driving transistor DT, a switching transistor SWT, and a sensing transistor SET) and a light-emitting element EL described above with reference to Figure 2 . For ease of description, Figure 3 components corresponding to the light-emitting element EL are not shown.

[0065] With reference to Figure 3 , the first to third sub-pixels SP1, SP2, and SP3 may receive a data voltage DATA from the first to third data lines DL1, DL2, and DL3, and receive at least one of a scan signal SCAN and a sense signal SENSE from the gate line GL. The scan signal SCAN and the sense signal SENSE may be provided to the switching transistor SWT and the sensing transistor SET through a single gate line GL corresponding to the scan signal SCAN and the sense signal SENSE, respectively. However, the scan signal SCAN and the sense signal SENSE may be provided separately through two separate lines (e.g., a gate line and a sense line).

[0066] The first to third data lines DL1, DL2, and DL3 may be disposed substantially parallel to the reference voltage line RVL, the high-potential voltage supply line VDDL, and the low-potential voltage supply line VSSL. The first to third data lines DL1, DL2, and DL3 may cross the gate line GL while defining a predetermined angle (e.g., a right angle or an acute angle of 90° or less). A pixel region of the sub-pixel may be defined by the first to third data lines DL1, DL2, and DL3 and the gate line GL that cross each other.

[0067] The reference voltage line RVL may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2. The reference voltage line RVL may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 and provide a reference voltage VREF to the sensing transistors SET of the first sub-pixel SP1 and the second sub-pixel SP2.

[0068] Different from the first sub-pixel SP1 and the second sub-pixel SP2, the third sub-pixel SP3 is disposed at a distance corresponding to the size of one sub-pixel from the reference voltage line RVL. Therefore, the reference voltage line RVL may provide the reference voltage VREF to the sensing transistor SET of the third sub-pixel SP3 via a jumper wire.

[0069] Since the reference voltage line RVL is disposed between the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 for the first sub-pixel SP1 can be disposed on the left side of the first sub-pixel SP1, and the second data line DL2 for the second sub-pixel SP2 can be disposed on the right side of the second sub-pixel SP2. In other words, the first sub-pixel SP1 can be disposed between the first data line DL1 and the reference voltage line RVL, and the second sub-pixel SP2 can be disposed between the second data line DL2 and the reference voltage line RVL.

[0070] The third sub-pixel SP3 can be disposed between the third data line DL3 and the low potential voltage supply line VSSL. Accordingly, the second data line DL2 and the third data line DL3 are disposed between the third sub-pixel SP3 and the second sub-pixel SP2. The third sub-pixel SP3 and the first sub-pixel SP1 can be formed to have substantially the same pattern, and the third sub-pixel SP3 and the second sub-pixel SP2 can be formed to have patterns facing each other in a mirror-like manner. Accordingly, similarly to the first sub-pixel SP1, the third data line DL3 is formed on the left side of the third sub-pixel SP3 to effectively supply the data voltage DATA to the third sub-pixel SP3.

[0071] In the display device according to the embodiment, the pixel may include a plurality of capacitors C1, C2, and C3. The plurality of capacitors may include: a first capacitor C1 corresponding to a storage capacitor; and second and third capacitors C2 and C3 corresponding to parasitic capacitors. In the present invention, the first capacitor C1 may be referred to as a storage capacitor, the second capacitor C2 may be referred to as a first parasitic capacitor, and the third capacitor C3 may be referred to as a second parasitic capacitor.

[0072] As described below with reference to Figure 4 the first capacitor C1 may include: a 1-1 capacitor C1a formed between the active layer ACT and the third wiring layer CLAD; and a 1-2 capacitor C1b formed between the active layer ACT and the first wiring layer LS.

[0073] The second capacitor C2 may be formed between the intermediate electrode line SD and the active layer ACT. The second capacitor C2 may be formed between the intermediate electrode line SD and the gate of the driving transistor DT. The third capacitor C3 may be formed between the intermediate electrode line SD and the source of the driving transistor DT. The third capacitor C3 may be formed between the intermediate electrode line SD and the third wiring layer CLAD. The intermediate electrode line SD may traverse the storage capacitor in which the first capacitor C1 is formed, and the intermediate electrode line SD may define the second capacitor C2 and the third capacitor C3 with the active layer ACT and the third wiring layer CLAD in the storage capacitor region. To this end, the intermediate electrode line SD may be disposed substantially parallel to the gate line GL.

[0074] In the display device according to an embodiment, the pixel may further include an intermediate electrode line SD.

[0075] The intermediate electrode line SD may be disposed substantially parallel to the gate line GL and is disposed to extend from the low potential voltage supply line VSSL without crossing the high potential voltage supply line VDDL. The intermediate electrode line SD may extend from the low potential voltage supply line VSSL to the storage capacitor of the first sub-pixel SP1 while traversing the storage capacitors of the second sub-pixel SP2 and the third sub-pixel SP3.

[0076] In addition, the intermediate electrode line SD may be disposed to cross a plurality of data lines DL. For example, the intermediate electrode line SD may be disposed to cross the plurality of data lines DL1, DL2, and DL3 included in one pixel (including the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3). In this case, the intermediate electrode line SD may be disposed to cross the plurality of data lines DL1, DL2, and DL3 and the reference voltage line RVL included in one pixel.

[0077] The intermediate electrode line SD may be electrically connected to the low potential voltage supply line VSSL. The intermediate electrode line SD may supply the low potential voltage VSS to the light emitting elements EL of the first to third sub-pixels SP1, SP2, and SP3.

[0078] Meanwhile, for ease of description, the intermediate electrode line SD may be interchanged with the intermediate electrode layer SD or the intermediate electrode line SD may be disposed in the intermediate electrode layer.

[0079] Referring to Figure 3 and 4 According to an embodiment of the present invention, the display device may include a first wiring layer LS, an active layer ACT, a second wiring layer GSS, an intermediate electrode layer SD, and a third wiring layer CLAD on a substrate SUB. The first wiring layer LS, the active layer ACT, the second wiring layer GSS, and the third wiring layer CLAD may be sequentially disposed on the substrate.

[0080] The first wiring layer LS can be a light-blocking layer and define a basic wiring structure for providing current to operate the pixels. The active layer ACT can form a plurality of transistors (e.g., a driving transistor DT, a sensing transistor SET, and a switching transistor SWT). The active layer ACT can be a semiconductor layer for the plurality of transistors including the driving transistor DT. The second wiring layer GSS can form the gate of each of the plurality of transistors (e.g., the driving transistor DT, the sensing transistor SET, and the switching transistor SWT). The intermediate electrode layer SD can be disposed between the active layer ACT and the third wiring layer CLAD and define parasitic capacitors (e.g., C2 and C3) with the active layer ACT and the third wiring layer CLAD. The third wiring layer CLAD can be electrically connected to different wiring layers (e.g., the first wiring layer LS and the second wiring layer GSS), the intermediate electrode layer SD, and the active layer ACT via a plurality of contact holes.

[0081] The first wiring layer LS can be disposed on the substrate SUB. The first wiring layer LS disposed on the substrate SUB can define a high-potential voltage supply line VDDL, a low-potential voltage supply line VSSL, data lines DL1, DL2, and DL3, and a reference voltage line RVL. The first wiring layer LS can be formed in the same layer as the high-potential voltage supply line VDDL, the low-potential voltage supply line VSSL, the data lines DL1, DL2, and DL3, and the reference voltage line RVL.

[0082] The first wiring layer LS can include a 1-1 wiring layer LS1, a 1-2 wiring layer LS2, a 1-3 wiring layer LS3, and a 1-4 wiring layer LS4. The 1-1 wiring layer LS1, the 1-2 wiring layer LS2, the 1-3 wiring layer LS3, and the 1-4 wiring layer LS4 can be made of the same material. The 1-1 wiring layer LS1 can be disposed below the storage capacitor and the driving transistor DT. The 1-2 wiring layer LS2 can be the data lines DL1, DL2, and DL3. The 1-3 wiring layer LS can be the high-potential voltage supply line VDDL. The 1-4 wiring layer LS4 can be the low-potential voltage supply line VSSL.

[0083] The buffer layer BUF can be disposed on the first wiring layer LS. The buffer layer BUF can be disposed between the first wiring layer LS and the active layer ACT and separate the active layer ACT and the first wiring layer LS. The first wiring layer LS (e.g., the 1-1 wiring layer LS1) and the active layer ACT can define a 1-2 capacitor C1b with the buffer layer BUF interposed therebetween. Specifically, the 1-1 wiring layer LS1 and the active layer ACT can define the 1-2 capacitor C1b in a region where the 1-1 wiring layer LS1 and the active layer ACT face each other up and down. The 1-2 capacitor C1b can be configured as a part of the first capacitor C1 corresponding to the storage capacitor.

[0084] The active layer ACT can be disposed on the buffer layer BUF. The active layer ACT and the second wiring layer GSS can form a transistor. For example, the transistor can include a switching transistor SWT, a sensing transistor SET, and a driving transistor DT. Refer to Figure 4 , in the A-A' cross-section, the second wiring layer GSS and the active layer ACT can form the driving transistor DT and the switching transistor SWT.

[0085] The active layer ACT can include a first active layer ACT1, a second active layer ACT2, and a third active layer ACT3. The first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 can be made of the same material. The first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 can be separated from each other.

[0086] The first active layer ACT1 can form the driving transistor DT, and can be connected to the 3-1 wiring layer CLAD1 corresponding to one end of the third capacitor C3 and the first capacitor C1a.

[0087] The second active layer ACT2 can form the switching transistor SWT, and is electrically connected to the data lines DL1, DL2, and DL3 and the gate of the driving transistor DT. One end of the second active layer ACT2 can be connected to the data lines DL1, DL2, and DL3, and the other end of the second active layer ACT2 can be connected to the 3-2 wiring layer CLAD2. The data voltage provided from the data lines DL1, DL2, and DL3 can be stored in the storage capacitor, and then transmitted to the gate of the driving transistor DT via the 3-2 wiring layer CLAD2.

[0088] The third active layer ACT3 can form the sensing transistor SET, and is electrically connected to the reference voltage line RVL and the 3-1 wiring layer CLAD1. The 3-1 wiring layer CLAD1 can correspond to one end of the first capacitor C1a and one end of the third capacitor C3.

[0089] One or more insulating layers can be disposed on the active layer ACT. For example, the insulating layer can include a gate insulating layer GI and one or more intermediate insulating layers ILD1 and ILD2. The structure of one or more insulating layers can be changed according to the stacking layout of each sub-pixel. Embodiments of the present invention are not limited thereto.

[0090] The intermediate electrode layer SD and the third wiring layer CLAD can be disposed on one or more insulating layers. The intermediate electrode layer SD can be disposed between the first intermediate insulating layer ILD1 and the second intermediate insulating layer ILD2, and the third wiring layer CLAD can be disposed on the second intermediate insulating layer ILD2. However, the present invention is not limited thereto.

[0091] The intermediate electrode layer SD can be set as a storage capacitor spanning multiple sub-pixels SP. For example, the intermediate electrode layer SD can be an electrode layer spanning the region corresponding to the storage capacitors (first capacitor C1) of the first to third sub-pixels SP1, SP2, and SP3.

[0092] In an embodiment, the intermediate electrode layer SD can be set substantially parallel to the gate line GL.

[0093] In an embodiment, the intermediate electrode layer SD can be disposed between the active layer ACT and the third wiring layer CLAD. The intermediate electrode layer SD and the active layer ACT define a second capacitor C2, and the intermediate electrode layer SD and the third wiring layer CLAD define a third capacitor C3. The second capacitor C2 and the third capacitor C3 can be parasitic capacitors. By using the second capacitor C2 and the third capacitor C3 (e.g., an increase in the number of parasitic capacitors), the boosting phenomenon can be reduced, and even when the gate of the driving transistor DT is charged with a voltage of the same level, the driving current of the sub-pixel can be reduced (see Figure 8 ). The reduction of the driving current can correspondingly improve the overall grayscale FOS quality.

[0094] In addition, the boosting phenomenon will be further described. Generally, when a certain gate line (e.g., the Nth gate line) is deactivated (turned off) and the next gate line (e.g., the N + 1th gate line) is activated (turned on), a high-potential voltage VDD can be applied to the pixels of the Nth gate line. During this process, the voltages of the gate node and the source node of the driving transistor DT are boosted.

[0095] After the boosting occurs, the current (driving current) of the pixel is determined by the voltage difference between the gate node and the source node. The current is the main element for determining the pixel brightness. The degree of boosting is determined by the capacitors (storage capacitors) applied to the gate node and the source node of the driving transistor DT. In this case, the boosting loss can be caused by the capacitance ratio of the storage capacitor and other capacitors. This loss can be called the boosting loss. According to an embodiment of the present invention, the boosting loss can be determined by the storage capacitor (e.g., the first capacitor C1) and other capacitors (e.g., the second capacitor C2 and the third capacitor C3).

[0096] In addition, according to an embodiment, without increasing the channel length of the driving transistor DT, low-current operation can be achieved by increasing the grayscale voltage. Therefore, the margin of the area for designing the pixel can be increased.

[0097] The second wiring layer GSS and the third wiring layer CLAD may be disposed on the insulating layer or between two or more insulating layers. The second wiring layer GSS may be disposed on the gate insulating layer GI, and the third wiring layer CLAD may be disposed on the second intermediate insulating layer ILD2. Specifically, the second wiring layer GSS may be disposed between the gate insulating layer GI and the first intermediate insulating layer ILD1, and the third wiring layer CLAD may be disposed on the second intermediate insulating layer ILD2 and covered by the passivation layer PAS.

[0098] The second wiring layer GSS may form the gates of the driving transistor DT, the switching transistor SWT, and the sensing transistor SET. For example, the second wiring layer GSS may include: the 2-1 wiring layer GSS1 corresponding to the gate of the driving transistor DT; and the 2-2 wiring layer GSS2 corresponding to the gates of the sensing transistor SET and the switching transistor SWT. The 2-2 wiring layer GSS2 may be a gate line GL or may be formed in the same layer as the gate line GL.

[0099] The third wiring layer CLAD may define a first capacitor C1a in the region facing the active layer ACT. The first capacitor C1a may be configured to correspond to a part of the first capacitor C1 of the storage capacitor. The first capacitor C1 may include the first capacitor C1a and the second capacitor C1b, and the capacitance of the first capacitor C1 may be defined by the first capacitor C1a and the second capacitor C1b. The storage capacitor in the storage capacitor region may be formed by coupling the first capacitor C1a and the second capacitor C1b.

[0100] The third wiring layer CLAD may include a 3-1 wiring layer CLAD1, a 3-2 wiring layer CLAD2, and a 3-3 wiring layer CLAD3.

[0101] The 3-1 wiring layer CLAD1 may be one end of the first capacitor C1 and one end of the third capacitor C3. One region of the 3-1 wiring layer CLAD1 may define the third capacitor C3 while facing the intermediate electrode layer SD, and another region of the 3-1 wiring layer CLAD1 may define the first capacitor C1a while facing the second active layer ACT2.

[0102] The 3-2 wiring layer CLAD2 may connect the 2-1 wiring layer GSS1 and the second active layer ACT2. The 2-1 wiring layer GSS1 may be the gate of the driving transistor DT. The second active layer ACT2 may form the first capacitor C1a with the 3-1 wiring layer CLAD1 and form the second capacitor C2 with the intermediate electrode layer SD.

[0103] The 3-3 wiring layer CLAD3 can be connected to the second active layer ACT2 and the data line DL. The 2-2 wiring layer GSS2 can be the gate of the switching transistor SWT. The 2-2 wiring layer GSS2 can be the gate of the sensing transistor SET. While the switching transistor SWT is turned on, the data voltage can be stored in the storage capacitor C1 via the second active layer ACT2.

[0104] The third wiring layer CLAD can further include the 3-4 wiring layer CLAD4. The 3-4 wiring layer CLAD4 can be connected to the reference voltage line RVL and the third active layer ACT3. Specifically, different from the first sub-pixel SP1 and the second sub-pixel SP2, the third sub-pixel SP3 can be arranged to be away from the reference voltage line RVL by the size of one sub-pixel. The reference voltage line RVL can supply the reference voltage VREF to the sensing transistor SET of the third sub-pixel SP3 via the 3-4 wiring layer CLAD4.

[0105] The third wiring layer CLAD can define a third capacitor C3 in the region facing the intermediate electrode layer SD. As described above, the third capacitor C3 can be a kind of parasitic capacitor and cause a propulsion loss in the storage capacitor region.

[0106] According to an embodiment of the present invention, the third wiring layer CLAD can be further disposed at other positions except for the 3-1 to 3-4 wiring layers CLAD1, CLAD2, CLAD3, and CLAD4 and connected to different component elements. The third wiring layer CLAD is not limited to the above wiring layers.

[0107] Figure 5 is a circuit diagram of a sub-pixel of a display device according to another embodiment of the present invention.

[0108] Except that the voltage received by the fourth node N4 in the Figure 5 display device is different from the voltage received by the fourth node N4 in the Figure 2 display device, Figure 5 the display device in Figure 2 has basically the same structure as the display device in

[0109] Figure 6 is a circuit diagram of a sub-pixel of a display device according to still another embodiment of the present invention.

[0110] Except that the line connected to the fourth node N4 in the display device of Figure 6 is different from the line connected to the fourth node N4 in the display device of Figure 2 the display devices in Figure 6 and Figure 2 are substantially the same in configuration. Accordingly, repeated descriptions of the same components will be omitted. According to an embodiment, the fourth node N4 may be electrically connected to the gate line GL. For example, one end of the intermediate electrode line SD may be connected to the gate line GL, and the intermediate electrode line SD may be provided to span the storage capacitors of a plurality of sub-pixels SP1, SP2, and SP3. In this case, the second capacitor C2 and the third capacitor C3 may be electrically connected to the gate line GL via the fourth node N4.

[0111] Figure 7 is a circuit diagram of a sub-pixel of a display device according to another embodiment of the present invention.

[0112] Except that an initialization line IL is further provided, Figure 7 the display devices in Figure 2 and Figure 7 are substantially the same in configuration. Accordingly, repeated descriptions of the same components will be omitted. Referring to

[0113] the fourth node N4 may be electrically connected to the initialization line IL. For example, one end of the intermediate electrode line SD may be connected to the initialization line IL, and the intermediate electrode line SD may be provided to span the storage capacitors of a plurality of sub-pixels SP1, SP2, and SP3. In this case, the second capacitor C2 and the third capacitor C3 may be electrically connected to the initialization line IL via the fourth node N4. As a reference, the initialization line IL may provide an initialization voltage VINIT.

[0113] Exemplary embodiments of the present invention may also be described as follows.

[0114] A display device according to an embodiment of the present invention may include a plurality of sub-pixels, each of the plurality of sub-pixels including: a driving transistor configured to operate a light-emitting element by receiving a data voltage; a switching transistor configured to apply the data voltage to a gate of the driving transistor; the light-emitting element including a cathode and an anode, the anode being connected to a source of the driving transistor, the cathode being electrically connected to a low-potential voltage supply line, wherein the low-potential voltage supply line may be electrically connected to an intermediate electrode line of a storage capacitor spanning the sub-pixel, wherein the low-potential voltage supply line supplies a low-potential voltage to the light-emitting element, and wherein the intermediate electrode line forms a first parasitic capacitor with the gate of the driving transistor and a second parasitic capacitor with the source of the driving transistor.

[0115] The storage capacitor may be formed between the gate and the source of the driving transistor, and the intermediate electrode line may cross the storage capacitor corresponding to the storage capacitor region.

[0116] The display device may further include a high-potential voltage supply line, wherein the gate of the driving transistor may be connected to the source of the switching transistor, the drain of the driving transistor may be connected to the high-potential voltage supply line, and the source of the driving transistor may be connected to the anode of the light-emitting element.

[0117] The intermediate electrode line may be provided from the low-potential voltage supply line without crossing the high-potential voltage supply line.

[0118] The display device may further include: a gate line configured to provide a scan signal or a sense signal; and a data line configured to provide the data voltage, wherein the gate of the switching transistor may be connected to the gate line, the drain of the switching transistor may be connected to the data line, and the source of the switching transistor may be connected to the gate of the driving transistor.

[0119] The intermediate electrode line may be provided in parallel with the gate line.

[0120] A group of a plurality of sub-pixels may constitute one pixel, and the intermediate electrode line may be provided to cross a plurality of data lines included in one pixel.

[0121] The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the plurality of data lines may include a first data line for the first sub-pixel, a second data line for the second sub-pixel, and a third data line for the third sub-pixel, and a reference voltage line may be provided between the first sub-pixel and the second sub-pixel, and the reference voltage line may provide a reference voltage to the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0122] The intermediate electrode line may be provided to cross the reference voltage line.

[0123] The display device may further include a sense transistor configured to control the voltage state of the source of the driving transistor, wherein the sense transistor may be connected between the source of the driving transistor and a reference voltage line configured to provide a reference voltage, and the gate of the sense transistor may be connected to the gate line.

[0124] The display device may further include a first wiring layer, an active layer, a second wiring layer, an intermediate electrode layer, and a third wiring layer that are sequentially disposed on a substrate, wherein a storage capacitor in the storage capacitor region may be constituted by coupling a 1-1 capacitor that can be formed between the third wiring layer and the active layer and a 1-2 capacitor that can be formed between the first wiring layer and the active layer.

[0125] The first wiring layer may be formed together with a high-potential voltage supply line, the low-potential voltage supply line, a data line, and a reference voltage line.

[0126] The active layer may be a semiconductor layer for a plurality of transistors including driving transistors.

[0127] The second wiring layer may be formed together with a gate line.

[0128] The third wiring layer may be electrically connected to the first wiring layer, the second wiring layer, the intermediate electrode layer, and the active layer via a plurality of contact holes.

[0129] The first parasitic capacitor may be formed between the active layer and the intermediate electrode layer in the storage capacitor region.

[0130] The second parasitic capacitor may be formed between the intermediate electrode layer and the third wiring layer in the storage capacitor region.

[0131] A pixel circuit according to an embodiment of the present invention may include: a light-emitting element; a driving transistor configured to operate the light-emitting element by receiving a data voltage; and a switching transistor configured to apply the data voltage to a gate of the driving transistor, wherein the light-emitting element may include a cathode and an anode, wherein the anode may be connected to a source of the driving transistor, wherein the cathode may be connected to a low-potential voltage supply line, wherein the low-potential voltage supply line may be electrically connected to an intermediate electrode line of a storage capacitor across a sub-pixel, wherein the low-potential voltage supply line supplies a low-potential voltage to the light-emitting element, wherein the intermediate electrode line and the gate of the driving transistor constitute a first parasitic capacitor, and and the source of the driving transistor constitute a second parasitic capacitor.

[0132] The storage capacitor may be formed between the gate and the source of the driving transistor, and the intermediate electrode line may span the storage capacitor corresponding to the storage capacitor region.

[0133] The pixel circuit may further include a high-potential voltage supply line, wherein the gate of the driving transistor may be connected to the source of the switching transistor, the drain of the driving transistor may be connected to the high-potential voltage supply line, and the source of the driving transistor may be connected to the anode of the light-emitting element.

[0134] Although the exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto, and can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the exemplary embodiments of the present invention are provided for exemplary purposes only and are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present invention. All technical concepts within the equivalent scope of the present invention should be construed as falling within the scope of the present invention.

Claims

1. A display device, comprising: Multiple sub-pixels, Each of the plurality of sub-pixels comprises: Light emitting element; a driving transistor configured to operate the light emitting element by receiving a data voltage; and a switching transistor configured to apply the data voltage to a gate of the driving transistor, The light emitting element comprises a cathode and an anode, wherein the anode is connected to the source of the driving transistor, wherein the cathode is electrically connected to a low potential voltage supply line, wherein the low potential voltage supply line supplies a low potential voltage to the light emitting element, The middle electrode line of the storage capacitor crossing the plurality of sub-pixels forms a first parasitic capacitor with the gate electrode of the driving transistor and forms a second parasitic capacitor with the source electrode of the driving transistor. 2 . The display device according to claim 1 , wherein the low potential voltage supply line is electrically connected to the intermediate electrode line. 3 . The display device according to claim 1 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to a high potential voltage supply line. 4 . The display device of claim 1 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to a gate line configured to provide a scan signal or a sensing signal. 5 . The display device of claim 1 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to an initialization line configured to provide an initialization voltage.

6. The display device according to claim 1, The storage capacitor is formed between the gate and the source of the driving transistor, and the intermediate electrode line crosses the storage capacitor in the storage capacitor region.

7. The display device according to claim 1, further comprising a high potential voltage supply line, The gate of the driving transistor is connected to the source of the switching transistor, the drain of the driving transistor is connected to the high potential voltage supply line, and the source of the driving transistor is connected to the anode of the light emitting element.

8. The display device according to claim 7, The intermediate electrode line is provided from the low potential voltage supply line without crossing the high potential voltage supply line.

9. The display device according to claim 1, further comprising: A gate line configured to provide a scanning signal or a sensing signal; as well as a data line configured to provide the data voltage, The gate of the switch transistor is connected to the gate line, the drain of the switch transistor is connected to the data line, and the source of the switch transistor is connected to the gate of the drive transistor.

10. The display device according to claim 9, The middle electrode lines are parallel to the gate lines.

11. The display device according to claim 9, A group of a plurality of sub-pixels constitutes one pixel, and the intermediate electrode line crosses a plurality of data lines included in the one pixel.

12. The display device according to claim 11, The plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, wherein the plurality of data lines include a first data line for the first sub-pixel, a second data line for the second sub-pixel, and a third data line for the third sub-pixel, The reference voltage line is located between the first sub-pixel and the second sub-pixel and provides a reference voltage to the first sub-pixel, the second sub-pixel and the third sub-pixel.

13. The display device according to claim 12, The middle electrode line crosses the reference voltage line.

14. The display device according to claim 9, further comprising: a sense transistor configured to control a voltage state of a source of the drive transistor, The sensing transistor is connected to a source of the driving transistor and a reference voltage line configured to provide a reference voltage, and a gate of the sensing transistor is connected to the gate line.

15. The display device according to claim 1, further comprising: A first wiring layer, an active layer, a second wiring layer, an intermediate electrode layer and a third wiring layer are sequentially arranged on a substrate, The storage capacitor in the storage capacitor region is formed by coupling a 1-1 capacitor located between the third wiring layer and the active layer and a 1-2 capacitor located between the first wiring layer and the active layer.

16. The display device according to claim 15, The first wiring layer is formed in the same layer as the high potential voltage supply line, the low potential voltage supply line, the data line and the reference voltage line.

17. The display device according to claim 15, The active layer is a semiconductor layer for a plurality of transistors including a driving transistor.

18. The display device according to claim 15, The second wiring layer is formed in the same layer as the gate line.

19. The display device according to claim 15, The third wiring layer electrically connects the first wiring layer, the second wiring layer, the intermediate electrode layer, and the active layer via a plurality of contact holes.

20. The display device according to claim 15, The first parasitic capacitor is formed between the active layer and the intermediate electrode layer in the storage capacitor region.

21. The display device according to claim 15, The second parasitic capacitor is formed between the intermediate electrode layer and the third wiring layer in the storage capacitor region.

22. The display device according to claim 15, The intermediate electrode layer is located between the first intermediate insulating layer and the second intermediate insulating layer.

23. The display device according to claim 22, The second wiring layer is located between the gate insulating layer and the first intermediate insulating layer, The third wiring layer is located on the second intermediate insulating layer and is covered by a passivation layer.

24. The display device according to claim 12, The third sub-pixel is spaced apart from the reference voltage line by a size of one sub-pixel.

25. A pixel circuit comprising: Light emitting element; a driving transistor configured to operate the light emitting element by receiving a data voltage; as well as a switching transistor configured to apply the data voltage to a gate of the driving transistor, The light emitting element comprises a cathode and an anode, wherein the anode is connected to the source of the driving transistor, wherein the cathode is connected to a low potential voltage supply line, and the low potential voltage supply line provides a low potential voltage to the light emitting element, The middle electrode line crossing the storage capacitor and the gate electrode of the driving transistor form a first parasitic capacitor, and the middle electrode line and the source electrode of the driving transistor form a second parasitic capacitor. 26 . The pixel circuit according to claim 25 , wherein the low potential voltage supply line is electrically connected to the intermediate electrode line. 27 . The pixel circuit according to claim 25 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to a high potential voltage supply line. 28 . The pixel circuit of claim 25 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to a gate line configured to provide a scan signal or a sensing signal. 29 . The pixel circuit of claim 25 , wherein the first parasitic capacitor and the second parasitic capacitor are electrically connected to an initialization line configured to provide an initialization voltage.

30. The pixel circuit according to claim 25, The storage capacitor is formed between the gate and the source of the driving transistor, and the intermediate electrode line crosses the storage capacitor in the storage capacitor region.

31. The pixel circuit according to claim 25, further comprising a high potential voltage supply line, The gate of the driving transistor is connected to the source of the switching transistor, the drain of the driving transistor is connected to the high potential voltage supply line, and the source of the driving transistor is connected to the anode of the light emitting element.

32. The pixel circuit according to claim 25, The storage capacitor includes a 1-1th capacitor located between the gate and source of the driving transistor and a 1-2th capacitor located between the source of the driving transistor and the low potential voltage line.

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