Chip read-write capability testing device, method, readable storage medium and system

Abstract

The application relates to a chip read-write capability test device, method, readable storage medium and system. The chip read-write capability test device is electrically connected with a to-be-tested chip. Based on a received control instruction, the test device generates and sends a control signal, an address signal and sample data to the to-be-tested chip. The control signal comprises a clock selection signal. When the clock selection signal is a first selection signal, an on-chip clock signal of the to-be-tested chip is acquired, and the control signal, the address signal, the sample data and read data are sent to the to-be-tested chip. The control signal comprises a clock signal generated based on the on-chip clock signal. When the clock selection signal is a second selection signal, the control signal, the address signal, the sample data and the read data are sent to the to-be-tested chip. The control signal comprises a clock signal generated based on a working frequency of the to-be-tested chip. The test result of the to-be-tested chip is determined through the sample data and the read data. The device can reduce the cost and improve the compatibility.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip read / write capability testing device, method, readable storage medium, and system. Background Technology

[0002] With the development of chip design and manufacturing, there are now different types of chips, such as microprocessors, memory, and FPGAs, which often have different electrical characteristics and communication protocols. However, due to the increase in chip types, testing chip read / write capabilities requires matching specific testing equipment to different chip types, resulting in poor compatibility and high costs.

[0003] SRAM memory chips typically operate at frequencies between 1MHz and 2MHz. If they have an internal clock source, the generated clock signal will also be within the 1MHz to 2MHz range. This requires the corresponding chip testing equipment to provide a 1MHz to 2MHz clock signal and to achieve good real-time control within this clock frequency range. Therefore, for chips with specific requirements for clock signals and real-time control during testing, the testing equipment needs to provide high-precision, stable, and flexible clock signals, as well as real-time control capabilities, to ensure the accuracy and effectiveness of the testing. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip read / write capability testing device, method, readable storage medium, and system that can ensure the accuracy and effectiveness of the test, addressing the aforementioned technical problems.

[0005] In a first aspect, this application provides a chip read / write capability testing device, which is electrically connected to the chip under test. The testing device is used to generate and send control signals, address signals, and sample data to the chip under test based on received control instructions; the control instructions include a clock selection signal.

[0006] When the clock selection signal is the first selection signal, the on-chip clock signal of the chip under test is acquired, and control signals, address signals, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal;

[0007] When the clock selection signal is the second selection signal, a control signal, an address signal, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, which is generated based on the operating frequency of the chip under test;

[0008] The chip read / write capability testing equipment is also used to determine the test results of the chip under test through the sample data and the read data.

[0009] In some embodiments, the control instructions include a test strategy, which includes multiple methods for verifying the read / write performance of the chip under test; the test equipment is also used to determine sample data based on the test strategy.

[0010] In some embodiments, the chip read / write capability testing device is also used for:

[0011] Based on the matching of the sample data and the read data, the test result of the chip under test is determined.

[0012] In some embodiments, the connection path between the chip read / write capability testing device and the chip under test includes a first path, a second path, and a third path, and the chip read / write capability testing device is further used for:

[0013] The address signal is transmitted through the first path; the address signal includes a read / write address.

[0014] Data signals are transmitted through the second channel, and the data signals include sample data or read data.

[0015] Control signals are transmitted through the third channel, and the control signals include read / write control signals and clock signals.

[0016] In some embodiments, the control instructions include configuration information and test instructions; the chip read / write capability testing device includes a main control device and a test execution device, wherein the main control device is communicatively connected to the test execution device;

[0017] The main control device is configured to: send configuration information corresponding to the chip under test to the test execution device; and send test commands to the test execution device.

[0018] The test execution device is configured to: configure itself based on the configuration information; generate and send control signals, address signals and sample data to the chip under test based on the test instructions, and receive read data; and determine the test result of the chip under test through the sample data and the read data.

[0019] In some embodiments, the configuration information includes read / write path width and address range; the test execution device includes a general-purpose input / output module;

[0020] The main control device is also used to send initialization commands to the test execution device;

[0021] The test execution device is used to initialize the general input / output module based on the initialization instruction; and to configure the initialized general input / output module based on the read / write path width and address range.

[0022] In some embodiments, the configuration information further includes the power supply voltage of the chip under test; the test execution device further includes a power supply module;

[0023] The main control device is also used to send initialization commands to the test execution device;

[0024] The test execution device is used to initialize the power module based on the initialization command; the power module is used to power on the chip under test based on the power supply voltage of the chip under test.

[0025] In some embodiments, the configuration information includes a clock selection signal; the test execution device further includes a timer;

[0026] The main control device is also used to send initialization commands to the test execution device;

[0027] The test execution device is used to initialize the timer based on the initialization instruction;

[0028] When the clock selection signal is the first selection signal, the timer is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is the second selection signal, the timer is used to generate a clock signal based on the operating frequency of the chip under test and send the clock signal to the chip under test.

[0029] In some embodiments, the main control device is further configured to send a query command to the test execution device;

[0030] The test execution device is also used to send the test results of the chip under test and / or test results that do not meet the preset conditions to the main control device based on the query command.

[0031] In some embodiments, the main control device is also used to send a standby command to the test execution device;

[0032] The test execution device is used to disconnect the connection with the chip under test and power down the chip under test based on the standby command.

[0033] Secondly, this application provides a chip read / write capability testing method, applied to a chip read / write capability testing device, the chip read / write capability testing method comprising:

[0034] Based on the received control commands, control signals, address signals, and sample data are generated and sent to the chip under test; the control commands include a clock selection signal.

[0035] When the clock selection signal is the first selection signal, the on-chip clock signal of the chip under test is acquired, and control signals, address signals, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal;

[0036] When the clock selection signal is the second selection signal, a control signal, an address signal, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, which is generated based on the operating frequency of the chip under test;

[0037] The test results of the chip under test are determined by using the sample data and the read data.

[0038] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip read / write capability testing method described in the second aspect.

[0039] Fourthly, this application provides a chip read / write capability testing system, including a chip under test and the chip read / write capability testing device described in the first aspect;

[0040] The chip under test is a memory chip; the memory chip includes a clock selector, a configuration selector, an on-chip clock source, and a memory module; wherein:

[0041] The clock selector is used to determine the operating clock signal of the memory chip based on the control signal received from the chip read / write capability testing device, from the clock signal input from the chip read / write capability testing device and the on-chip clock signal generated by the on-chip clock source;

[0042] The configuration selector is used to configure the on-chip clock source and / or the memory module based on the control signal received from the chip read / write capability testing device.

[0043] The on-chip clock source is used to generate at least one on-chip clock signal based on the settings of the configuration selector;

[0044] The storage module is used to write the sample data and / or read the data based on the control signal, address signal, sample data and working clock signal received from the chip read / write capability testing device.

[0045] The aforementioned chip read / write capability testing equipment, method, computer-readable storage medium, and system acquire the on-chip clock signal of the chip under test (DUT) when the clock selection signal is a first selection signal, and generate a clock signal based on the on-chip clock signal, which is generally synchronized with the on-chip clock signal. When the clock selection signal is a second selection signal, the testing equipment generates an external clock signal based on the operating frequency of the DUT. Based on received control commands, the testing equipment sends control signals, address signals, and sends sample data or receives read data to the DUT. The testing equipment also determines the test result of the DUT using the sample data and the read data. This allows for selection between the on-chip clock signal of the DUT or the external clock signal of the testing equipment, and control of read / write operations based on the selected clock signal. This overcomes the limitations of traditional equipment in clock source adaptability, enabling highly compatible read / write testing of various chip types, thereby reducing costs and improving compatibility. On the other hand, the aforementioned chip read / write capability testing equipment, chip read / write capability testing methods, computer-readable storage media, and chip read / write capability testing systems have excellent testing effects on the read / write performance of storage chips. They can meet the requirements of this type of storage chip for clock signals within its operating frequency range and can achieve good real-time control within this clock frequency range. Attached Figure Description

[0046] Figure 1 This is a schematic diagram showing the connection between the chip read / write capability testing device and the chip under test in one embodiment.

[0047] Figure 2 This is a schematic diagram showing the connection between the chip read / write capability testing device and the chip under test in another embodiment;

[0048] Figure 3 This is a structural block diagram of a chip read / write capability testing device in one embodiment;

[0049] Figure 4 This is a schematic diagram showing the connection between the chip read / write capability testing device and the chip under test in another embodiment;

[0050] Figure 5 This is a block diagram of the memory chip in one embodiment;

[0051] Figure 6 This is a block diagram of the memory chip in another embodiment;

[0052] Figure 7 This is a schematic diagram of the structure of a clock adjuster provided in an embodiment of this application;

[0053] Figure 8 This is a circuit diagram of a current source component provided in an embodiment of this application;

[0054] Figure 9 This is a schematic diagram of a ring oscillator provided in an embodiment of this application;

[0055] Figure 10 This is a schematic diagram of the circuit structure of multiple on-chip clock generators provided in the embodiments of this application;

[0056] Figure 11 This is a schematic diagram of the overall structure of an on-chip clock signal generation circuit provided in an embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0058] Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, some design, manufacturing, or production modifications based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0059] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0060] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0061] Example 1

[0062] like Figure 1 As shown, a chip read / write capability testing device is provided. The chip read / write capability testing device is electrically connected to the chip under test. The testing device is used to generate and send control signals, address signals, and sample data to the chip under test based on received control instructions. The control instructions include a clock selection signal.

[0063] When the clock selection signal is the first selection signal, the on-chip clock signal of the chip under test is acquired, and control signals, address signals, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal;

[0064] When the clock selection signal is the second selection signal, a control signal, an address signal, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, which is generated based on the operating frequency of the chip under test;

[0065] The chip read / write capability testing equipment is also used to determine the test results of the chip under test through the sample data and the read data.

[0066] Among them, the control command can be a control command sent by the user or the host computer, which is used to control the chip read and write capability testing equipment to generate or synchronize clock signals, and then perform read and write capability testing on the chip under test.

[0067] Furthermore, the control instructions include a clock selection signal, which can be a first selection signal or a second selection signal. The first selection signal is used to select the on-chip clock signal of the chip under test (DUT) for reading / writing capability testing; the second selection signal is used to select an external clock signal generated by the test equipment for reading / writing capability testing.

[0068] When the clock selection signal is the first selection signal, the on-chip clock signal on the chip under test is obtained, and a synchronous clock signal is generated based on the on-chip clock signal.

[0069] When the clock selection signal is the second selection signal, the external clock signal generated by the test equipment is sent. The external clock signal needs to be generated based on the operating frequency of the chip under test to ensure that it conforms to the operating frequency of the chip under test, so as to ensure the accuracy and effectiveness of the test.

[0070] Furthermore, based on the control instructions, control signals, address signals, and sample data can be generated. Control signals can include read / write control signals and clock signals. Read / write control signals control whether the current operation is a write or read operation, while address signals control the address to be written or read. Sample data can be the data written for the write operation. The clock signal is crucial for reading and writing tests of the chip under test, especially in chips like SRAM. Because SRAM circuits use synchronous clock circuits, the start of a read / write operation is triggered by a specific clock edge; therefore, the chip read / write capability testing equipment must be driven and triggered by the same clock.

[0071] Furthermore, the testing of chip read and write capabilities may include, but is not limited to, write speed testing, read speed testing, and accuracy testing. Among these, accuracy testing can be determined by comparing the received read data with the sent sample data, thereby determining whether the chip's read and write performance meets expectations.

[0072] This embodiment provides a chip read / write capability testing device. When the clock selection signal is a first selection signal, it acquires the on-chip clock signal of the chip under test (DUT) and sends control signals, address signals, and sample data to the DUT, while also receiving read data. The control signal includes a clock signal generated based on the on-chip clock signal. When the clock selection signal is a second selection signal, it sends control signals, address signals, and sample data to the DUT and receives read data. The control signal also includes a clock signal generated based on the operating frequency of the DUT. The testing device further determines the test result of the DUT using the sample data and the read data. This allows for selection between the on-chip clock signal of the DUT or the external clock signal of the testing device, and clock control for read / write testing based on the selected clock signal. This overcomes the limitations of traditional devices in terms of clock signals, enabling highly compatible read / write testing of various chip types, thereby reducing costs and improving compatibility. Simultaneously, it can also meet the requirements of some DUTs with specific operating frequency ranges, achieving good real-time control within this clock frequency range.

[0073] In some embodiments, the control instructions include a test strategy, which includes multiple methods for verifying the read / write performance of the chip under test; the test equipment is also used to determine sample data based on the test strategy.

[0074] The testing strategy includes preset testing methods and steps, which may include various methods for verifying the read and write performance of the chip under test. For example, the methods for verifying the chip under test may be one or more of the following: single read / write test, continuous read / write test, random address access test, extreme condition test, error injection test, etc. Other verification methods may also be included, which are not limited in this embodiment.

[0075] Based on the aforementioned testing strategy, sample data is determined, which can be done by generating targeted sample data according to the verification methods in the testing strategy. For example, when performing a random address access test, the sample data can include a series of randomly generated addresses and corresponding write data.

[0076] This embodiment provides a chip read / write capability testing device. By determining sample data based on the aforementioned testing strategy, it can provide more comprehensive and in-depth testing services for diverse testing needs, thereby improving the quality and efficiency of testing.

[0077] In some embodiments, the test equipment is also used for:

[0078] Based on the matching of the sample data and the read data, the test result of the chip under test is determined.

[0079] The test result of the chip under test is determined based on the matching of the sample data and the read data. This can be achieved by comparing the sample data and the read data, thereby verifying whether the data transmission of the chip under test is correct during read and write operations, and thus evaluating its function and performance.

[0080] Furthermore, if the sample data and the read data are consistent, it is a complete match. A threshold can be set for the proportion of data consistency, thus dividing it into partial match and complete mismatch, thereby obtaining more detailed test results and helping to discover potential problems.

[0081] This embodiment provides a chip read / write capability testing device that ensures the accuracy of test results by comparing sample data and read data bit by bit. Through automated data comparison and error recording, it improves the efficiency of fault diagnosis, thereby achieving the effect of improving the quality and efficiency of testing.

[0082] In some of these embodiments, such as Figure 2 As shown, the connection path between the test device and the chip under test includes a first path 101, a second path 102, and a third path 103. The test device is also used for:

[0083] Address signals are transmitted through the first channel 101; the address signals include read / write addresses, i.e., addresses for writing / reading data;

[0084] Data signals are transmitted through the second channel 102, and the data signals include sample data or read data, i.e., data written / read.

[0085] Control signals are transmitted through the third channel 103. The control signals include at least one read / write control signal for controlling whether the current operation is a write or a read, and at least one clock signal.

[0086] The first path 101 can be referred to as the address path, the second path 102 as the data path, and the third path 103 as the control path. The first path 101 is used to send address signals, which can include either read or write addresses. Specifically, the write address corresponds to the address where sample data is to be written, and the read address corresponds to the address where the received data is read.

[0087] Sending address signals via the first path 101 enables independent transmission of address signals, avoiding interference from other signals. Sending data signals via the second path 102 ensures the integrity and reliability of data transmission, especially in high-speed or large-data-volume scenarios. The third path 103, the control path, sends control signals, including at least read / write control signals and clock signals, ensuring the timeliness and accuracy of control commands, enabling the test equipment to precisely control the read / write operations of the chip under test.

[0088] This embodiment provides a chip read / write capability testing device. By setting up a first channel, a second channel, and a third channel, the testing device can complete the chip read / write capability test more efficiently and accurately, meeting the testing needs of different types of chips and achieving the effect of improving test quality and compatibility.

[0089] In some embodiments, the control commands include configuration information and test commands; such as Figure 3 As shown, the chip read / write capability testing equipment includes a main control device 11 and a test execution device 12, wherein the main control device 11 is communicatively connected to the test execution device 12; the main control device 11 is used to send configuration information corresponding to the chip under test to the test execution device 12; and to send test commands to the test execution device 12.

[0090] The test execution device 12 is used to configure itself based on the configuration information; generate and send control signals, address signals and sample data to the chip under test based on the test instructions, and receive read data; and determine the test result of the chip under test through the sample data and the read data.

[0091] The chip read / write capability testing equipment can be divided into a main control device 11 and a test execution device 12. The main control device 11 sends configuration information from the control command to the test execution device 12, enabling the test execution device 12 to configure itself. Furthermore, the configuration information can include one or more of the following: signal path width, address range, power supply voltage, clock selection signal, etc.

[0092] The configured test execution device 12 generates control signals, address signals, and sample data according to the test instructions, and receives and reads data. The test result of the chip under test is determined using the sample data and the read data.

[0093] After obtaining the test results, the test execution device 12 can also feed the test results back to the main control device 11. The main control device 11 can generate a detailed test report based on the test results and provide it to the user through a user interface or file output.

[0094] This embodiment provides a chip read / write capability testing device. Through the separate design of the main control device and the test execution device, the test system can be flexibly configured and expanded to adapt to different types of chips and test requirements. The real-time communication connection between the main control device and the test execution device allows users to monitor the test progress and results in real time, and also adjust the test parameters in a timely manner, thereby improving the test quality and test efficiency.

[0095] In some embodiments, the configuration information includes the read / write path width and address range; such as Figure 3 As shown, the test execution device 12 includes a general-purpose input / output module 121;

[0096] The main control device 11 is also used to send initialization commands to the test execution device 12;

[0097] The test execution device 12 is used to initialize the general input / output module 121 based on the initialization instruction; and to configure the initialized general input / output module 121 based on the read / write path width and address range.

[0098] The read / write path width can be the path width during the read / write test process, and for example, it can include the data path width and the address path width. The data path width can be the path width of the second path, and the address path width can be the path width of the first path. For example, the width can be 8 bits, 16 bits, 32 bits, etc. The address range can be the specified address space range of the chip under test.

[0099] The main control device 11 is used to send initialization commands to the test execution device 12. The initialization commands can be used to initialize the general input / output module 121. Alternatively, configuration information and initialization commands can be sent to the test execution device 12, causing the test execution device 12 to respond to the initialization commands and configure itself based on the configuration information.

[0100] During initialization, the general-purpose input / output module 121 is configured according to the read / write path bit width and address range, thus obtaining the configured general-purpose input / output module 121.

[0101] In one specific embodiment, the configuration information may include the bit width of the data path, the bit width of the address path, the address range, the power supply voltage of the chip under test, the clock source of the chip under test, the measurement strategy, etc.

[0102] This embodiment provides a chip read / write capability testing device. By configuring the read / write path width and address range in the configuration information, it ensures that the test execution device can correctly configure the general input / output module, thereby accurately sending and receiving signals and improving the accuracy of the test. The initialization and configuration of the general input / output module can be adjusted according to different chips and test requirements, improving the system's flexibility and adaptability, thereby achieving the effect of improving test quality and compatibility.

[0103] In some embodiments, the configuration information also includes the power supply voltage of the chip under test; the test execution device 12 also includes a power module 122;

[0104] The main control device 11 is also used to send initialization commands to the test execution device 12;

[0105] The test execution device 12 is used to initialize the power module 122 based on the initialization command; the power module 122 is used to power on the chip under test based on the power supply voltage of the chip under test.

[0106] The main control device 11 sends an initialization command to the test execution device 12, so that the test execution device 12 initializes the power module 122, which can enable the power module 122 to power on the chip under test according to the configured power supply voltage.

[0107] After the chip under test is powered on, the test execution device 12 can generate control signals, address signals and sample data according to the test instructions, and transmit or interact with the control signals, address signals and data signals.

[0108] This embodiment provides a chip read / write capability testing device. By configuring the correct power supply voltage, it ensures that the chip under test can operate safely during the test and avoids chip damage caused by voltage mismatch. The read / write path width, address range, and power supply voltage of the chip under test in the configuration information ensure that the test execution device can correctly configure the general input / output module and power supply module, thereby accurately sending and receiving signals, improving the accuracy of the test, and thus achieving the effect of improving test quality and compatibility.

[0109] In some embodiments, the initialization of the test execution device 12 also includes the initialization of the timer 123. The configuration information also includes a clock selection signal; the test execution device 12 also includes the timer 123.

[0110] The main control device 11 is also used to send initialization commands to the test execution device 12;

[0111] The test execution device 12 is used to initialize the timer 123 based on the initialization instruction;

[0112] When the clock selection signal is the first selection signal, the timer 123 is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is the second selection signal, the timer 123 is used to generate the external clock signal and output the external clock signal to the chip under test.

[0113] The clock selection signal can specify the clock source for the chip under test (DUT), used to select either an on-chip clock signal or an external clock signal. Timer 123 is used to obtain the clock selection signal based on the clock source signal and to synchronize the on-chip clock signal on the DUT, or to generate an external clock signal and send it to the DUT.

[0114] It should be noted that in this embodiment, a timer is used to synchronize the on-chip clock signal or generate an external clock signal. However, in other embodiments, the test execution device 12 can be designed differently based on different application scenarios. For example, the test execution device 12 can generate an external clock signal in the following ways: using a crystal oscillator, controlling the voltage source to change periodically through programming, configuring a corresponding waveform generator or function generator, etc. Similarly, the test execution device 12 can also use other methods to synchronize the clock signal, and this application does not impose specific limitations. In this embodiment, after sending the initialization command, the general-purpose input / output module 121, the timer 123, and the power supply module 122 are initialized according to the initialization command, so that the power supply module 122 powers on the chip under test, the timer 123 generates an external clock signal or synchronizes the on-chip clock signal, and the general-purpose input / output module 121 generates control signals, address signals, and sample data according to the configuration.

[0115] This embodiment provides a chip read / write capability testing device. By using the clock selection signal in the configuration information, it ensures that the test execution device can correctly configure the timer module and generate a suitable clock signal, thereby improving the accuracy of the test. Through the clock selection function of the timer module, it ensures that precise clock synchronization can be achieved when using an on-chip clock or an external clock, improving the reliability and consistency of the test, thereby achieving the effect of improving test quality and compatibility.

[0116] In some embodiments, the main control device is further configured to send a query instruction to the test execution device; the test execution device is further configured to send the test results of the chip under test and / or test results that do not meet preset conditions to the main control device based on the query instruction.

[0117] The query command can be used to query the test results of chips that do not meet preset conditions. The main control device can send the query command in real time to obtain the real-time test results of the chips under test, or it can be sent after some or all of the chips under test have been tested, or it can be sent based on user operation. This embodiment does not limit the scope of the query command.

[0118] Based on the query command, test results from the chip under test that do not meet the preset conditions are sent to the main control device. This can be achieved by responding to the query command, filtering the test results to obtain a set of test results that do not meet the preset conditions, and then sending these results to the main control device. Furthermore, the test results may include information such as exception type, exception address, and exception data to help users quickly locate and resolve faults. For example, exception types may include data mismatch, read / write timeout, etc.

[0119] This embodiment provides a chip read / write capability testing device. Through a query command and a feedback mechanism for specific test results, users can more efficiently obtain and analyze test results, especially those that do not meet preset conditions. This helps to quickly locate and solve problems. At the same time, by only sending test results that do not meet preset conditions, the amount of data transmitted is reduced, and the system's response speed and efficiency are improved, thereby achieving the effect of improving testing efficiency.

[0120] In some embodiments, the main control device is further configured to send a standby command to the test execution device; the test execution device is configured to, based on the standby command, close the connection with the chip under test and power down the chip under test.

[0121] The standby command is used to control the test execution device to be in standby mode. After the test execution device enters standby mode, it can wait for the initialization command to be received again, power on the chip under test, and configure the general input / output module and timer.

[0122] This embodiment provides a chip read / write capability testing device. By disconnecting the connection with the chip under test and powering it off, it can prevent accidental current flow or signal interference in non-testing states, thus protecting the safety of the chip under test and the testing device. Safely disconnecting the connection and powering off can also reduce wear and tear on the device, extend the service life of the testing device and the chip under test, and reduce equipment maintenance costs.

[0123] To more clearly illustrate the technical solution of this application, a detailed embodiment is also provided.

[0124] In one embodiment, a chip read / write capability testing device is provided for testing the read / write performance of an SRAM memory chip, such as... Figure 4As shown, it includes a main control unit and a test execution unit. The chip under test is a chip with SRAM storage units, and its external interface can be divided into three groups: a data path (i.e., data written / read); an address path (i.e., the address for writing / reading data); and a control path.

[0125] The control path includes at least: a read / write control signal to control whether the current operation is writing or reading; and at least one clock signal, which can be generated internally by the chip under test and needs to be output to the outside of the chip, or it can be input from an external source.

[0126] The test execution device is used for:

[0127] (1) Clock generation or synchronization: when the clock of the chip under test is input from the outside, the required clock is generated; when the clock is generated internally by the chip under test, the clock is synchronized.

[0128] (2) Based on the clock signal, output or read the required control, address and data path signals within the corresponding time window.

[0129] (3) Without affecting the output and reading of control, address and data path signals, complete the real-time analysis of the read data, determine whether the data meets the expected results, and save the addresses and data that do not meet the expected results.

[0130] (4) Without affecting the output and input of control, address, and data path signals, respond to requests from the master control device via short-distance communication cables and protocols, including: (a) requests to adjust the measurement strategy and (b) requests to query addresses and data that do not meet expectations. After addresses and data that do not meet expectations are fed back to the master control device, the fed-back results can be discarded in order to reduce the storage space occupied by the test execution device.

[0131] The external clock signal can be generated by using a crystal oscillator, programming the voltage source to change periodically, or configuring the test execution device with a corresponding waveform generator or function generator to generate the clock. The on-chip clock signal of the chip under test can be generated by using a numerically controlled ring oscillator, a voltage-controlled ring oscillator, a phase-locked loop, or other circuits.

[0132] Synchronous clock signals refer to the synchronization of the output and capture signals of the test execution device with the operating clock of the chip under test (DUT). Since SRAM circuits are synchronous clock circuits, the start of read / write operations is triggered by a specific clock edge. Therefore, the operation of the test equipment requires a synchronous clock signal to drive and trigger the same operation, such as a timer. The test equipment has an internal high-frequency clock of known frequency that drives a counter. When a clock signal under test is input to the test equipment, the edge of the clock signal triggers the counter to zero. The maximum count value recorded by the counter is the ratio of the internal and external clock frequencies, thus allowing the measurement of the clock frequency under test. The test equipment can then use the counter value to complete the signal output and capture at the corresponding time points.

[0133] The main control device is used for:

[0134] (1) Send instructions to the test execution device via short-distance communication cables and protocols to control the latter's measurement strategy and read addresses and data that do not meet the expected results;

[0135] (2) Send the collected addresses and data that do not meet the expected results to the database through long-distance communication or wireless communication; or store the addresses and data that do not meet the expected results in a large-capacity memory.

[0136] In one specific embodiment, the main control device possesses strong communication and / or storage capabilities and supports at least one short-range communication protocol, such as I2C, SPI, or UART, and at least one long-range / wireless communication protocol, such as Ethernet or WiFi. The test execution device possesses strong real-time control capabilities and supports at least one short-range communication protocol, such as I2C, SPI, or UART. The test execution device also possesses high real-time control capabilities to meet the real-time requirements of data, address, and control path signals.

[0137] In scenarios where the chip under test (DUT) is an SRAM memory chip, its operating frequency is typically between 1MHz and 2MHz. If an internal clock signal is generated, its frequency will also be within the 1MHz to 2MHz range. Therefore, the test execution device must be capable of providing a 1MHz to 2MHz clock signal and achieving good real-time control within this clock frequency range.

[0138] If the real-time requirements of the chip under test (DUT) within its operating frequency range, as well as the requirements for long-distance communication, wireless communication, or large-capacity storage, can be met, the main control unit and the test execution unit can be integrated into the same device. When the main control unit and the test execution unit are the same device, short-distance communication between them becomes internal data transmission, and standard protocols such as I2C, SPI, and UART are not required.

[0139] The operation of a chip read / write capability testing device may include the following steps:

[0140] The main control device performs the following operations:

[0141] (1) The main control device is initialized by sending a command to the test execution device through short-range communication to initialize the latter.

[0142] (2) The main control device sends configuration information to the test execution device according to the design of the target chip under test, including: data path width (e.g., 32), address path width (e.g., 18), address range (e.g., 0x00000 ~ 0x3FFFF, where 0x indicates that the following numbers are hexadecimal numbers), power supply voltage of the chip under test, clock source (clock selection signal) of the chip under test, and measurement strategy. For example, one of the strategies includes four test steps, namely, write all 1, read all 1, write all 0 and read all 00.

[0143] (3) The main control device sends a start measurement command to the test execution device.

[0144] (4) The main control device sends a measurement result query command to the test execution device at certain time intervals.

[0145] (5) If the test execution device finds results that do not meet expectations during the measurement process, it will feed back the relevant signals to the main control device. The main control device will send the signals to the database via long-distance communication or wireless communication, or store them in a large-capacity storage, depending on the configuration.

[0146] (6) When the response of the query command is that the measurement is finished, send a measurement standby command to the test execution device and then end the measurement.

[0147] The test execution device performs the following:

[0148] (1) After powering on, it enters standby mode and waits for commands from the main control device.

[0149] (2) Upon receiving the initialization command, initialize each module, including the general-purpose input / output module, the power supply module, the timer, etc. Among them, the general-purpose input / output module is used to output and capture test signals; the power supply module is used to supply power to the chip under test; and the timer is used to synchronize the on-chip clock signal of the test chip or provide an external clock signal to the test chip.

[0150] (3) After receiving the configuration information, power on the chip under test according to the power supply voltage information, configure the general input / output module as a data path, address path and control path; save the data bit width, address bit width and address range; configure the timer; if the clock source is the test execution device, output the timer clock after certain steps; if the clock source is the chip under test, input the clock signal to the timer in order to understand the actual frequency; initialize the measurement data according to the measurement strategy.

[0151] (4) After receiving the start measurement command, the chip under test is read sequentially according to the measurement strategy, data bit width, address bit width, and address range configuration. For example, the measurement strategy is "all write 1, all read 1, all write 0, all read 0", the data bit width is 32 bits, the address bit width is 18 bits, and the address range is 0x00000~0x3FFFF. First, it writes all 32 bits of 1s sequentially from address 0x00000 to 0x3FFFF; then, it reads data sequentially from address 0x00000 to 0x3FFFF. The expected result should be all 32 bits of 1s. If not, the addresses and data that do not meet the expectations are temporarily stored, awaiting query from the master control device. Next, it writes all 32 bits of 0s sequentially from address 0x00000 to 0x3FFFF; then, it reads data sequentially from address 0x00000 to 0x3FFFF. The expected result should be all 32 bits of 0s. If not, the addresses and data that do not meet the expectations are temporarily stored, awaiting query from the master control device. Finally, it enters the measurement completion state, awaiting query from the master control device.

[0152] (5) During the measurement, a query command will be received from the main control device. If there are addresses and data that do not meet expectations, the addresses and data that do not meet expectations will be reported back, and the relevant records will be discarded; if there is no data that does not meet expectations, the measurement will be reported as in progress or as finished, depending on the current measurement status.

[0153] (6) Upon receiving the standby command, if there is a clock output, turn off the clock output; turn off the timer; configure all general-purpose input / output modules to a high-impedance state, i.e., disconnect them from the chip under test, thus powering down the chip under test. Then enter the standby state. While in standby state, the power supply of the test execution device can be safely turned off at any time.

[0154] This embodiment provides a chip read / write capability testing device that can select either the on-chip clock signal of the chip under test or the external clock signal of the testing device as the test clock signal. This overcomes the limitations of traditional devices in clock source adaptability, enabling highly compatible read / write tests for various chip types, thereby reducing costs and improving compatibility. By determining sample data based on the aforementioned testing strategy, more comprehensive and in-depth testing services can be provided for diverse testing needs, improving testing quality and efficiency. Bit-by-bit comparison of sample data and read data ensures the accuracy of test results. Automated data comparison and error logging improve the efficiency of fault diagnosis, further enhancing testing quality and efficiency. By setting up first, second, and third paths, the testing device can more efficiently and accurately complete chip read / write capability tests, meeting the testing needs of different types of chips and improving testing quality and compatibility. The separate design of the main control unit and the test execution unit allows for flexible configuration and expansion of the test system, adapting to different types of chips and testing needs. Real-time communication between the main control unit and the test execution unit enables users to monitor test progress and results in real time and adjust test parameters promptly, thereby improving test quality and efficiency. The read / write path width and address range in the configuration information ensure that the test execution unit can correctly configure the general-purpose input / output modules, accurately sending and receiving signals and improving test accuracy. The initialization and configuration of the general-purpose input / output modules can be adjusted according to different chips and testing requirements, improving system flexibility and adaptability, thus enhancing test quality and compatibility. Correct power supply voltage configuration ensures the safe operation of the chip under test (DUT) during testing, avoiding chip damage due to voltage mismatch. The read / write path width, address range, and DUT power supply voltage in the configuration information ensure that the test execution unit can correctly configure the general-purpose input / output modules and power supply modules, accurately sending and receiving signals and improving test accuracy, thus enhancing test quality and compatibility. By configuring the clock source information, the test execution device can correctly configure the timer module to generate appropriate clock signals, thereby improving test accuracy. The timer module's clock selection function ensures precise clock synchronization when using either an on-chip clock or an external clock, improving test reliability and consistency, thus enhancing test quality and compatibility. Through query commands and feedback mechanisms for specific test results, users can more efficiently obtain and analyze test results, especially those that do not meet preset conditions, facilitating rapid problem identification and resolution. Furthermore, sending only test results that do not meet preset conditions reduces data transmission volume, improving system response speed and efficiency, thereby enhancing test efficiency.By disconnecting the connection to the chip under test (DUT) and powering it off, you can prevent accidental current flow or signal interference in non-testing states, protecting the DUT and test equipment. Safely disconnecting the connection and powering off can also reduce equipment wear, extend the lifespan of the test equipment and the DUT, and reduce equipment maintenance costs.

[0155] Each module in the aforementioned chip read / write capability testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0156] Based on the same inventive concept, this application also provides a chip read / write capability testing method for implementing the chip read / write capability testing device described above. The solution provided by this method is similar to the implementation described in the chip read / write capability testing device. Therefore, the specific limitations in one or more chip read / write capability testing method embodiments provided below can be found in the limitations of the chip read / write capability testing device described above, and will not be repeated here.

[0157] In one embodiment, this application provides a chip read / write capability testing method, applied to a chip read / write capability testing device, the chip read / write capability testing method comprising:

[0158] Based on the received control commands, control signals, address signals, and sample data are generated and sent to the chip under test; the control commands include a clock selection signal.

[0159] When the clock selection signal is the first selection signal, the on-chip clock signal of the chip under test (DUT) is acquired, and control signals, address signals, sample data are sent to the DUT, as well as read data is received; wherein, the control signal includes a clock signal, which is generated based on the on-chip clock signal; when the clock selection signal is the second selection signal, control signals, address signals, sample data are sent to the DUT, as well as read data is received; wherein, the control signal includes a clock signal, which is generated based on the operating frequency of the DUT.

[0160] The test results of the chip under test are determined by using the sample data and the read data.

[0161] In some embodiments, the control instructions include a test strategy, which includes multiple methods for verifying the read / write performance of the chip under test; the test equipment is also used to determine sample data based on the test strategy.

[0162] In some embodiments, determining the test result of the chip under test using the sample data and the read data includes: determining the test result of the chip under test based on the matching of the sample data and the read data.

[0163] In some embodiments, the connection path between the test device and the chip under test includes a first path, a second path, and a third path connection, and the sending of read / write control signals, sending of address signals, and sending of sample data or receiving of read data includes:

[0164] The address signal is transmitted through the first path; the address signal includes a read / write address.

[0165] Data signals are transmitted through the second channel, and the data signals include sample data or read data.

[0166] Control signals are transmitted through the third channel, and the control signals include read / write control signals and clock signals.

[0167] In some embodiments, the device configures itself based on configuration information corresponding to the chip under test; generates and sends control signals, address signals, and sample data to the chip under test based on test instructions, and receives read data; and determines the test result of the chip under test through the sample data and the read data.

[0168] In some embodiments, the configuration information includes the read / write path width and address range; before generating control signals, address signals and sample data based on the received control instructions, the method further includes: initializing the general input / output module; and configuring the initialized general input / output module based on the read / write path width and address range.

[0169] In some embodiments, the configuration information further includes the power supply voltage of the chip under test; before generating control signals, address signals and sample data based on the received control instructions, the method further includes: initializing the power supply module; the power supply module is used to power on the chip under test based on the power supply voltage of the chip under test.

[0170] In some embodiments, the configuration information further includes a clock selection signal; before generating the control signal, address signal, and sample data based on the received control instructions, the method further includes: initializing a timer; when the clock selection signal is a first selection signal, the timer is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is a second selection signal, the timer is used to generate a clock signal based on the operating frequency of the chip under test and send the clock signal to the chip under test.

[0171] In some embodiments, after determining the test results of the chip under test using the sample data and the read data, the method further includes: generating a query instruction; and based on the query instruction, determining the test results of the chip under test that do not meet preset conditions.

[0172] In some embodiments, after determining the test result of the chip under test using the sample data and the read data, the method further includes: generating a standby command; based on the standby command, closing the connection with the chip under test, and powering down the chip under test.

[0173] Example 2

[0174] like Figure 1 As shown, a chip read / write capability testing system is provided, including the chip under test and the chip read / write capability testing device according to any one of the embodiments in Example 1 above;

[0175] The chip under test uses, for example Figure 5 The memory chip shown includes a clock selector, a configuration selector, an on-chip clock source, and a memory module; wherein:

[0176] The clock selector is used to determine the operating clock signal of the memory chip based on the control signal received from the chip read / write capability testing device, from the clock signal input from the chip read / write capability testing device and the on-chip clock signal generated by the on-chip clock source;

[0177] The configuration selector is used to configure the on-chip clock source and / or the memory module based on the control signal received from the chip read / write capability testing device.

[0178] The on-chip clock source is used to generate at least one on-chip clock signal based on the settings of the configuration selector;

[0179] The storage module is used to write the sample data and / or read the data from the control signal, address signal, sample data and working clock signal received from the chip read / write capability testing device.

[0180] In one embodiment, the memory chip further includes data pads, address pads, and control pads, used as external interfaces to transmit data signals, address signals, and control signals respectively.

[0181] In one embodiment, the control signal includes an input clock signal and a clock selection signal; when the clock selection signal is an external clock, the clock selector is used to receive the input clock signal and use the input clock signal as the operating clock signal of the memory chip.

[0182] In one embodiment, the control signal further includes a clock output signal; when the clock selection signal is an internal clock, the clock selector is used to receive the on-chip clock signal generated by the on-chip clock source and use the on-chip clock signal as the working clock signal of the memory chip; the working clock signal is also used to output the clock output signal to an external device.

[0183] In one embodiment, the control signal further includes a configuration selection signal and a configuration input signal; when the configuration selection signal is to use input configuration, the configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal.

[0184] In one embodiment, the control signal further includes a configuration protocol signal; the memory chip further includes a configuration register for storing preset configuration information; when the configuration selection signal is to use internal configuration, the configuration register is used to receive the configuration protocol signal and transmit the configuration information to the configuration selector; the configuration selector is used to configure the on-chip clock source and / or memory module based on the configuration information.

[0185] In one embodiment, the storage module includes a timing balancing module and multiple storage repositories, the timing balancing module being connected to each of the multiple storage repositories; the timing balancing module is used to receive a working clock signal, and transmit the working clock signal to the storage repositories after delay compensation based on delay parameters; the configuration selector further includes a delay configuration module, the delay configuration module being used to configure the delay parameters of the timing balancing module based on the received signal.

[0186] In one embodiment, the storage repository includes multiple storage repository units; the timing balancing module includes a delay main module and at least one delay adjustment module, the delay adjustment module being connected to the output terminal of the delay main module, wherein: the delay main module is used to delay the input working clock signal for a first time and then output a first signal; the delay adjustment module is used to receive corresponding delay parameters according to delay requirements, and after delaying the first signal for a second time, output a second signal to the multiple storage repository units; the Chebyshev distance or Euclidean distance between the delay adjustment module and the multiple storage repository units is equal.

[0187] In one embodiment, the on-chip clock source includes a clock adjuster and multiple on-chip clock generators, with different on-chip clock generators generating clock signals of different frequencies. Based on the configuration selector, a target clock generator is determined from the multiple on-chip clock generators, and the clock signal generated by the target clock generator is output to the clock adjuster. The clock adjuster fine-tunes the clock signal generated by the target on-chip clock generator based on a control signal to obtain a fine-tuned clock signal corresponding to the control signal, which serves as the final clock signal.

[0188] In one specific embodiment, the memory chip includes SRAM memory cells, such as... Figure 6 As shown, it includes three sets of external interfaces, including a data path for transmitting data to be written / read, an address path for transmitting addresses for data to be written / read, and a control path. Among them, the signals transmitted by the control path include at least: a read / write control signal for controlling whether the current operation is a write or a read, and at least one clock signal; in addition, the signals transmitted by the control path may also include: (1) a configuration protocol signal for configuring the configuration register inside the chip; (2) a configuration selection signal and a configuration input signal; (3) a clock selection signal, a clock input signal, and a clock output signal.

[0189] In this embodiment, the memory chip is an SRAM chip controlled by a clock signal. The clock signal can be generated internally by the SRAM chip, and the SRAM chip will output the internally generated clock signal to the outside of the chip. The clock signal can also be input by a chip read / write capability testing device.

[0190] This embodiment's memory chip includes multiple banks, each bank comprising at least one bank cell array, and each bank cell comprising at least one storage sub-cell. Multiple storage sub-cells within the same bank cell array constitute a storage sub-cell array. Each storage sub-cell in the array can share the same control logic circuit to achieve data storage. Since the banks are relatively large and may be distributed across various corners of the chip, and each bank cell requires data, address, delay selection, and a system clock, this embodiment uses a timing balancing module to address the clock signal delay issue in order to ensure that the delays of these signals reaching each bank cell are as consistent as possible.

[0191] The memory chip also includes a clock selector, which selects one of a clock input and an on-chip clock as the operating clock signal based on a clock selection signal. When the clock selection signal is an external clock, the clock selector receives the input clock signal and uses it as the operating clock signal for the memory chip. When the clock selection signal is an internal clock, the clock selector receives the on-chip clock signal generated by the on-chip clock source and uses it as the operating clock signal for the memory chip; the operating clock signal is also used as the clock output signal to external test equipment.

[0192] The memory chip also includes a configuration selector and a configuration register, the latter storing preset configuration information. When the configuration selection signal is for input configuration, the configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal. When the configuration selection signal is for internal configuration, the configuration register receives the configuration protocol signal and transmits the configuration information to the configuration selector; the configuration selector then configures the on-chip clock source and / or memory module based on the configuration information.

[0193] Depending on the clock selection signal and configuration selection signal in the control path, the memory chip in this embodiment can implement at least four operating modes:

[0194] Working Mode 1:

[0195] The clock selection signal selects the clock input as the operating clock signal for the memory chip, and the configuration selection signal selects the input configuration. The configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal.

[0196] In this mode, since the configuration selection signal selects to use the input configuration, the configuration information output by the configuration register is ignored. In this mode, the configuration protocol and the working content of the configuration register are not referenced.

[0197] Similarly, since the on-chip clock will be ignored when the clock selection signal uses the clock input signal, the operation of the on-chip clock source will be either disabled or ignored.

[0198] The signals input to the "timing balance module" include: data signals and address signals; operating clock signals, which are the system clock output by the clock input signal via the clock selector; and configuration input signals, which are the delay selection signals output by the clock source and delay configuration input via the configuration selector.

[0199] This operating mode is the basic operating mode, in which test signals, control signals and clock signals are directly driven by external test equipment. It offers high testing flexibility and the memory chip is not limited by the test equipment. However, it cannot run high-frequency tests, and the test speed and chip area are significantly reduced.

[0200] Working Mode 2:

[0201] The clock selection signal uses the clock input signal as the system's operating clock signal, while the configuration selection signal uses the internal configuration.

[0202] In this mode, since the on-chip clock will be ignored when the clock selection signal uses the clock input signal, the on-chip clock source will either be disabled or ignored.

[0203] Since the configuration selection signal uses internal configuration, namely the clock source and delay configuration internal signals, the corresponding configuration parameters are transmitted to the configuration register through the configuration protocol signal. The configuration selector configures the on-chip clock source and / or memory module based on the configuration parameters.

[0204] The signals input to the timing balancing module include: data signals and address signals; operating clock signals, which are system signals output from the clock input signal via the clock selector; and delay selection signals output from the configuration protocol signal via the configuration register and configuration selector.

[0205] In this operating mode, the clock and test signals are provided by external test equipment, while the control signals are provided by the memory chip itself. This ensures test flexibility while providing more control bits and reducing the number of configuration input I / O ports, but at the cost of test preparation time.

[0206] Working Mode 3:

[0207] The clock selection signal uses the on-chip clock as the system's operating clock signal, i.e., the on-chip clock signal is used as the system's operating clock signal. The configuration selection signal uses input configuration, and the configuration selector configures the on-chip clock source and / or memory module based on the configuration input signal.

[0208] In this mode, since the configuration selection signal uses input configuration, the configuration information output by the configuration register is ignored. The configuration protocol and the contents of the configuration register are not referenced in this mode. Because the clock selection signal uses the on-chip clock signal, multiple on-chip clock generators generate multiple clock sources. The clock source selection signal output by the configuration selector determines which on-chip clock generator's clock signal will be output to the on-chip clock, i.e., used as the on-chip clock signal.

[0209] The signals input to the timing balancing module include: data signals and address signals; operating clock signals, i.e., the system clock output by the on-chip clock signal via the clock selector; and configuration input signals, i.e., the delay selection signal output by the clock source and delay configuration input via the configuration selector.

[0210] In this operating mode, the clock signal is generated internally by the memory chip, and the external test equipment provides test and control signals. This can ensure a certain degree of test flexibility and improve the quality of the clock signal. However, the external test equipment has high requirements for clock synchronization with the internal clock of the memory chip and for the real-time performance of the external test equipment.

[0211] Working Mode 4:

[0212] The clock selection signal selects the on-chip clock as the system's operating clock signal, while the configuration selection signal selects the internal configuration.

[0213] In this mode, since the configuration selection signal uses the internal configuration (i.e., the internal clock source and delay configuration signals), the corresponding configuration parameters must be transmitted to the configuration register via the configuration protocol signal. The configuration selector then configures the on-chip clock source and / or memory module based on these parameters. Because the clock selection signal uses the on-chip clock signal, multiple on-chip clock generators generate multiple clock sources. The clock source selection signal output by the configuration selector determines which on-chip clock generator's clock signal will be output to the on-chip clock, i.e., used as the on-chip clock signal.

[0214] The signals input to the timing balancing module include: data signals and address signals; the operating clock signal, which is the system clock output by the on-chip clock signal through the clock selector; and the delay selection signal output by the configuration protocol signal through the configuration register and the configuration selector.

[0215] In this operating mode, the test signal, control signal, and clock signal are all generated internally by the memory chip, which can greatly improve the test frequency and better reflect the chip's read and write performance. However, it sacrifices test flexibility and requires additional design to complete the test and transmit the test results.

[0216] The memory chip in this embodiment can perfectly support at least four of the above-mentioned working modes, can match the read and write test requirements of different scenarios, supports high-frequency testing, can achieve precise timing control, and can be widely used in read and write tests of different memory chips.

[0217] Furthermore, the on-chip clock source also includes a data-controlled oscillator (DCO). A DCO is an oscillator based on digital signal processing technology. Its working principle is to adjust the oscillator frequency by controlling the frequency of a digital signal. The DCO, as an on-chip clock generation circuit, can provide different frequency ranges. In this embodiment, the clock signal is generated internally using a DCO to ensure that the frequency of the on-chip generated clock signal matches the chip's corresponding operating frequency.

[0218] The on-chip clock source includes multiple on-chip clock generators and clock adjusters. Different on-chip clock generators generate clock signals of different frequencies. The clock signal generated by the target clock generator is output to the clock adjuster. The clock adjuster fine-tunes the clock signal generated by the target on-chip clock generator based on control signals to obtain the fine-tuned clock signal corresponding to the control signals, which serves as the final clock signal. Figure 11 The diagram shown is a schematic representation of the overall structure of an on-chip clock signal generation circuit according to this embodiment. Figure 9 As shown, digital control performs path selection, and the frequency is coarsely adjusted by the effective number of stages in the ring oscillator circuit, thereby generating multiple frequencies, resulting in a wide adjustable frequency range. The single-stage delay of the ring oscillator in the clock adjuster is controlled based on the control current signal, so as to finely adjust the clock signal using the ring oscillator and obtain the oscillation frequency of the finely adjusted clock signal.

[0219] Specifically, the generation of the clock signal from the on-chip clock source may include the following steps:

[0220] Step S201: Determine the target on-chip clock generator from multiple on-chip clock generators based on the chip's operating frequency.

[0221] The frequency of the clock signal generated by the on-chip clock generator is within a preset frequency range; the operating frequency of the chip is within a preset frequency range, that is, this preset frequency range is based on the operating frequency of the chip, and the operating frequency of the chip will be within this preset frequency range.

[0222] An on-chip clock source can include multiple on-chip clock generators and clock adjusters. Different on-chip clock generators generate clock signals of different frequencies, enabling the memory chip to operate at different frequencies.

[0223] Typically, a preset frequency range can be determined based on the operating frequency required for the memory chip to operate. Specifically, the operating frequency of the memory chip must fall within the preset frequency range. Furthermore, the on-chip clock generator whose clock signal frequency falls within the preset frequency range is identified as the target on-chip clock generator. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is within the same frequency range as the operating frequency of the memory chip, thus achieving coarse adjustment of the clock signal on the memory chip.

[0224] Step S202: Input multiple control signals into the clock adjuster to fine-tune the clock signal and obtain the oscillation frequency of the fine-tuned clock signal corresponding to each control signal.

[0225] The clock adjuster includes adjusting single-stage delays based on control signals.

[0226] Furthermore, multiple control signals are input into the clock adjuster. The single-stage delay of the clock adjuster corresponding to each control signal is different. Thus, by adjusting the single-stage delay of the clock adjuster through multiple control signals, the clock signal output by the on-chip clock generator is adjusted, and the oscillation frequency of the clock signal corresponding to each control signal is obtained.

[0227] Step S203: Determine the target control signal based on the operating frequency of the memory chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal.

[0228] Furthermore, the control signal corresponding to the clock signal oscillation frequency that is consistent with the operating frequency of the memory chip or within a preset error range is determined as the target control signal.

[0229] Step S204: Based on the target on-chip clock generator and the target control signal, control the generation of the final clock signal.

[0230] Furthermore, a target on-chip clock generator is determined from multiple on-chip clock generators, and the target control signal is input into the clock adjuster. The clock adjuster is then used to fine-tune the clock signal generated by the target on-chip clock generator to obtain the final clock signal, so that the oscillation frequency of the final clock signal can be consistent with the chip's operating frequency or within a preset error range.

[0231] In the above implementation process, based on the operating frequency of the memory chip, a target on-chip clock generator is determined from multiple on-chip clock generators. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is within the same frequency range as the operating frequency of the memory chip, achieving coarse adjustment of the clock signal. Furthermore, multiple control signals are input into the clock adjuster, thereby adjusting the single-stage delay of the clock adjuster through each control signal, thus adjusting the clock signal output by the target on-chip clock generator. By determining the target control signal based on the operating frequency of the memory chip and the oscillation frequency of the finely adjusted clock signal corresponding to each control signal, fine adjustment of the clock signal is achieved, ensuring that the frequency of the final output clock signal is consistent with the operating frequency of the chip or within a preset error range.

[0232] Furthermore, the control signals are digital signals, such as... Figure 7 As shown, the clock adjuster includes a digitally controlled current source, a ring oscillator, and a feedback loop. A digital signal is input to the digitally controlled current source, which outputs a control current signal. This control current signal can control the output frequency of the ring oscillator by controlling a single-stage delay. Inputting multiple control signals into the clock adjuster to fine-tune the clock signal and obtain the fine-tuned clock signal oscillation frequency corresponding to each control signal can include the following steps:

[0233] Step 1: The current source component in the clock regulator converts the digital signal into a control current signal.

[0234] Step 2: Based on the control current signal, control the single-stage delay of the ring oscillator in the clock adjuster to fine-tune the clock signal and obtain the oscillation frequency of the fine-tuned clock signal.

[0235] For example, the control signal can be a digital signal, and the frequency formula of the ring oscillator is:

[0236]

[0237] Among them, f osc Let denot n represent the frequency of the ring oscillator, n represent the number of stages in the ring oscillator, and τ represent the single-stage delay of the ring oscillator. Therefore, the frequency of the ring oscillator can be adjusted by controlling its number of stages and single-stage delay.

[0238] Specifically, after multiple digital signals are input into the clock regulator, the current source component in the clock regulator converts the digital signals into control current signals. Further, the single-stage delay of the ring oscillator in the clock regulator is controlled by the control current signal. By adjusting the single-stage delay of the ring oscillator, the clock signal is fine-tuned, and the oscillation frequency of the fine-tuned clock signal corresponding to each digital signal is obtained.

[0239] In the above implementation process, the digital signal is converted into a control current signal by the current source component in the clock regulator, and the single-stage delay of the ring oscillator in the clock regulator is controlled by the control current signal, thereby realizing the fine adjustment of the clock signal by the ring oscillator.

[0240] Furthermore, based on the chip's operating frequency and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, the target control signal is determined, including: among the oscillation frequencies of the fine-tuned clock signals corresponding to multiple control signals, the control signal corresponding to the clock signal that is consistent with the operating frequency or within a preset error range is determined as the target control signal.

[0241] Specifically, when determining the target control signal, the control signal corresponding to the clock signal that is consistent with the operating frequency or within the preset error range among the oscillation frequencies of the finely tuned clock signals corresponding to multiple control signals is determined as the target control signal. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is consistent with the chip's operating frequency or within the preset error range, thus ensuring that the clock signal frequency of the on-chip generator in the chip is within the corresponding chip's operating frequency range.

[0242] Furthermore, the single-stage delay of the ring oscillator in the clock adjuster based on the control current signal, in order to fine-tune the clock signal using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal, may include the following steps:

[0243] Step 1: Reduce the oscillation frequency to obtain the reduced oscillation frequency.

[0244] Step 2: Deduplicate the oscillation frequency after frequency reduction to obtain the deduplicated oscillation frequency.

[0245] Step 3: Convert the deduplicated oscillation frequency into a feedback current signal through the feedback loop in the clock adjuster.

[0246] Step 4: Based on the control current signal and the feedback current signal, control the single-stage delay of the ring oscillator in the clock adjuster to fine-tune the clock signal using the ring oscillator and obtain the oscillation frequency of the fine-tuned clock signal.

[0247] To achieve a relatively linear oscillator using a digitally controlled current source, the DCO function can be improved through negative feedback techniques. The feedback loop is formed by sampling the output and mixing it with the input. Because the frequency of the oscillator output is too high, there is no time to directly sample through capacitor charging and discharging.

[0248] Specifically, the output frequency of the ring oscillator can be reduced using a frequency divider circuit to obtain the reduced oscillation frequency. This reduced oscillation frequency is then deduplicated using a non-overlapping pulse generation circuit to obtain the final oscillation frequency. Furthermore, the deduplicated oscillation frequency is converted into a feedback current signal through a feedback loop in a clock regulator.

[0249] Furthermore, the control current signal and the feedback current signal are combined, and the combined signal controls the single-stage delay of the ring oscillator in the clock adjuster, so as to use the ring oscillator to fine-tune the clock signal and obtain the oscillation frequency of the fine-tuned clock signal.

[0250] The target control signal is determined based on the chip's operating frequency and the oscillation frequency of the clock signal corresponding to each control signal. This also includes ensuring that the stability of the oscillation frequency of the fine-tuned clock signal is higher than a preset value.

[0251] Furthermore, after fine-tuning the clock signal of the ring oscillator, the stability of the oscillation frequency of the fine-tuned clock signal is higher than the preset value. Specifically, this preset value can be determined according to the chip's operating frequency, application scenario requirements, etc.

[0252] In the above implementation process, the frequency of the ring oscillator output is reduced by a frequency divider circuit. Instead of an overlapping pulse generation circuit, the frequency of the reduced oscillation frequency is deduplicated. The deduplicated oscillation frequency is then converted into a feedback current signal through the feedback loop in the clock regulator. The control current signal and the feedback current signal are then combined, and the combined signal controls the single-stage delay of the ring oscillator in the clock regulator, thus realizing the loop regulation of the clock regulator.

[0253] Furthermore, the current source component is also used to generate various proportional currents via digital signal control.

[0254] The current source assembly includes a current source, a matching transistor, and a digitally controlled transistor. The first terminal of the matching transistor is connected to the current source, the second terminal of the matching transistor is connected to the digitally controlled transistor, and the third terminal of the matching transistor is connected to a ring oscillator. The matching transistor is used to stabilize the current output by the current source and input the stabilized current into the ring oscillator through the third terminal of the matching transistor. The first terminal of the digitally controlled transistor is connected to a first digital signal, and the second terminal of the digitally controlled transistor is connected to the second terminal of the matching transistor. The digitally controlled transistor is used to control the magnitude of the current output by the matching transistor based on the first digital signal.

[0255] Specifically, the current source component generates various proportional currents through digital signal control. Figure 8 This is a circuit diagram of a current source component provided in an embodiment of this application, such as... Figure 8As shown, the circuit includes a current source, a matching transistor, and a digitally controlled transistor. The matching transistor (in the solid box) replicates the current from the stable current source (Iref) in binary mode via a current mirror. The digitally controlled transistor (in the dashed box) is the parallel binary weighted transistor controlled by the digital input code. The transistor is turned on / off using digital codes, thus determining the current through Ms1. The output node is connected to a single, permanently conducting transistor (MS2), and the binary weighted transistor is separated from this node to reduce the impact of voltage level changes in the digital control signal on the current value. The transistor size increases in binary order. This section uses eight digital signals C0, C1, C2… and C8 as controllable signal inputs, corresponding to 512 input levels from 00000000 to 11111111, providing 512 different current values.

[0256] In the above implementation process, a current source component consisting of a current source, a matching transistor, and a digitally controlled transistor is used to generate different proportional currents by a digitally controlled current source.

[0257] Furthermore, the ring oscillator in the clock regulator includes multiple differential units, each of which includes a latch and two inverters for driving current into the latch. The latch includes two cross-coupled inverters.

[0258] For example, Figure 9 This is a schematic diagram of a ring oscillator provided in an embodiment of this application, as shown below. Figure 9 The oscillator shown is a ring structure (a), consisting of four differential units. Figure 9 (c) in the diagram represents the current source component. Each differential unit (b) is implemented using a cross-coupled structure, which includes two cross-coupled inverters (solid boxes) used as latches and two inverters (dashed boxes) responsible for driving current into the latches. To change the latching speed, and thus the delay of each unit, we varied the current intensity (cs1 / cs2) driving the inverter. To improve the jitter performance of the oscillator, an inverter is used in each output node to adjust the swing level. The oscillator produces eight different phases at the output.

[0259] In the above implementation, a ring oscillator structure consisting of four differential units, including latches and two inverters for driving current into the latches, and the latches including two cross-coupled inverters, enables the ring oscillator to output multiple different phases.

[0260] In one embodiment, the plurality of on-chip clock generators include a ring oscillator circuit and a multiplexer. Determining a target on-chip clock generator from the plurality of on-chip clock generators based on the chip's operating frequency may include the following steps:

[0261] Step 1: The ring oscillator circuit adjusts the effective number of stages in the oscillation path through a multiplexer to generate clock signals of different frequencies;

[0262] Step 2: Input the selection signal into the multiplexer to determine the effective number of stages of the ring oscillator circuit, thereby determining the target on-chip clock generator; the frequency of the clock signal generated by the target on-chip clock generator is within the preset frequency range; the operating frequency of the chip is within the preset frequency range.

[0263] Specifically, Figure 10 This is a schematic diagram of the circuit structure of multiple on-chip clock generators (including a ring oscillator circuit and a multiplexer) provided in the embodiments of this application. It includes a ring oscillator circuit composed of a NAND gate, K delay units, and a 16-to-1 multiplexer, where K is an even number greater than 0. The NAND gate includes two input terminals and one output terminal, one of which, EN, is used to connect an external start control signal to control the switching of the circuit. The delay units are connected in series, with the input terminal of the first delay unit connected to the output terminal of the NAND gate, and the output terminal of the last delay unit connected to one input of the 16-to-1 multiplexer. Each delay unit consists of an odd number of inverters. The 16-to-1 multiplexer includes 16 inputs (dividing the K delay units into 16 equal segments), four digital control selection signals S1 / S2 / S3 / S4, and one output. The output terminal of the 16-to-1 multiplexer is connected to the other input terminal of the NAND gate, forming a ring oscillator structure. Four digital signals S1 / S2 / S3 / S4 are used as controllable signal inputs, corresponding to 16 input levels from 0000 to 1111, with 0000 corresponding to the highest effective level and the lowest oscillation frequency output. Coarse frequency adjustment is achieved by selecting a 16-to-1 multiplexer to control the path selection and adjusting the effective level in the oscillation path.

[0264] When determining the target on-chip clock generator, the ring oscillator circuit adjusts the effective number of stages in the oscillation path through a multiplexer to generate clock signals of different frequencies.

[0265] Furthermore, the selection signal is input to the multiplexer to determine the effective number of stages of the ring oscillator circuit. When the frequency of the clock signal generated by a certain on-chip clock generator is within the preset frequency range, and the operating frequency of the chip is within the preset frequency range, the on-chip clock generator is determined as the target on-chip clock generator.

[0266] In the above implementation process, the 16-to-1 multiplexer is controlled by the selection signal to select the path, and the effective number of stages in the oscillation path is adjusted to determine the target on-chip clock generator, thereby achieving coarse frequency adjustment. This ensures that the frequency of the clock signal generated by the target on-chip clock generator is within the preset frequency range, and the operating frequency of the chip is within the preset frequency range.

[0267] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0268] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, it implements the chip read / write capability testing method of any of the above embodiments:

[0269] Based on the received control commands, control signals, address signals, and sample data are generated; the control signals include read / write control signals and clock selection signals; and the control signals are sent to the chip under test.

[0270] When the clock selection signal is the first selection signal, the on-chip clock signal of the chip under test is acquired, and read / write control signals, address signals, sample data, and read data are sent based on the on-chip clock signal.

[0271] When the clock selection signal is the second selection signal, the external clock signal generated by the chip read / write capability testing device is sent to the chip under test, and read / write control signal, address signal, sample data, and read data are sent based on the external clock signal.

[0272] The test results of the chip under test are determined by using the sample data and the read data.

[0273] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0274] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0275] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0276] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip read / write capability testing device, characterized in that, The chip read / write capability testing equipment is electrically connected to the chip under test (DUT). The testing equipment generates and sends control signals, address signals, and sample data to the DUT based on received control commands. The control commands include a clock selection signal. The DUT includes a clock selector, a configuration selector, an on-chip clock source, and a memory module. The control signals also include a configuration selection signal and a configuration input signal. When the configuration selection signal is set to input configuration, the configuration selector configures the on-chip clock source and / or the memory module based on the configuration input signal. The on-chip clock source includes multiple on-chip clock generators and clock adjusters, with different on-chip clock generators generating clock signals of different frequencies. The clock adjuster includes a digitally controlled current source, a ring oscillator, and a feedback loop. A digital signal is input to the digitally controlled current source, which outputs a control current signal. The control current signal and the feedback current signal control the output frequency of the ring oscillator through a single-stage delay. The feedback current signal is obtained by down-converting and deduplicating the oscillation frequency through the feedback loop in the clock adjuster. The oscillation frequency stability of the fine-tuned clock signal is higher than a preset value. The process involves several steps: First, based on the operating frequency of the memory chip, a target on-chip clock generator is selected from multiple on-chip clock generators. The frequency of the clock signal generated by the target on-chip clock generator is aligned with the operating frequency of the memory chip, achieving coarse adjustment of the clock signal. Second, multiple control signals are input into a clock adjuster to fine-tune the clock signal, obtaining the oscillation frequency of the fine-tuned clock signal corresponding to each control signal. Third, based on the operating frequency of the memory chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, a target control signal is determined. Finally, a ring oscillator is used to fine-tune the clock signal, obtaining the oscillation frequency of the fine-tuned clock signal. When the clock selection signal is the first selection signal, the on-chip clock signal of the chip under test is acquired, and control signals, address signals, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal; When the clock selection signal is the second selection signal, a control signal, an address signal, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, which is generated based on the operating frequency of the chip under test; The chip read / write capability testing device is also used to determine the test result of the chip under test by using the sample data and the read data.

2. The chip read / write capability testing device according to claim 1, characterized in that, The control instructions include a test strategy, which includes multiple methods for verifying the read / write performance of the chip under test. The testing equipment is also used to determine sample data based on the testing strategy.

3. The chip read / write capability testing device according to claim 1, characterized in that, Also used for: Based on the matching of the sample data and the read data, the test result of the chip under test is determined.

4. The chip read / write capability testing device according to claim 1, characterized in that, The connection path between the testing equipment and the chip under test includes a first path, a second path, and a third path. The chip read / write capability testing equipment is also used for: The address signal is transmitted through the first path; the address signal includes a read / write address. Data signals are transmitted through the second channel, and the data signals include sample data or read data. Control signals are transmitted through the third channel, and the control signals include read / write control signals and clock signals.

5. The chip read / write capability testing device according to claim 1, characterized in that, The control commands include configuration information and test commands; the chip read / write capability testing equipment includes a main control device and a test execution device, and the main control device is communicatively connected to the test execution device. The main control device is configured to: send configuration information corresponding to the chip under test to the test execution device; and send test commands to the test execution device. The test execution device is configured to: configure itself based on the configuration information; generate and send control signals, address signals and sample data to the chip under test based on the test instructions, and receive read data; and determine the test result of the chip under test through the sample data and the read data.

6. The chip read / write capability testing device according to claim 5, characterized in that, The configuration information includes the read / write path width and address range; the test execution device includes a general-purpose input / output module. The main control device is also used to send initialization commands to the test execution device; The test execution device is used to initialize the general input / output module based on the initialization instruction; and to configure the initialized general input / output module based on the read / write path width and address range.

7. The chip read / write capability testing device according to claim 5, characterized in that, The configuration information also includes the power supply voltage of the chip under test; the test execution device also includes a power module. The main control device is also used to send initialization commands to the test execution device; The test execution device is used to initialize the power module based on the initialization command; the power module is used to power on the chip under test based on the power supply voltage of the chip under test.

8. The chip read / write capability testing device according to claim 5, characterized in that, The configuration information includes a clock selection signal; the test execution device also includes a timer; The main control device is also used to send initialization commands to the test execution device; The test execution device is used to initialize the timer based on the initialization instruction; When the clock selection signal is the first selection signal, the timer is used to synchronize the on-chip clock signal of the chip under test; when the clock selection signal is the second selection signal, the timer is used to generate a clock signal based on the operating frequency of the chip under test and send the clock signal to the chip under test.

9. The chip read / write capability testing device according to claim 5, characterized in that, The main control device is also used to send query commands to the test execution device; The test execution device is also used to send the test results of the chip under test and / or test results that do not meet the preset conditions to the main control device based on the query command.

10. The chip read / write capability testing device according to claim 5, characterized in that, The main control device is also used to send a standby command to the test execution device; The test execution device is used to disconnect the connection with the chip under test and power down the chip under test based on the standby command.

11. A method for testing chip read / write capabilities, characterized in that, The chip read / write capability testing method, applicable to chip read / write capability testing equipment, includes: Based on the received control commands, control signals, address signals, and sample data are generated and sent to the chip under test (DUT). The control commands include a clock selection signal, a configuration selection signal, and a configuration input signal. The DUT includes a clock selector, a configuration selector, an on-chip clock source, and a storage module. When the configuration selection signal is set to input configuration, the configuration selector configures the on-chip clock source and / or the storage module based on the configuration input signal. The on-chip clock source includes multiple on-chip clock generators and clock adjusters, with different on-chip clock generators generating clock signals of different frequencies. The clock adjuster includes a digitally controlled current source, a ring oscillator, and a feedback loop. A digital signal is input to the digitally controlled current source, and a control current signal is output. The control current signal and the feedback current signal control the output frequency of the ring oscillator by controlling a single-stage delay. The feedback current signal is obtained by converting the oscillation frequency through the feedback loop in the clock adjuster after the feedback loop performs frequency reduction and deduplication processing on the oscillation frequency; the stability of the oscillation frequency of the fine-tuned clock signal is higher than the preset value; wherein, according to the operating frequency of the memory chip, a target on-chip clock generator is determined from multiple on-chip clock generators, so that the frequency of the clock signal generated by the target on-chip clock generator is in the same frequency range as the operating frequency of the memory chip, thereby achieving coarse adjustment of the clock signal; multiple control signals are input into the clock adjuster to fine-tune the clock signal, and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal is obtained; based on the operating frequency of the memory chip and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, a target control signal is determined; the clock signal is fine-tuned using a ring oscillator, and the oscillation frequency of the fine-tuned clock signal is obtained; When the clock selection signal is the first selection signal, the on-chip clock signal of the chip under test is acquired, and control signals, address signals, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, and the clock signal is generated based on the on-chip clock signal; When the clock selection signal is the second selection signal, a control signal, an address signal, sample data are sent to the chip under test, and read data is received; wherein, the control signal includes a clock signal, which is generated based on the operating frequency of the chip under test; The test results of the chip under test are determined by using the sample data and the read data.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip read / write capability testing method as described in claim 11.

13. A chip read / write capability testing system, characterized in that, Includes the chip under test and the chip read / write capability testing device according to any one of claims 1 to 10; The chip under test is a memory chip; the memory chip includes a clock selector, a configuration selector, an on-chip clock source, and a memory module. The on-chip clock source includes multiple on-chip clock generators and clock adjusters, with different on-chip clock generators generating clock signals of different frequencies. The clock adjuster includes a digitally controlled current source, a ring oscillator, and a feedback loop. A digital signal is input to the digitally controlled current source, which outputs a control current signal. The control current signal and the feedback current signal control the output frequency of the ring oscillator by controlling a single-stage delay. The feedback current signal is obtained by the feedback loop in the clock adjuster after the feedback loop performs frequency down-conversion and deduplication processing on the oscillation frequency. The oscillation frequency stability of the fine-tuned clock signal is higher than a preset value. The process involves several steps: First, based on the operating frequency of the memory chip, a target on-chip clock generator is selected from multiple on-chip clock generators. The target on-chip clock generator's clock signal frequency is aligned with the memory chip's operating frequency, achieving coarse adjustment of the clock signal. Second, multiple control signals are input into a clock adjuster to fine-tune the clock signal, obtaining the oscillation frequency of the fine-tuned clock signal corresponding to each control signal. Third, based on the memory chip's operating frequency and the oscillation frequency of the fine-tuned clock signal corresponding to each control signal, a target control signal is determined. Finally, a ring oscillator is used to fine-tune the clock signal, obtaining the oscillation frequency of the fine-tuned clock signal. The clock selector is used to determine the operating clock signal of the memory chip based on the control signal received from the chip read / write capability testing device, from the clock signal input from the chip read / write capability testing device and the on-chip clock signal generated by the on-chip clock source; The configuration selector is used to configure the on-chip clock source and / or the memory module based on the control signal received from the chip read / write capability testing device; the control signal includes a configuration selection signal and a configuration input signal; when the configuration selection signal is to use input configuration, the configuration selector configures the on-chip clock source and / or the memory module based on the configuration input signal; The on-chip clock source is used to generate at least one on-chip clock signal based on the settings of the configuration selector; The storage module is used to write the sample data and / or read the data based on the control signal, address signal, sample data and working clock signal received from the chip read / write capability testing device.

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