Synchronization method of synchronization pulse signal

Abstract

The invention relates to a synchronization pulse signal synchronization method, belongs to the technical field of pulse signal synchronization, and solves the problems of low adjustment speed and low efficiency of a synchronization pulse signal synchronization method in the prior art. The method comprises the following steps: a source end periodically generates a synchronization pulse signal and sends the synchronization pulse signal to a destination end; the destination end judges whether the delay value of the synchronous pulse signal needs to be adjusted or not, if yes, the delay value of the received synchronous pulse signal is adjusted, and the delay value is recorded; otherwise, acquiring a historically recorded delay value, and delaying the received synchronization pulse signal according to the delay value; and sending the delayed synchronous pulse signal to a sampling circuit, and generating a pulse signal at a destination end. And rapid and stable pulse signal synchronization is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of pulse signal synchronization, and particularly to a synchronization method for synchronous pulse signals. Background Art

[0002] When synchronizing signals, the circuit receiving the synchronous pulse signal needs to ensure that the phase of the pulse signal sampled each time is fixed. However, even for the same clock source, after frequency multiplication and frequency division operations within different circuits, the phase relationship between the working clock of the circuit receiving the synchronous pulse signal and the synchronous pulse has a certain randomness. At the same time, hardware differences will also bring uncertainties. The superposition of the two leads to the uncertainty of sampling the synchronous pulse signal by the circuit receiving the synchronous pulse signal, which will cause the rising edge of the synchronous pulse signal to be close to the rising edge of the working clock signal, and the sampling result to randomly jump between 0 / 1, thus resulting in unstable sampling results. Therefore, it is necessary to adjust the phase of the synchronous pulse signal to improve sampling stability. However, the existing synchronous pulse signal delay adjustment methods have a slow adjustment speed and need to be readjusted each time the chip is powered on, with low synchronization efficiency. Summary of the Invention

[0003] In view of the above analysis, embodiments of the present invention aim to provide a synchronization method for synchronous pulse signals to solve the problems of slow adjustment speed and low efficiency of the synchronous pulse signal synchronization method.

[0004] On the one hand, embodiments of the present invention provide a synchronization method for synchronous pulse signals, including the following steps:

[0005] The source end periodically generates a synchronous pulse signal and sends it to the destination end;

[0006] The destination end determines whether it is necessary to adjust the delay value of the synchronous pulse signal. If necessary, it adjusts the delay value of the received synchronous pulse signal and records the delay value; otherwise, it obtains the historically recorded delay value and delays the received synchronous pulse signal according to the delay value.

[0007] Send the delayed synchronous pulse signal to the sampling circuit to generate a pulse signal at the destination end.

[0008] Based on a further improvement of the above method, if the destination end receives the synchronous pulse signal for the first time, it determines that it is necessary to adjust the delay value of the received synchronous pulse signal; otherwise, it is not necessary to adjust the delay value of the received synchronous pulse signal.

[0009] Based on a further improvement of the above method, the following method is used to adjust the delay value of the received synchronous pulse signal:

[0010] S21. Set the current delay value to 0;

[0011] S22. Delay the synchronization pulse signal according to the current delay value;

[0012] S23. Sample the synchronization pulse signal using a phase detection circuit, and determine whether the sampling result is the target result; if so, complete the adjustment of the delay value of the received synchronization pulse signal, otherwise, increment the current delay value by 1; if the current delay value exceeds the maximum delay value, feedback an error message, otherwise, return to step S22.

[0013] Based on a further improvement of the above method, the phase detection circuit includes the synchronization pulse signal rising edge detection circuit and the clock signal detection circuit;

[0014] The synchronization pulse signal detection circuit is used to determine the rising edge of the input pulse signal and generate a decision signal when the rising edge of the synchronization pulse signal arrives;

[0015] The clock signal detection circuit is used to perform multi-stage storage of the working clock at the destination end, and use the working clock and each stage storage value of the working clock as the sampling result, and determine whether the sampling result is the target result when the decision signal is valid.

[0016] Based on a further improvement of the above method, the following method is used to determine the target result:

[0017] Determine the sampling result when the pulse signal has a 0 phase difference from the working clock according to the multiple relationship between the sampling clock and the working clock at the destination end;

[0018] Calculate the corresponding sampling results at other phase differences according to the sampling result at the 0 phase difference;

[0019] Take the sampling result corresponding to the phase difference closest to as the target result;

[0020] where N represents the multiple of the sampling clock frequency relative to the working clock frequency.

[0021] Based on a further improvement of the above method, determining the sampling result when the pulse signal has a 0 phase difference from the working clock according to the multiple relationship between the sampling clock and the working clock at the destination end includes:

[0022] When , the median values of the sampling results at the 0 phase difference are successively 1 zero, ones, zeros;

[0023] When , the median values of the target sequence are successively 3 ones, zeros, One 1; where N represents the multiple of the sampling clock frequency relative to the working clock frequency.

[0024] Based on a further improvement of the above method, the clock signal detection circuit includes a plurality of cascaded flip - flops and a lookup table unit;

[0025] The data input terminal of the first flip - flop of the clock signal detection circuit is connected to the working clock of the destination end; the data input terminal of the subsequent flip - flop is connected to the output terminal of the previous flip - flop;

[0026] The clock signal input terminal of each flip - flop of the clock signal detection circuit is connected to the sampling clock of the destination end;

[0027] The working clock and the output terminal of each flip - flop of the clock signal detection circuit are connected to the address input terminal of the lookup table unit.

[0028] Based on a further improvement of the above method, the number of flip - flops in the clock signal detection circuit is set according to the multiple of the sampling clock frequency relative to the working clock frequency of the destination end.

[0029] Based on a further improvement of the above method, the lookup table unit is a lookup table unit with multiple - bit input and 2 - bit output; the output data of the phase detection circuit is used as the lookup address to input the lookup table unit, and the lookup table unit outputs the data stored at the address as a mark of whether it is the target phase.

[0030] Based on a further improvement of the above method, the following method is used to determine the data stored at each address of the lookup table unit:

[0031] According to the frequency - doubling relationship between the sampling clock and the working clock, determine the address when the pulse signal has a 0 - phase difference with the working clock as the target address;

[0032] Calculate the corresponding target addresses for other phase differences according to the target address at the 0 - phase difference;

[0033] Write 1 to the target address in the lookup table unit that is closest to Write 0 to the target addresses corresponding to other phase differences.

[0034] Compared with the prior art, in the method of the present invention, the source end periodically sends synchronization pulses, and the destination end determines whether it is necessary to adjust the delay. When it is necessary to adjust the delay, the delay of the received synchronization pulse signal is adjusted, and the delay value is recorded. When no adjustment is required, the delay is directly performed according to the previously recorded delay value. Therefore, when power is restored, the delay value can be directly read without readjustment, thereby improving the efficiency of delay adjustment. The synchronized pulse signal after delay is sent to the sampling circuit to generate a pulse signal at the destination end, thus stably generating the pulse signal and improving the efficiency and accuracy of synchronization.

[0035] In the present invention, the above technical solutions can be combined with each other to achieve more preferred combined solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages will be obvious from the description or can be understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained from the content specifically pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings are only for the purpose of illustrating specific embodiments and are not considered as a limitation of the present invention. Throughout the drawings, the same reference numerals represent the same components;

[0037] Figure 1 It is a schematic diagram of the application scenario of the synchronization method of the synchronization pulse signal according to an embodiment of the present invention;

[0038] Figure 2 It is a flowchart of the synchronization method of the synchronization pulse signal according to an embodiment of the present invention;

[0039] Figure 3 It is a schematic diagram of the timing relationship according to an embodiment of the present invention;

[0040] Figure 4 It is a schematic diagram of the timing relationship according to an embodiment of the present invention;

[0041] Figure 5 It is a schematic diagram of the timing relationship according to an embodiment of the present invention;

[0042] Figure 6 It is a schematic diagram of the timing relationship according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The following will specifically describe the preferred embodiments of the present invention with reference to the drawings. The drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.

[0044] As Figure 1As shown, when chip A (source end) with the same clock source sends a synchronization pulse to chip B (destination end), after B detects the rising edge of the synchronization pulse, it generates a synchronization pulse, which can be used as a valid marker for subsequent signal processing. Although chips A and B have the same clock source, after internal frequency multiplication and frequency division operations, the phase relationship between the sampling clock and the synchronization pulse in chip B has a certain randomness; at the same time, hardware differences will also bring uncertainties. The superposition of the two leads to the uncertainty of chip B sampling the synchronization pulse. When the rising edge of the pulse signal is close to the rising edge of the clock signal, the sampling result randomly jumps between 0 / 1, resulting in chip B being unable to stably sample the synchronization pulse, thus affecting subsequent other processes.

[0045] Based on this, a specific embodiment of the present invention discloses a synchronization method for synchronization pulse signals, as Figure 2 shown, including the following steps:

[0046] S1. The source end periodically generates a synchronization pulse signal and sends it to the destination end;

[0047] S2. The destination end determines whether it is necessary to adjust the delay value of the synchronization pulse signal. If necessary, it adjusts the delay value of the received synchronization pulse signal and records the delay value; otherwise, it obtains the recorded delay value and delays the received synchronization pulse signal according to the delay value.

[0048] S3. Send the delayed synchronization pulse signal to the sampling circuit to generate a pulse signal at the destination end.

[0049] During implementation, after power-on, the source end (chip A) periodically sends a synchronization pulse. The destination end determines whether it is necessary to adjust the delay value. When it is necessary to adjust the delay value, it adjusts the delay value of the received synchronization pulse signal and records the delay value. When no adjustment is required, it can directly delay according to the previously recorded delay value, so that when power-on again, it can directly read the delay value without re-adjustment, thereby improving the efficiency of delay adjustment. Send the delayed synchronization pulse signal to the sampling circuit to generate a pulse signal at the destination end, thus stably generating a pulse signal and improving the efficiency and accuracy of synchronization.

[0050] During implementation, at the destination end, it can be judged whether it is the first time to receive the synchronization pulse signal through a status bit. If the destination end receives the synchronization pulse signal for the first time, it is judged that it is necessary to adjust the delay value of the received synchronization pulse signal; otherwise, it is not necessary to adjust the delay value of the received synchronization pulse signal.

[0051] During implementation, step S2 adjusts the delay value of the received synchronization pulse signal in the following manner:

[0052] S21. Set the current delay value to 0;

[0053] S22. Delay the synchronization pulse signal according to the current delay value;

[0054] S23. Sample the synchronization pulse signal by using a phase detection circuit, and determine whether the sampling result is the target result; if so, complete the adjustment of the delay value of the received synchronization pulse signal, otherwise, increment the current delay value by 1; if the current delay value exceeds the maximum delay value, feedback an error message, otherwise, return to step S22.

[0055] During implementation, a delay unit can be used to delay the synchronization pulse signal. The delay value K indicates that the synchronization pulse signal is delayed by K cascaded delay units. The maximum delay value is determined according to the frequency of the working clock in the clock domain of the destination end. For example, if the time delay of each delay unit is 36 ps and the frequency of the working clock is 600 MHz, then at least 48 delay units are required. Therefore, the range of the delay value is 0 - 47, and the maximum delay value is 47.

[0056] The current clock domain is the clock domain of chip B. The working clock of the current clock domain is obtained by dividing the sampling clock.

[0057] Specifically, the phase detection circuit includes the rising edge detection circuit of the synchronization pulse signal and the clock signal detection circuit;

[0058] The rising edge detection circuit of the synchronization pulse signal is used to judge the rising edge of the input pulse signal and generate a decision signal when the rising edge of the synchronization pulse signal arrives;

[0059] The clock signal detection circuit is used to perform multi - stage storage on the working clock of the destination end, and use the working clock and each stage storage value of the working clock as the sampling result. When the decision signal is valid, the decision signal judges whether the sampling result is the target result.

[0060] During implementation, in order to obtain a stable pulse signal and avoid metastability, the input synchronization pulse signal is clocked multiple times through the rising edge detection circuit of the synchronization pulse signal to obtain a stable rising edge of the synchronization pulse signal. The rising edge detection circuit of the synchronization pulse signal includes three cascaded flip - flops, an inverter circuit, and an AND gate;

[0061] The data input terminal of the first flip - flop of the synchronization pulse signal detection circuit receives the pulse signal; the data input terminal of the subsequent flip - flop is connected to the output terminal of the previous flip - flop;

[0062] The output terminal of the last flip - flop of the synchronization pulse signal detection circuit is connected to the input terminal of the inverter circuit;

[0063] The clock signal input terminal of each flip-flop of the synchronization pulse signal detection circuit is connected to the sampling clock of the current clock domain;

[0064] The output terminal of the penultimate flip-flop of the synchronization pulse signal detection circuit and the output terminal of the inversion circuit are connected to the input terminal of the AND gate; the output terminal of the AND gate outputs a decision signal.

[0065] During implementation, in order to accurately detect the state of the working clock at the rising edge of the pulse signal, the clock signal detection circuit includes a plurality of cascaded flip-flops and a lookup table unit;

[0066] The data input terminal of the first flip-flop of the clock signal detection circuit is connected to the working clock of the destination end; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop;

[0067] The clock signal input terminal of each flip-flop of the clock signal detection circuit is connected to the sampling clock of the destination end;

[0068] The working clock and the output terminal of each flip-flop of the clock signal detection circuit are connected to the address input terminal of the lookup table unit.

[0069] During implementation, the phase difference relationship between the input pulse signal and the working clock is related to the frequency multiplication relationship between the sampling clock and the working clock. Therefore, the number of flip-flops in the clock signal detection circuit is set according to the multiple of the sampling clock frequency of the destination end relative to the working clock frequency.

[0070] For example, if the frequency of the sampling clock is 4 times that of the working clock, 3-stage flip-flops are used; if the frequency of the sampling clock is 5 times that of the working clock, 4-stage flip-flops are used, that is, the number of flip-flops is the frequency multiplication factor minus one.

[0071] The value of the working clock at the current moment and the output results of the multi-stage flip-flops constitute the sampling result corresponding to the current phase.

[0072] During implementation, in order to quickly determine whether the sampling result is the target result, the lookup table unit is a lookup table unit with multiple-bit input and 2-bit output; the output data of the phase detection circuit is used as the lookup address to input the lookup table unit, and the lookup table unit outputs the data stored at the address as a mark of whether it is the target phase.

[0073] During implementation, the number of input bit positions of the lookup table unit is the multiple of the sampling clock frequency of the current clock domain relative to the working clock frequency. Therefore, by using the working clock and the stored value of each stage of the working clock as the address, the data stored in the lookup table can be quickly read to obtain the result.

[0074] That is, the working clock and the output terminals of each flip-flop in the clock signal detection circuit are connected to the address input terminals of the look-up table unit, and the address of the look-up table stores the flag indicating whether the phase corresponding to the address is the target phase. For example, if three-stage registers are adopted, the register value sequence includes four elements, namely the working clock value at the current moment, the first-stage register value of the working clock (the output value of the first flip-flop), the second-stage register value of the working clock (the output value of the second flip-flop), and the third-stage register value of the working clock (the output value of the third flip-flop).

[0075] Specifically, the following method is used to determine the target result:

[0076] According to the multiple relationship between the sampling clock at the destination end and the working clock, determine the sampling result when the pulse signal has a 0-phase difference from the working clock;

[0077] Calculate the corresponding sampling results for other phase differences according to the sampling result at the 0-phase difference;

[0078] Take the sampling result corresponding to the phase difference closest to as the target result;

[0079] wherein, N represents the multiple of the sampling clock frequency relative to the working clock frequency.

[0080] Since the target addresses for other phase relationships between the pulse signal and the working clock can be calculated based on the target address when the pulse signal is in the same phase as the working clock (i.e., 0 phase), in implementation, first calculate the target address when the pulse signal is in the same phase as the working clock (i.e., 0 phase), and calculate the corresponding target addresses for other phase differences according to the target address at the 0-phase difference.

[0081] Since the synchronous pulse signal rising edge detection circuit includes three-stage flip-flops, the rising edge detected is the rising edge after delaying the pulse signal by three sampling periods, that is, the decision signal is the signal triggered by the pulse signal after delaying by 3 sampling periods.

[0082] The multiple of the sampling clock frequency relative to the working clock frequency is usually more than 4 times.

[0083] Specifically, according to the multiple relationship between the sampling clock at the destination end and the working clock, determining the sampling result when the pulse signal has a 0-phase difference from the working clock includes:

[0084] When , the median values of the sampling results at the 0-phase difference are successively 1 zero, ones, zeros;

[0085] When , the values in the target sequence are successively 3 ones, zeros, One 1; where N represents the multiple of the sampling clock frequency relative to the working clock frequency.

[0086] The high and low levels of the working clock are each maintained for a number of sampling clock cycles. If that is, N = 4 or N = 5, at the decision moment, the working clock is at a low level. Since Therefore, the first-stage register value and the second-stage register value of the working clock are both 1. Since Therefore, the remaining register values are all 0, that is, the corresponding target address values are successively 1 zero, a number of 1s, a number of 0s. When N = 4, the target address is 0110; when N = 5, the target address is 01100.

[0087] When N = 4, the timing relationship between the pulse signal, the working clock, and the multi-stage register values of the working clock is as Figure 3 shown. clk600 represents the working clock signal, clk_d1 represents the first-stage register value of the working clock, clk_d2 represents the second-stage register value of the working clock, and clk_d3 represents the third-stage register value of the working clock.

[0088] If at the decision moment, the working clock, the first-stage register value, and the second-stage register value of the working clock are all 1, and the subsequent a number of register values are 0, a number of 1s. Therefore, the value of the corresponding target address is 3 1s, a number of 0s, a number of 1s.

[0089] For example, when N = 6, the timing relationship between the pulse signal, the working clock, and the multi-stage register values of the working clock is as Figure 4 shown. clk400 represents the working clock signal, clk_d1 represents the first-stage register value of the working clock, clk_d2 represents the second-stage register value of the working clock, clk_d3 represents the third-stage register value of the working clock, clk_d4 represents the third-stage register value of the working clock, and clk_d5 represents the third-stage register value of the working clock. The target address is 111000.

[0090] Then, calculate the corresponding target addresses for other phase differences based on the target address at 0 phase difference, specifically including:

[0091] When the phase difference is , circularly shift the target address at 0 phase difference to the left by k bits to obtain the corresponding target address;

[0092] where N represents the multiple of the sampling clock frequency relative to the working clock frequency, and 0 ≤ k < N.

[0093] Since the pulse signal is the signal sampled by the sampling clock, therefore, the phase difference between the pulse signal and the working clock includes N cases, that is, the phase difference is 0,

[0094] When N = 4, the rising edge of the working clock is after the rising edge of the pulse signal in the cycle. The timing relationship of the pulse signal, the working clock, and the multi-stage register values of the working clock is as Figure 5 shown. The corresponding register value sequence at this time is 1100. The rising edge of the working clock is after the rising edge of the pulse signal in the cycle. The timing relationship of the pulse signal, the working clock, and the multi-stage register values of the working clock is as Figure 6 shown. The corresponding register value sequence at this time is 1001.

[0095] Therefore, when the phase is , the target address with a phase difference of 0 is circularly shifted left by k bits to obtain the target address corresponding to the phase difference of .

[0096] When the rising edge of the pulse signal and the rising edge of the working clock signal are far apart, the sampling is more stable. Therefore, when the phase difference is , the two rising edges are the farthest. Therefore, write 1 to the target address closest to in the lookup table unit, and write 0 to the target addresses corresponding to other phase differences.

[0097] For example, when N = 4, the address corresponding to a phase difference of 0 is 0110. Therefore, store 0 at the address 0110 in the lookup table, the address corresponding to the phase difference is 1100. Therefore, store 0 at the address 1100 in the lookup table, the address corresponding to the phase difference is 1001. Therefore, store 1 at the address 1001 in the lookup table.

[0098] The phase difference includes N cases. Therefore, the phase difference values are stored in the subsequent N addresses, and the lookup table has 2 N addresses. Therefore, 2 N - 1 can be stored in other addresses to represent non-phase differences. When 1 is found, output 1, indicating the target result; when 0 is found, the lookup table outputs 0, indicating that it is not the target result. When 2 N - 1 is found, output 3, indicating that the circuit is faulty.

[0099] The lookup table needs to output 3 values. Therefore, the output bit number of the lookup table unit is 2 bits.

[0100] When the judgment unit determines that the current phase is not the target phase, it sends a delay signal to the delay circuit to delay the synchronous pulse signal until the target phase is found.

[0101] If the current sampling result is not the target result, the delay value is incremented by 1, and then the delay synchronization pulse signal is delayed. If the delay value exceeds the maximum delay value, it indicates a circuit error and an error alarm is issued.

[0102] If it is determined to be the target result, the current delay value is recorded, for example, recorded in the OTP, the status bit is set to a flag indicating that the synchronization pulse signal is not received for the first time. When the next synchronization pulse arrives or the next power-on occurs, the delay circuit directly reads the recorded delay value, delays the synchronization pulse signal, and sends the delayed synchronization pulse signal to the sampling circuit, generating a pulse signal at the destination end, without the need to re-adjust the delay, thus improving the synchronization efficiency.

[0103] Those skilled in the art can understand that all or part of the processes of implementing the above-described embodiment methods can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a magnetic disk, an optical disk, a read-only memory, or a random access memory, etc.

[0104] The above is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A synchronization method for synchronization pulse signals, characterized in that, It includes the following steps: The source end periodically generates a synchronization pulse signal and sends it to the destination end; The destination end determines whether it is necessary to adjust the delay value of the synchronization pulse signal. If so, it adjusts the delay value of the received synchronization pulse signal and records the delay value; otherwise, it obtains the historically recorded delay value and delays the received synchronization pulse signal according to the delay value; The delayed synchronization pulse signal is sent to the sampling circuit to generate a pulse signal at the destination end.

2. The synchronization method of the synchronization pulse signal according to claim 1, characterized in that If the destination end receives the synchronization pulse signal for the first time, it determines whether it is necessary to adjust the delay value of the received synchronization pulse signal; Otherwise, it is not necessary to adjust the delay value of the received synchronization pulse signal.

3. The synchronization method of the synchronization pulse signal according to claim 1, characterized in that, The following method is used to adjust the delay value of the received synchronization pulse signal: S21. Set the current delay value to 0; S22. Delay the synchronization pulse signal according to the current delay value; S23. Use a phase detection circuit to sample the synchronization pulse signal and determine whether the sampling result is the target result; If so, the adjustment of the delay value of the received synchronization pulse signal is completed; otherwise, increment the current delay value by 1; If the current delay value exceeds the maximum delay value, feedback an error message; otherwise, return to step S22.

4. The synchronization method of the synchronization pulse signal according to claim 3, characterized in that, The phase detection circuit includes the synchronization pulse signal rising edge detection circuit and the clock signal detection circuit; The synchronization pulse signal detection circuit is used to judge the rising edge of the input pulse signal and generate a decision signal when the rising edge of the synchronization pulse signal arrives; The clock signal detection circuit is used to perform multi-stage storage of the working clock at the destination end, and use the working clock and each stage storage value of the working clock as the sampling result. When the decision signal is valid, the decision signal judges whether the sampling result is the target result.

5. The synchronization method of the synchronization pulse signal according to claim 3, characterized in that, The following method is used to determine the target result: According to the multiple relationship between the sampling clock and the working clock at the destination end, determine the sampling result when the pulse signal has a 0 phase difference from the working clock; Calculate the corresponding sampling results at other phase differences according to the sampling result at the 0 phase difference; Take the sampling result corresponding to the phase difference closest to as the target result; Wherein, N represents the multiple of the sampling clock frequency relative to the working clock frequency.

6. The synchronization method of the synchronization pulse signal according to claim 5, characterized in that, According to the multiple relationship between the sampling clock and the working clock at the destination end, determining the sampling result when the pulse signal has a 0 phase difference from the working clock includes: When the median values of the sampling results at 0 phase difference are successively 1 zero, zero​ When the values in the target sequence are 3 ones in sequence, zeros, ones; where N represents the multiple of the sampling clock frequency relative to the operating clock frequency.

7. The synchronization method of the synchronization pulse signal according to claim 4, characterized in that The clock signal detection circuit includes a plurality of cascaded flip-flops and a lookup table unit; The data input terminal of the first flip-flop of the clock signal detection circuit is connected to the working clock at the destination end; the data input terminal of the subsequent flip-flop is connected to the output terminal of the previous flip-flop; The clock signal input terminal of each flip-flop of the clock signal detection circuit is connected to the sampling clock at the destination end; The working clock and the output terminal of each flip-flop of the clock signal detection circuit are connected to the address input terminal of the lookup table unit.

8. The synchronization method of the synchronization pulse signal according to claim 7, wherein The number of flip-flops in the clock signal detection circuit is set according to the multiple of the sampling clock frequency relative to the working clock frequency at the destination end.

9. The synchronization method of the synchronization pulse signal according to claim 7, characterized in that, The lookup table unit is a lookup table unit with multi-bit input and 2-bit output; the output data of the phase detection circuit is input into the lookup table unit as a lookup address, and the data stored at the address is output by the lookup table unit as a flag indicating whether it is the target phase.

10. The synchronization method of the synchronization pulse signal according to the claim, characterized in that, The data stored at each address of the lookup table unit is determined in the following manner: Based on the multiple relationship between the sampling clock and the working clock, the address when the pulse signal has a 0-phase difference from the working clock is determined as the target address; Based on the target address at the 0-phase difference, the corresponding target addresses at other phase differences are calculated; Write a 1 to the target address in the lookup table unit that is closest to and write a 0 to the target addresses corresponding to other phase differences.

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