Sequence processing method, chip and optical module

Abstract

The invention discloses a sequence processing method, a chip and an optical module, and belongs to the technical field of communication. The sequence processing method comprises the following steps: after obtaining a plurality of intermediate bit sequences according to an initial bit sequence and an expansion table, respectively carrying out distribution matching processing on the plurality of intermediate bit sequences to obtain a plurality of target bit sequences, and combining the obtained target bit sequences. The expansion table is used for indicating a one-to-one correspondence relationship between the 2d first bit sequences and the 2d second bit sequences, and the number of low-amplitude bits of the 2d second bit sequences is greater than or equal to the number of low-amplitude bits of the second bit sequences except the 2d second bit sequences in the 2h second bit sequences; the low-amplitude bit number of the second bit sequence is the number of bits used for mapping to the lowest-amplitude bit in the plurality of target bit sequences corresponding to the second bit sequence. The problem that the bit sequence processing mode is relatively single is solved, and the method and the device are used for sequence processing.

Description

Technical Field

[0001] The present application relates to the field of communication technologies, and particularly to a sequence processing method, a chip, and an optical module. Background Art

[0002] In a communication system, communication can be carried out between a sending node and a receiving node.

[0003] In related technologies, a sending node can process a bit sequence to be transmitted, then modulate symbols according to the processed sequence, and after processing the modulated symbols, transmit them to a receiving node through a channel. The receiving node will perform an inverse process of the process executed by the sending node on the received symbols to recover the above bit sequence.

[0004] However, the processing method of the bit sequence in related technologies is relatively single. Summary of the Invention

[0005] The present application provides a sequence processing method, a chip, and an optical module, which can solve the problem that the processing method of the bit sequence in related technologies is relatively single.

[0006] In a first aspect, the present application provides a sequence processing method, which includes: obtaining a plurality of intermediate bit sequences according to an initial bit sequence and an expansion table, and then respectively performing distribution matching processing on the plurality of intermediate bit sequences to obtain a plurality of target bit sequences; finally, merging the obtained target bit sequences.

[0007] The expansion table is used to indicate the one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences. The number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d; the first bit sequence is composed of a first type of bit segment of a plurality of bit subsequences in the initial bit sequence, and the second bit sequence is composed of a second type of bit segment of a plurality of intermediate bit sequences, and the second type of bit segment is a plurality of bits at the highest bit of the intermediate bit sequence; the low-amplitude bit numbers of 2 d second bit sequences are all greater than or equal to the low-amplitude bit numbers of 2 h second bit sequences except 2 d second bit sequences; the low-amplitude bit number of any second bit sequence is: the number of bits used to map to the lowest amplitude bit among the plurality of target bit sequences corresponding to any second bit sequence;

[0008] In the sequence processing method provided by the embodiments of the present application, first, multiple intermediate bit sequences are obtained according to an initial bit sequence and an expansion table, then distribution matching processing is respectively performed on the multiple intermediate bit sequences to obtain multiple target bit sequences, and finally the obtained target bit sequences are merged. This sequence processing method is different from the sequence processing methods in the related art. Therefore, the sequence processing methods are enriched.

[0009] Moreover, in the one-to-one correspondence indicated by the expansion table, for the 2 d second bit sequences, the number of low-amplitude bits is greater than or equal to that of the 2 h second bit sequences other than the 2 d second bit sequences in the second bit sequences. Therefore, for the 2 d second bit sequences in the one-to-one correspondence indicated by the above expansion table, the number of low-amplitude bits is relatively large. Therefore, in the multiple target bit sequences obtained after the distribution matching processing of the multiple intermediate bit sequences obtained according to the expansion table, the number of bits used to map to the lowest amplitude bit in each target bit sequence is relatively large. Generally, the larger the number of bits used to map to the lowest amplitude bit in the target bit sequence, the better the signal transmission effect. Since the number of bits used to map to the lowest amplitude bit in the multiple target bit sequences obtained by the distribution matching processing is relatively large, the signal transmission effect in the present application is better. Moreover, the sequence processing flow of the solution provided by the present application is relatively simple, and the implementation complexity is relatively low.

[0010] Optionally, the minimum value of the number of low-amplitude bits of the 2 d second bit sequences is u + 1, and the maximum value of the number of low-amplitude bits of the 2 h second bit sequences other than the 2 d second bit sequences in the second bit sequences is u, where u ≥ 0.

[0011] For example, the intermediate bit sequence includes 11 bits, and the second bit sequence includes: a continuous first second-type bit segment and a second second-type bit segment; the 2 d second bit sequences include:

[0012] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0013] a second bit sequence in which the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 0);

[0014] a second bit sequence in which the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (0, 0, 0);

[0015] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0016] A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0017] A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0018] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0019] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0020] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1);

[0021] A second bit sequence where the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0022] A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0023] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0024] A second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0025] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1);

[0026] A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0027] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0028] Among various second - type bit segments provided in this application, the bits in the second - type bit segment are arranged from left to right in the order from the lowest - order bit to the highest - order bit or from the highest - order bit to the lowest - order bit. In each second - type bit segment, the bit position of the w - th bit from left to right is higher than or lower than the bit position of the (w + 1) - th bit, where w≥1. Additionally, assuming that the second - type bit segment includes y bits, then the y bits in this second - type bit segment are also the highest - order y bits in the middle - bit sequence including this second - type bit segment; and the highest - order bit in each second - type bit segment is also the bit at the highest - bit position of the middle - bit sequence including this second - type bit segment. Subsequent examples of second - type bits also satisfy the above conditions, and this application will not elaborate further.

[0029] Optionally, 2 d The minimum value of the number of low - amplitude bits in two second - bit sequences is u, 2 h Among two second - bit sequences, except for 2 d two second - bit sequences, the maximum value of the number of low - amplitude bits in the remaining second - bit sequences is u, where u≥0; 2 d Two second - bit sequences include: 2 h v second - bit sequences in two second - bit sequences where the number of low - amplitude bits is greater than u, and any 2 d -(v) second - bit sequences among multiple second - bit sequences where the number of low - amplitude bits is u, where v≥1.

[0030] For example, the middle - bit sequence includes 10 bits, and the second - bit sequence includes: the consecutive first second - type bit segment and the second second - type bit segment, 2 d Two second - bit sequences include:

[0031] A second - bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0032] A second - bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0033] A second - bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0034] A second - bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0035] A second - bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0036] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0037] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0038] A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0039] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1);

[0040] A second bit sequence where the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0041] A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0042] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0043] A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 1, 0);

[0044] A second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0045] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1);

[0046] And, any one of the following second bit sequences:

[0047] A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0048] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0049] Wherein, the bits in the second - type bit segment are arranged from left to right in ascending or descending order of bit positions.

[0050] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, 2 d The second bit sequences include:

[0051] The second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0052] The second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0053] The second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0054] The second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0055] The second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0056] The second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0);

[0057] The second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 0, 1, 0);

[0058] The second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 1, 0);

[0059] The second bit sequence in which the first second-type bit segment is (1, 1, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0060] The second bit sequence in which the first second-type bit segment is (1, 0, 1, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0061] The second bit sequence in which the first second-type bit segment is (0, 0, 1, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0062] The second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0063] A second bit sequence where the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0064] A second bit sequence where the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0065] A second bit sequence where the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0066] And any one of the following second bit sequences:

[0067] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 1, 0);

[0068] A second bit sequence where the first second-type bit segment is (0, 1, 1, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0069] Wherein, the bits in the second-type bit segment are arranged from left to right in ascending or descending order of bit positions.

[0070] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, and 2 d second bit sequences include:

[0071] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0072] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0073] A second bit sequence where the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0074] A second bit sequence where the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0075] A second bit sequence where the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0076] A second bit sequence where the first second-type bit segment is (1, 1, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0077] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0);

[0078] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0);

[0079] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0);

[0080] A second bit sequence where the first second - type bit segment is (0, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0081] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0);

[0082] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0);

[0083] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0084] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0085] And, any two of the following second bit sequences:

[0086] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0);

[0087] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0);

[0088] A second bit sequence where the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0089] A second bit sequence where the first second - type bit segment is (1, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0090] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0);

[0091] A second bit sequence where the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0092] Among them, the bits in the second - type bit segment are arranged from left to right in ascending or descending order of bit positions.

[0093] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: consecutive first and second second - type bit segments. 2 d The two second bit sequences include:

[0094] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0095] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0096] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0097] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0098] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0099] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0);

[0100] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0101] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0102] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0103] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0104] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0105] And any five of the following second bit sequences:

[0106] A second bit sequence in which the first second - type bit segment is (0, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0107] A second bit sequence in which the first second - type bit segment is (1, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0108] A second bit sequence in which the first second - type bit segment is (0, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0109] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0110] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0111] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0112] A second bit sequence in which the first second - type bit segment is (1, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0113] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 1, 0, 0);

[0114] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0);

[0115] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0, 0, 0);

[0116] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0, 0, 0);

[0117] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 1, 0, 0);

[0118] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0, 0, 0);

[0119] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 1, 0, 0);

[0120] Among them, the bits in the second - type bit segment are arranged from left to right in the order from the lowest - order bit to the highest - order bit or from the highest - order bit to the lowest - order bit.

[0121] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second - type bit segment and a second second - type bit segment. 2 d The second bit sequences include:

[0122] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0123] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0124] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0125] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0126] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0127] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0128] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0129] And, any nine of the following second bit sequences:

[0130] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 0, 1, 0, 0, 0, 0);

[0131] A second bit sequence where the first second-type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0132] A second bit sequence where the first second-type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0133] A second bit sequence where the first second-type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0134] A second bit sequence where the first second-type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0135] A second bit sequence where the first second-type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0136] A second bit sequence where the first second-type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0137] A second bit sequence where the first second-type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0138] A second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0139] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0140] A second bit sequence in which the first second - type bit segment is (0, 0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0141] Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position.

[0142] In a second aspect, the present application provides a sequence processing method, which includes: splitting a plurality of target bit sequences from a bit sequence; performing an inverse process of distribution matching processing on the plurality of target bit sequences to obtain a plurality of intermediate bit sequences; and obtaining an initial bit sequence according to the plurality of intermediate bit sequences and an expansion table. The expansion table is used to indicate the one - to - one correspondence between 2 d first bit sequences and 2 d second bit sequences. The number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h > d; the first bit sequence is composed of the first - type bit segments of a plurality of bit subsequences in the initial bit sequence, the second bit sequence is composed of the second - type bit segments of a plurality of intermediate bit sequences, and the second - type bit segment is a plurality of bits at the highest bit position of the intermediate bit sequence; the low - amplitude bit numbers of 2 d second bit sequences are all greater than or equal to the low - amplitude bit numbers of the second bit sequences except for the 2 h second bit sequences among the 2 d second bit sequences; the low - amplitude bit number of any second bit sequence is: the number of bits used to map to the lowest amplitude bit among the plurality of target bit sequences corresponding to any second bit sequence.

[0143] In a third aspect, the present application provides a chip, which includes a processor and an interface. The processor is used to run any one of the sequence processing methods provided in the first aspect to process the bit sequence, and the processor is further used to obtain a data frame according to the bit sequence obtained by processing the bit sequence, and the interface is used to output the data frame.

[0144] In a fourth aspect, the present application provides a chip, which includes a processor and an interface. The interface is used to receive a data frame, the processor is used to obtain a bit sequence according to the data frame, and run the method executed by the second sequence processing device provided in the embodiments of the present application to process the obtained bit sequence.

[0145] In a fifth aspect, an embodiment of the present application further provides an optical module, which includes an optical transceiver and a chip. The chip is configured to run the method described in any design of the first aspect to process a bit sequence, and the chip is further configured to obtain a first data frame according to the bit sequence processed by running the method described in any design of the first aspect. The optical transceiver is configured to transmit a first optical signal according to the first data frame; the optical transceiver is configured to obtain a second data frame according to a received second optical signal, and the chip is configured to obtain a bit sequence according to the second data frame and run the method described in any design of the second aspect to process the bit sequence obtained according to the second data frame.

[0146] For the effects of the above second aspect to fifth aspect, reference may be made to the effects of the corresponding designs in the first aspect, and details are not described herein again. BRIEF DESCRIPTION OF THE DRAWINGS

[0147] Figure 1 Schematic diagram of a communication system provided by an embodiment of the present application;

[0148] Figure 2 A Figure 1 Schematic diagram of the structure of the first sequence processing module in;

[0149] Figure 3 Flowchart of a sequence processing method provided by an embodiment of the present application;

[0150] Figure 4 Schematic diagram of the relationship between a bit sequence to be processed and an initial bit sequence provided by an embodiment of the present application;

[0151] Figure 5 Another schematic diagram of the relationship between a bit sequence to be processed and an initial bit sequence provided by an embodiment of the present application;

[0152] Figure 6 Schematic diagram of Example 1 provided by an embodiment of the present application;

[0153] Figure 7 Schematic diagram of Example 2 provided by an embodiment of the present application;

[0154] Figure 8 Schematic diagram of Example 3 provided by an embodiment of the present application;

[0155] Figure 9 Schematic diagram of Example 4 provided by an embodiment of the present application;

[0156] Figure 10 Schematic diagram of Example 5 provided by an embodiment of the present application;

[0157] Figure 11Schematic diagram of Example 6 provided by the embodiments of the present application;

[0158] Figure 12 Schematic structural diagram of a sequence processing device provided by the embodiments of the present application;

[0159] Figure 13 Schematic structural diagram of another sequence processing device provided by the embodiments of the present application;

[0160] Figure 14 Schematic diagram of a chip provided by the embodiments of the present application;

[0161] Figure 15 Schematic diagram of an optical module provided by the embodiments of the present application. Detailed implementation manners

[0162] To make the principles and technical solutions of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0163] The present application provides a communication system, which can be an optical communication system such as a metropolitan area telecommunication transmission system, a metropolitan area data center interconnection (DCI) system, etc.

[0164] As Figure 1 shown, the communication system includes: a sending node 01 and a receiving node 02, and a communication connection is established between the sending node 01 and the receiving node 02 through a channel 03. Both the sending node 01 and the receiving node 02 can be communication devices (such as routers, optical transmission devices (such as optical line terminals (OLT), optical network terminals (ONT), etc.)), or can be a part of a communication device, such as a chip in a communication device (such as an optical signal digital signal process (ODSP) chip), an optical module (which can be a pluggable optical module, a non-pluggable optical module, a coherent communication optical module), etc.

[0165] The channel 03 can be a wired channel, such as an optical fiber.

[0166] Taking the example that both the sending node 01 and the receiving node 02 are optical modules in a communication device. The sending node 01 can send a signal to the receiving node 02 through the channel 03 to achieve communication between the sending node 01 and the receiving node 02. Exemplarily, the sending node 01 can perform sending processing on the bit sequence to obtain a data frame, and send an optical signal to the channel 03 according to the data frame; the receiving node 02 can receive the optical signal sent by the sending node 01 from the channel 03, recover the data frame according to the optical signal, and perform receiving processing on the data frame to obtain a bit sequence. This receiving processing is the inverse processing of the sending processing.

[0167] Please continue to refer to Figure 1 , the sending node 01 includes: a data source 011, a first sequence processing module 012, a first signal processing module 013, and an optical transmitter 014. The data source 011, the first sequence processing module 012, the first signal processing module 013, the optical transmitter 014, and the channel 03 are connected in sequence. The data source 011 is used to provide a bit sequence to the first sequence processing module 012. The bit sequence includes multiple bits, and the bit can be a 0 bit or a 1 bit. The values of different bits in the bit sequence can be the same or different. The first sequence processing module 012 can perform sequence processing (including encoding, modulation, etc.) on the bit sequence to obtain multiple symbols, and transmit the multiple symbols to the first signal processing module 013. The first signal processing module 013 can perform framing processing on the multiple symbols to obtain a data frame; the optical transmitter 014 is used to transmit an optical signal to the channel 03 according to the data frame, so as to transmit the optical signal to the receiving node 02 through the channel 03.

[0168] The receiving node 02 includes: a data sink 021, a second sequence processing module 022, a second signal processing module 023, and an optical receiver 024. The data sink 021, the second sequence processing module 022, the second signal processing module 023, the optical receiver 024, and the channel 03 are connected in sequence. The optical receiver 024 can receive the optical signal sent by the sending node 01 from the channel 03 and recover the data frame according to the optical signal. The second signal processing module 023 can perform operations such as dispersion compensation, synchronization, and phase recovery on the data frame, and then perform the inverse processing of the framing processing to obtain multiple symbols, and transmit the multiple symbols to the second sequence processing module 022. The second sequence processing module 022 can perform the inverse processing of the sequence processing (including decoding, demodulation, etc.) on the multiple symbols to obtain a bit sequence, and then transmit the bit sequence to the data sink 021.

[0169] It can be understood that the sending node 01 can also have the function of the receiving node 02. Therefore, the sending node 01 can also serve as a receiving node; the receiving node 02 can also have the function of the sending node 01. Therefore, the receiving node 02 can also serve as a sending node. This application does not make any restrictions on this. When a node has the functions of both a sending node and a receiving node at the same time, the node includes Figure 1 the information source 011, the first sequence processing module 012, the first signal processing module 013, the optical transmitter 014, the information sink 021, the second sequence processing module 022, the second signal processing module 023, and the optical receiver 024 in

[0170] Furthermore, the probabilistic constellation shaping (PCS) technology is introduced in the sending node. For example, before the first signal processing module 013 processes the sequence to obtain symbols, the first signal processing module 013 first performs PCS processing on the sequence. After that, the sequence obtained by the PCS processing is further processed to obtain symbols. The PCS technology can change the probability of the constellation point symbols appearing while keeping the positions of the constellation point symbols (the constellation point symbols are simply referred to as symbols) on the signal constellation diagram unchanged, making the probabilities of the various constellation point symbols appear non-uniformly distributed. Furthermore, it can reduce the probability of the symbols with higher amplitude bits appearing, improve the transmission effect of the signal, enhance the transmission performance of the communication system, and achieve a larger baud rate or a longer transmission distance. By statistically analyzing multiple groups of bit sequences (each group of bit sequences includes the bit sequences before and after PCS processing, and the bit sequences before PCS processing in different groups are different), it can be found that when the bit sequence before PCS processing is an equiprobable bit sequence (the probability of each bit in the bit sequence being a 0 bit and a 1 bit is approximately equal), the bit sequence after PCS processing is a non-equiprobable bit sequence (the probability of each bit in the bit sequence being a 0 bit and a 1 bit is not equal).

[0171] Exemplarily, the structure of the first sequence processing module in the sending node can be as Figure 2 shown. Please refer to Figure 2, the first sequence processing module 012 includes: a PCS processing module 0121, a forward error correction (FEC) encoding module 0122, and a symbol mapping module 0123. Among them, the PCS processing module 0121 can perform PCS processing on a bit sequence including k bits in the bit sequence provided by the information source to obtain a bit sequence including N bits, where 1 < k < N. The FEC encoding module 0122 can perform FEC encoding on the bit sequence including N bits output by the PCS processing module 0121 and the remaining bit sequence in the bit sequence provided by the information source except for the bit sequence processed by the PCS processing module 0121, and transmit the bit sequence obtained by FEC encoding to the symbol mapping module 0123. The symbol mapping module 0123 can modulate symbols according to the bit sequence obtained by FEC encoding and output the modulated symbols. Among them, the bits in the bit sequence obtained by PCS processing will be mapped by the symbol mapping module 0123 to the amplitude bits of the symbols. In the embodiments of the present application, the symbol has two amplitude bits, one high amplitude bit (referred to as the highest amplitude bit) and the other low amplitude bit (referred to as the lowest amplitude bit), and the amplitude of the highest amplitude bit is higher than that of the lowest amplitude bit. For example, in the present application, it is taken as an example that the 0 bit in the bit sequence will be mapped by the symbol mapping module 0123 to the higher amplitude bit, and the 1 bit in the bit sequence will be mapped by the symbol mapping module 0123 to the lower amplitude bit. Optionally, it can also be that the 1 bit in the bit sequence is mapped to the higher amplitude bit, and the 0 bit in the bit sequence is mapped to the lower amplitude bit. Generally speaking, the first bit is used to map to the first amplitude bit, the second bit is used to map to the second amplitude bit, the first amplitude bit is higher than the second amplitude bit, the first bit is the 0 bit and the second bit is the 1 bit, or the first bit is the 1 bit and the second bit is the 0 bit.

[0172] It can be understood that since the receiving process performed by the receiving node and the sending process performed by the sending node are inverse processes to each other, the processing performed by the second sequence processing module in the receiving node includes the inverse process of PCS processing.

[0173] It can be seen that the processing method of the sequence by the sending node in the related art is relatively single.

[0174] Based on this, the embodiments of the present application provide a sequence processing method. The processing method of the bit sequence by this sequence processing method is different from the methods provided in the related art. Therefore, it can enrich the processing methods of the bit sequence. In addition, this sequence processing method can process the bit sequence to obtain a non-uniform probability bit sequence including more bits (such as 0 or 1) used to map to the lowest amplitude bit.

[0175] The sequence processing method provided by the embodiment of this application is executed by the sequence processing device (referred to as the first sequence processing device) in the above-mentioned sending node and the sequence processing device (referred to as the second sequence processing device) in the receiving node. The first sequence processing device can be the sending node, or the first sequence processing device is the first sequence processing module or other modules such as the PCS processing module in the sending node; the second sequence processing device can be the receiving node, or the second sequence processing device is the second sequence processing module or other modules in the receiving node. Exemplarily, Figure 3 is a flowchart of a sequence processing method provided by the embodiment of this application, as Figure 3 shown, the sequence processing method includes:

[0176] S101. The first sequence processing device obtains a plurality of intermediate bit sequences according to the initial bit sequence and the expansion table. Among them, the expansion table is used to indicate the one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences. The number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d; the first bit sequence is composed of the first type of bit segments of a plurality of bit subsequences in the initial bit sequence, and the second bit sequence is composed of the second type of bit segments of the above-mentioned plurality of intermediate bit sequences. The second type of bit segment is a plurality of bits at the highest bit of the intermediate bit sequence.

[0177] The initial bit sequence includes a plurality of bit subsequences. The initial bit sequence can be composed of the bits in the plurality of bit subsequences, or can be composed of the bits in the plurality of bit subsequences and other bits. The order of the bits in the bit subsequence can be the same as or different from the order of the bits in the initial bit sequence. Optionally, the number of bits in the plurality of bit subsequences can be the same or different. When the number of bits in the plurality of bit subsequences is the same, the number of bits in these bit subsequences can be values such as 6, 7, 8, 9, or 10, and the embodiment of this application does not limit this.

[0178] In S101, the first sequence processing device obtains a plurality of intermediate bit sequences according to the initial bit sequence and the expansion table.

[0179] The expansion table is also called a correspondence table, a decision table, a decision expansion table, a mapping table, etc.

[0180] Exemplarily, the expansion table is used to indicate 2 d first bit sequences and 2 dIn the one-to-one correspondence of a second bit sequence, the first bit sequence includes a plurality of first-type bit segments, and the first bit sequence includes a total of d bits; the second bit sequence includes a plurality of second-type bit segments, and the number of bits in the second bit sequence is h; the initial bit sequence includes a plurality of bit subsequences, and the i-th bit subsequence among the plurality of bit subsequences includes: 2 d the i-th first-type bit segment in the target first bit sequence among the first bit sequences, 1≥1; the plurality of bits at the highest position of the j-th intermediate bit sequence among the plurality of intermediate bit sequences are: the j-th second-type bit segment in the target second bit sequence corresponding to the target first bit sequence, j≥1.

[0181] Exemplarily, taking d = 2 as an example, 2 d first bit sequences and 2 d the one-to-one correspondence of second bit sequences can be shown in Table 1 below. This correspondence includes: the correspondence between the first bit sequence 1 and a second bit sequence (including the second-type bit segment 2.1, the second-type bit segment 3.1, the second-type bit segment 4.1); the correspondence between the first bit sequence 2 and another second bit sequence (including the second-type bit segment 2.2, the second-type bit segment 3.2, the second-type bit segment 4.2); the correspondence between the first bit sequence 3 and yet another second bit sequence (including the second-type bit segment 2.3, the second-type bit segment 3.3, the second-type bit segment 4.3); the correspondence between the first bit sequence 4 and still another second bit sequence (including the second-type bit segment 2.4, the second-type bit segment 3.4, the second-type bit segment 4.4). In S101, the first sequence processing device can first obtain the to-be-searched bit sequence according to the first-type bit segments in the plurality of bit subsequences. The to-be-searched bit sequence includes the first-type bit segments in the plurality of bit subsequences. Then, the first sequence processing device will search for the to-be-searched bit sequence among the plurality of first bit sequences until the target first bit sequence identical to the to-be-searched bit sequence is found. Then, the first sequence processing device will further find the target second bit sequence corresponding to the target first bit sequence, and according to the one-to-one correspondence between the plurality of second-type bit segments in the target second bit sequence and the plurality of intermediate bit sequences, use each second-type bit segment in the target bit sequence group as the second-type bit segment in the corresponding intermediate bit sequence. Thus, the first sequence processing device can obtain the second-type bit segments in the plurality of intermediate bit sequences.

[0182] Table 1

[0183]

[0184] Furthermore, 2 d first bit sequences and 2 dIn the one-to-one correspondence with the second bit sequences, the first bit sequence can also be represented by multiple first-type bit segments in the first bit sequence. The multiple first-type bit segments in the target first bit sequence are in one-to-one correspondence with the first-type bit segments in the multiple bit subsequences, and the first-type bit segments in the target first bit sequence include the corresponding first-type bit segments. In this case, the correspondence shown in Table 1 can be as shown in Table 2. The first bit sequence 1 in Table 1 is represented by the first-type bit segment 1.1 and the first-type bit segment 1.2 in Table 2. The first bit sequence 2 in Table 1 is represented by the first-type bit segment 2.1 and the first-type bit segment 2.2 in Table 2. The first bit sequence 3 in Table 1 is represented by the first-type bit segment 3.1 and the first-type bit segment 3.2 in Table 2. The first bit sequence 4 in Table 1 is represented by the first-type bit segment 4.1 and the first-type bit segment 4.2 in Table 2.

[0185] Table 2

[0186]

[0187]

[0188] Optionally, the number of bits in the multiple intermediate bit sequences may be the same or different. When the number of bits in the multiple intermediate bit sequences is the same, the number of bits in the multiple intermediate bit sequences may all be 10 or 11, etc., and the embodiments of the present application do not limit this. In addition, the number of bit subsequences in the initial bit sequence and the number of target bit sequences may be the same or different, and the embodiments of the present application do not limit this.

[0189] S102. The first sequence processing device respectively performs distribution matching processing on the multiple intermediate bit sequences to obtain multiple target bit sequences. In the one-to-one correspondence indicated by the expansion table, the low-amplitude bit numbers of the two second bit sequences are both greater than or equal to the low-amplitude bit numbers of the second bit sequences other than the two second bit sequences; the low-amplitude bit number of any second bit sequence is: the number of bits used to map to the lowest amplitude bit in the multiple target bit sequences corresponding to the second bit sequence. d The low-amplitude bit numbers of the two second bit sequences are both greater than or equal to h the low-amplitude bit numbers of the second bit sequences other than the two second bit sequences; d the low-amplitude bit number of any second bit sequence is: the number of bits used to map to the lowest amplitude bit in the multiple target bit sequences corresponding to the second bit sequence.

[0190] Multiple intermediate bit sequences correspond one-to-one with multiple target bit sequences. After obtaining the multiple intermediate bit sequences, the first sequence processing device can perform distribution matching processing on the multiple intermediate bit sequences respectively to obtain the target bit sequence corresponding to each intermediate bit sequence. Distribution matching (DM) processing is used to convert a bit sequence into a bit sequence with unequal probabilities. The intermediate bit sequences that need to undergo distribution matching processing can be bit sequences with equal probabilities or bit sequences with unequal probabilities. In the embodiments of this application, taking the implementation of distribution matching processing using a look-up table (LUT) as an example, it can be understood that distribution matching processing may not be implemented using a look-up table, and the embodiments of this application do not limit this.

[0191] When the distribution matching processing is implemented using a look-up table, each of the multiple intermediate bit sequences has its own corresponding table. This table includes the correspondence between multiple index bit sequences and multiple result bit sequences. The number of bits (such as 0 bits) in the result bit sequences corresponding to the multiple index bit sequences that are used to map to the lowest magnitude bit is positively correlated with the value of the index bit sequence. The bits in the bit sequence can be 0 bits or 1 bits, and the value of the bit sequence refers to the value of the binary number represented by this bit sequence. The first sequence processing device will look up the table corresponding to each intermediate bit sequence according to the intermediate bit sequence, find the index bit sequence in the table that is the same as the intermediate bit sequence, and use the result bit sequence corresponding to this index bit sequence as the target bit sequence corresponding to this intermediate bit sequence.

[0192] In addition, the above-mentioned multiple index bit sequences are usually arranged in a certain order. In this order, the second index bit sequence is obtained by changing the lowest bit of the first index bit sequence; the penultimate index bit sequence is obtained by changing the highest bit of the second-to-last index bit sequence. When the multiple index bit sequences are arranged in this order, the subsequent index bit sequences are obtained by changing one or more bit positions of the previous index bit sequence, and the one or more bit positions start from including the lowest bit at the beginning and gradually evolve to include the highest bit. The multiple index bit sequences include the intermediate bit sequence. The lowest bit in the intermediate bit sequence is the lowest bit in the index bit sequence that is the same as the intermediate bit sequence, and the highest bit in the intermediate bit sequence is the highest bit in the index bit sequence that is the same as the intermediate bit sequence.

[0193] The distribution matching processing performed on different intermediate bit sequences can be the same or different. When the distribution matching processing is implemented using a look-up table, the tables corresponding to different intermediate bit sequences can be the same or different, and the embodiments of this application do not limit this.

[0194] Optionally, the sum of the number of bits in multiple intermediate bit sequences is greater than the number of bits in the initial bit sequence, and the sum of the number of bits in multiple target bit sequences is also greater than the number of bits in the initial bit sequence. Additionally, the number of bits in a target bit sequence may be equal to the number of bits in the intermediate bit sequence corresponding to that target bit sequence. Of course, the number of bits in a target bit sequence may also be less than or greater than the number of bits in the intermediate bit sequence corresponding to that target bit sequence.

[0195] In the one-to-one correspondence indicated by the expansion table, the length of the bits in the second bit sequence is h, where h > d. The 2 d second bit sequences in this one-to-one correspondence are 2 h part of the second bit sequences among the 2 d second bit sequences. The 2 h second bit sequences in the embodiments of this application refer to the 2 d second bit sequences in the one-to-one correspondence indicated by the expansion packet. d

[0196] 2 h Among the 2 second bit sequences, each second bit sequence corresponds to multiple target bit sequences, and the multiple target bit sequences are respectively obtained by performing the above distribution matching process on the multiple intermediate bit sequences corresponding to the second bit sequence.

[0197] In one case, the multiple intermediate bit sequences are divided into multiple groups of intermediate bit sequences, and the multiple groups of intermediate bit sequences correspond one-to-one to multiple second type bit segments in the second bit sequence. Each second type bit segment in the multiple second type bit segments is the highest bit segment of each intermediate bit sequence in the corresponding group of intermediate bit sequences. It can be seen that the group of intermediate bit sequences corresponding to each second type bit segment is: the intermediate bit sequences with the highest bit segment being the second type bit segment.

[0198] In another case, the multiple intermediate bit sequences correspond one-to-one to multiple second type bit segments in the second bit sequence, and each second type bit segment in the multiple second type bit segments is the highest bit segment of the corresponding intermediate bit sequence. It can be seen that the intermediate bit sequence corresponding to each second type bit segment is: any intermediate bit sequence with the highest bit segment being the second type bit segment.

[0199] ​Each second bit sequence has a number of low - amplitude bits. The number of low - amplitude bits of each second bit sequence is: the number of bits in the multiple target bit sequences corresponding to this second bit sequence that are used to map to the lowest amplitude bit, that is, the sum of the number of bits in the multiple target bit sequences that are used to map to the lowest amplitude bit. Optionally, the number of low - amplitude bits of each second bit sequence can also be: the average value of the number of bits in the multiple target bit sequences corresponding to this second bit sequence that are used to map to the lowest amplitude bit.

[0200] There are h bits in the second bit sequence. In this application, each bit in the bit sequence has two values (0 or 1). Therefore, the number of values of the second bit sequence is 2 h species, and these values are also the above - mentioned 2 h second bit sequences. When screening 2 h second bit sequences from 2 d second bit sequences, it is necessary to base on the number of low - amplitude bits of each second bit sequence in the 2 h second bit sequences, so as to screen out 2 d second bit sequences with a higher number of low - amplitude bits. In this way, it can be ensured that the number of low - amplitude bits of the 2 d second bit sequences is greater than or equal to the number of low - amplitude bits of any second bit sequence in the 2 h second bit sequences except the 2 d second bit sequences.

[0201] When the number of low - amplitude bits of the 2 d second bit sequences is greater than or equal to the number of low - amplitude bits of any second bit sequence in the 2 h second bit sequences except the 2 d second bit sequences, the number of high - amplitude bits of the 2 d second bit sequences is less than or equal to the number of high - amplitude bits of any second bit sequence in the 2 h second bit sequences except the 2 d second bit sequences. The number of high - amplitude bits of each second bit sequence is: the number of bits in the multiple target bit sequences corresponding to this second bit sequence that are used to map to the highest amplitude bit, that is, the sum of the number of bits in the multiple target bit sequences that are used to map to the highest amplitude bit. Optionally, the number of high - amplitude bits of each second bit sequence can also be: the average value of the number of bits in the multiple target bit sequences corresponding to this second bit sequence that are used to map to the highest amplitude bit.

[0202] It can be seen that the 2 dThe number of low-amplitude bits in each second bit sequence is relatively large. Therefore, among the multiple target bit sequences obtained after S102 for the multiple intermediate bit sequences obtained according to this expansion table in S101, the number of bits used to map to the lowest amplitude bit in each target bit sequence is relatively large. Generally, the larger the number of bits used to map to the lowest amplitude bit in the target bit sequence, the better the signal transmission effect; since the number of bits used to map to the lowest amplitude bit in the multiple target bit sequences obtained in S102 is relatively large, therefore, the signal transmission effect in this application is better.

[0203] S103. The first sequence processing device combines the obtained target bit sequences.

[0204] The first sequence processing device can combine the obtained target bit sequences in any order. Moreover, when the first sequence processing device combines these target bit sequences, it can combine these target bit sequences in order, or it can also scatter the bits in these target bit sequences; the bit order in the target bit sequence and the bit order in the combined bit sequence can be the same or different, and the embodiments of this application do not limit this.

[0205] S104. The first sequence processing device transmits the bit sequence obtained from the combined target bit sequences to the second sequence processing device.

[0206] S105. The second sequence processing device splits the received bit sequence into multiple target bit sequences.

[0207] S106. The second sequence processing device performs the inverse process of the distribution matching process on the multiple target bit sequences to obtain multiple intermediate bit sequences.

[0208] S107. The second sequence processing device obtains the initial bit sequence according to the multiple intermediate bit sequences and the expansion table.

[0209] The above S105 and S103 are inverse operations to each other, S106 and S102 are inverse operations to each other, and S107 and S101 are inverse operations to each other. Therefore, S105 can refer to S103, S106 can refer to S102, and S107 can refer to S101. The embodiments of this application will not elaborate here.

[0210] In summary, in the sequence processing method provided by the embodiments of this application, multiple intermediate bit sequences are first obtained according to the initial bit sequence and the expansion table, then the distribution matching process is respectively performed on the multiple intermediate bit sequences to obtain multiple target bit sequences, and finally the obtained target bit sequences are combined. This sequence processing method is different from the sequence processing methods in the related art. Therefore, the sequence processing methods are enriched.

[0211] Moreover, in the one-to-one correspondence indicated by the extended table, for the 2 d low-amplitude bit counts of the second bit sequences are all greater than or equal to 2 h among the second bit sequences, for the second bit sequences other than the 2 d second bit sequences, the low-amplitude bit counts of the second bit sequences. Therefore, for the 2 d second bit sequences in the one-to-one correspondence indicated by the above extended table, the low-amplitude bit counts are all larger. Thus, among the multiple target bit sequences obtained after the distributed matching process for the multiple intermediate bit sequences obtained according to this extended table, the number of bits used to map to the lowest amplitude bit in each target bit sequence is larger. Generally, the larger the number of bits used to map to the lowest amplitude bit in the target bit sequence, the better the signal transmission effect; since the number of bits used to map to the lowest amplitude bit in the multiple target bit sequences obtained by the distributed matching process is larger, therefore, the signal transmission effect in this application is better.

[0212] Moreover, the sequence processing flow of the solution provided in this application is relatively simple, and the implementation complexity is relatively low.

[0213] In the related art, the rate loss R loss is negatively correlated with the signal transmission effect. Therefore, if R loss is reduced, the signal transmission effect can also be improved. However, reducing R loss requires increasing the size of the table in the above lookup table method, such that the storage space required for this table will increase exponentially. If a better signal transmission effect is required, then the storage space required for this table is very large. Moreover, when the storage space is large, the complexity of the lookup table method is relatively high, and the power consumption required to search the table is also relatively high. In this application, without increasing the above table, the signal transmission effect can be improved. Therefore, this application will not cause an increase in the storage space required for the table, as well as problems of relatively high complexity and power consumption. Therefore, the method provided in this application can be used for a sequence processing device with high power consumption constraints, which is conducive to the sequence processing device achieving a longer transmission distance. Optionally, based on the embodiments of this application, the above table can also be increased simultaneously to reduce R loss and further improve the signal transmission effect, increase the transmission distance, and reduce the transmission bit error rate. This application does not make any limitations in this regard.

[0214] Furthermore, among the 2 h second bit sequences, there are second bit sequences with the same low-amplitude bit count. In this way, when screening 2 h second bit sequences among the 2 d second bit sequences, if the minimum value of the low-amplitude bit counts of the 2 d second bit sequences is u, among the 2 h second bit sequences, except for the 2d If the maximum value of the number of low - amplitude bits of a second bit sequence other than the second bit sequence is also u, then, 2 d the second bit sequences include: 2 h v second bit sequences in the second bit sequences where the number of low - amplitude bits is greater than u, and any 2 d - v second bit sequences in the multiple second bit sequences where the number of low - amplitude bits is u, where both u and v are integers greater than or equal to 1. It can be seen that 2 h the v second bit sequences in the second bit sequences where the number of low - amplitude bits is greater than u can be screened out first, and then any 2 d - v second bit sequences are screened out from the multiple second bit sequences where the number of low - amplitude bits is u, so as to obtain 2 d second bit sequences. In this case, 2 d the number of low - amplitude bits of any second bit sequence in the second bit sequences is greater than 2 h the number of low - amplitude bits of any second bit sequence other than the 2 d second bit sequences in the second bit sequences.

[0215] In addition, if 2 d the minimum value of the number of low - amplitude bits of the second bit sequences is u + 1, and 2 h the maximum value of the number of low - amplitude bits of the second bit sequences other than the 2 d second bit sequences is u. Then, only the second bit sequences in the 2 h second bit sequences where the number of low - amplitude bits is greater than u need to be screened out to obtain 2 d second bit sequences. In this case, 2 d the number of low - amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h the number of low - amplitude bits of any second bit sequence other than the 2 d second bit sequences in the second bit sequences.

[0216] 2 d In the one - to - one correspondence between 2 d first bit sequences and 2 d second bit sequences, there are multiple implementation methods for the 2

[0217] 1. The first implementation method of the 2 d second bit sequences.

[0218] In the first implementation method, 2 d the number of low - amplitude bits of any second bit sequence in the second bit sequences is greater than 2h the number of low - amplitude bits of any second bit sequence other than the two second bit sequences d in the second bit sequences

[0219] In this first implementable manner, the middle bit sequence includes 11 bits, the second type of bit segment includes 3 bits, and the second bit sequences include: a consecutive first second - type bit segment and a second second - type bit segment; two d second bit sequences can be represented by the 16 second bit sequences shown in Table 3

[0220] It can be seen that two d second bit sequences include:

[0221] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0222] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0223] a second bit sequence in which the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0224] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0225] a second bit sequence in which the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0226] a second bit sequence in which the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0227] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0228] a second bit sequence in which the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0229] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1);

[0230] a second bit sequence in which the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0231] A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0232] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0233] A second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0234] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1);

[0235] A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0236] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0237] In various second - type bit segments provided in the embodiments of the present application (including second - type bit segments provided by other implementable manners in the future), the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position. In each second - type bit segment, the bit position of the w - th bit from left to right is higher or lower than the bit position of the (w + 1)-th bit, where w≥1. Additionally, assuming that the second - type bit segment includes y bits, then the y bits in the second - type bit segment are also the highest - order y bits in the intermediate bit sequence including this second - type bit segment; and, the highest - order bit in each second - type bit segment is also the bit at the highest bit position of the intermediate bit sequence including this second - type bit segment. In the embodiments of the present application, the high - low situation of the bit positions of the bits in the second - type bit segment is the same as the high - low situation of the bit positions of the bits in the intermediate bit sequence where this second - type bit segment is located.

[0238] Optionally, in this first implementable manner, 2 d first bit sequences may include 16 first bit sequences. In the one - to - one correspondence between the 2 d first bit sequences and the 2 d second bit sequences:

[0239] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0240] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (1, 0, 0);

[0241] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second - type bit segment is (1, 0, 0), and the second second - type bit segment is (0, 0, 0);

[0242] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (0, 1, 0);

[0243] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second - type bit segment is (0, 1, 0), and the second second - type bit segment is (0, 0, 0);

[0244] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second - type bit segment is (1, 1, 0), and the second second - type bit segment is (0, 0, 0);

[0245] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (1, 1, 0);

[0246] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second - type bit segment is (1, 0, 0), and the second second - type bit segment is (1, 0, 0);

[0247] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (0, 0, 1);

[0248] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second - type bit segment is (0, 0, 1), and the second second - type bit segment is (0, 0, 0);

[0249] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second - type bit segment is (0, 1, 0), and the second second - type bit segment is (1, 0, 0);

[0250] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second - type bit segment is (1, 0, 0), and the second second - type bit segment is (0, 1, 0);

[0251] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second - type bit segment is (1, 0, 1), and the second second - type bit segment is (0, 0, 0);

[0252] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (1, 0, 1);

[0253] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 1), the first second - type bit segment is (1, 1, 0), and the second second - type bit segment is (1, 0, 0);

[0254] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1), the first second - type bit segment is (1, 0, 0), and the second second - type bit segment is (1, 1, 0).

[0255] 2 d The one - to - one correspondence between 2 d first bit sequences and 2

[0256] Table 3

[0257]

[0258]

[0259] It can be understood that, based on the above 2 d first bit sequences and the above 2 d second bit sequences, the one - to - one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 3. For example, swap the second bit sequences corresponding to any two of the above - mentioned first bit sequences. Or, shuffle the order of the 16 second bit sequences in Table 3 while keeping the order of the 16 first bit sequences in Table 3 unchanged.

[0260] 2, 2 d The second implementation method of 2

[0261] In this second implementation method, 2d The number of low - amplitude bits in any one of the second bit sequences is greater than or equal to 2 h in the second bit sequences except for 2 d the number of low - amplitude bits in any one of the second bit sequences.

[0262] In this second implementation, the middle bit sequence includes 10 bits, the second - type bit segment includes 3 bits, and the second bit sequences include: the consecutive first second - type bit segment and the second second - type bit segment; 2 d The 2 second bit sequences can include any one of the 15 second bit sequences shown in Table 4 and the 2 second bit sequences shown in Table 5.

[0263] It can be seen that 2 d the 2 second bit sequences include:

[0264] a second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0265] a second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0266] a second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0267] a second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0268] a second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0269] a second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0270] a second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0271] a second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0272] a second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1);

[0273] A second bit sequence where the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0274] A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0275] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0276] A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 1, 0);

[0277] A second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0278] A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1);

[0279] And any one of the following second bit sequences:

[0280] A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0281] A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0282] Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest - order bit to the highest - order bit or from the highest - order bit to the lowest - order bit.

[0283] Optionally, in this second implementation manner, the 2 d first bit sequences may include 16 first bit sequences. In the one - to - one correspondence between the 2 d first bit sequences and the 2 d second bit sequences:

[0284] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0285] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0286] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second - type bit segment is (1, 0, 0), and the second second - type bit segment is (0, 0, 0);

[0287] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (0, 1, 0);

[0288] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second - type bit segment is (0, 1, 0), and the second second - type bit segment is (0, 0, 0);

[0289] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second - type bit segment is (1, 0, 0), and the second second - type bit segment is (1, 0, 0);

[0290] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (1, 1, 0);

[0291] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second - type bit segment is (1, 1, 0), and the second second - type bit segment is (0, 0, 0);

[0292] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second - type bit segment is (0, 0, 0), and the second second - type bit segment is (0, 0, 1);

[0293] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second - type bit segment is (0, 0, 1), and the second second - type bit segment is (0, 0, 0);

[0294] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second - type bit segment is (0, 1, 0), and the second second - type bit segment is (1, 0, 0);

[0295] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second - type bit segment is (1, 0, 0), and the second second - type bit segment is (0, 1, 0);

[0296] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second - type bit segment is (0, 1, 0), and the second second - type bit segment is (0, 1, 0);

[0297] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second-type bit segment is (1, 0, 1), and the second second-type bit segment is (0, 0, 0);

[0298] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 1), the first second-type bit segment is (0, 0, 0), and the second second-type bit segment is (1, 0, 1);

[0299] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1), the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0), or the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0).

[0300] 2 d The one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences can be shown in Table 4 and Table 5. Among them, Table 4 shows 16 first bit sequences and 15 second bit sequences, and for one first bit sequence in Table 4, the corresponding second bit sequence is empty. This second bit sequence can be any of the two second bit sequences shown in Table 5. The first bit sequences in Table 4 also include a continuous first first-type bit segment and a second first-type bit segment, and the first first-type bit segment and the second first-type bit segment are arranged from left to right in Table 4. The first first-type bit segment or the second first-type bit segment is multiple bits of the highest bit in the first bit sequence. The first second-type bit segment and the second second-type bit segment in the second bit sequence are also arranged from left to right in Table 4 and Table 5. The first second-type bit segment or the second second-type bit segment is multiple bits of the highest bit in the second bit sequence.

[0301] Table 4

[0302]

[0303]

[0304] Table 5

[0305]

[0306] It can be understood that among the above 2 d first bit sequences and the above 2 dBased on a second bit sequence, the one-to-one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 4 and Table 5. For example, swap the second bit sequences corresponding to any two first bit sequences in the above example. Another example is to scramble the order of the 16 second bit sequences jointly given in Table 4 and Table 5 (15 second bit sequences in Table 4 and any one of the two second bit sequences given in Table 5), and keep the order of the 16 first bit sequences in Table 4 unchanged.

[0307] 3, 2 d The third implementation manner of the second bit sequence.

[0308] In this third implementation manner, 2 d The number of low-amplitude bits of any one of the second bit sequences is greater than or equal to 2 h For any one of the second bit sequences except 2 d The number of low-amplitude bits of any one of the second bit sequences.

[0309] In this third implementation manner, the middle bit sequence includes 10 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes: the consecutive first second type of bit segment and the second second type of bit segment; 2 d The second bit sequences can include the 15 second bit sequences shown in Table 6 and any one of the 2 second bit sequences shown in Table 7.

[0310] It can be seen that 2 d The second bit sequences include:

[0311] The second bit sequence where the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0312] The second bit sequence where the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (1, 0, 0, 0);

[0313] The second bit sequence where the first second type of bit segment is (1, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0314] The second bit sequence where the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (0, 1, 0, 0);

[0315] The second bit sequence where the first second type of bit segment is (0, 1, 0, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0316] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0);

[0317] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0);

[0318] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0);

[0319] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0320] A second bit sequence where the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0321] A second bit sequence where the first second - type bit segment is (0, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0322] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0323] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0324] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0);

[0325] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 1, 0, 0);

[0326] And, any one of the following second bit sequences:

[0327] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0);

[0328] A second bit sequence where the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0329] Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit to the highest bit or from the highest bit to the lowest bit.

[0330] Optionally, under this third implementable manner, 2 d first bit sequences may include 16 first bit sequences, and in the one-to-one correspondence between the 2 d first bit sequences and the 2 d second bit sequences:

[0331] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second-type bit segment is (0, 0, 0, 0), and the second second-type bit segment is (0, 0, 0, 0);

[0332] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second-type bit segment is (0, 0, 0, 0), and the second second-type bit segment is (1, 0, 0, 0);

[0333] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second-type bit segment is (1, 0, 0, 0), and the second second-type bit segment is (0, 0, 0, 0);

[0334] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second-type bit segment is (0, 0, 0, 0), and the second second-type bit segment is (0, 1, 0, 0);

[0335] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second-type bit segment is (0, 1, 0, 0), and the second second-type bit segment is (0, 0, 0, 0);

[0336] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second-type bit segment is (0, 0, 0, 0), and the second second-type bit segment is (1, 1, 0, 0);

[0337] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second-type bit segment is (0, 0, 0, 0), and the second second-type bit segment is (0, 0, 1, 0);

[0338] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second-type bit segment is (0, 0, 0, 0), and the second second-type bit segment is (1, 0, 1, 0);

[0339] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second-type bit segment is (1, 1, 0, 0), and the second second-type bit segment is (0, 0, 0, 0);

[0340] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second-type bit segment is (1, 0, 1, 0), and the second second-type bit segment is (0, 0, 0, 0);

[0341] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second-type bit segment is (0, 0, 1, 0), and the second second-type bit segment is (0, 0, 0, 0);

[0342] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second-type bit segment is (1, 0, 0, 0), and the second second-type bit segment is (1, 0, 0, 0);

[0343] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second-type bit segment is (0, 1, 0, 0), and the second second-type bit segment is (1, 0, 0, 0);

[0344] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second-type bit segment is (1, 0, 0, 0), and the second second-type bit segment is (0, 1, 0, 0);

[0345] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 1), the first second-type bit segment is (0, 1, 0, 0), and the second second-type bit segment is (0, 1, 0, 0);

[0346] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1), the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 1, 0), or the first second-type bit segment is (0, 1, 1, 0) and the second second-type bit segment is (0, 0, 0, 0).

[0347] 2 d first bit sequences and 2 dThe one-to-one correspondence of the second bit sequences can be shown in Table 6 and Table 7. Among them, Table 6 shows 16 first bit sequences and 15 second bit sequences, and for one of the first bit sequences in Table 6, the corresponding second bit sequence is empty. This second bit sequence can be any one of the two second bit sequences shown in Table 7. The first bit sequences in Table 6 also include a continuous first type of bit segment and a second type of bit segment, and the first type of bit segment and the second type of bit segment are arranged from left to right in Table 6. The first type of bit segment or the second type of bit segment is a plurality of bits at the highest position in the first bit sequence. The first type of bit segment and the second type of bit segment in the second bit sequence are also arranged from left to right in Table 6 and Table 7. The first type of bit segment or the second type of bit segment is a plurality of bits at the highest position in the second bit sequence.

[0348] Table 6

[0349]

[0350]

[0351] Table 7

[0352]

[0353] It can be understood that based on the above 2 d first bit sequences and the above 2 d second bit sequences, the one-to-one correspondence between the first bit sequences and the second bit sequences can also be different from that shown in Table 6 and Table 7. For example, swap the second bit sequences corresponding to any two of the above examples. Another example is to shuffle the order of the 16 second bit sequences jointly given by Table 6 and Table 7 (15 second bit sequences in Table 6 and any one of the two second bit sequences given by Table 7), and keep the order of the 16 first bit sequences in Table 6 unchanged.

[0354] 4. The fourth implementation manner of 2 d second bit sequences.

[0355] In this fourth implementation manner, the number of low-amplitude bits of any one of the 2 d second bit sequences is greater than or equal to the number of low-amplitude bits of any one of the 2 h second bit sequences other than the 2 d second bit sequences.

[0356] In the fourth implementation, the middle bit sequence includes 11 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes: the consecutive first second type of bit segment and the second second type of bit segment; 2 d The two second bit sequences may include any two of the 14 second bit sequences shown in Table 8 and the 6 second bit sequences shown in Table 9.

[0357] It can be seen that 2 d The two second bit sequences include:

[0358] The second bit sequence in which the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0359] The second bit sequence in which the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (1, 0, 0, 0);

[0360] The second bit sequence in which the first second type of bit segment is (1, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0361] The second bit sequence in which the first second type of bit segment is (0, 1, 0, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0362] The second bit sequence in which the first second type of bit segment is (1, 0, 0, 0) and the second second type of bit segment is (1, 0, 0, 0);

[0363] The second bit sequence in which the first second type of bit segment is (1, 1, 0, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0364] The second bit sequence in which the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (0, 1, 0, 0);

[0365] The second bit sequence in which the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (1, 1, 0, 0);

[0366] The second bit sequence in which the first second type of bit segment is (0, 0, 0, 0) and the second second type of bit segment is (0, 0, 1, 0);

[0367] The second bit sequence in which the first second type of bit segment is (0, 0, 1, 0) and the second second type of bit segment is (0, 0, 0, 0);

[0368] The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0);

[0369] The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0);

[0370] The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0371] The second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0372] And any two of the following second bit sequences:

[0373] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0);

[0374] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0);

[0375] The second bit sequence where the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0376] The second bit sequence where the first second - type bit segment is (1, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0377] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0);

[0378] The second bit sequence where the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0379] Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest - order bit to the highest - order bit or from the highest - order bit to the lowest - order bit.

[0380] Optionally, in this fourth implementation manner, 2 d first bit sequences can include 16 first bit sequences, and in the one - to - one correspondence between 2 d first bit sequences and 2 d second bit sequences:

[0381] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second - type bit segment is (0, 0, 0, 0), and the second second - type bit segment is (0, 0, 0, 0);

[0382] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second - type bit segment is (0, 0, 0, 0), and the second second - type bit segment is (1, 0, 0, 0);

[0383] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second - type bit segment is (1, 0, 0, 0), and the second second - type bit segment is (0, 0, 0, 0);

[0384] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second - type bit segment is (0, 1, 0, 0), and the second second - type bit segment is (0, 0, 0, 0);

[0385] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second - type bit segment is (1, 0, 0, 0), and the second second - type bit segment is (1, 0, 0, 0);

[0386] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second - type bit segment is (1, 1, 0, 0), and the second second - type bit segment is (0, 0, 0, 0);

[0387] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second - type bit segment is (0, 0, 0, 0), and the second second - type bit segment is (0, 1, 0, 0);

[0388] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second - type bit segment is (0, 0, 0, 0), and the second second - type bit segment is (1, 1, 0, 0);

[0389] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second - type bit segment is (0, 0, 0, 0), and the second second - type bit segment is (0, 0, 1, 0);

[0390] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second - type bit segment is (0, 0, 1, 0), and the second second - type bit segment is (0, 0, 0, 0);

[0391] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second - type bit segment is (1, 0, 0, 0), and the second second - type bit segment is (1, 1, 0, 0);

[0392] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 1), the first second - type bit segment is (1, 0, 0, 0), and the second second - type bit segment is (0, 1, 0, 0);

[0393] In the second bit sequence corresponding to the first bit sequence (1, 1, 0, 0), the first second - type bit segment is (0, 1, 0, 0), and the second second - type bit segment is (1, 0, 0, 0);

[0394] In the second bit sequence corresponding to the first bit sequence (1, 1, 1, 0), the first second - type bit segment is (1, 1, 0, 0), and the second second - type bit segment is (1, 0, 0, 0);

[0395] The second bit sequence corresponding to the first bit sequence (1, 1, 0, 1) and the second bit sequence corresponding to the first bit sequence (1, 1, 1, 1) are any two of the following second bit sequences:

[0396] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0);

[0397] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0);

[0398] A second bit sequence in which the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0399] A second bit sequence in which the first second - type bit segment is (1, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0400] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0);

[0401] A second bit sequence in which the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0).

[0402] 2 d first bit sequences and 2 dThe one-to-one correspondence of the second bit sequences can be shown in Table 8 and Table 9. Among them, Table 8 shows 16 first bit sequences and 14 second bit sequences, and for two first bit sequences in Table 8, the corresponding second bit sequences are empty. The second bit sequences corresponding to these two first bit sequences can be any two of the 6 second bit sequences shown in Table 9. The first bit sequences in Table 8 also include a consecutive first type bit segment and a second type bit segment, and the first type bit segment and the second type bit segment are arranged from left to right in Table 8. The first type bit segment or the second type bit segment is multiple bits of the highest bit in the first bit sequence. The first second type bit segment and the second second type bit segment in the second bit sequence are also arranged from left to right in Table 8 and Table 9. The first second type bit segment or the second second type bit segment is multiple bits of the highest bit in the second bit sequence.

[0403] Table 8

[0404]

[0405]

[0406] Table 9

[0407]

[0408] It can be understood that based on the above 2 d first bit sequences and the above 2 d second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 8 and Table 9. For example, swap the second bit sequences corresponding to any two first bit sequences in the above example. Another example is to scramble the order of the 16 second bit sequences jointly given by Table 8 and Table 9 (the 14 second bit sequences in Table 8 and any two of the six second bit sequences given by Table 9), and keep the order of the 16 first bit sequences in Table 8 unchanged.

[0409] 5. The fifth implementation manner of 2 d second bit sequences.

[0410] In this fifth implementation manner, the number of low-amplitude bits of any one of the 2 d second bit sequences is greater than or equal to the number of low-amplitude bits of any one of the 2 h second bit sequences except the 2 d second bit sequences.

[0411] In the fifth implementable manner, the middle bit sequence includes 10 bits, the second type of bit segment includes 6 bits, and the second bit sequence includes: a consecutive first second type of bit segment and a second second type of bit segment; 2 d The two second bit sequences may include 11 second bit sequences shown in Table 10 and any 5 second bit sequences among the 14 second bit sequences shown in Table 11.

[0412] It can be seen that 2 d The two second bit sequences include:

[0413] A second bit sequence in which the first second type of bit segment is (0, 0, 0, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0, 0, 0);

[0414] A second bit sequence in which the first second type of bit segment is (0, 0, 0, 0, 0, 0) and the second second type of bit segment is (1, 0, 0, 0, 0, 0);

[0415] A second bit sequence in which the first second type of bit segment is (0, 0, 0, 0, 0, 0) and the second second type of bit segment is (0, 1, 0, 0, 0, 0);

[0416] A second bit sequence in which the first second type of bit segment is (1, 0, 0, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0, 0, 0);

[0417] A second bit sequence in which the first second type of bit segment is (0, 1, 0, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0, 0, 0);

[0418] A second bit sequence in which the first second type of bit segment is (0, 0, 0, 0, 0, 0) and the second second type of bit segment is (1, 1, 0, 0, 0, 0);

[0419] A second bit sequence in which the first second type of bit segment is (1, 1, 0, 0, 0, 0) and the second second type of bit segment is (0, 0, 0, 0, 0, 0);

[0420] A second bit sequence in which the first second type of bit segment is (0, 1, 0, 0, 0, 0) and the second second type of bit segment is (0, 1, 0, 0, 0, 0);

[0421] A second bit sequence in which the first second type of bit segment is (0, 1, 0, 0, 0, 0) and the second second type of bit segment is (1, 0, 0, 0, 0, 0);

[0422] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0423] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0424] And any five of the following second bit sequences:

[0425] A second bit sequence in which the first second - type bit segment is (0, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0426] A second bit sequence in which the first second - type bit segment is (1, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0427] A second bit sequence in which the first second - type bit segment is (0, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0428] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0429] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0430] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0431] A second bit sequence in which the first second - type bit segment is (1, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0432] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 1, 0, 0);

[0433] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0);

[0434] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0, 0, 0);

[0435] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0, 0, 0);

[0436] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 1, 0, 0);

[0437] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0, 0, 0);

[0438] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 1, 0, 0);

[0439] Among them, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position.

[0440] Optionally, in this fifth implementable manner, 2 d first bit sequences can include 16 first bit sequences, and in the one - to - one correspondence between 2 d first bit sequences and 2 d second bit sequences:

[0441] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 0), the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0442] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 0), the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0443] In the second bit sequence corresponding to the first bit sequence (0, 0, 0, 1), the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0444] In the second bit sequence corresponding to the first bit sequence (0, 0, 1, 1), the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0445] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 0), the first second - type bit segment is (0, 1, 0, 0, 0, 0), and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0446] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 0), the first second - type bit segment is (0, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 1, 0, 0, 0, 0);

[0447] In the second bit sequence corresponding to the first bit sequence (1, 0, 0, 1), the first second - type bit segment is (1, 1, 0, 0, 0, 0), and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0448] In the second bit sequence corresponding to the first bit sequence (1, 0, 1, 1), the first second - type bit segment is (0, 1, 0, 0, 0, 0), and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0449] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 0), the first second - type bit segment is (0, 1, 0, 0, 0, 0), and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0450] In the second bit sequence corresponding to the first bit sequence (0, 1, 1, 0), the first second - type bit segment is (1, 0, 0, 0, 0, 0), and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0451] In the second bit sequence corresponding to the first bit sequence (0, 1, 0, 1), the first second - type bit segment is (1, 0, 0, 0, 0, 0), and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0452] The second bit sequences corresponding to the first bit sequence (0, 1, 1, 1), the first bit sequence (1, 1, 0, 0), the first bit sequence (1, 1, 1, 0), the first bit sequence (1, 1, 0, 1), and the first bit sequence (1, 1, 1, 1) are any five of the following second bit sequences:

[0453] A second bit sequence in which the first second - type bit segment is (0, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0454] A second bit sequence in which the first second - type bit segment is (1, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0455] A second bit sequence in which the first second - type bit segment is (0, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0456] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0457] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0458] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0459] A second bit sequence in which the first second - type bit segment is (1, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0460] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 1, 0, 0);

[0461] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0);

[0462] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0, 0, 0);

[0463] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0, 0, 0);

[0464] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 1, 0, 0);

[0465] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0, 0, 0);

[0466] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 1, 0, 0).

[0467] 2 d The one - to - one correspondence between 2 d first bit sequences and 2

[0468] Table 10

[0469]

[0470] Table 11

[0471]

[0472]

[0473] It can be understood that based on the above - mentioned 2 d first bit sequences and the above - mentioned 2 d second bit sequences, the one - to - one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 10 and Table 11. For example, swap the second bit sequences corresponding to any two of the above - mentioned first bit sequences. Another example is to shuffle the order of the 16 second bit sequences jointly given by Table 10 and Table 11 (the 11 second bit sequences in Table 8 and any five of the 14 second bit sequences given by Table 11), and keep the order of the 16 first bit sequences in Table 10 unchanged.

[0474] 6. The sixth implementation method of 2 d second bit sequences.

[0475] In this sixth implementation method, 2 dThe number of low - amplitude bits in any second bit sequence among the second bit sequences is greater than or equal to 2 h except for 2 d in the second bit sequences, the number of low - amplitude bits in any second bit sequence other than the 2

[0476] In the sixth implementation, the middle bit sequence includes 11 bits, the second - type bit segment includes 7 bits, and the second bit sequence includes: the consecutive first second - type bit segment and the second second - type bit segment; 2 d The 2

[0477] It can be seen that the 2 d second bit sequences include:

[0478] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0479] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0480] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0481] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0482] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0483] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0484] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0485] And, any nine second bit sequences from the following second bit sequences:

[0486] The second bit sequence where the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 0, 1, 0, 0, 0, 0);

[0487] The second bit sequence where the first second-type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0488] The second bit sequence where the first second-type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0489] The second bit sequence where the first second-type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0490] The second bit sequence where the first second-type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0491] The second bit sequence where the first second-type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0492] The second bit sequence where the first second-type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0493] The second bit sequence where the first second-type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0494] The second bit sequence where the first second-type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0495] The second bit sequence where the first second-type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0496] The second bit sequence where the first second-type bit segment is (0, 0, 1, 0, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0497] Wherein, the bits in the second-type bit segment are arranged from left to right in the order from the lowest bit to the highest bit or from the highest bit to the lowest bit according to the bit positions.

[0498] Optionally, in this sixth implementation manner, 2 d first bit sequences may include 16 first bit sequences. In the one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences:

[0499] Among the second bit sequences corresponding to the first bit sequence (0, 0, 0, 0), the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0), and the second second-type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0500] Among the second bit sequences corresponding to the first bit sequence (0, 0, 1, 0), the first second-type bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second-type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0501] Among the second bit sequences corresponding to the first bit sequence (0, 0, 0, 1), the first second-type bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second-type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0502] Among the second bit sequences corresponding to the first bit sequence (0, 0, 1, 1), the first second-type bit segment is (1, 0, 0, 0, 0, 0, 0), and the second second-type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0503] Among the second bit sequences corresponding to the first bit sequence (1, 0, 0, 0), the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0), and the second second-type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0504] Among the second bit sequences corresponding to the first bit sequence (1, 0, 1, 0), the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0), and the second second-type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0505] Among the second bit sequences corresponding to the first bit sequence (1, 0, 0, 1), the first second-type bit segment is (0, 0, 0, 0, 0, 0, 0), and the second second-type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0506] The second bit sequences corresponding to the first bit sequences (1, 0, 1, 1), (0, 1, 0, 0), (0, 1, 1, 0), (0, 1, 0, 1), (0, 1, 1, 1), (1, 1, 0, 0), (1, 1, 1, 0), (1, 1, 0, 1), (1, 1, 1, 1) are any nine of the following second bit sequences:

[0507] The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0, 0);

[0508] The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0509] The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0510] The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0511] The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0512] The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0513] The second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0514] The second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0515] The second bit sequence where the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0516] The second bit sequence where the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0517] The second bit sequence where the first second - type bit segment is (0, 0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0).

[0518] 2 d one - to - one correspondences between 2 d second bit sequences can be shown in Table 12 and Table 13. Among them, Table 12 shows 16 first bit sequences and 7 second bit sequences, and for 9 first bit sequences in Table 11, the corresponding second bit sequences are empty. The second bit sequences corresponding to these five first bit sequences can be any 9 of the 11 second bit sequences shown in Table 12. The first bit sequences in Table 12 also include consecutive first first - type bit segments and second first - type bit segments, and the first first - type bit segment and the second first - type bit segment are arranged from left to right in Table 12. The first first - type bit segment or the second first - type bit segment is multiple bits of the highest bit in the first bit sequence. The first second - type bit segment and the second second - type bit segment in the second bit sequence are also arranged from left to right in Table 12 and Table 13. The first second - type bit segment or the second second - type bit segment is multiple bits of the highest bit in the second bit sequence.

[0519] Table 12

[0520]

[0521] Table 13

[0522]

[0523] It can be understood that among the above - mentioned 2 d first bit sequences and the above - mentioned 2 dBased on the second bit sequence, the one-to-one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 12 and Table 13. For example, swap the second bit sequences corresponding to any two first bit sequences in the above example. Another example is to shuffle the order of the 16 second bit sequences jointly given in Table 12 and Table 13 (7 second bit sequences in Table 12 and any 9 of the 11 second bit sequences given in Table 13), while keeping the order of the 16 first bit sequences in Table 12 unchanged.

[0524] 7, 2 d The seventh implementation manner of the second bit sequence.

[0525] In this seventh implementation manner, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h Among the second bit sequences, except for 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0526] In the seventh implementation manner, the middle bit sequence includes 10 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. These 2 d The second bit sequences include 256 second bit sequences, and these 256 second bit sequences include 246 second bit sequences shown in Table 14 and any 10 of the 24 second bit sequences shown in Table 15. In Table 14 and Table 15, the second bit sequence includes 4 consecutive second type of bit segments, and these 4 second type of bit segments can be the 4 second type of bit segments arranged from left to right in Table 14 and Table 15. Among them, the bits in the bit sequence are arranged from left to right in the order of bit positions from low to high.

[0527] Optionally, under this seventh implementation manner, 2 d The first bit sequences can include 256 first bit sequences, 2 d The one-to-one correspondence between the first bit sequences and 2 d The second bit sequences can be as shown in Table 14, and among them, the second bit sequences corresponding to some first bit sequences are empty, and these second bit sequences corresponding to the first bit sequences can be any 10 of the 24 second bit sequences shown in Table 15. In Table 14, the first type of bit segment counted from left to right or the second type of bit segment is the multiple bits of the highest bit in the first bit sequence; in Table 14 and Table 15, the first type of bit segment counted from left to right or the second type of bit segment is the multiple bits of the highest bit in the second bit sequence.

[0528] It can be understood that, based on the above-mentioned 2 d first bit sequences and the above-mentioned 2 d second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 14 and Table 15. For example, swap the second bit sequences corresponding to any two first bit sequences in the above example. Another example is to scramble the order of the 256 second bit sequences jointly given by Table 14 and Table 15 (246 second bit sequences in Table 14 and any 10 second bit sequences among the 24 second bit sequences given by Table 15), and keep the order of the 256 first bit sequences in Table 14 unchanged.

[0529] Table 14

[0530]

[0531]

[0532]

[0533]

[0534]

[0535]

[0536] Table 15

[0537]

[0538] 8. The eighth implementation manner of 2 d second bit sequences.

[0539] In this eighth implementation manner, the low-amplitude bit number of any one of the 2 d second bit sequences is greater than the low-amplitude bit number of any one of the 2 h second bit sequences except for the 2 d second bit sequences.

[0540] In the eighth implementation manner, the middle bit sequence includes 11 bits, the second type of bit segment includes 3 bits, and the second bit sequence includes 4 second type of bit segments. These 2 dThe second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include the 256 second bit sequences shown in Table 16. In Table 16, the second bit sequence includes 4 consecutive second type bit segments, and these 4 second type bit segments can be the 4 second type bit segments arranged from left to right in Table 16. Among them, the bits in the second type bit segment are arranged from left to right in the order from the lowest bit to the highest bit or from the highest bit to the lowest bit.

[0541] Optionally, in this eighth implementation manner, 2 d first bit sequences may include 256 first bit sequences, and the one-to-one correspondence between the 2 d first bit sequences and the 2 d second bit sequences may be as shown in Table 16. In Table 16, the first first type bit segment or the second first type bit segment counted from left to right are multiple bits of the highest bit in the first bit sequence, and the first second type bit segment or the second second type bit segment counted from left to right are multiple bits of the highest bit in the second bit sequence.

[0542] It can be understood that, based on the above 2 d first bit sequences and the above 2 d second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 16. For example, swap the second bit sequences corresponding to any two first bit sequences in the above example. Another example is to scramble the order of the 256 second bit sequences given in Table 16 while keeping the order of the 256 first bit sequences in Table 16 unchanged.

[0543] Table 16

[0544]

[0545]

[0546]

[0547]

[0548]

[0549]

[0550] 9. The ninth implementation manner of 2 d second bit sequences.

[0551] In this ninth implementation manner, the number of low-amplitude bits of any second bit sequence in the 2 d second bit sequences is greater than or equal to the number of low-amplitude bits of the 2 h second bit sequences except the 2d The number of low - amplitude bits of any second bit sequence other than the second bit sequence.

[0552] In the ninth implementation, the intermediate bit sequence includes 10 bits, the second - type bit segment includes 3 bits, and the second bit sequence includes 4 second - type bit segments. These 2 d second bit sequences include 64 second bit sequences, and these 64 second bit sequences include 61 second bit sequences shown in Table 17 and any 3 second bit sequences among the 12 second bit sequences shown in Table 18. In Table 17 and Table 18, the second bit sequence includes 4 consecutive second - type bit segments, and these 4 second - type bit segments can be the 4 second - type bit segments arranged from left to right in Table 17 and Table 18. Among them, the bits in the second - type bit segment are arranged from left to right in the order from low bit to high bit or from high bit to low bit.

[0553] Optionally, in this ninth implementation, 2 d first bit sequences can include 64 first bit sequences. 2 d The one - to - one correspondence between 2 d first bit sequences and 2

[0554] second bit sequences can be as shown in Table 17. And, in Table 17, the second bit sequences corresponding to some first bit sequences are empty, and the second bit sequences corresponding to these first bit sequences can be any 3 of the 12 second bit sequences shown in Table 18. In Table 17, the first first - type bit segment or the second first - type bit segment counted from left to right is the multiple bits of the highest bit in the first bit sequence; in Table 17 and Table 18, the first second - type bit segment or the second second - type bit segment counted from left to right is the multiple bits of the highest bit in the second bit sequence. d first bit sequences and the above - mentioned 2 d second bit sequences, the one - to - one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 17 and Table 18. For example, swap the second bit sequences corresponding to any two first bit sequences in the above example. Another example is to shuffle the order of the 64 second bit sequences jointly given in Table 17 and Table 18 (61 second bit sequences in Table 17 and any 3 of the 12 second bit sequences given in Table 18), and keep the order of the 64 first bit sequences in Table 17 unchanged.

[0555] Table 17

[0556]

[0557]

[0558] Table 18

[0559]

[0560] 10, 2 d The tenth implementation of the second bit sequence.

[0561] In this tenth implementation, 2 d the number of low-amplitude bits of any one of the second bit sequences in the 2 h second bit sequences is greater than or equal to the number of low-amplitude bits of any one of the second bit sequences other than the 2 d second bit sequences.

[0562] In the tenth implementation, the middle bit sequence includes 11 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes 4 second type of bit segments. These 2 d second bit sequences include 256 second bit sequences, and these 256 second bit sequences include 212 second bit sequences shown in Table 19 and any 44 second bit sequences among the 56 second bit sequences shown in Table 20. In Table 19 and Table 20, the second bit sequence includes 4 consecutive second type of bit segments, and these 4 second type of bit segments can be the 4 second type of bit segments arranged from left to right in Table 19 and Table 20. Among them, the bits in the second type of bit segment are arranged from left to right in the order of bit position from low to high or from high to low.

[0563] Optionally, under this tenth implementation, the 2 d first bit sequences can include 256 first bit sequences, and the one-to-one correspondence between the 2 d first bit sequences and the 2 d second bit sequences can be as shown in Table 19. And some of the second bit sequences corresponding to the first bit sequences in Table 19 are empty, and the second bit sequences corresponding to these first bit sequences can be any 44 of the 56 second bit sequences shown in Table 20. In Table 19, the first type of bit segment counted from left to right or the second type of bit segment is the multiple bits of the highest bit in the first bit sequence; in Table 19 and Table 20, the first type of bit segment counted from left to right or the second type of bit segment is the multiple bits of the highest bit in the second bit sequence.

[0564] It can be understood that among the above 2 d first bit sequences and the above 2 dBased on the second bit sequence, the one-to-one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 19 and Table 20. For example, the second bit sequences corresponding to any two first bit sequences in the above example are swapped. Another example is to shuffle the order of the 256 second bit sequences jointly given by Table 19 and Table 20 (212 second bit sequences in Table 19 and any 44 of the 56 second bit sequences given by Table 20), while keeping the order of the 256 first bit sequences in Table 19 unchanged.

[0565] Table 19

[0566]

[0567]

[0568]

[0569]

[0570]

[0571]

[0572] Table 20

[0573]

[0574]

[0575] 11, 2 d The eleventh implementation manner of the two second bit sequences.

[0576] In this eleventh implementation manner, for any one of the two second bit sequences, the number of low-amplitude bits is greater than or equal to the number of low-amplitude bits of any one of the two second bit sequences other than the two second bit sequences. d For any one of the two second bit sequences, the number of low-amplitude bits is greater than or equal to the number of low-amplitude bits of any one of the two second bit sequences other than the two second bit sequences. h For any one of the two second bit sequences, the number of low-amplitude bits is greater than or equal to the number of low-amplitude bits of any one of the two second bit sequences other than the two second bit sequences. d For any one of the two second bit sequences, the number of low-amplitude bits is greater than or equal to the number of low-amplitude bits of any one of the two second bit sequences other than the two second bit sequences.

[0577] In the eleventh implementation manner, the middle bit sequence includes 10 bits, the second type of bit segment includes 6 bits, and the second bit sequence includes 4 second type of bit segments. These two dThe second bit sequence includes 256 second bit sequences, and the 256 second bit sequences include 121 second bit sequences shown in Table 21 and any 135 second bit sequences among the 174 second bit sequences shown in Table 22. In Table 21 and Table 22, the second bit sequence includes 4 consecutive second type bit segments, and these 4 second type bit segments can be the 4 second type bit segments arranged from left to right in Table 20 and Table 21. Among them, the bits in the second type bit segment are arranged from left to right in the order of lowest bit to highest bit or highest bit to lowest bit.

[0578] Optionally, in this eleventh implementation manner, 2 d first bit sequences may include 256 first bit sequences, and the one-to-one correspondence between the 2 d first bit sequences and the 2 d second bit sequences may be as shown in Table 21. Moreover, for some first bit sequences in Table 21, the corresponding second bit sequences are empty, and the second bit sequences corresponding to these first bit sequences may be any 135 second bit sequences among the 174 second bit sequences shown in Table 22. In Table 21, the first first type bit segment or the second first type bit segment counted from left to right is the multiple bits of the highest bit in the first bit sequence; in Table 21 and Table 22, the first second type bit segment or the second second type bit segment counted from left to right is the multiple bits of the highest bit in the second bit sequence.

[0579] It can be understood that based on the above 2 d first bit sequences and the above 2 d second bit sequences, the one-to-one correspondence between the first bit sequence and the second bit sequence may also be different from that shown in Table 21 and Table 22. For example, swap the second bit sequences corresponding to any two first bit sequences in the above example. Another example is to scramble the order of the 256 second bit sequences jointly given by Table 21 and Table 22 (121 second bit sequences in Table 21 and any 135 second bit sequences among the 174 second bit sequences given by Table 22), and keep the order of the 256 first bit sequences in Table 21 unchanged.

[0580] Table 21

[0581]

[0582]

[0583]

[0584]

[0585]

[0586]

[0587]

[0588] Table 22

[0589]

[0590]

[0591]

[0592]

[0593]

[0594] 12, 2 d The twelfth implementation of the two second bit sequences.

[0595] In this twelfth implementation, for any one of the two second bit sequences, the number of low-amplitude bits is greater than or equal to the number of low-amplitude bits of any other second bit sequence among the two second bit sequences. d the number of low-amplitude bits of any one of the two second bit sequences is greater than or equal to h the number of low-amplitude bits of any other second bit sequence among the two second bit sequences except for d the two second bit sequences.

[0596] In the twelfth implementation, the middle bit sequence includes 10 bits, the second type of bit segment includes 7 bits, and the second bit sequence includes 4 second type of bit segments. These two second bit sequences include 256 second bit sequences, which include 255 second bit sequences shown in Table 23 and any one second bit sequence among the 324 second bit sequences shown in Table 24. In Table 23 and Table 24, the second bit sequence includes 4 consecutive second type of bit segments, and these 4 second type of bit segments can be the 4 second type of bit segments arranged from left to right in Table 23 and Table 24. Among them, the bits in the second type of bit segment are arranged from left to right in the order of bit positions from low to high or from high to low. d Optionally, under this twelfth implementation, the two first bit sequences may include 256 first bit sequences. The two first bit sequences and the two

[0597] Optionally, under this twelfth implementation, the two first bit sequences can include 256 first bit sequences. The two first bit sequences and the two d the two first bit sequences can include 256 first bit sequences, and the two d the two first bit sequences and the two dThe one-to-one correspondence of the second bit sequences can be as shown in Table 23. Moreover, for some of the first bit sequences in Table 23, the corresponding second bit sequences are empty, and the second bit sequences corresponding to these first bit sequences can be any one of the 324 second bit sequences shown in Table 24. In Table 23, the first or second first-type bit segment counted from left to right is multiple bits of the highest bit in the first bit sequence; in Table 23 and Table 24, the first or second second-type bit segment counted from left to right is multiple bits of the highest bit in the second bit sequence.

[0598] It can be understood that based on the above 2 d first bit sequences and the above 2 d second bit sequences, the one-to-one correspondence between the first bit sequences and the second bit sequences can also be different from that shown in Table 23 and Table 24. For example, swap the second bit sequences corresponding to any two of the above examples. Another example is to scramble the order of the 256 second bit sequences jointly given by Table 23 and Table 24 (the 255 second bit sequences in Table 23 and any one of the 324 second bit sequences given in Table 24), and keep the order of the 256 first bit sequences in Table 23 unchanged.

[0599] Table 23

[0600]

[0601]

[0602]

[0603]

[0604]

[0605]

[0606]

[0607] Table 24

[0608]

[0609]

[0610]

[0611]

[0612]

[0613]

[0614]

[0615]

[0616] 13.2 d A thirteenth possible implementation of the second bit sequence.

[0617] In the thirteenth possible implementation, 2 d The number of low-amplitude bits of any second bit sequence in the second bit sequences is greater than or equal to 2 h The second bit sequence is divided by 2 d The number of low-amplitude bits of any second bit sequence other than the second bit sequences.

[0618] In a thirteenth possible implementation manner, the intermediate bit sequence includes 10 bits, the second type of bit segment includes 4 bits, and the second bit sequence includes 4 second type of bit segments. d The second bit sequence includes 1024 second bit sequences, and the 1024 second bit sequences include 903 second bit sequences shown in Table 25, and any 121 second bit sequences among the 156 second bit sequences shown in Table 26. In Tables 25 and 26, the second bit sequence includes 4 consecutive second-type bit segments, and the 4 second-type bit segments can be the 4 second-type bit segments arranged from left to right in Tables 25 and 26. The bits in the second-type bit segment are arranged from left to right in the order of bit positions from low to high or from high to low.

[0619] Optionally, in the thirteenth possible implementation, 2 d The first bit sequence may include 1024 first bit sequences, 2 d The first bit sequence and 2 d The one-to-one correspondence between the first bit sequences and the second bit sequences can be shown in Table 25, and the second bit sequences corresponding to some first bit sequences in Table 25 are empty, and the second bit sequences corresponding to these first bit sequences can be any 121 second bit sequences among the 156 second bit sequences shown in Table 26. In Table 25, the first first-category bit segment or the second first-category bit segment from left to right is the most significant bits in the first bit sequence; in Tables 25 and 26, the first second-category bit segment or the second second-category bit segment from left to right is the most significant bits in the second bit sequence.

[0620] It is understandable that in the above 2 d The first bit sequence and the above 2 dBased on the second bit sequence, the one-to-one correspondence between the first bit sequence and the second bit sequence can also be different from that shown in Table 25 and Table 26. For example, the second bit sequences corresponding to any two first bit sequences in the above example are interchanged. Another example is to shuffle the order of the 1024 second bit sequences jointly given in Table 25 and Table 26 (903 second bit sequences in Table 25 and any 121 of the 156 second bit sequences given in Table 26), while keeping the order of the 1024 first bit sequences in Table 25 unchanged.

[0621] Table 25

[0622]

[0623]

[0624]

[0625]

[0626]

[0627]

[0628]

[0629]

[0630]

[0631]

[0632]

[0633]

[0634]

[0635]

[0636]

[0637]

[0638]

[0639]

[0640]

[0641]

[0642]

[0643]

[0644]

[0645]

[0646] Table 26

[0647]

[0648]

[0649]

[0650]

[0651] According to the various realizable manners of the foregoing 2 d second bit sequences, it can be known that in the one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences, the 2 d second bit sequences are related not only to d, but also to the number of bits in the intermediate bit sequence, the number of bits in the second type of bit segment, and the number of second type of bit segments.

[0652] The number of bits in the intermediate bit sequence determines the size of the table searched for subsequent distribution matching processing, as well as the correspondence between each index bit sequence and the result bit sequence in the table.

[0653] Exemplarily, the table searched for in the distribution matching processing corresponding to the foregoing various realizable manners may include the correspondence between an index bit sequence of 10 bits and a result bit sequence of 10 bits (as shown in Table 27), or the correspondence between an index bit sequence of 11 bits and a result bit sequence of 11 bits (as shown in Table 28).

[0654] In Table 27 and Table 28, it is taken as an example that a 0 bit is mapped to a higher amplitude bit and a 1 bit is mapped to a lower amplitude bit. Among them, the index bit sequence includes a total of Y bits, Y>1, Y = 10 in Table 27, Y = 11 in Table 28, and the first bit to the Yth bit of the index bit sequence are represented as [1:Y]. The Yth bit is the highest bit. The result bit sequence includes N bits, N>1, N = 10 in Table 27, N = 11 in Table 28, the first bit in the result bit sequence is represented as N[1], the second bit in the result bit sequence is represented as N[2], and so on.

[0655] Table 27

[0656]

[0657] Table 28

[0658]

[0659]

[0660] Optionally, assume that the number of the first type of bit segments in the first bit sequence is p, the number of the second type of bit segments in the second bit sequence is q, the number of bits in the first type of bit segments is c, and the number of bits in the second type of bit segments is e. Then, p, q, c, and e in this application can have multiple values.

[0661] Exemplarily, p = 2, c = 2, q = 2, e = 3; or, p = 2, c = 2, q = 2, e = 4; or, p = 2, c = 2, q = 2, e = 6; or, p = 2, c = 2, q = 2, e = 7; or, p = 4, c = 2, q = 4, e = 3; or, p = 4, c = 2, q = 4, e = 4; or, p = 4, c = 2, q = 4, e = 6; or, p = 4, c = 2, q = 4, e = 7; or, p = 4, q = 4, e = 3; among the 4 first-type bit segments, c of two first-type bit segments is 1, and c of the other two first-type bit segments is 2; or, p = 4, q = 4, e = 4; among the 4 first-type bit segments, c of two first-type bit segments is 2, and c of the other two first-type bit segments is 3. It can be understood that the values of p, q, c, and e can also be different from the values listed here, and the embodiments of this application do not limit this.

[0662] Optionally, the number of bits in the above bit subsequence and the number of bits in the middle bit sequence can both have multiple implementation manners.

[0663] For example, the bit subsequence includes 6 bits, and the middle bit sequence includes 10 bits or 11 bits;

[0664] Or, the bit subsequence includes 8 bits, and the middle bit sequence includes 10 bits;

[0665] Or, the bit subsequence includes 9 bits, and the middle bit sequence includes 10 bits or 11 bits;

[0666] Or, the bit subsequence includes 10 bits, and the middle bit sequence includes 11 bits;

[0667] Alternatively, p = 4. Among the four first-type bit segments, two first-type bit segments each include 1 bit, and the other two first-type bit segments each include 2 bits; among the four bit subsequences, two bit subsequences include 8 bits, and the other two bit subsequences include 9 bits; the middle bit sequence includes 10 bits; the first-type bit segment in the bit subsequence including 8 bits includes 1 bit; the first-type bit segment in the bit subsequence including 9 bits includes 2 bits.

[0668] Alternatively, p = 4. Among the four first-type bit segments, two first-type bit segments each include 2 bits, and the other two first-type bit segments each include 3 bits; among the four bit subsequences, two bit subsequences include 8 bits, and the other two bit subsequences include 9 bits; the middle bit sequence includes 10 bits; the first-type bit segment of the bit subsequence including 8 bits includes 2 bits; the first-type bit segment of the bit subsequence including 9 bits includes 3 bits.

[0669] It can be understood that the number of bits in the bit subsequence and the number of bits in the middle bit sequence can also be different from the number of bits listed here, and the embodiments of the present application do not limit this.

[0670] Any one of the above values of p, q, c, and e can be combined with any one of the implementation manners of the number of bits in the above bit subsequence and the number of bits in the middle bit sequence.

[0671] For example, when p = 2, q = 2, e = 3, and c = 2, the bit subsequence includes 9 bits, and the middle bit sequence includes 10 bits;

[0672] Alternatively, when p = 2, q = 2, e = 3, and c = 2, the bit subsequence includes 10 bits, and the middle bit sequence includes 11 bits;

[0673] Alternatively, when p = 2, q = 2, e = 4, and c = 2, the bit subsequence includes 8 bits, and the middle bit sequence includes 10 bits;

[0674] Alternatively, when p = 2, q = 2, e = 4, and c = 2, the bit subsequence includes 9 bits, and the middle bit sequence includes 11 bits;

[0675] Alternatively, when p = 2, q = 2, e = 6, and c = 2, the bit subsequence includes 6 bits, and the middle bit sequence includes 10 bits;

[0676] Alternatively, when p = 2, q = 2, e = 7, and c = 2, the bit subsequence includes 6 bits, and the middle bit sequence includes 11 bits;

[0677] Alternatively, when p = 4, q = 4, e = 3, and c = 2, the bit subsequence includes 9 bits, and the middle bit sequence includes 10 bits;

[0678] Alternatively, when p = 4, q = 4, e = 3, and c = 2, the bit subsequence includes 10 bits, and the middle bit sequence includes 11 bits;

[0679] Alternatively, when p = 4, q = 4, e = 3; among the 4 first - type bit segments, c of two first - type bit segments is 1, and c of the other two first - type bit segments is 2, among the 4 bit subsequences, two bit subsequences include 8 bits, and the other two bit subsequences include 9 bits; the middle bit sequence includes 10 bits; the first - type bit segment in the bit subsequence including 8 bits includes 1 bit; the first - type bit segment in the bit subsequence including 9 bits includes 2 bits;

[0680] Alternatively, when p = 4, q = 4, e = 4, and c = 2, the bit subsequence includes 9 bits, and the middle bit sequence includes 11 bits;

[0681] Alternatively, when p = 4, q = 4, e = 6, and c = 2, the bit subsequence includes 6 bits, and the middle bit sequence includes 10 bits;

[0682] Alternatively, when p = 4, q = 4, e = 7, and c = 2, the bit subsequence includes 6 bits, and the middle bit sequence includes 11 bits;

[0683] Alternatively, when p = 4, q = 4, e = 4; among the 4 first - type bit segments, c of two first - type bit segments is 2, and c of the other two first - type bit segments is 3, among the 4 bit subsequences, two bit subsequences include 8 bits, and the other two bit subsequences include 9 bits; the middle bit sequence includes 10 bits; the first - type bit segment in the bit subsequence including 8 bits includes 2 bits; the first - type bit segment of the bit subsequence including 9 bits includes 3 bits.

[0684] Optionally, before the above - mentioned S101, the first sequence processing device may also divide multiple bit subsequences in the initial bit sequence from the to - be - processed bit sequence. The to - be - processed bit sequence may belong to the bit stream received by the first sequence processing device, and the first sequence processing device may select that number of bits as the to - be - processed bits in the received bit stream according to the number of bits in the to - be - processed bit sequence.

[0685] Further, in the above embodiments, an initial bit sequence is taken as an example. Optionally, there may be multiple initial bit sequences. In this case, the first sequence processing device may obtain multiple target bit sequences according to each initial bit sequence in S101 and S102 above, and merge all the target bit sequences obtained according to the multiple initial bit sequences in S103.

[0686] The multiple initial bit sequences may be received by the first sequence processing device, or may be obtained by the first sequence processing device by dividing the bit sequence to be processed.

[0687] In the case where the multiple initial bit sequences are obtained by dividing the bit sequence to be processed, the first sequence processing device may divide the bit sequence to be processed into multiple initial bit sequences, or the first sequence processing device may divide the bit sequence to be processed into multiple bit subsequences among the multiple initial bit sequences. In addition, the multiple initial bit sequences are continuous or discontinuous in the bit sequence to be processed. In the embodiments of the present application, the case where the multiple initial bit sequences are continuous in the bit sequence to be processed is taken as an example.

[0688] In addition, in the process of the first sequence processing device obtaining the intermediate bit sequence according to different initial bit sequences, the expansion tables used may be the same or different. The embodiments of the present application do not limit this.

[0689] Exemplarily, assume that there are two initial bit sequences, namely initial bit sequence 1 and initial bit sequence 2. As Figure 4 shown, the first sequence processing device may split the bit sequence to be processed into initial bit sequence 1 and initial bit sequence 2.

[0690] The first sequence processing device may obtain intermediate bit sequence 1.1 and intermediate bit sequence 1.2 according to initial bit sequence 1. Intermediate bit sequence 1.1 is related to both bit subsequence 1.1 and bit subsequence 1.2 in initial bit sequence 1, and intermediate bit sequence 1.2 is related to both bit subsequence 1.1 and bit subsequence 1.2 in initial bit sequence 1. The first sequence processing device may further obtain target bit sequence 1.1 according to intermediate bit sequence 1.1, and obtain target bit sequence 1.2 according to intermediate bit sequence 1.2.

[0691] The first sequence processing device can also obtain an intermediate bit sequence 2.1 and an intermediate bit sequence 2.2 based on the initial bit sequence 2. The intermediate bit sequence 2.1 is related to both the bit subsequence 2.1 and the bit subsequence 2.2 in the initial bit sequence 2, and the intermediate bit sequence 2.2 is related to both the bit subsequence 2.1 and the bit subsequence 2.2 in the initial bit sequence 2. The first sequence processing device can also obtain a target bit sequence 2.1 based on the intermediate bit sequence 2.1 and obtain a target bit sequence 2.2 based on the intermediate bit sequence 2.2.

[0692] Also, by way of example, assume there are two initial bit sequences, namely the initial bit sequence 1 and the initial bit sequence 2, as Figure 5 shown. The first sequence processing device can split the bit sequence to be processed into a bit subsequence 1.1, a bit subsequence 1.2, a bit subsequence 2.1, and a bit subsequence 2.2. Among them, the initial bit sequence 1 includes the bit subsequence 1.1 and the bit subsequence 1.2, and the initial bit sequence 2 includes the bit subsequence 2.1 and the bit subsequence 2.2.

[0693] The first sequence processing device can obtain an intermediate bit sequence 1.1 and an intermediate bit sequence 1.2 based on the initial bit sequence 1 (including the bit subsequence 1.1 and the bit subsequence 1.2). The intermediate bit sequence 1.1 is related to both the bit subsequence 1.1 and the bit subsequence 1.2, and the intermediate bit sequence 1.2 is related to both the bit subsequence 1.1 and the bit subsequence 1.2. The first sequence processing device can also obtain a target bit sequence 1.1 based on the intermediate bit sequence 1.1 and obtain a target bit sequence 1.2 based on the intermediate bit sequence 1.2.

[0694] The first sequence processing device can also obtain an intermediate bit sequence 2.1 and an intermediate bit sequence 2.2 based on the initial bit sequence 2 (including the bit subsequence 2.1 and the bit subsequence 2.2). The intermediate bit sequence 2.1 is related to both the bit subsequence 2.1 and the bit subsequence 2.2, and the intermediate bit sequence 2.2 is related to both the bit subsequence 2.1 and the bit subsequence 2.2. The first sequence processing device can also obtain a target bit sequence 2.1 based on the intermediate bit sequence 2.1 and obtain a target bit sequence 2.2 based on the intermediate bit sequence 2.2.

[0695] In the embodiments of the present application, taking the number of initial bit sequences as 2 as an example, it can be understood that the number of initial bit sequences can also be greater than 2.

[0696] Optionally, in the embodiments of the present application, the number of bits in the bit sequence to be processed is 72, 106, or 116, and the number of bits in the bit sequence obtained by combining the target bit sequences (that is, the bit sequence obtained after combination) is 128.

[0697] It can be understood that the number of bits in the bit sequence to be processed may not be 72, 106, or 116 either, and the number of bits in the bit sequence obtained after merging may not be 64 or 128 either. The embodiments of the present application do not limit this.

[0698] The distribution matching process for the intermediate bit sequence in S102 above can be implemented by means of a lookup table.

[0699] When performing distribution matching using a lookup table, the table can be searched according to the intermediate bit sequence to obtain the target bit sequence corresponding to the intermediate bit sequence. The lookup table includes the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences. The tables searched by the first sequence processing device in the process of obtaining the corresponding target bit sequences according to different intermediate bit sequences can be the same or different.

[0700] Optionally, when 0 bits are mapped to higher amplitude bits and 1 bits are mapped to lower amplitude bits, the value of the index bit sequence is positively correlated with the number of 0 bits in the result bit sequence. When 1 bits are mapped to higher amplitude bits and 0 bits are mapped to lower amplitude bits, the value of the index bit sequence is positively correlated with the number of 1 bits in the result bit sequence.

[0701] The multiple index bit sequences can be arranged in ascending or descending order of values in sequence. Of course, the multiple index bit sequences may not be arranged in this order. The present application does not limit this.

[0702] Exemplarily, taking the case where 0 bits are mapped to higher amplitude bits and 1 bits are mapped to lower amplitude bits as an example, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences can be as shown in Table 29 below. Among them, the index bit sequence includes a total of Y bits, Y>1, and the 1st bit to the Yth bit of the index bit sequence are represented as [1:Y]. The Yth bit is the highest bit. The result bit sequence includes N bits, N>1, the 1st bit in the result bit sequence is represented as N[1], the 2nd bit in the result bit sequence is represented as N[2], and so on. When Y = 10, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences can be as shown in Table 27 above; when Y = 11, the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences can be as shown in Table 28 above.

[0703] Table 29

[0704]

[0705] Assume there are X index bit sequences. The number of 0 bits in the result bit sequence corresponding to the 1st index bit sequence is 0, the th index bit sequence to the The number of 0 bits in the result bit sequence corresponding to an index bit sequence is s, and the number of 1 bits is N - s, where s is a positive integer and 1 ≤ s ≤ N. denotes the combination operation, which represents the number of all combinations of taking c (c ≤ N) elements from N different elements, and is called the combination number of taking c elements from N different elements. “!” denotes factorial. For example,

[0706] Exemplarily, as shown in Table 29, the number of 0 bits in the result bit sequence corresponding to the 1st index bit sequence is 0; the number of 0 bits in the result bit sequences corresponding to the 2nd index bit sequence to the 1 + Nth index bit sequence is 1; the number of 0 bits in the result bit sequences corresponding to the 2 + Nth index bit sequence to the 1 + N + N(N - 1) / 2th index bit sequence is 2; and so on.

[0707] It should be noted that the number of 0 bits in the result bit sequences corresponding to the index bit sequence to the

[0708] index bit sequence is all s, and the number of 1 bits is all N - s. Therefore, there is no fixed order among these index bit sequences, and the order of these index bit sequences can be arbitrarily interchanged.

[0709] Optionally, the index bit sequence may be sorted according to the probability that each bit in the result bit sequence is a 0 bit, so that the probability that each bit in the multiple result bit sequences is a 0 bit is the same. The proportion of 0 bits in the multiple values of bits in different orders in the multiple result bit sequences is the same. In other words, the index bit sequence may be sorted according to the principle of making the probability that each bit in all possible result bit sequences used is a 0 bit as close as possible. Which result bit sequences in the lookup table can be used is determined by the value range of the index bit sequence.

[0710] Taking Table 27 above as an example, Table 27 has 1024 rows, each row has a 10-bit index bit sequence and a 10-bit result bit sequence, and the index bit sequences and result bit sequences of any two rows are different. When the first bit of the index bit sequence is the least significant bit and the tenth bit is the most significant bit, the 1024 rows are sorted in ascending order according to the value of the index bit sequence. Bit 0 in the result bit sequence in Table 27 is used to map to the lowest amplitude, and bit 1 is used to map to the highest amplitude. In order to make the target bit sequence generated by lookup table 27 have the best PCS performance, the result bit sequences with fewer 0 bits in all possible result bit sequences will be preferentially placed in the rows with smaller row numbers. Exemplarily, Table 27 can be divided into 11 regions according to the number of 0 bits in the result bit sequence, that is, the first row, the second to the eleventh row, the twelfth to the fifty-sixth row, the fifty-seventh to the one hundred and seventy-sixth row, the one hundred and seventy-seventh to the three hundred and eighty-sixth row, the three hundred and eighty-seventh row to the six hundred and thirty-eighth row, the six hundred and thirty-ninth to the eight hundred and forty-eighth row, the eight hundred and forty-ninth to the nine hundred and sixty-eighth row, the nine hundred and sixty-ninth to the one thousand and thirteenth row, the one thousand and fourteenth to the one thousand and twenty-third row, the one thousand and twenty-fourth row, corresponding to 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 bits 0 and 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 bits 1 in the result bit sequence. For the regions corresponding to multiple rows, there is no sorting requirement for the output sequences within the region, that is, swapping the result bit sequences within the region does not affect the PCS performance. In Table 27, let the first bit of the result bit sequence be the least significant bit and the tenth bit be the most significant bit, and the values of the result bit sequences are sorted in ascending order within the region.

[0711] Taking Table 28 above as an example, Table 28 has 2048 rows, each row having an 11-bit index bit sequence and an 11-bit result bit sequence, and the index bit sequences and result bit sequences of any two rows are different. When the first bit of the index bit sequence is the least significant bit and the tenth bit is the most significant bit, the 2048 rows are sorted in ascending order according to the values of the index bit sequences. In Table 28, bit 0 in the result bit sequence is used to map to the lowest amplitude, and bit 1 is used to map to the highest amplitude. In order to make the target bit sequence generated by looking up Table 28 have the best PCS performance, sequences with fewer 0 bits among all possible result bit sequences will be preferentially placed in rows with smaller row numbers. Specifically, Table 28 can be divided into 12 regions according to the number of 0 bits in the output sequence, namely the 1st row, the 2nd to 12th rows, the 13th to 67th rows, the 68th to 232nd rows, the 233rd to 562nd rows, the 563rd to 1024th rows, the 1025th to 1486th rows, the 1487th to 1816th rows, the 1817th to 1981st rows, the 1982nd to 2036th rows, the 2037th to 2047th rows, and the 2048th row, corresponding to 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 bits of 0 and 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 bits of 1 in the result bit sequence respectively. For regions corresponding to multiple rows, there is no sorting requirement for the output sequences within the region, that is, swapping the result bit sequences within the region does not affect the PCS performance. Particularly, in Table 28, the first bit of the result bit sequence is set as the least significant bit and the 11th bit is set as the most significant bit, and the values of the result bit sequences are sorted in ascending order within the region.

[0712] The number X of index bit sequences among the above-mentioned multiple index bit sequences satisfies X ≤ 2 N , and X ≤ 2 Y .

[0713] Optionally, the number of bits in each of the multiple intermediate bit sequences is u, and the u-th bit of the intermediate bit sequence is the most significant bit; the multiple intermediate bit sequences include different intermediate bit sequences that are different in the t-th bit. 1 < t = u; or, 1 < t < u, and any bit from the (t + 1)-th bit to the u-th bit of the multiple intermediate bit sequences is the same. In this case, the first sequence processing device can perform distribution matching processing on any one of the multiple intermediate bit sequences in multiple ways.

[0714] Exemplarily, when the first sequence processing device performs distribution matching processing on any one of the multiple intermediate bit sequences in the first manner, it can, according to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences, use the first result bit sequence corresponding to the first index bit sequence among the multiple index bit sequences as the target bit sequence corresponding to this intermediate bit sequence; the first index bit sequence includes: the valid bit segment composed of the 1st bit to the (t - 1)th bit in the intermediate bit sequence.

[0715] Also exemplarily, when the first sequence processing device performs distribution matching processing on any one of the multiple intermediate bit sequences in the second manner, when the tth bit in the intermediate bit sequence is the target class bit, the first sequence processing device, according to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences, uses the first result bit sequence corresponding to the first index bit sequence among the multiple index bit sequences as the target bit sequence corresponding to the intermediate bit sequence; the first index bit sequence includes: the valid bit segment composed of the 1st bit to the (t - 1)th bit in the intermediate bit sequence; the target class bit is 0 bit or 1 bit; when the tth bit is not the target class bit, the first sequence processing device performs an inversion process on the valid bit segment (the inversion process is used to update 0 bit to 1 bit and 1 bit to 0 bit); then, the first sequence processing device, according to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences, obtains the second result bit sequence corresponding to the second index bit sequence among the multiple index bit sequences (the second index bit sequence includes: the valid bit segment after the inversion process), and performs an inversion process on the second result bit sequence to obtain the target bit sequence corresponding to the intermediate bit sequence.

[0716] In the distribution matching processing of the second manner, in the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences, fewer index bit sequences can be used. Therefore, the index bit sequences that will not be used in this correspondence and their corresponding result bit sequences can be deleted from this correspondence. In this way, in this correspondence, there can be fewer multiple index bit sequences and also fewer multiple result bit sequences.

[0717] Exemplarily, the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences in the distribution matching processing of the second manner can be less than the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences in the distribution matching processing of the first manner. Moreover, the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences in the distribution matching processing of the second manner is greater than or equal to half of the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences in the distribution matching processing of the first manner.

[0718] For example, in the process of obtaining the target bit sequence according to the intermediate bit sequence, the searched Table 27 can be replaced with the following Table 30, and the searched Table 28 can be replaced with the following Table 31. Moreover, when searching Tables 30 and 31, the second method described above can be used to perform distribution matching processing on any one of the multiple intermediate bit sequences. Table 30 includes the result bit sequences in the upper half of Table 27, and Table 30 can also be replaced with a table including the result bit sequences in the lower half of Table 27; Table 31 includes the result bit sequences in the upper half of Table 28, and Table 31 can also be replaced with a table including the result bit sequences in the lower half of Table 28.

[0719] Table 30

[0720]

[0721] Table 31

[0722]

[0723] Assume that the highest-order bit in the intermediate bits is the t-th bit arranged from low to high in terms of bit positions. Taking Table 30 as an example, as shown in Table 30, the table has 512 rows, each row has a 9-bit index bit sequence and a 10-bit result bit sequence, and the index bit sequences and result bit sequences of any two rows are different.

[0724] When searching Table 30, if the highest-order bit of the intermediate bit sequence is 0, directly search Table 30 according to the sequence composed of the bits except the highest-order bit in this intermediate bit sequence to obtain a result bit sequence, and use this result bit sequence as the target bit sequence corresponding to this intermediate bit sequence.

[0725] If the highest-order bit of the intermediate bit sequence is 1, perform an inversion process on the sequence composed of the bits except the highest-order bit in this intermediate bit sequence, search Table 30 according to the bit sequence obtained by the inversion process to obtain a result bit sequence, then perform an inversion process on this result bit sequence, and use the bit sequence obtained by this inversion process as the target bit sequence corresponding to this intermediate bit sequence.

[0726] The method of searching Table 31 is similar to the method of searching Table 30, and the embodiments of the present application will not elaborate here.

[0727] The number X of index bit sequences ≥ 2 (u-t-1) 。

[0728] It can be understood that the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the distribution matching processing of the second method can also be the same as the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences under the distribution matching processing of the first method.

[0729] Generally speaking, the value of the number X of index bit sequences is divided into the following three cases in total.

[0730] The first case is X > 2 (u-t) , and there are index bit sequences that cannot be found at this time. When the number Y of bits in the index bit sequence exceeds u - t (there are an additional Y - u - t fixed bits), during table lookup, the effective bit segment composed of the 1st to (t - 1)th bits in the middle bit sequence and the additional Y - u - t fixed bits can be combined to obtain a new bit sequence, and then this bit sequence is compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. Among them, the above-mentioned additional Y - u - t fixed bits can be the same as or different from the u - t fixed bits in the middle bit sequence. When Y = u, during table lookup, the middle bit sequence can be directly compared with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. It can be seen that in the first case, the distribution matching process of the above first method can be used to search for the target bit sequence.

[0731] The second case is X = 2 (u-t) , and there are no index bit sequences that cannot be found at this time. At this time, Y can be equal to u - t. During table lookup, directly compare the effective bit segment composed of the 1st to (t - 1)th bits in the middle bit sequence with multiple index bit sequences to find the corresponding index bit sequence and its corresponding result bit sequence. It can be seen that in the second case, the distribution matching process of the above first method can be used to search for the target bit sequence.

[0732] The third case is 2 (u-t-1) ≤ X < 2 (u-t) , and at this time, the number of index bit sequences is small, and all rows in the table match at least half of all possible middle bit sequences. At this time, the number Y of bits in the index bit sequence can be u - t - 1. In the third case, the distribution matching process of the above second method can be used to search for the target bit sequence.

[0733] Since the operations performed by the second sequence processing device are inverse to those performed by the first sequence processing device, therefore, the second sequence processing device can also perform the inverse processing of the distribution matching process on any one of the multiple target bit sequences in multiple ways.

[0734] Exemplarily, if the number of bits in the intermediate bit sequence is equal to the number of bits in the index bit sequence, the inverse process of the distribution matching process for the target bit sequence can be performed in the first manner; if the number of bits in the intermediate bit sequence is less than the number of bits in the result bit sequence, the inverse process of the distribution matching process for the target bit sequence can be performed in the second manner.

[0735] When performing the inverse process of the distribution matching process for the target bit sequence in the first manner, the first index bit sequence corresponding to the first result bit sequence among the multiple result bit sequences can be used as the intermediate bit sequence corresponding to the target bit sequence according to the one-to-one correspondence between the multiple index bit sequences and the multiple result bit sequences; the first result bit sequence includes: the target bit sequence.

[0736] When performing the inverse process of the distribution matching process for the target bit sequence in the second manner, after inverting the above first index bit sequence, target class bits (or sequentially target class bits and at least one fixed bit) can be added after the highest bit to obtain the intermediate bit sequence corresponding to the target bit sequence.

[0737] The value of the second type of bit segment in the multiple intermediate bit sequences depends on the value of the first type of bit segment in the multiple bit subsequences, and each intermediate bit sequence is related to each bit subsequence. When the value of the first type of bit segment in any one of the multiple bit subsequences changes, the value of the second type of bit segment in the multiple intermediate bit sequences changes. The first sequence processing device will comprehensively consider in combination with the value of the first type of bit segment in the multiple bit subsequences to determine the value of the second type of bit segment in the multiple intermediate bit sequences, so that the value of the obtained intermediate bit sequence is more conducive to improving the signal transmission effect.

[0738] Exemplarily, the bit subsequence includes a first type of bit segment, and the intermediate bit sequence includes a second type of bit segment. The multiple bit subsequences include: a first bit subsequence and a second bit subsequence. Each bit subsequence in the multiple bit subsequences includes a first type of bit segment (also referred to as a decision bit segment), and the number of bits in the first type of bit segment is greater than or equal to 1. The first type of bit segment in the bit subsequence may include the highest bit in the bit subsequence, or may not include the highest bit. This application does not make a limitation in this regard. For example, assume that the first bit subsequence includes a first type of bit segment D1, and the second bit subsequence includes a first type of bit segment D2; the first type of bit segment D1 is the higher-order bit segment in the first bit subsequence, and this first type of bit segment D1 includes the highest bit in the first bit subsequence; the first type of bit segment D2 is the higher-order bit segment in the second bit subsequence, and this first type of bit segment D2 includes the highest bit in the second bit subsequence. The first type of bit segment in the bit subsequence may be consecutive bits or non-consecutive bits in the intermediate bit sequence.

[0739] The second type of bit segment includes the highest bit in the intermediate bit sequence; the second type of bit segment in the intermediate bit sequence may be consecutive bits in the intermediate bit sequence that include the highest bit. The multiple intermediate bit sequences include: a first intermediate bit sequence and a second intermediate bit sequence. Each intermediate bit sequence in the multiple intermediate bit sequences includes a second type of bit segment (also referred to as an extended bit segment), and the second type of bit segment in the intermediate bit sequence includes the highest bit in the intermediate bit sequence. The second type of bit segment in the intermediate bit sequence may be consecutive bits in the intermediate bit sequence that include the highest bit. For example, the first intermediate bit sequence includes a second type of bit segment E1, and the second intermediate bit sequence includes a second type of bit segment E2; the second type of bit segment E1 is the higher-order bit segment in the first intermediate bit sequence, and this second type of bit segment E1 includes the highest bit in the first intermediate bit sequence; the second type of bit segment E2 is the higher-order bit segment in the second intermediate bit sequence, and this second type of bit segment E2 includes the highest bit in the second intermediate bit sequence.

[0740] The value of the first type of bit segment in the first bit subsequence is a first numerical value, and the value of the first type of bit segment in the second bit subsequence is a second numerical value; the value of the second type of bit segment in the first intermediate bit sequence is a third numerical value, and the value of the second type of bit segment in the second intermediate bit sequence is a fourth numerical value. The absolute value of the difference between the first numerical value and the second numerical value is less than the absolute value of the difference between the third numerical value and the fourth numerical value; the third numerical value is greater than the first numerical value and the second numerical value, and the fourth numerical value is less than the first numerical value and the second numerical value.

[0741] Of course, the first value, the second value, the third value, and the fourth value may not satisfy this relationship either, and the embodiments of the present application do not limit this. For example, the absolute value of the difference between the first value and the second value may be equal to the absolute value of the difference between the third value and the fourth value. The third value may be less than or equal to the first value or the second value, and the fourth value may be greater than or equal to the first value or the second value.

[0742] Assume that the 0 bits in the result bit sequence are used to map to higher amplitude bits (amplitude bits of the symbol). If the number of 0 bits in the result bit sequence is larger, then the more symbols with higher amplitude bits are modulated according to the result bit sequence, and the worse the transmission effect of the signal is. Therefore, in the related art, before looking up the sequence in the table, 0 bits are also added after the bit sequence to lock the bit sequence in the index bit sequence with fewer 0 bits in the corresponding result bit sequences of multiple index bit sequences. Furthermore, since the number of 0 bits in the result bit sequence found in the table according to the bit sequence after adding 0 bits is smaller, it is beneficial to improve the transmission effect of the signal. However, usually the sending node performs PCS processing on multiple bit sequences in parallel, and then merges and outputs the multiple bit sequences obtained after PCS processing. When the sending node performs PCS processing on multiple bit sequences in parallel, in some cases, the total number of 0 bits in the merged bit sequence is still large.

[0743] Assume that the value of the sequence obtained by adding 0 bits after the highest bit of the first bit subsequence (a bit position higher than the highest bit) is the fifth value, and the value of the sequence obtained by adding 0 bits after the highest bit of the second bit subsequence is the sixth value. Then, when the absolute value of the difference between the first value and the second value is less than the absolute value of the difference between the third value and the fourth value; the third value is greater than the first value and the second value, and the fourth value is less than the first value and the second value, the absolute value of the difference between the fifth value and the sixth value is less than the absolute value of the difference between the third value and the fourth value; the third value is greater than the fifth value and the sixth value, and the fourth value is less than the fifth value and the sixth value.

[0744] Take the example where 0 bits are mapped to higher magnitude bits and 1 bits are mapped to lower magnitude bits. Assume that the above distribution matching process is implemented using a lookup table, and the table looked up in the lookup table includes the one-to-one correspondence between multiple index bit sequences and multiple result bit sequences. Moreover, the number of 0 bits in the result bit sequences corresponding to the multiple index bit sequences is positively correlated with the value of the index bit sequences. Then, the number of 0 bits in the result bit sequence obtained by looking up the table according to the sequence obtained by directly appending 0 bits after the highest bit of the first bit subsequence is the first number, and the number of 0 bits in the result bit sequence obtained by looking up the table according to the sequence obtained by directly appending 0 bits after the highest bit of the second bit subsequence is the second number; the number of 0 bits in the result bit sequence (target bit sequence) obtained by looking up the table according to the first intermediate bit sequence is the third number, and the number of 0 bits in the result bit sequence (target bit sequence) obtained by looking up the table according to the fourth intermediate bit sequence is the fourth number; the sum of the third number and the fourth number is less than the sum of the first number and the second number. In this way, after merging these two target bit sequences, a bit sequence with fewer 0 bits can be obtained, which is beneficial to improving the transmission effect of the signal.

[0745] In the embodiments of the present application, take the example where the absolute value of the difference between the first value and the second value is less than the absolute value of the difference between the third value and the fourth value; the third value is greater than the first value and the second value, and the fourth value is less than the first value and the second value. Of course, the first value, the second value, the third value, and the fourth value may not satisfy this relationship, and the embodiments of the present application do not limit this. The absolute value of the difference between the first value and the second value may also be equal to the absolute value of the difference between the third value and the fourth value. The third value may also be less than or equal to the first value or the second value, and the fourth value may also be greater than or equal to the first value or the second value. For example, the first value is equal to the third value, and the second value is equal to the third value.

[0746] In the embodiments of the present application, take the example where the absolute value of the difference between the first value and the second value is less than the absolute value of the difference between the third value and the fourth value, and the third value is greater than the first value and the second value, and the fourth value is less than the first value and the second value. It can be understood that the absolute value of the difference between the first value and the second value may also be equal to the absolute value of the difference between the third value and the fourth value; the third value may also be less than or equal to the first value and the second value; the fourth value may also be greater than or equal to the first value and the second value. In other words, at least one of the three conditions that the absolute value of the difference between the first value and the second value is less than the absolute value of the difference between the third value and the fourth value, the third value is greater than the first value and the second value, and the fourth value is less than the first value and the second value is satisfied, or none of these three conditions is satisfied.

[0747] Further, the bit subsequence further includes a third type of bit segment (also referred to as a bit segment to be reallocated) other than the first type of bit segment; the intermediate bit sequence further includes a fourth type of bit segment (also referred to as a bit segment that has been reallocated) other than the second type of bit segment. The fourth type of bit segment in multiple intermediate bit sequences includes: the bits in the third type of bit segment in multiple bit subsequences.

[0748] Exemplarily, the first bit subsequence includes, in addition to the first type of bit segment D1, a third type of bit segment f1; the second bit subsequence includes, in addition to the first type of bit segment D2, a third type of bit segment f2; the first intermediate bit sequence includes, in addition to the second type of bit segment E1, a fourth type of bit segment F1; the second intermediate bit sequence includes, in addition to the second type of bit segment E2, a fourth type of bit segment F2. Moreover, the whole formed by the fourth type of bit segment F1 and the fourth type of bit segment F2 includes the bits in the whole formed by the third type of bit segment f1 and the third type of bit segment f2.

[0749] Optionally, when multiple intermediate bit sequences correspond one-to-one with multiple bit subsequences, the fourth type of bit segment in each intermediate bit sequence among the multiple intermediate bit sequences includes: the bits in the third type of bit segment in the bit subsequence corresponding to this intermediate bit sequence. Further, the fourth type of bit segment in this intermediate bit sequence includes: the third type of bit segment in the bit subsequence corresponding to this intermediate bit sequence.

[0750] The multiple fourth type of bit segments in multiple intermediate bit sequences may or may not include the third type of bit segment. In other words, one third type of bit segment may be the whole or part of the fourth type of bit segment in an intermediate bit sequence as a whole, or after the bits in this one third type of bit segment are scattered, they are respectively the whole or part of the fourth type of bit segments in multiple intermediate bit sequences.

[0751] Further, the number of bits in the above-mentioned bit sequence to be processed, the bit sequence obtained after merging, the bit subsequence, and the intermediate bit sequence can all have various situations.

[0752] For example, the number of bits in the bit sequence to be processed is 116, the number of bits in the bit sequence obtained after merging is 128, the bit sequence to be processed is divided into 12 bit subsequences, and the number of bits in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10 respectively; the number of bits in the intermediate bit sequences are: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 10 bits are obtained from two bit subsequences with 9 bits; two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 10 bits;

[0753] Alternatively, the number of bits in the bit sequence to be processed is 106, the number of bits in the obtained bit sequence after merging is 128, the bit sequence to be processed is divided into 12 bit subsequences, and the number of bits in the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, 9, and 9 respectively; the number of bits in the intermediate bit sequences are: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; two intermediate bit sequences with 10 bits are obtained from two bit subsequences with 8 bits; in some of the bit subsequences with 9 bits, two intermediate bit sequences with 10 bits are obtained from two bit subsequences with 9 bits; in the other bit subsequences with 9 bits, two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 9 bits;

[0754] Alternatively, the number of bits in the bit sequence to be processed is 72, the number of bits in the obtained bit sequence after merging is 128, the bit sequence to be processed is divided into 12 bit subsequences, and the number of bits in the 12 bit subsequences are all 6; the number of bits in the 12 intermediate bit sequences are: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in some of the bit subsequences with 6 bits, two intermediate bit sequences with 10 bits are obtained from two bit subsequences with 6 bits; in the other bit subsequences with 6 bits, two intermediate bit sequences with 11 bits are obtained from two bit subsequences with 6 bits;

[0755] The number of bits in the bit sequence to be processed is 116, and the number of bits in the obtained bit sequence after merging is 128; the bit sequence to be processed is divided into 12 bit subsequences; the number of bits in the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10 respectively; the number of bits in the intermediate bit sequences are: 10, 10, 10, 10, 11, 11, 11, 11; four intermediate bit sequences with 10 bits are obtained from 4 bit subsequences with 9 bits, and four intermediate bit sequences with 11 bits are obtained from 4 bit subsequences with 10 bits;

[0756] Alternatively, the number of bits in the bit sequence to be processed is 106, and the number of bits in the resulting bit sequence after merging is 128. The bit sequence to be processed is divided into 12 bit subsequences, and the number of bits in the 12 bit subsequences are 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, and 9 respectively; the number of bits in the intermediate bit sequences are: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; according to two bit subsequences with 8 bits each and two bit sequences with 9 bits each, 4 intermediate bit sequences with 10 bits each are obtained; according to 4 bit subsequences with 9 bits each, 4 intermediate bit sequences with 11 bits each are obtained.

[0757] Alternatively, the number of bits in the bit sequence to be processed is 72, and the number of bits in the resulting bit sequence after merging is 128. The bit sequence to be processed is divided into 12 bit subsequences, and the number of bits in each of the 12 bit subsequences is 6; the number of bits in the 12 intermediate bit sequences are: 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11; in a part of the bit subsequences with 6 bits each, 4 intermediate bit sequences with 10 bits each are obtained according to 4 bit subsequences with 6 bits each; in another part of the bit subsequences with 6 bits each, 4 intermediate bit sequences with 11 bits each are obtained according to 4 bit subsequences with 6 bits each.

[0758] The embodiments of the present application do not limit the order of each bit subsequence. Correspondingly, the order of the intermediate bit sequences obtained according to the bit subsequences is not limited either. In addition, the elements in the bit subsequence can be continuous or discontinuous in the bit sequence to be processed, and multiple bit subsequences can be continuous or discontinuous in the bit sequence to be processed.

[0759] The sequence processing method provided by the embodiments of the present application will be further described through the following examples. In the following examples, the bits in each bit sequence are arranged from left to right in ascending order of bit position, and, in the bit sequence, the xth bit is lower than the (x + 1)th bit, where x ≥ 1.

[0760] Example 1: As Figure 6 shown, the number of bits in the bit sequence to be processed is 116, and the number of bits in the resulting bit sequence after merging is 128.

[0761] The bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequence are consecutive in the bit sequence to be processed, and the r-th bit subsequence and the (r + 1)-th bit subsequence among the 12 bit subsequences are consecutive in the bit sequence to be processed, where r ≥ 1. The number of bits in the 1st to 12th bit subsequences among the 12 bit subsequences are 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, and 10 in sequence.

[0762] Among the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed form an initial bit sequence. The 12 bit subsequences altogether form 6 initial bit sequences. Moreover, among the 6 initial bit sequences, the s-th initial bit sequence and the (s + 1)-th initial bit sequence are consecutive in the bit sequence to be processed, where s ≥ 1.

[0763] As Figure 6 shown, the bit subsequence represents the p-th bit subsequence in the m-th initial bit sequence (also referred to as the initial bit sequence m), where m ≥ 1 and p ≥ 1. For example, represents the 1st bit subsequence in the 1st initial bit sequence, represents the 2nd bit subsequence in the 1st initial bit sequence. represents the 1st bit subsequence in the 2nd initial bit sequence, represents the 2nd bit subsequence in the 2nd initial bit sequence. And so on, which will not be elaborated in the embodiments of the present application here.

[0764] k[B:C] represents that: the bit subsequence includes A bits, and these A bits are the B-th bit to the C-th bit in the bit sequence to be processed. A > 1, 1 ≤ B < C. For example, k[1:9] represents that: the bit subsequence includes 9 bits, and these 9 bits are the 1st bit to the 9th bit in the bit sequence to be processed. k[10:18] represents that: the bit subsequence includes 9 bits, and these 9 bits are the 10th bit to the 18th bit in the bit sequence to be processed. And so on, which will not be elaborated in the embodiments of the present application here.

[0765] The first sequence processing device needs to perform bit processing 1 on the initial bit sequence 1, bit processing 2 on the initial bit sequence 2, bit processing 3 on the initial bit sequence 3, bit processing 4 on the initial bit sequence 4, bit processing 5 on the initial bit sequence 5, and bit processing 6 on the initial bit sequence 6. The first sequence processing device respectively obtains the intermediate bit sequences according to the first initial bit sequence to the sixth initial bit sequence among the 6 initial bit sequences, and the number of bits in the obtained intermediate bit sequences are successively: 10, 10, 11, 11, 11, 11. The first sequence processing device can obtain two intermediate bit sequences according to each of the 6 initial bit sequences. The number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the first initial bit sequence is 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the second initial bit sequence is 10, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the third initial bit sequence is 11, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the fourth initial bit sequence is 11, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the fifth initial bit sequence is 11, and the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the sixth initial bit sequence is 11.

[0766] As Figure 6 shown, the first sequence processing device performs bit processing on the m-th initial bit sequence, and the q-th intermediate bit sequence obtained is expressed as where q ≥ 1. It is expressed as: including D bits, where D > 1. For example, the first sequence processing device performs bit processing on the first initial bit sequence, and the first intermediate bit sequence obtained is expressed as It is expressed as: including 10 bits. The first sequence processing device performs bit processing on the first initial bit sequence, and the second intermediate bit sequence obtained is expressed as It is expressed as: including 10 bits. And so on, which will not be elaborated in the embodiments of the present application.

[0767] The first sequence processing device can query the expansion table according to the first type of bit segment in multiple subsequences of the initial bit sequence to obtain the second type of bit segment in multiple intermediate bit sequences. The first sequence processing device can also obtain the fourth type of bit segment in multiple intermediate bit sequences according to the third type of bit segment in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained.

[0768] In the process that the first sequence processing device obtains the intermediate bit sequence according to different initial bit sequences, the extended tables queried can be the same or different.

[0769] Exemplarily, in each of the above bit subsequences and , the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (denoted as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (denoted as [1:7]). In each of the above intermediate bit sequences W1 1 , W2 1 , W1 2 and W2 2 , the second type of bit segment includes the 8th bit to the 10th bit from left to right in the intermediate bit sequence (denoted as [8:10]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (denoted as [1:7]). The first sequence processing device queries the extended tables shown in Table 4 and Table 5 according to the bit subsequences k1 1 , k2 1 , and can obtain the intermediate bit sequences W1 1 , W2 1 . The first sequence processing device queries the extended tables shown in Table 4 and Table 5 according to the bit subsequences k1 2 and k2 2 in, and can obtain the intermediate bit sequences W1 2 and W 2 .

[0770] In each of the above bit subsequences , the first type of bit segment includes the 9th bit to the 10th bit of the highest bit from left to right in the bit subsequence (denoted as [9:10]), and the third type of bit segment includes the 1st bit to the 8th bit from left to right in the bit subsequence (denoted as [1:8]). In each of the above intermediate bit sequences , the second type of bit segment includes the 9th bit to the 11th bit from left to right in the intermediate bit sequence (denoted as [9:11]), and the fourth type of bit segment includes the 1st bit to the 8th bit from left to right in the intermediate bit sequence (denoted as [1:8]). The first sequence processing device queries the extended table shown in Table 3 according to the bit subsequence , and can obtain the intermediate bit sequence The first sequence processing device queries the extended table shown in Table 3 according to the bit subsequence in, and can obtain the intermediate bit sequence The first sequence processing device, based on the bit subsequence queries the extended table shown in Table 3, and can obtain the intermediate bit sequence The first sequence processing device, based on the bit subsequence queries the extended table shown in Table 3, and can obtain the intermediate bit sequence

[0771] The first sequence processing device performs bit processing m on the m-th initial bit sequence to obtain the intermediate bit sequence Here, take the extended tables used for bit processing 1 to 2 to indicate the one-to-one correspondence shown in Tables 4 and 5, and the extended tables used for bit processing 3 to 6 to indicate the one-to-one correspondence shown in Table 3 as an example.

[0772] The first sequence processing device performs bit processing on the m-th initial bit sequence, and the obtained intermediate bit sequence The distribution matching process performed is called distribution matching process m-q. For example, the first sequence processing device performs bit processing on the 1st initial bit sequence, and the obtained intermediate bit sequence performs the distribution matching process 1-1.

[0773] N[V:Z] represents the target bit sequence corresponding to the intermediate bit sequence which includes G bits, G>1, and the target bit sequence includes the V-th bit to the Z-th bit in the merged bit sequence, 1≤V<Z. For example, N[1:10] represents the target bit sequence corresponding to the intermediate bit sequence which includes 10 bits, and the target bit sequence includes the 1st bit to the 10th bit in the merged bit sequence. N[11:20] represents the target bit sequence corresponding to the intermediate bit sequence which includes 10 bits, and the target bit sequence includes the 11th bit to the 20th bit in the merged bit sequence.

[0774] When the first sequence processing device performs distribution matching processing on each intermediate bit sequence in the intermediate bit sequence and to obtain the corresponding target bit sequence, it can obtain the corresponding target bit sequence by looking up the table shown in Table 27. When the first sequence processing device performs distribution matching processing on the intermediate bit sequence When performing distribution matching processing on each intermediate bit sequence in [[]] to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0775] After processing the bit sequence to be processed using the solution of this example, the probability that the combined bit sequence obtained is mapped to a high amplitude bit is reduced to approximately 36.52%.

[0776] Example 2, such as Figure 7 As shown, the number of bits in the bit sequence to be processed is 106, and the number of bits in the combined bit sequence is 128.

[0777] Figure 7 The meanings of the symbols in [[]] can be referred to Figure 6 the meanings of the symbols in [[]], which are not elaborated herein in this application.

[0778] The bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequence are consecutive in the bit sequence to be processed, and the r-th bit subsequence and the (r + 1)-th bit subsequence among the 12 bit subsequences are consecutive in the bit sequence to be processed, where r ≥ 1; the number of bits in the 1st to 12th bit subsequences among the 12 bit subsequences are 9, 9, 8, 8, 9, 9, 9, 9, 9, 9, 9, and 9 in sequence.

[0779] Among the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed form an initial bit sequence. A total of 6 initial bit sequences are formed by the 12 bit subsequences. Moreover, among the 6 initial bit sequences, the s-th initial bit sequence and the (s + 1)-th initial bit sequence are consecutive in the bit sequence to be processed, where s ≥ 1.

[0780] The first sequence processing device needs to perform bit processing 1 on the initial bit sequence 1, bit processing 2 on the initial bit sequence 2, bit processing 3 on the initial bit sequence 3, bit processing 4 on the initial bit sequence 4, bit processing 55 on the initial bit sequence 5, and bit processing 6 on the initial bit sequence 6. The first sequence processing device respectively obtains the number of bits in the intermediate bit sequences according to the first initial bit sequence to the sixth initial bit sequence among the 6 initial bit sequences, which are: 10, 10, 11, 11, 11, 11. The first sequence processing device can obtain two intermediate bit sequences according to each of the 6 initial bit sequences. The number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the first initial bit sequence is 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the second initial bit sequence is 10, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the third initial bit sequence is 11, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the fourth initial bit sequence is 11, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the fifth initial bit sequence is 11, and the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the sixth initial bit sequence is 11.

[0781] The first sequence processing device can query the expansion table according to the first type of bit segment in multiple subsequences in the initial bit sequence to obtain the second type of bit segment in multiple intermediate bit sequences. The first sequence processing device can also obtain the fourth type of bit segment in multiple intermediate bit sequences according to the third type of bit segment in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained.

[0782] In the process of the first sequence processing device obtaining intermediate bit sequences according to different initial bit sequences, the expansion tables queried can be the same or different. Moreover, in each bit subsequence, the first type of bit segment includes the two highest bits in the bit subsequence, and the third type of bit segment includes the bits in the bit subsequence except these two bits. In each intermediate bit sequence, the second type of bit segment includes the three highest bits in the intermediate bit sequence, and the fourth type of bit segment includes the bits in the intermediate bit sequence except these three bits.

[0783] Exemplarily, in each of the above bit subsequences the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (denoted as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (denoted as [1:7]).

[0784] The above bit subsequence and In each bit subsequence, the first type of bit segment includes the 7th bit to the 8th bit from left to right in the bit subsequence (denoted as [7:8]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (denoted as [1:6]).

[0785] The above intermediate bit sequence and In each intermediate bit sequence, the second type of bit segment includes the 7th bit to the 10th bit from left to right in the intermediate bit sequence (denoted as [7:10]), and the fourth type of bit segment includes the 1st bit to the 6th bit from left to right in the intermediate bit sequence (denoted as [1:6]).

[0786] The above intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 8th bit to the 11th bit from left to right in the intermediate bit sequence (denoted as [8:11]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (denoted as [1:7]).

[0787] The first sequence processing device performs bit processing m on the m-th initial bit sequence to obtain an intermediate bit sequence Here, the expansion tables used for bit processing 1 are all used to indicate the one-to-one correspondence shown in Tables 4 and 5, the expansion tables used for bit processing 2 are all used to indicate the one-to-one correspondence shown in Tables 6 and 7, and the expansion tables used for bit processing 3 to 6 are all used to indicate the one-to-one correspondence shown in Tables 8 and 9 as an example.

[0788] When the first sequence processing device performs distribution matching processing on each intermediate bit sequence in the intermediate bit sequence and to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 27. When the first sequence processing device performs distribution matching processing on each intermediate bit sequence in the intermediate bit sequence to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0789] After processing the bit sequence to be processed using the solution of this example, the probability that the combined bit sequence is mapped to a high amplitude bit is reduced to about 30.69%.

[0790] Example 3. As Figure 8 shown, the number of bits in the bit sequence to be processed is 72, and the number of bits in the combined bit sequence is 128.

[0791] Figure 8 The meanings of the symbols in Figure 6 The meanings of the symbols in will not be elaborated in this application.

[0792] Please refer to Figure 8 , the bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequence are consecutive in the bit sequence to be processed, and the r-th bit subsequence and the (r + 1)-th bit subsequence among the 12 bit subsequences are consecutive in the bit sequence to be processed, where r ≥ 1; among the 12 bit subsequences, every two consecutive bit subsequences in the bit sequence to be processed form an initial bit sequence. Among the 6 initial bit sequences formed by the 12 bit subsequences, the s-th initial bit sequence and the (s + 1)-th initial bit sequence are consecutive in the bit sequence to be processed, where s ≥ 1; the number of bits in each of the 12 bit subsequences from the 1st bit subsequence to the 12th bit subsequence is 6; the number of bits in the intermediate bit sequences obtained respectively according to the 1st initial bit sequence to the 6th initial bit sequence among the 6 initial bit sequences are successively: 10, 10, 11, 11, 11, 11. The first sequence processing device can obtain two intermediate bit sequences according to each of the 6 initial bit sequences. The number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the 1st initial bit sequence is 10; the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the 2nd initial bit sequence is 10, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the 3rd initial bit sequence is 11, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the 4th initial bit sequence is 11, the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the 5th initial bit sequence is 11, and the number of bits in the two intermediate bit sequences obtained by the first sequence processing device according to the 6th initial bit sequence is 11.

[0793] The first sequence processing module can query the expansion table according to the first type of bit segments in multiple subsequences of the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences according to the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained according to the initial bit sequence.

[0794] In the process of the first sequence processing device obtaining intermediate bit sequences according to different initial bit sequences, the expansion tables queried can be the same or different.

[0795] Exemplarily, the above-mentioned bit subsequence In each bit subsequence, the first type of bit segment includes the 5th bit to the 6th bit from left to right in the bit subsequence (denoted as [5:6]), and the third type of bit segment includes the 1st bit to the 4th bit from left to right in the bit subsequence (denoted as [1:4]).

[0796] The above intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 5th bit to the 10th bit from left to right in the intermediate bit sequence (denoted as [5:10]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (denoted as [1:4]).

[0797] The above intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 5th bit to the 11th bit from left to right in the intermediate bit sequence (denoted as [5:11]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (denoted as [1:4]).

[0798] The first sequence processing device performs bit processing m on the m-th initial bit sequence to obtain an intermediate bit sequence Here, take the expansion tables used in bit processing 1 and 2 as examples, both of which are used to indicate the one-to-one correspondence shown in Table 10 and Table 11, and the expansion tables used in bit processing 3 to 6 are used to indicate the one-to-one correspondence shown in Table 12 and Table 13.

[0799] When the first sequence processing module performs distribution matching processing on each intermediate bit sequence in the intermediate bit sequence to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 27. When the first sequence processing module performs distribution matching processing on each intermediate bit sequence in the intermediate bit sequence to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0800] After processing the bit sequence to be processed using the solution of this example, the probability that the combined bit sequence is mapped to a high amplitude bit is reduced to about 17.11%.

[0801] Example 4: As Figure 9 shown, the number of bits in the bit sequence to be processed is 116, and the number of bits in the combined bit sequence is 128.

[0802] Figure 9 The meanings of each symbol in Figure 6 can be referred to, and the present application will not elaborate here.

[0803] Please refer to Figure 9 , the bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequence are consecutive in the bit sequence to be processed, and the r-th bit subsequence and the (r + 1)-th bit subsequence among the 12 bit subsequences are consecutive in the bit sequence to be processed, where r ≥ 1; among the 12 bit subsequences, every 4 consecutive bit subsequences in the bit sequence to be processed form an initial bit sequence. Among the 3 initial bit sequences formed by the 12 bit subsequences, the s-th initial bit sequence and the (s + 1)-th initial bit sequence are consecutive in the bit sequence to be processed, where s ≥ 1; the number of bits in the 1st to 4th bit subsequences among the 12 bit subsequences is 9 each, and the number of bits in the 5th to 12th bit subsequences among the 12 bit subsequences is 10 each; the number of bits in the intermediate bit sequences obtained according to the 1st to 3rd initial bit sequences among the 3 initial bit sequences are 10, 11, and 11 respectively. The first sequence processing device can obtain four intermediate bit sequences according to each of the 3 initial bit sequences. The number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the 1st initial bit sequence is 10 each; the number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the 2nd initial bit sequence is 11 each, and the number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the 3rd initial bit sequence is 11 each.

[0804] The first sequence processing module can query the expansion table according to the first type of bit segments in multiple subsequences of the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences according to the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained according to the initial bit sequence.

[0805] In the process of the first sequence processing device obtaining intermediate bit sequences according to different initial bit sequences, the queried expansion tables can be the same or different. The first sequence processing device performs bit processing m on the m-th initial bit sequence to obtain an intermediate bit sequence Here, take the expansion table used for bit processing 1 to indicate the one-to-one correspondence shown in Tables 14 and 15, and the expansion tables used for bit processing 2 to 3 to indicate the one-to-one correspondence shown in Table 16 as an example.

[0806] Exemplarily, the above bit subsequence In each bit subsequence, the first type of bit segment includes the 8th bit to the 9th bit from left to right in this bit subsequence (denoted as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in this bit subsequence (denoted as [1:7]). The above-mentioned bit subsequence In each bit subsequence, the first type of bit segment includes the 9th bit to the 10th bit from left to right in this bit subsequence (denoted as [9:10]), and the third type of bit segment includes the 1st bit to the 8th bit from left to right in this bit subsequence (denoted as [1:8]).

[0807] The above-mentioned intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 8th bit to the 10th bit from left to right in this intermediate bit sequence (denoted as [8:10]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in this intermediate bit sequence (denoted as [1:7]).

[0808] The above-mentioned intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 9th bit to the 11th bit from left to right in this intermediate bit sequence (denoted as [9:11]), and the fourth type of bit segment includes the 1st bit to the 8th bit from left to right in this intermediate bit sequence (denoted as [1:8]).

[0809] When the first sequence processing module performs distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 27. When the first sequence processing module performs distribution matching processing on each intermediate bit sequence in to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0810] After processing the bit sequence to be processed using the solution of this example, the probability that the combined bit sequence is mapped to a high amplitude bit is reduced to about 35.57%.

[0811] Example 5. As Figure 10 shown, the number of bits in the bit sequence to be processed is 106, and the number of bits in the combined bit sequence is 128.

[0812] Figure 10 The meanings of the symbols in can be referred to Figure 6 the meanings of the symbols in, which are not elaborated in this application.

[0813] Please refer to Figure 10, the bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequences are consecutive in the bit sequence to be processed, and the r-th bit subsequence and the (r + 1)-th bit subsequence among the 12 bit subsequences are consecutive in the bit sequence to be processed, where r ≥ 1; among the 12 bit subsequences, every 4 consecutive bit subsequences in the bit sequence to be processed form an initial bit sequence. Among the 3 initial bit sequences formed by the 12 bit subsequences, the s-th initial bit sequence and the (s + 1)-th initial bit sequence are consecutive in the bit sequence to be processed, where s ≥ 1; the number of bits in the 1st bit subsequence to the 2nd bit subsequence among the 12 bit subsequences is 8, and the number of bits in the 3rd bit subsequence to the 12th bit subsequence among the 12 bit subsequences is 9; the number of bits in the intermediate bit sequences obtained respectively according to the 1st initial bit sequence to the 3rd initial bit sequence among the 3 initial bit sequences are: 10, 11, 11. The first sequence processing device can obtain four intermediate bit sequences according to each of the 3 initial bit sequences. The number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the 1st initial bit sequence is 10; the number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the 2nd initial bit sequence is 11, and the number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the 3rd initial bit sequence is 11.

[0814] The first sequence processing module can query an expansion table according to the first type of bit segments in multiple subsequences of the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences according to the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained according to the initial bit sequence.

[0815] In the process of the first sequence processing device obtaining intermediate bit sequences according to different initial bit sequences, the expansion tables queried can be the same or different. The first sequence processing device performs bit processing m on the m-th initial bit sequence to obtain an intermediate bit sequence Here, take the expansion table used for bit processing 1 to indicate the one-to-one correspondence shown in Table 17 and Table 18, and the expansion tables used for bit processing 2 to 3 to indicate the one-to-one correspondence shown in Table 19 and Table 20 as an example.

[0816] Exemplarily, in each of the above bit subsequences , the first type of bit segment includes the 8th bit from left to right in the bit subsequence (denoted as [8]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (denoted as [1:7]). The above bit subsequence In each bit subsequence, the first type of bit segment includes the 8th bit to the 9th bit from left to right in the bit subsequence (denoted as [8:9]), and the third type of bit segment includes the 1st bit to the 7th bit from left to right in the bit subsequence (denoted as [1:7]).

[0817] The above intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 8th bit to the 10th bit from left to right in the intermediate bit sequence (denoted as [8:10]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (denoted as [1:7]).

[0818] The above intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 8th bit to the 11th bit from left to right in the intermediate bit sequence (denoted as [8:11]), and the fourth type of bit segment includes the 1st bit to the 7th bit from left to right in the intermediate bit sequence (denoted as [1:7]).

[0819] When the first sequence processing module performs distribution matching processing on each intermediate bit sequence in the intermediate bit sequence to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 27. When the first sequence processing module performs distribution matching processing on each intermediate bit sequence in the intermediate bit sequence to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0820] After processing the bit sequence to be processed using the solution of this example, the probability that the combined bit sequence is mapped to a high amplitude bit is reduced to about 29.81%.

[0821] Example 6. As Figure 11 shown, the number of bits in the bit sequence to be processed is 72, and the number of bits in the combined bit sequence is 128.

[0822] Figure 11 The meanings of the symbols in Figure 6 can be referred to, and the present application will not elaborate here.

[0823] Please refer to Figure 11, the bit sequence to be processed is divided into 12 bit subsequences. The bits in the bit subsequence are consecutive in the bit sequence to be processed, and the r-th bit subsequence and the (r + 1)-th bit subsequence among the 12 bit subsequences are consecutive in the bit sequence to be processed, where r ≥ 1. Among the 12 bit subsequences, every 4 consecutive bit subsequences in the bit sequence to be processed form an initial bit sequence. Among the 3 initial bit sequences formed by the 12 bit subsequences, the s-th initial bit sequence and the (s + 1)-th initial bit sequence are consecutive in the bit sequence to be processed, where s ≥ 1. The number of bits in each of the 12 bit subsequences is 6. The number of bits in the intermediate bit sequences obtained respectively according to the first to the third initial bit sequences among the 3 initial bit sequences are: 10, 11, 11. The first sequence processing device can obtain four intermediate bit sequences according to each of the 3 initial bit sequences. The number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the first initial bit sequence is 10 for each; the number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the second initial bit sequence is 11 for each, and the number of bits in the four intermediate bit sequences obtained by the first sequence processing device according to the third initial bit sequence is 11 for each.

[0824] The first sequence processing module can query an expansion table according to the first type of bit segments in multiple subsequences in the initial bit sequence to obtain the second type of bit segments in multiple intermediate bit sequences. The first sequence processing module can also obtain the fourth type of bit segments in multiple intermediate bit sequences according to the third type of bit segments in the multiple subsequences. In this way, multiple intermediate bit sequences can be obtained according to the initial bit sequence.

[0825] In the process of the first sequence processing device obtaining intermediate bit sequences according to different initial bit sequences, the expansion tables queried can be the same or different. The first sequence processing device performs bit processing m on the m-th initial bit sequence to obtain the intermediate bit sequence W q m . Here, take the expansion tables used in bit processing 1 to all indicate the one-to-one correspondence shown in Table 21 and Table 22, and the expansion tables used in bit processing 2 to 3 to all indicate the one-to-one correspondence shown in Table 23 and Table 24 as an example.

[0826] Exemplarily, in each of the above-mentioned bit subsequences , the first type of bit segments include the 5th bit to the 6th bit from left to right in the bit subsequence (denoted as [5:6]), and the third type of bit segments include the 1st bit to the 4th bit from left to right in the bit subsequence (denoted as [1:4]).

[0827] The above-mentioned intermediate bit sequences In each of the intermediate bit sequences, the second type of bit segment includes the 5th bit to the 10th bit from left to right in the intermediate bit sequence (denoted as [5:10]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (denoted as [1:4]).

[0828] The above-mentioned intermediate bit sequence In each of the intermediate bit sequences, the second type of bit segment includes the 5th bit to the 11th bit from left to right in the intermediate bit sequence (denoted as [5:11]), and the fourth type of bit segment includes the 1st bit to the 4th bit from left to right in the intermediate bit sequence (denoted as [1:4]).

[0829] When the first sequence processing module performs distribution matching processing on each intermediate bit sequence to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 27. When the first sequence processing module performs distribution matching processing on each intermediate bit sequence to obtain the corresponding target bit sequence, the corresponding target bit sequence can be obtained by looking up the table shown in Table 28.

[0830] After processing the bit sequence to be processed using the solution of this example, the probability that the combined bit sequence obtained is mapped to a high amplitude bit is reduced to about 16.27%.

[0831] Example 7: On the basis of the previous Example 5, the extended table used in Bit Processing 1 changes, and this extended table is used to indicate the one-to-one correspondence shown in Table 25 and Table 26.

[0832] Moreover, in each of the above-mentioned bit subsequences the first type of bit segment includes the 7th bit to the 8th bit from left to right in the bit subsequence (denoted as [7:8]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (denoted as [1:6]). In each of the above-mentioned bit subsequences the first type of bit segment includes the 7th bit to the 9th bit from left to right in the bit subsequence (denoted as [7:9]), and the third type of bit segment includes the 1st bit to the 6th bit from left to right in the bit subsequence (denoted as [1:6]).

[0833] The above-mentioned intermediate bit sequence In each intermediate bit sequence, the second type of bit segment includes the 7th to 10th bits from left to right in the intermediate bit sequence (denoted as [7:10]), and the fourth type of bit segment includes the 1st to 6th bits from left to right in the intermediate bit sequence (denoted as [1:6]).

[0834] After processing the bit sequence to be processed using the solution of this example, the probability that the merged bit sequence obtained is mapped to a high amplitude bit is reduced to approximately 29.56%.

[0835] The above examples can also have other variations.

[0836] For example, multiple bit processing cases are provided in the above examples. For example, bit processing 1 to 6 in each of Examples 1, 2, and 3, bit processing 1 to 3 in each of Examples 4, 5, and 6, and bit processing 1 in Example 7. Each bit processing is used to obtain multiple intermediate bit sequences from an initial bit sequence. On this basis, these bit processings can be combined arbitrarily to obtain a new example. The number of bits in the bit sequence to be processed and / or the number of bits in the bit sequence obtained after merging in the new example are different from those in the previous Examples 1 to 6.

[0837] Furthermore, the processing performed by the above first sequence processing device can be referred to as PCS coding processing. In PCS coding processing, the serial-to-parallel conversion process of splitting the bit sequence to be processed can be implemented using a demultiplexer (DeMUX). The process of obtaining multiple intermediate bit sequences from the initial bit sequence can be referred to as a redistribution and bit extension process, and the parallel-to-serial conversion process of merging multiple target bit sequences can be implemented using a multiplexer (MUX).

[0838] It can be understood that the process of splitting the bit sequence to be processed may not be implemented using a device. For example, it can be implemented by connecting a single data line to multiple data lines. The single data line is used to transmit the bit sequence to be processed, and the multiple data lines are used to transmit multiple bit subsequences (or multiple initial bit sequences) respectively. The process of merging multiple target bit sequences may also not be implemented using a device. For example, it can be implemented by connecting a single data line to multiple data lines. The multiple data lines are used to transmit multiple target bit sequences respectively, and the single data line is used to transmit the merged bit sequence.

[0839] Optionally, in the sequence processing method provided by the embodiments of the present application, the operations performed by the first sequence processing device may not include the above S102 and S103, and the operations performed by the second sequence processing device may not include the above S105 and S106. The first sequence processing device only needs to obtain a plurality of intermediate bit sequences according to the initial bit sequence. The second sequence processing device only needs to obtain the initial bit sequence according to the plurality of intermediate bit sequences.

[0840] In the embodiments of the present application, taking the first bit position in the bit sequence or bit segment being represented as 1 as an example, optionally, it may also be that the first bit position is represented as 0.

[0841] Based on the sequence processing method provided by the embodiments of the present application, the embodiments of the present application also provide the following several sequence processing devices.

[0842] Exemplarily, Figure 12 is a schematic structural diagram of a sequence processing device provided by an embodiment of the present application. This sequence processing device may be the aforementioned first sequence processing device. Figure 12 The shown sequence processing device has the functions of the aforementioned first sequence processing device. Figure 12 The functions of the shown sequence processing device may refer to the functions of the aforementioned first sequence processing device.

[0843] As Figure 12 shown, this sequence processing device includes: an acquisition module 1201, a distribution matching module 1202, and a merging module 1203.

[0844] The acquisition module 1201 is used to obtain a plurality of intermediate bit sequences according to the initial bit sequence and the expansion table; the expansion table is used to indicate the one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences. The number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d; the first bit sequence is composed of the first type of bit segments of multiple bit subsequences in the initial bit sequence, and the second bit sequence is composed of the second type of bit segments of multiple intermediate bit sequences. The second type of bit segment is multiple bits of the highest bit of the intermediate bit sequence.

[0845] The distribution matching module 1202 is used to perform distribution matching processing on the plurality of intermediate bit sequences respectively to obtain a plurality of target bit sequences; the low-amplitude bit numbers of 2 d second bit sequences are all greater than or equal to 2 h in the 2 dThe number of low - amplitude bits of a second bit sequence other than the second bit sequence; the number of low - amplitude bits of any second bit sequence is: the number of bits in the multiple target bit sequences corresponding to any second bit sequence that are used to map to the lowest - amplitude bit; the multiple intermediate bit sequences correspond one - to - one with the multiple target bit sequences, and each target bit sequence is obtained by performing distribution matching processing on the corresponding intermediate bit sequence.

[0846] The merging module 1203 is used to merge the obtained target bit sequences.

[0847] Optionally, d the minimum value of the number of low - amplitude bits of the two second bit sequences is u + 1, h among the two second bit sequences, d the maximum value of the number of low - amplitude bits of the second bit sequences other than the two second bit sequences is u, where u≥0.

[0848] For example, the intermediate bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second - type bit segment and a second second - type bit segment; d the two second bit sequences include:

[0849] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0850] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0851] a second bit sequence in which the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0852] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0853] a second bit sequence in which the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0854] a second bit sequence in which the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0855] a second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0856] a second bit sequence in which the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0857] a second bit sequence in which the first second-class bit segment is (0, 0, 0) and the second second-class bit segment is (0, 0, 1);

[0858] a second bit sequence in which the first second-class bit segment is (0, 0, 1) and the second second-class bit segment is (0, 0, 0);

[0859] a second bit sequence in which the first second-class bit segment is (0, 1, 0) and the second second-class bit segment is (1, 0, 0);

[0860] a second bit sequence in which the first second-class bit segment is (1, 0, 0) and the second second-class bit segment is (0, 1, 0);

[0861] a second bit sequence in which the first second-class bit segment is (1, 0, 1) and the second second-class bit segment is (0, 0, 0);

[0862] a second bit sequence in which the first second-class bit segment is (0, 0, 0) and the second second-class bit segment is (1, 0, 1);

[0863] a second bit sequence in which the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0864] A second bit sequence in which the first second-class bit segment is (1, 0, 0) and the second second-class bit segment is (1, 1, 0);

[0865] In the various second-category bit segments given in the embodiments of the present application, the bits in the second-category bit segments are arranged from left to right in the order of bit positions from low to high or from high to low. In each second-category bit segment, the bit position of the w-th bit from left to right is higher or lower than the bit position of the w+1-th bit, w≥1. In addition, assuming that the second-category bit segment includes y bits, then the y bits in the second-category bit segment are also the y bits with the highest bit in the intermediate bit sequence including the second-category bit segment; and the highest bit in each second-category bit segment is also the bit with the highest bit position in the intermediate bit sequence including the second-category bit segment.

[0866] Optionally, 2 d The minimum value of the number of low-amplitude bits in the second bit sequence is u,2 h The second bit sequence is divided by 2 d The maximum number of low-amplitude bits of the second bit sequence other than the second bit sequence is u, u ≥ 0; 2 d The second bit sequence includes: 2 h v second bit sequences whose number of low amplitude bits is greater than u among the second bit sequences, and any 2 of the multiple second bit sequences whose number of low amplitude bits is ud - v second bit sequences, where v ≥ 1.

[0867] For example, the middle bit sequence includes 10 bits, and the second bit sequences include: a consecutive first second - type bit segment and a second second - type bit segment, 2 d The 2 second bit sequences include:

[0868] A second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0869] A second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0870] A second bit sequence in which the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0);

[0871] A second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0872] A second bit sequence in which the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0873] A second bit sequence in which the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0);

[0874] A second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0);

[0875] A second bit sequence in which the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0);

[0876] A second bit sequence in which the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1);

[0877] A second bit sequence in which the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0);

[0878] A second bit sequence in which the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0);

[0879] A second bit sequence in which the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0);

[0880] A second bit sequence where the first second-type bit segment is (0, 1, 0) and the second second-type bit segment is (0, 1, 0);

[0881] A second bit sequence where the first second-type bit segment is (1, 0, 1) and the second second-type bit segment is (0, 0, 0);

[0882] A second bit sequence where the first second-type bit segment is (0, 0, 0) and the second second-type bit segment is (1, 0, 1);

[0883] And any one of the following second bit sequences:

[0884] A second bit sequence where the first second-type bit segment is (1, 1, 0) and the second second-type bit segment is (1, 0, 0);

[0885] A second bit sequence where the first second-type bit segment is (1, 0, 0) and the second second-type bit segment is (1, 1, 0);

[0886] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: consecutive first and second second-type bit segments, and 2 d second bit sequences include:

[0887] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0888] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0889] A second bit sequence where the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0890] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0891] A second bit sequence where the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0892] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 1, 0, 0);

[0893] A second bit sequence where the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 0, 1, 0);

[0894] A second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (1, 0, 1, 0);

[0895] A second bit sequence in which the first second-type bit segment is (1, 1, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0896] A second bit sequence in which the first second-type bit segment is (1, 0, 1, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0897] A second bit sequence in which the first second-type bit segment is (0, 0, 1, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0898] A second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0899] A second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (1, 0, 0, 0);

[0900] A second bit sequence in which the first second-type bit segment is (1, 0, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0901] A second bit sequence in which the first second-type bit segment is (0, 1, 0, 0) and the second second-type bit segment is (0, 1, 0, 0);

[0902] And, any one of the following second bit sequences:

[0903] A second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 1, 1, 0);

[0904] A second bit sequence in which the first second-type bit segment is (0, 1, 1, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0905] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, 2 d second bit sequences include:

[0906] A second bit sequence in which the first second-type bit segment is (0, 0, 0, 0) and the second second-type bit segment is (0, 0, 0, 0);

[0907] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0908] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0909] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0910] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0911] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0912] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0);

[0913] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0);

[0914] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0);

[0915] A second bit sequence where the first second - type bit segment is (0, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0916] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0);

[0917] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0);

[0918] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0919] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0);

[0920] And any two of the following second bit sequences:

[0921] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0);

[0922] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0);

[0923] A second bit sequence in which the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0924] A second bit sequence in which the first second - type bit segment is (1, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0925] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0);

[0926] A second bit sequence in which the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0);

[0927] For another example, the middle bit sequence includes 10 bits, and the second bit sequence includes: consecutive first and second second - type bit segments. 2 d The second bit sequences include:

[0928] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0929] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0930] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0931] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0932] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0933] A second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0);

[0934] A second bit sequence where the first second - type bit segment is (1, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0935] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0936] A second bit sequence where the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0937] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0);

[0938] A second bit sequence where the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0);

[0939] And any five second bit sequences from the following second bit sequences:

[0940] A second bit sequence where the first second - type bit segment is (0, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0941] A second bit sequence where the first second - type bit segment is (1, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0942] A second bit sequence where the first second - type bit segment is (0, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0943] A second bit sequence where the first second - type bit segment is (0, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0944] A second bit sequence where the first second - type bit segment is (1, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0945] The second bit sequence where the first second - type bit segment is (0, 1, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0946] The second bit sequence where the first second - type bit segment is (1, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0);

[0947] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 1, 0, 0);

[0948] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0);

[0949] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0, 0, 0);

[0950] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0, 0, 0);

[0951] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 1, 0, 0);

[0952] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0, 0, 0);

[0953] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 1, 0, 0);

[0954] For another example, the middle bit sequence includes 11 bits, and the second bit sequence includes: the consecutive first second - type bit segment and the second second - type bit segment. 2 d The second bit sequences include:

[0955] The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0956] The second bit sequence where the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0957] A second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0958] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0959] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0960] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0961] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0962] And, any nine second bit sequences among the following second bit sequences:

[0963] A second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0, 0);

[0964] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0965] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0966] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0967] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0968] A second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0969] A second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0970] A second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0);

[0971] A second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0);

[0972] A second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0);

[0973] A second bit sequence in which the first second - type bit segment is (0, 0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0);

[0974] For another example, the middle bit sequence includes 10 bits, the second - type bit segment includes 3 bits, and the second bit sequence includes 4 second - type bit segments. These 2 d second bit sequences include 256 second bit sequences. The 256 second bit sequences include 246 second bit sequences shown in Table 14 and any 10 second bit sequences among the 24 second bit sequences shown in Table 15. In Table 14 and Table 15, the second bit sequence includes 4 consecutive second - type bit segments, and these 4 second - type bit segments can be the 4 second - type bit segments arranged from left to right in Table 14 and Table 15.

[0975] For another example, the middle bit sequence includes 11 bits, the second - type bit segment includes 3 bits, and the second bit sequence includes 4 second - type bit segments. These 2 d second bit sequences include 256 second bit sequences. The 256 second bit sequences include 256 second bit sequences shown in Table 16. In Table 16, the second bit sequence includes 4 consecutive second - type bit segments, and these 4 second - type bit segments can be the 4 second - type bit segments arranged from left to right in Table 16.

[0976] For another example, the middle bit sequence includes 10 bits, the second - type bit segment includes 3 bits, and the second bit sequence includes 4 second - type bit segments. These 2 dThe second bit sequence includes 64 second bit sequences, and the 64 second bit sequences include 61 second bit sequences shown in Table 17 and any 3 second bit sequences among the 12 second bit sequences shown in Table 18. In Table 17 and Table 18, the second bit sequence includes 4 consecutive second type bit segments, and these 4 second type bit segments can be the 4 second type bit segments arranged from left to right in Table 17 and Table 18.

[0977] For another example, the middle bit sequence includes 11 bits, the second type bit segment includes 4 bits, and the second bit sequence includes 4 second type bit segments. These 2 d second bit sequences include 256 second bit sequences, and the 256 second bit sequences include 212 second bit sequences shown in Table 19 and any 44 second bit sequences among the 56 second bit sequences shown in Table 20. In Table 19 and Table 20, the second bit sequence includes 4 consecutive second type bit segments, and these 4 second type bit segments can be the 4 second type bit segments arranged from left to right in Table 19 and Table 20.

[0978] For another example, the middle bit sequence includes 10 bits, the second type bit segment includes 6 bits, and the second bit sequence includes 4 second type bit segments. These 2 d second bit sequences include 256 second bit sequences, and the 256 second bit sequences include 121 second bit sequences shown in Table 21 and any 135 second bit sequences among the 174 second bit sequences shown in Table 22. In Table 21 and Table 22, the second bit sequence includes 4 consecutive second type bit segments, and these 4 second type bit segments can be the 4 second type bit segments arranged from left to right in Table 20 and Table 21.

[0979] For another example, the middle bit sequence includes 10 bits, the second type bit segment includes 7 bits, and the second bit sequence includes 4 second type bit segments. These 2 d second bit sequences include 256 second bit sequences, and the 256 second bit sequences include 255 second bit sequences shown in Table 23 and any 1 second bit sequence among the 324 second bit sequences shown in Table 24. In Table 23 and Table 24, the second bit sequence includes 4 consecutive second type bit segments, and these 4 second type bit segments can be the 4 second type bit segments arranged from left to right in Table 23 and Table 24.

[0980] For another example, the middle bit sequence includes 10 bits, the second type bit segment includes 4 bits, and the second bit sequence includes 4 second type bit segments. These 2 dThe second bit sequence includes 1,024 second bit sequences, and the 1,024 second bit sequences include 903 second bit sequences shown in Table 25 and any 121 second bit sequences among the 156 second bit sequences shown in Table 26. In Table 25 and Table 26, the second bit sequence includes 4 consecutive second type bit segments, and these 4 second type bit segments can be the 4 second type bit segments arranged from left to right in Table 25 and Table 26.

[0981] Optionally, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence as shown in Table 3; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 4 and Table 5; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 6 and Table 7; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 8 and Table 9; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 10 and Table 11; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 12 and Table 13; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 14 and Table 15; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence as shown in Table 16; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 17 and Table 18; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 19 and Table 20; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 21 and Table 22; or, 2 d first bit sequences and 2 d second bit sequences can have a one-to-one correspondence jointly shown by Table 23 and Table 24; or, 2 d first bit sequences and 2d The one-to-one correspondence of a second bit sequence can be shown jointly by Table 25 and Table 26.

[0982] Exemplarily, Figure 13 FIG. is a schematic structural diagram of another sequence processing device provided by an embodiment of the present application. The sequence processing device may be the aforementioned second sequence processing device. Figure 13 The shown sequence processing device has the functions of the aforementioned second sequence processing device. Figure 13 The functions of the shown sequence processing device may refer to the functions of the aforementioned second sequence processing device.

[0983] As Figure 13 shown, the sequence processing device includes: a splitting module 1301, a distribution matching module 1302, and an obtaining module 1303.

[0984] The splitting module 1301 is configured to split a plurality of target bit sequences from a bit sequence.

[0985] The distribution matching module 1302 is configured to perform an inverse process of distribution matching processing on the plurality of target bit sequences to obtain a plurality of intermediate bit sequences.

[0986] The obtaining module 1303 is configured to obtain an initial bit sequence according to the plurality of intermediate bit sequences and an expansion table. The expansion table is used to indicate the one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences. The number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d. The first bit sequence is composed of a first type of bit segment of a plurality of bit subsequences in the initial bit sequence, and the second bit sequence is composed of a second type of bit segment of a plurality of intermediate bit sequences. The second type of bit segment is a plurality of bits at the highest bit of the intermediate bit sequence. The low-amplitude bit numbers of 2 d second bit sequences are all greater than or equal to the low-amplitude bit numbers of the second bit sequences other than the 2 h second bit sequences among the 2 d second bit sequences. The low-amplitude bit number of any second bit sequence is: the number of bits used to map to the lowest amplitude bit in the plurality of target bit sequences corresponding to any second bit sequence.

[0987] An embodiment of the present application further provides a chip. As Figure 14 shown, the chip includes a processor 1401 and an interface 1402, and the processor 1401 is connected to the interface 1402.

[0988] The processor 1401 is configured to run the method executed by the first sequence processing device provided in the embodiments of the present application to process a bit sequence, which may be the above-mentioned initial bit sequence or the above-mentioned sequence to be processed. The processor is further configured to obtain a data frame according to the bit sequence processed by running the method executed by the first sequence processing device provided in the embodiments of the present application. The interface 1402 is configured to output the data frame. Exemplarily, for the process by which the processor 1401 obtains a data frame according to the processed bit sequence, reference may be made to the process by which the foregoing first sequence processing module 012 obtains a data frame according to the bit sequence.

[0989] And / or, the interface 1402 is configured to receive a data frame, the processor 1401 is configured to obtain a bit sequence according to the data frame, and run the method executed by the second sequence processing device provided in the embodiments of the present application to process the obtained bit sequence. For the process by which the processor 1401 obtains a bit sequence according to the data frame, reference may be made to the process by which the foregoing second sequence processing module 022 obtains a bit sequence according to the data frame.

[0990] The chip may be integrated by Figure 1 the source 011, the first sequence processing module 012, and the first signal processing module 013 in Figure 1 or the chip is integrated by the sink 021, the second sequence processing module 022, and the second signal processing module 023 in Figure 1 or the chip is integrated by the source 011, the first sequence processing module 012, the first signal processing module 013, the sink 021, the second sequence processing module 022, and the second signal processing module 023 in

[0991] Embodiments of the present application further provide an optical module, as shown in Figure 15 , the optical module includes an optical transceiver 130 and a chip 140, and the chip 140 may be the chip shown in Figure 14 . The chip 140 is configured to run any method executed by the first sequence processing device provided in the embodiments of the present application to process a bit sequence, and the chip is further configured to obtain a first data frame according to the bit sequence processed by running any method executed by the first sequence processing device provided in the embodiments of the present application. The optical transceiver 130 is configured to transmit a first optical signal according to the first data frame; the optical transceiver 130 is configured to obtain a second data frame according to the received second optical signal, and the chip is configured to obtain a bit sequence according to the second data frame, and run any method executed by the second sequence processing device provided in the embodiments of the present application to process the bit sequence obtained according to the second data frame.

[0992] The present application provides a computer-readable storage medium, characterized in that instructions are stored in the computer-readable storage medium, and when the instructions run on a computer, the computer is caused to execute the method performed by the first sequence processing device or the second sequence processing device in any of the sequence processing methods provided by the embodiments of the present application.

[0993] The present application provides a computer program product containing instructions, and when the computer program product runs on a computer, the computer is caused to execute the method performed by the first sequence processing device or the second sequence processing device in any of the sequence processing methods provided by the embodiments of the present application.

[0994] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product, and the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a readable storage medium of the computer, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium, or a semiconductor medium (such as a solid-state drive), etc.

[0995] The method embodiments provided by the embodiments of the present application can be mutually referred to the corresponding device embodiments, and the embodiments of the present application do not make any limitations in this regard. The order of the steps of the method embodiments provided by the embodiments of the present application can be appropriately adjusted, and the steps can also be increased or decreased accordingly according to the situation. Any person skilled in the art in the technical field disclosed by the present application can easily think of a changed method, which should be covered by the protection scope of the present application, and thus will not be elaborated herein.

[0996] In this application, terms such as "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and "a plurality" means two or more, unless otherwise clearly defined. In the corresponding embodiments provided in this application, it should be understood that the disclosed structure can be implemented in other constitutive manners. For example, the above-described embodiments are merely illustrative. The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0997] As described above, the above are only alternative embodiments of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A sequence processing method, characterized in that, The method includes: Obtain a plurality of intermediate bit sequences according to an initial bit sequence and an expansion table; the expansion table is used to indicate a one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences, the number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d; the first bit sequence is composed of a first type of bit segments of a plurality of bit subsequences in the initial bit sequence, and the second bit sequence is composed of a second type of bit segments of the plurality of intermediate bit sequences, and the second type of bit segments are a plurality of bits at the highest position of the intermediate bit sequence; Perform distributed matching processing on the multiple intermediate bit sequences respectively to obtain multiple target bit sequences; the 2 d low-amplitude bit counts of the two second bit sequences are both greater than or equal to the low-amplitude bit counts of the second bit sequences other than the two second bit sequences among the four second bit sequences; the low-amplitude bit count of any second bit sequence is: the number of bits used to map to the lowest amplitude bit among the multiple target bit sequences corresponding to the any second bit sequence; h Among the four second bit sequences, the low-amplitude bit counts of the second bit sequences other than the two second bit sequences; d the low-amplitude bit count of any second bit sequence is: the number of bits used to map to the lowest amplitude bit among the multiple target bit sequences corresponding to the any second bit sequence; merging the obtained target bit sequence.

2. The method according to claim 1, characterized in that, The minimum number of low-amplitude bits in the two d second bit sequences is u + 1, and the two h second bit sequences except the two d second bit sequences have a maximum number of low-amplitude bits of u, where u ≥ 0.

3. The method according to claim 2, wherein The middle bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment; the 2 d second bit sequences include: A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0); A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1); A second bit sequence where the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0); A second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1); A second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit to the highest bit or from the highest bit to the lowest bit.

4. The method according to claim 1, wherein The said 2 d The minimum value of the number of low-amplitude bits in the said 2 h second bit sequences is u, and the maximum value of the number of low-amplitude bits in the second bit sequences other than the said 2 d second bit sequences among the said 2 second bit sequences is u, where u ≥ 0; The said 2 d The two second bit sequences include: the said 2 h Among the two second bit sequences, v second bit sequences with the number of low-amplitude bits greater than u, and any 2 of the multiple second bit sequences with the number of low-amplitude bits being u d -v second bit sequences, where v≥1.

5. The method according to claim 4, wherein The intermediate bit sequence includes 10 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, the 2 d second bit sequences include: A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 0); A second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 0); A second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 1, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (0, 0, 1); The second bit sequence where the first second - type bit segment is (0, 0, 1) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (1, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0) and the second second - type bit segment is (0, 1, 0); The second bit sequence where the first second - type bit segment is (1, 0, 1) and the second second - type bit segment is (0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0) and the second second - type bit segment is (1, 0, 1); And any one of the following second bit sequences: The second bit sequence where the first second - type bit segment is (1, 1, 0) and the second second - type bit segment is (1, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0) and the second second - type bit segment is (1, 1, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit to the highest bit or from the highest bit to the lowest bit.

6. The method according to claim 4, wherein The middle bit sequence includes 10 bits. The second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, the 2 d second bit sequences include: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); And any one of the following second bit sequences: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position.

7. The method according to claim 4, characterized in that The intermediate bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, the 2 d second bit sequences include: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0); The second bit sequence where the first second - type bit segment is (0, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0); The second bit sequence where the first second - type bit segment is (1, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0); The second bit sequence where the first second - type bit segment is (0, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 1, 0, 0) and the second second - type bit segment is (1, 0, 0, 0); And any two of the following second bit sequences: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0); The second bit sequence where the first second - type bit segment is (1, 0, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (1, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0); The second bit sequence where the first second - type bit segment is (0, 1, 1, 0) and the second second - type bit segment is (0, 0, 0, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest - order bit to the highest - order bit or from the highest - order bit to the lowest - order bit.

8. The method according to claim 4, characterized in that, The middle bit sequence includes 10 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, and the 2 d second bit sequences include: The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0); The second bit sequence where the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0); And any five of the following second bit sequences: The second bit sequence in which the first second - type bit segment is (0, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 1, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 1, 1, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 1, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 1, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 1, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 1, 0, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order of bit positions from low to high or from high to low.

9. The method according to claim 4, wherein The middle bit sequence includes 11 bits, and the second bit sequence includes: a consecutive first second-type bit segment and a second second-type bit segment, the 2 d second bit sequences include: The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 1, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 0, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (1, 1, 0, 0, 0, 0, 0); And any nine of the following second bit sequences: The second bit sequence in which the first second - type bit segment is (0, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 0, 1, 0, 0, 0, 0); The second bit sequence in which the first second - type bit segment is (1, 0, 0, 0, 0, 0, 0) and the second second - type bit segment is (0, 1, 0, 0, 0, 0, 0); The first second - type bit segment is (1, 0, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (1, 1, 0, 0, 0, 0, 0); The first second - type bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (1, 0, 0, 0, 0, 0, 0); The first second - type bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (0, 1, 0, 0, 0, 0, 0); The first second - type bit segment is (0, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (1, 1, 0, 0, 0, 0, 0); The first second - type bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (1, 0, 0, 0, 0, 0, 0); The first second - type bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (0, 1, 0, 0, 0, 0, 0); The first second - type bit segment is (1, 1, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (1, 1, 0, 0, 0, 0, 0); The first second - type bit segment is (1, 0, 0, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (1, 0, 0, 0, 0, 0, 0); The first second - type bit segment is (0, 0, 1, 0, 0, 0, 0), and the second second - type bit segment is a second bit sequence of (0, 0, 0, 0, 0, 0, 0); Wherein, the bits in the second - type bit segment are arranged from left to right in the order from the lowest bit position to the highest bit position or from the highest bit position to the lowest bit position.

10. A sequence processing method, characterized in that, The method includes: Splitting a plurality of target bit sequences from a bit sequence; Performing an inverse process of distribution matching processing on the plurality of target bit sequences to obtain a plurality of intermediate bit sequences; Obtain an initial bit sequence according to the multiple intermediate bit sequences and the expansion table; the expansion table is used to indicate the one-to-one correspondence between 2 d first bit sequences and 2 d second bit sequences, the number of bits in the first bit sequence is d, d≥2, and the number of bits in the second bit sequence is h, h>d; the first bit sequence is composed of the first type of bit segments of multiple bit subsequences in the initial bit sequence, and the second bit sequence is composed of the second type of bit segments of the multiple intermediate bit sequences, and the second type of bit segment is multiple bits of the highest bit of the intermediate bit sequence; the low-amplitude bit numbers of the 2 d second bit sequences are all greater than or equal to the low-amplitude bit numbers of the second bit sequences other than the 2 h second bit sequences among the 2 d second bit sequences; the low-amplitude bit number of any second bit sequence is: the number of bits used to map to the lowest amplitude bit among the multiple target bit sequences corresponding to the any second bit sequence.

11. A chip, characterized in that, The chip includes a processor and an interface. The processor is configured to run the method according to any one of claims 1 to 9 to process the bit sequence, and the processor is further configured to obtain a data frame according to the processed bit sequence, and the interface is configured to output the data frame.

12. A chip, characterized in that, The chip includes a processor and an interface. The interface is configured to receive a data frame, the processor is configured to obtain a bit sequence according to the data frame, and run the method according to claim 10 to process the obtained bit sequence.

13. An optical module, characterized in that, Including an optical transceiver and a chip; The chip is configured to run the method according to any one of claims 1 to 9 to process the bit sequence, and the chip is further configured to obtain a first data frame according to the bit sequence processed by running the method according to any one of claims 1 to 9, and the optical transceiver is configured to transmit a first optical signal according to the first data frame; The optical transceiver is configured to obtain a second data frame based on the received second optical signal. The chip is configured to obtain a bit sequence based on the second data frame, and execute the method recited in claim 10 to process the bit sequence obtained based on the second data frame.

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