Methods of forming microelectronic devices using directed self-assembly and related microelectronic devices

Abstract

The invention relates to a method of forming a microelectronic device using directed self-assembly and a related microelectronic device. A method of forming a microelectronic device includes forming a first trench in a semiconductor structure with semiconductor pillars interposed therebetween and forming a first insulating structure in the first trench having a second insulating structure. The method also includes forming a first conductive structure adjacent the first end of the semiconductor pillar and the first insulating structure portion and forming a mask adjacent the first conductive structure and the first insulating structure exposed portion, the uppermost mask being a neutral layer mask for forming a polymeric mask via directed self-assembly. The method further includes forming a second trench using the polymeric mask and removing portions of the first conductive structure exposed by the third trench to form a first conductive member having an opening therebetween. The method also includes forming a second conductive structure adjacent a sidewall of the semiconductor pillar and forming a third conductive structure adjacent a second end of the semiconductor pillar.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 616,065, filed on December 29, 2023, entitled "METHODS OF FORMING MICROELECTRONIC DEVICES UTILIZING DIRECTED SELF-ASSEMBLY AND RELATED MICROELECTRONIC DEVICES", and also claims the benefit of the filing date of U.S. Patent Application No. 18 / 956,895, filed on November 22, 2024, entitled "METHODS OF FORMING MICROELECTRONIC DEVICES UTILIZING DIRECTED SELF-ASSEMBLY AND RELATED MICROELECTRONIC DEVICES". FIELD OF THE DISCLOSURE

[0003] In various embodiments, the present disclosure generally relates to the field of microelectronic device design and manufacturing. More specifically, the present disclosure relates to methods of forming microelectronic devices using directed self-assembly and related microelectronic devices, memory devices, and electronic systems. BACKGROUND OF THE DISCLOSURE

[0004] Microelectronic device designers typically desire to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the spacing distance between adjacent features. Additionally, microelectronic device designers typically desire to design architectures that are not only small but also provide performance advantages and simplify design and / or manufacturing techniques.

[0005] A relatively common microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in a computer or other electronic device. There are many types of memory, including (but not limited to) random access memory (RAM) and dynamic random access memory (DRAM). SUMMARY OF THE DISCLOSURE

[0006] Disclosed is a method of forming a microelectronic device and it includes: forming a first trench extending into a semiconductor structure, the semiconductor structure including a substrate for forming semiconductor pillars between neighbors in the first trench. Forming a first insulating structure in the first trench, each first insulating structure having a second insulating structure therein. Forming a first conductive structure adjacent to a first end of the semiconductor pillar and a portion of the first insulating structure. Forming one or more masks adjacent to the exposed portion of the first conductive structure and the first insulating structure, the uppermost of the one or more masks including a neutral layer mask. A block copolymer is formed adjacent to the neutral layer mask and annealed to form a self-assembled array of a first polymeric structure and a second polymeric structure. The first polymeric structure or the second polymeric structure is selectively removed, and the remaining one of the first polymeric structure or the second polymeric structure forms a polymeric mask. Using the polymeric mask to form a second trench in the one or more masks. Forming a sacrificial material in the second trench and removing the remaining portion of the one or more masks to form a third trench through the sacrificial material and expose an upper surface of the first conductive structure. Removing a portion of the first conductive structure exposed by the third trench to form a first conductive member having an opening therebetween. Forming a second conductive structure adjacent to at least one sidewall of at least one of the semiconductor pillars and forming a third conductive structure adjacent to a second end of the semiconductor pillar.

[0007] Disclosed is another method of forming a microelectronic device and it includes forming a semiconductor structure having a substrate. Forming a first trench that extends into the semiconductor structure in a first direction and is arranged parallel to each other in a second direction. Semiconductor pillars are formed and inserted between neighbors in the first trench in the second direction. Forming an insulating structure in the first trench and it includes a lower section and an upper section. The lower section exhibits a first width defined at least in part by a horizontal distance between sidewalls of adjacent semiconductor pillars in the second direction, and the upper section exhibits a second width defined at least in part by a horizontal distance between its sidewalls in the second direction. The first width is greater than the second width. A shoulder region is formed between the sidewalls of the lower section of the insulating structure and the sidewalls of the upper section of the insulating structure. A first conductive structure is formed adjacent to a first end of the semiconductor pillar and extends adjacent to the shoulder region of the adjacent insulating structure. Removing a portion of the first conductive structure to form a first conductive member having an opening therebetween. Forming a second conductive structure adjacent to one of the sidewalls of at least one of the semiconductor pillars and forming a third conductive structure adjacent to a second end of the semiconductor pillar.

[0008] Also disclosed is a microelectronic device including an insulating structure and one or more vertical access devices. The insulating structure is disposed in a first direction and inserted between semiconductor pillars and alternates with the semiconductor pillars in a second direction. Each insulating structure includes a lower section, an upper section, and a shoulder region between a sidewall of the lower section of the insulating structure and a sidewall of the upper section of the insulating structure. The lower section exhibits a first width defined at least in part in the second direction by a distance between sidewalls of adjacent semiconductor pillars. The upper section exhibits a second width defined at least in part in the second direction by a distance between its sidewalls. The first width is greater than the second width. The one or more vertical access devices include one of the semiconductor pillars having oppositely disposed source / drain regions and a channel region vertically therebetween. A gate electrode is adjacent to and in electrical communication with the one of the semiconductor pillars. A first conductive member extends adjacent to one end of the one of the semiconductor pillars and adjacent to the shoulder region of an adjacent insulating structure. The first conductive member is in electrical communication with one of the source / drain regions and a conductive structure is in electrical communication with the other of the source / drain regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To understand the present disclosure in detail, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which like elements are generally denoted by like numerals, and in which:

[0010] Figures 1A to 12A is a simplified top view of a microelectronic device structure at different processing stages of a method of forming a microelectronic device in accordance with an embodiment of the present disclosure;

[0011] Figures 1B to 12B is in accordance with an embodiment of the present disclosure and corresponds respectively to Figures 1A to 12A a simplified cross-sectional view along line B-B thereof;

[0012] Figure 5C is a simplified top view of an exemplary neutral layer mask including a guiding pattern in accordance with an embodiment of the present disclosure; and

[0013] Figure 13 is a schematic circuit diagram of a memory cell array including a microelectronic device in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The following description provides specific details such as material composition, shape, and size in order to provide a detailed description of embodiments of the present disclosure. However, those of ordinary skill in the art should understand that the embodiments of the present disclosure can be practiced without using these specific details. In fact, the embodiments of the present disclosure can be practiced in combination with conventional microelectronic device manufacturing techniques used in the industry. Additionally, the description provided below does not form a complete process flow for manufacturing a microelectronic device (such as a memory device). The structures described below do not form a complete microelectronic device. Only those process operations and structures required to understand the embodiments of the present disclosure are described in detail below. Additional operations for forming a complete microelectronic device from the structures can be performed by conventional manufacturing techniques.

[0015] The diagrams presented herein are for illustrative purposes only and do not imply an actual diagram of any specific material, component, structure, device, or system. Variations in the shapes depicted in the diagrams due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein should not be construed as limited to any specific shape or region illustrated, but rather include shape deviations caused by, for example, manufacturing. For example, a region illustrated or described as box-shaped may have rough and / or non-linear features, and a region illustrated or described as circular may contain some rough and / or linear features. Additionally, the sharp angles illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the exact shape of the regions and do not limit the scope of the claims. The diagrams are not necessarily drawn to scale. Also, common elements between the diagrams may retain the same numerical designations.

[0016] As used herein, "memory device" means and includes microelectronic devices that exhibit memory functionality but are not necessarily limited to memory functionality. In other words and by way of non-limiting example only, the term "memory device" includes not only conventional memories (such as conventional non-volatile memories, conventional volatile memories), but also application-specific integrated circuits (ASICs) (such as system-on-a-chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0017] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are referenced to the primary plane of the structure and are not necessarily defined by the earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the primary plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the primary plane of the structure. The primary plane of the structure is defined by a surface of the structure that has a relatively greater area than other surfaces of the structure. Referring to the various figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis (Z direction) and may be parallel to the indicated “X” axis (X direction) and / or parallel to the indicated “Y” axis (Y direction); and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, may be perpendicular to the indicated “X” axis, and may be perpendicular to the indicated “Y” axis.

[0018] As used herein, features (such as structures, materials, regions, devices) described as being “adjacent” to each other mean and include the features of one (or several) disclosed entities that are positioned closest (e.g., nearest) to each other. Additional features (such as additional regions, additional structures, additional devices) of one (or several) disclosed entities that do not match the “adjacent” features may be disposed between the “adjacent” features. In other words, the “adjacent” features may be positioned adjacent to each other such that no other features intervene between the “adjacent” features; or the “adjacent” features may be positioned non-adjacent to each other such that at least one feature of an entity other than the entity associated with at least one “adjacent” feature is positioned between the “adjacent” features. Thus, features described as being “vertically adjacent” to each other mean and include the features of one (or several) disclosed entities that are vertically closest (e.g., vertically nearest) to each other. Additionally, features described as being “horizontally adjacent” to each other mean and include the features of one (or several) disclosed entities that are horizontally closest (e.g., horizontally nearest) to each other.

[0019] As used herein, for ease of description, other spatially relative terms (such as “below,” “under,” “bottom,” “above,” “over,” “top,” and the like) may be used to describe the relationship of one element or feature to another (or other) element or feature, as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to cover different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, an element described as being “below” or “under” or “on the bottom” of another element or feature will be oriented “above” or “on the top” of the other element or feature. Thus, those of ordinary skill in the art will understand that the term “below” can cover both the above and below orientations, depending on the context in which the term is used. The material may be oriented in other ways (rotated 90 degrees, inverted, etc.) and the spatially relative descriptors used herein are interpreted accordingly.

[0020] As used herein, when referring to a numerical value of a particular parameter, the terms "about" and "approximate" include the numerical value and the degree of variation within the acceptable tolerances of the particular parameter that would be understood by a person of ordinary skill in the art. For example, "about" or "approximate" with respect to a numerical value can include additional numerical values within the range from 90.0% to 110.0% of the numerical value, such as within the range from 95.0% to 105.0% of the numerical value, within the range from 97.5% to 102.5% of the numerical value, within the range from 99.0% to 101.0% of the numerical value, within the range from 99.5% to 100.5% of the numerical value, or within the range from 99.9% to 100.1% of the numerical value.

[0021] As used herein, when referring to a parameter, property, or condition, the term "substantially" means and includes the parameter, property, or condition being equal to or within a degree of variation from a given value such that a person of ordinary skill in the art would understand that the given value is acceptably met, such as within acceptable manufacturing tolerances. For example, depending on the particular parameter, property, or condition being substantially met, the parameter, property, or condition can be "substantially" the value when the given value is met at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0022] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0024] As used herein, the terms "configured" and "configuration" mean and refer to the size, shape, material composition, orientation, and arrangement of the material, structure, assembly, or device involved for promoting the involved operation or property of the material, structure, assembly, or device involved in a predetermined manner.

[0025] As used herein, "conductive material" means and includes conductive materials such as one or more of the following: metals (such as tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (such as Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steels, low-carbon steels, stainless steels), conductive metal-containing materials (such as conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (such as conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). Additionally, "conductive structure" means and includes a structure formed of and containing conductive material.

[0026] As used herein, "insulating material" means and includes electrical insulating materials such as one or more of the following: at least one dielectric oxide material (such as one or more of the following: silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ), and magnesium oxide (MgO x ))), at least one dielectric nitride material (such as silicon nitride (SiN y ))), at least one dielectric oxynitride material (such as silicon oxynitride (SiO x N y ))), at least one dielectric carbon oxide material (such as silicon carbon oxide (SiO x C y ))), at least one hydrogenated dielectric carbon oxide material (such as hydrogenated silicon carbon oxide (SiC x O y H z ))), and at least one dielectric carbon oxynitride material (such as silicon carbon oxynitride (SiO x C z N y ))). Chemical formulas containing one or more of "x", "y", and "z" herein (such as SiOx , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C y , SiC x O y H z , SiO x C z N y ) represents a material having an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) per atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since chemical formulas represent relative atomic ratios rather than absolute chemical structures, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having an elemental composition that cannot be represented by a well-defined ratio of natural numbers and that violates the law of definite proportions. Additionally, "insulating structure" means and includes a structure formed of and including an insulating material.

[0027] As used herein, the term "semiconductor material" refers to a material having a conductivity intermediate between that of an insulating material and that of a conductive material. For example, a semiconductor material may have a conductivity at room temperature of from about 10 -8 Siemens per centimeter (S / cm) to about 10 4 S / cm (10 6 S / m). Examples of semiconductor materials include elements found in column IV of the periodic table, such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include (but are not limited to) compound semiconductor materials, such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., Al X Ga 1-X As) and quaternary compound semiconductor materials (e.g., Ga X In 1-X As Y P 1-Y)。The compound semiconductor material may include (but is not limited to) a combination of elements from columns III and V of the periodic table (III-V semiconductor materials) or a combination of elements from columns II and VI of the periodic table (II-VI semiconductor materials). Further examples of semiconductor materials include oxide semiconductor materials such as zinc tin oxide (Zn x Sn y O, commonly referred to as "ZTO"), indium zinc oxide (In x Zn y O, commonly referred to as "IZO"), zinc oxide (Zn x O), indium gallium zinc oxide (In x Ga y Zn z O, commonly referred to as "IGZO"), indium gallium silicon oxide (In x Ga y Si z O, commonly referred to as "IGSO"), indium tungsten oxide (In x W y O, commonly referred to as "IWO"), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxynitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium zinc tin oxide (Zr x Zn y Sn zO) and other similar materials.

[0028] As used herein, the term "sacrificial material" means and includes materials that are formed and / or employed during a manufacturing process but are then completely or partially removed before the completion of the manufacturing process.

[0029] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique including (but not limited to): spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the particular material to be formed, the technique for depositing or growing the material can be selected by one of ordinary skill in the art. Additionally, unless the context otherwise indicates, the removal of the materials described herein can be accomplished by any suitable technique including (but not limited to): etching (e.g., dry etching, wet etching, vapor etching, atomic layer etching (ALE)), ion milling, planarization by polishing (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0030] Figures 1A to 12A is a simplified top view of a microelectronic device structure (e.g., a memory device structure, e.g., a DRAM device structure) at different processing stages of a method of forming a microelectronic device (e.g., a memory device, e.g., a DRAM device) using directed self-assembly (DSA) according to an embodiment of the present disclosure. Figures 1B to 12B corresponds respectively to Figures 1A to 12A is a simplified cross-sectional view taken along line B-B thereof. From the description provided below, one of ordinary skill in the art will readily appreciate that the methods described herein can be used to form various microelectronic devices, e.g., for advantageously forming microelectronic devices using directed self-assembly.

[0031] Figure 1A is a top view of a microelectronic device structure 10 according to an embodiment of the present disclosure, and Figure 1B corresponds to Figure 1A is a simplified cross-sectional view taken along line 1B-1B of the top view. In the figures and specifically, in Figures 1A to 12B the "A" symbol after the numerical figure number should indicate a top view, while the "B" symbol should indicate the corresponding cross-sectional view taken along line B-B. As can be seen from Figure 1A and 1B the microelectronic device structure 10 includes a memory cell region "M" and a peripheral region "P".

[0032] First, referring to Figure 1A and 1B, the microelectronic device structure 10 includes a first substrate 20. The configuration of the structure formed by directed self-assembly (DSA) is related to the surface energy of the surface of the first substrate 20. In cases where the surface energy of the substrate surface is not conducive to DSA, the surface energy can be modified (e.g., improved) by forming additional structures (such as cylindrical structures, layered structures, spiral structures, spherical structures) on the substrate surface. In some embodiments, the first substrate 20 is formed of and includes a material that beneficially affects the surface energy to facilitate the DSA process, as described in detail below. The first substrate 20 can be formed of and include at least one insulating material (such as silicon dioxide).

[0033] The microelectronic device structure 10 according to an embodiment of the present disclosure includes a semiconductor structure 21 formed adjacent to the first substrate 20 (such as on, above the first substrate 20) by any suitable process (such as blanket coating, chemical vapor deposition (CVD), physical vapor deposition (PVD) (such as sputtering)). The semiconductor structure 21 includes a substrate 22 and semiconductor pillars 23 formed of semiconductor material and extending (such as vertically upward in the Z direction) from the substrate 22 and integral with the substrate 22 (such as as a single entity). The semiconductive structure 21 can be formed of and include at least one semiconductive material, such as silicon (such as single-crystalline silicon, polycrystalline silicon).

[0034] In addition, the microelectronic device structure 10 includes first trenches 25 that extend parallel to each other (such as vertically downward in the Z direction) into the semiconductor structure 21 and are inserted between adjacent semiconductor pillars 23 in the Y direction. Referring again to Figure 1A and 1B , a first mask 24 is formed and patterned adjacent to the semiconductor structure 21 (such as on, above the semiconductor structure 21), and the first trenches 25 can be formed into the semiconductor structure 21 by a first material removal process (such as a first process including lithographic patterning and etching via the first mask 24). The first mask 24 can be formed of a sacrificial material (such as a hard mask material or a photoresist material). The first material removal process can also remove at least a portion of the semiconductor structure 21 adjacent to the peripheral region P of the microelectronic device structure 10 (such as on, above the peripheral region P).

[0035] The first trenches 25 can be formed to penetrate into the semiconductor structure 21 and terminate at a first depth D1 (such as the depth from the uppermost surface of the first mask 24 to the upper surface of the substrate 22), as Figure 1Bshown in. For example, the first depth D1 can be in the range from about 100 nanometers (nm) to about 250 nm, such as from about 150 nm to about 200 nm (e.g., about 150 nm). In some embodiments, portions of the semiconductor structure 21 adjacent to the peripheral region P of the microelectronic device structure 10 (e.g., on, above the peripheral region P) are also removed to the first depth D1. The first trench 25 can exhibit a first width W1 that is at least partially defined by the distance between the sidewalls of adjacent ones of the semiconductor pillars 23, as also shown in Figure 1B shown in. The first width W1 of the first trench 25 can be in the range from about 5 nm to about 25 nm or from about 5 nm to about 15 nm or from about 15 nm to about 25 nm (e.g., about 20 nm).

[0036] Continuing to refer to Figure 1A and 1B , in some embodiments, the semiconductor pillars 23 have a generally oval (e.g., egg-shaped, island-shaped) configuration. In some embodiments, the semiconductor pillars 23 can have a substantially constant width along their length. In other embodiments, the semiconductor pillars 23 have a tapered configuration (not shown) that is narrower near the top and wider near the bottom (e.g., wider near the substrate 22 of the semiconductor structure 21).

[0037] Next referring to Figure 2A and 2B , the insulating material 26 is formed by any suitable process (e.g., non-conformally deposited) to substantially fill the first trench 25 ( Figure 1B ) and fill portions of the microelectronic device structure 10 adjacent to the substrate 22 and the peripheral region P (e.g., on, above the substrate 22 and the peripheral region P). The insulating material 26 can include (but is not limited to) one or more of a dielectric oxide material (e.g., silicon dioxide) and a dielectric nitride material (e.g., silicon nitride). The first insulating structure 27 is formed by the insulating material 26 within the first trench 25 ( Figure 1B ) between the semiconductor pillars 23. The first insulating structure 27 can be alternating with the semiconductor pillars 23 in the Y direction. Additionally, the first insulating structure 27 can extend substantially parallel to the semiconductor pillars 23. In some embodiments, the upper surface of the first insulating structure 27 is substantially coplanar with the upper surface of the first mask 24 remaining adjacent to the semiconductor pillars 23 (e.g., on, above the semiconductor pillars 23). The coplanar upper surface of the first insulating structure 27 and the upper surface of the first mask 24 can be formed using a suitable planarization process, such as chemical mechanical planarization (CMP).

[0038] The second insulating structure 28 can be formed in the insulating material 26 of the first insulating structure 27, adjacent to the memory cell region M of the microelectronic device structure 10 (e.g., on, above the memory cell region M) (e.g., in the first insulating structure 27 between the semiconductor pillars 23), asFigure 2B shown in. According to some embodiments, the second insulating structure 28 is configured and arranged to separate and minimize (e.g., prevent) current leakage between adjacent ones of the semiconductor pillars 23 of the microelectronic device structure 10. The second insulating structure 28 may be formed of one or more of insulating materials, such as doped insulating materials. In some embodiments, the second insulating structure 28 is formed of phosphorous-doped polysilicon (DOPOS).

[0039] The third insulating structure 29 may be formed in the peripheral region P of the microelectronic device structure 10 adjacent to (e.g., on, over) the substrate 22. The third insulating structure 29 may be formed of the same insulating material as the insulating material 26 or a different insulating material from the insulating material 26. One or more second insulating structures 28 may also be formed in the third insulating structure 29, such as Figure 2B shown in. As before, the second insulating material 28 may be formed of a doped insulating material. In some embodiments, the second insulating structure 28 is formed in a third insulating structure 29 of phosphorous-doped polysilicon (DOPOS).

[0040] A second material removal process (e.g., wet etching, dry etching) is performed to remove the first mask 24 from the microelectronic device structure 10. The second material removal process may also remove a portion of the first insulating structure 27 to form an upper section 27' of the first insulating structure 27. The second material removal process may be performed in one or more operations. In a first operation, the first mask 24 is removed by a first wet etching process, thereby exposing the upper surface of the underlying semiconductor pillars 23. In a second operation, a second wet etching process is performed to remove the upper portion of the first insulating structure 27 to form its upper section 27', and to remove the upper portion of the third insulating structure 29 to form its upper section 29'. As can be seen from Figure 3A and 3B visible, the upper section 27' of the first insulating structure 27 exhibits a second width W2. In some embodiments, the first width W1 is greater than the second width W2, such that the width of the upper section 27' is reduced relative to the first width W1 of the first insulating structure 27 that has been formed (i.e., the first width W1 of the lower section of the first insulating structure 27). The second width W2 of the upper section 27' of the first insulating structure 27 may be in the range from about 5 nm to about 25 nm or from about 5 nm to about 15 nm or from about 10 nm to about 20 nm (e.g., about 10 nm). A shoulder region is formed between the sidewalls of the lower section and the upper section 27' of the first insulating structure 27.

[0041] Continuing to refer to Figure 3A and 3B, the first conductive structure 30 is formed adjacent to (e.g., on, above) the semiconductor pillar 23 and along portions of the sidewalls of the upper section 27' and the upper section 29'. The first conductive structure 30 can be used as a source / drain line. As can be seen from Figure 3B , the first conductive structure 30 can be adjacent to (e.g., on, above) the shoulder region of the first insulating structure 27 and extend between portions of the sidewalls of the upper section 27' of the first insulating structure 27 and portions of the sidewalls of the upper section 29' of the third insulating structure 29. The first conductive structure 30 can be formed of one or more conductive materials, such as titanium, titanium nitride, cobalt, molybdenum, or tungsten. In some embodiments, the first conductive structure 30 can be formed of titanium nitride and tungsten. In other embodiments, the first conductive structure can be formed of one or more of titanium, cobalt, and molybdenum.

[0042] The width of the upper section 27' of the first insulating structure 27 decreases from a first width W1 to a second width W2 (e.g., tapers), resulting in an increase in the lateral dimension of the first conductive structure 30 disposed between the upper sections 27' of the first insulating structure 27, which results in an increase (e.g., expansion) in the active region of the first conductive structure 30. The increase in the active region of the first conductive structure 30 can improve (e.g., increase) the current flowing through it, thereby resulting in an improvement (e.g., higher) in the operating efficiency of the microelectronic device 100 (see Figure 12A and 12B ) containing the microelectronic device structure 10. The upper section 27' extends from the shoulder region between the sidewall of the insulating structure 27 and the sidewall of the upper section 27' (e.g., extends vertically upward in the Z direction). In some embodiments, the upper section 27' extends between and above the upper surfaces 31 of the first conductive structure 30, as shown in Figure 3B . The upper section 27' exhibits a first height H1 that substantially corresponds to the thickness of the first mask 24 ( Figure 1B and 2B ). In some embodiments, the first height H1 can range from about 5 nm to about 25 nm or from about 10 nm to about 40 nm or from about 20 nm to about 30 nm (e.g., about 25 nm). The second height H2 is exhibited by the portion of the upper section 27' of the first insulating structure 27 that extends (e.g., extends vertically upward in the Z direction) beyond the upper surface 31 of the first conductive structure 30. In some embodiments, the second height H2 can range from about 2 nm to about 15 nm or from about 3 nm to about 10 nm or from about 4 nm to about 6 nm (e.g., about 5 nm). The second height H2 corresponds to the step height (e.g., protrusion) of a subsequently conformally formed material. Additionally, the step height (e.g., protrusion) of the subsequently conformally formed material resulting from the second height H2 at least partially defines the thickness of the neutral layer mask 38 ( Figure 5B ) for the directed self-assembly process, as described in more detail below.

[0043] Next, referring to Figure 4A and 4B , the second mask 32 is formed (e.g., conformally formed) adjacent to the upper section 27' of the first conductive structure 30, the first insulating structure 27, and the upper section 29' of the third insulating structure 29 (e.g., on, above the first conductive structure 30, the upper section 27' of the first insulating structure 27, and the upper section 29' of the third insulating structure 29). In some embodiments, the second mask 32 is formed of carbon (e.g., amorphous carbon). The third mask 34 can be formed (e.g., conformally formed) adjacent to the second mask 32 (e.g., on, above the second mask 32). The third mask 34 can be formed of any suitable mask material (e.g., silicon oxynitride, silicon dioxide, silicon nitride, spin-on glass). Since the second mask 32 and the third mask 34 are conformally formed, the configurations (e.g., protrusions) of the upper section 27' of the first insulating structure 27 and the upper section 29' of the third insulating structure 29 are translated into the second mask 32 and the third mask 34. Thus, the upper surface 35 of the third mask 34 adjacent to the upper section 27' of the first insulating structure 27 (e.g., on, above the upper section 27' of the first insulating structure 27) includes a configuration (e.g., protrusion, step height) corresponding to the height H2 between the upper surface 31 of the first conductive structure 30 and the uppermost surface of the upper section 27', as Figure 4B shown.

[0044] Referring to Figure 5A and 5B , a neutral layer mask 38 (e.g., a layered mask) is formed in the memory cell region M of the microelectronic device structure 10 adjacent to the upper surface 35 of the third mask 34 (e.g., on, above the upper surface 35 of the third mask 34). A portion of the neutral layer mask 38 adjacent to (e.g., overlying) the configuration (e.g., protrusion, step height) of the upper section 27' of the first insulating structure 27 translated into the third mask 34 can be removed such that the upper surface 35 of the third mask 34 and the upper surface of the neutral layer mask 38 are coplanar with each other. As can be seen from Figure 5B , the thickness of the neutral layer mask 38 is at least partially defined by a configuration (e.g., protrusion, step height) resulting from the translation of the second height H2 of the upper section 27' of the first insulating structure 27 into the third mask 34. A fourth mask 36 (e.g., a photoresist mask) is formed in the peripheral region P of the microelectronic device structure 10 adjacent to a portion of the third mask 34 (e.g., on, above the portion of the third mask 34) that lacks (e.g., does not have) the neutral layer mask 38 formed thereon. The fourth mask 36 protects the peripheral region P of the microelectronic device structure 10 during the directed self-assembly process, as described below.

[0045] A directed self-assembly (DSA) process can utilize any suitable self-assembling block copolymer material that phase separates and aligns during processing (e.g., annealing). During the DSA process, the polymer blocks of the block copolymer material phase separate and self-assemble into corresponding polymer blocks, thereby forming ordered domains of nanoscale dimensions. The domain size can range from about 5 nm to about 55 nm, such as from about 5 nm to about 50 nm or from about 10 nm to about 55 nm. By way of example only, if the block copolymer material is a diblock copolymer, the block copolymer material can self-assemble into A blocks and B blocks. However, other block copolymer materials can be used, such as triblock or multiblock copolymers. The film morphology (including the domain size and period (L o )(e.g., L from about 15 nm to about 50 nm o )) can be controlled by the chain length, molecular weight (MW), and volume fraction of the AB blocks of the block copolymer to produce, for example, a lamellar morphology. After self-assembly, one of the block copolymers can be selectively removed to form a pattern of a polymeric structure (e.g., polymeric structure 40) having a nanoscale third width W3, such as from about 2 nm to about 100 nm (e.g., from about 10 nm to about 100 nm, from about 5 nm to about 30 nm, from about 5 nm to about 15 nm, from about 2 nm to about 15 nm). The pattern is used as a mask to form nanoscale features (e.g., sub-lithographic features that are not easily or uniformly achievable via lithography) in the underlying material. The width of the nanoscale features can range from about 10 nm to about 100 nm, such as from about 10 nm to about 50 nm, from about 10 nm to about 40 nm, from about 10 nm to about 30 nm, or from about 10 nm to about 20 nm.

[0046] In some embodiments in accordance with the present disclosure, the DSA process utilizes a polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) block copolymer. The properties of the block copolymer (e.g., the PS-b-PMMA block copolymer) control the size, shape, and uniformity of the polymeric structures (e.g., polymeric structure 40) formed via the DSA process. The PS-b-PMMA block copolymer is applied (e.g., spin-coated) from a dilute solution of the block copolymer in an organic solvent adjacent to the neutral layer mask 38 (e.g., on, over the neutral layer mask 38). In some embodiments, a thin layer or film of the PS-b-PMMA block copolymer material (e.g., a thin layer or film having a thickness ranging from about 40 nm to about 100 nm) may be deposited over the neutral layer mask 38, after which the PS-b-PMMA block copolymer is exposed to an annealing operation. The annealing operation causes phase separation between the block copolymers (e.g., polystyrene and poly(methyl methacrylate)), thereby forming an array of polystyrene structures and poly(methyl methacrylate) structures that self-align (e.g., self-assemble) with a well-defined high-contrast pattern adjacent to the neutral layer mask 38 (e.g., on, over the neutral layer mask 38). In some embodiments, the neutral layer mask 38 may include a guiding pattern 39 formed thereon. Figure 5C Illustrate the neutral layer mask 38 (e.g., a layered mask) on which the guiding pattern 39 is formed. The guiding pattern 39 at least partially defines an initial position for the self-alignment (e.g., self-assembly) of the array of polystyrene structures and poly(methyl methacrylate) structures during the annealing operation. The density of the guiding pattern 39 is generally much smaller than the density of the polymeric structures (e.g., polymeric structure 40) formed adjacent to the neutral layer mask 38 (e.g., on, over the neutral layer mask 38). This is the result of pattern multiplication that occurs in the block copolymer (e.g., the PS-b-PMMA block copolymer) during the annealing operation.

[0047] In some embodiments, the block copolymer is exposed to a thermal annealing operation. The thermal annealing operation may be carried out at a temperature in the range of about 200 degrees Celsius (°C) to about 300 °C or about 220 °C to about 280 °C or about 240 °C to about 260 °C (e.g., about 260 °C). Additionally, the thermal annealing operation may be performed for a predetermined amount of time to obtain a desired contrast between the individual blocks of the block copolymer, such as about 1 minute to about 10 minutes or about 2 minutes to about 8 minutes or about 4 minutes to about 6 minutes (e.g., about 5 minutes). The fourth mask 36 protects the peripheral region P of the microelectronic device structure 10 during the DSA process (e.g., annealing). In some embodiments, the annealing operation is carried out in an inert gas (e.g., nitrogen) environment. In other embodiments, the block copolymer is exposed to a chemical annealing operation to effect phase separation and subsequent self-alignment (i.e., self-assembly) of the different components of the block copolymer.

[0048] After the annealing operation is completed, a third material removal process can be performed to selectively remove one of the copolymer structures (e.g., removing the poly(methyl methacrylate) structure) and the other of the copolymer structures (e.g., the polystyrene structure) remains in a well-defined array adjacent to the neutral layer mask 38 (e.g., on, above the neutral layer mask 38). As can be seen from Figure 5A and 5B , after the annealing operation and the third material removal process, the polymeric structure 40 (e.g., the polystyrene structure) remains in a well-defined array adjacent to the upper surface of the neutral layer mask 38 (e.g., on, above the upper surface of the neutral layer mask 38). Specifically, the well-defined array of polymeric structures 40 at least partially defines the self-assembled polymeric mask 40'. As used herein, a "well-defined array" of polymeric structures 40 means and includes an array of polymeric structures 40 having a pitch (i.e., the center-to-center distance from its immediate neighbor) ranging from about 15 nm to about 50 nm, wherein the individual polymeric structures 40 have an effective diameter (e.g., the third width W3) ranging from about 2 nm to about 100 nm (e.g., from about 5 nm to about 30 nm). As can be seen from Figure 5A and 5B , the self-assembled polymeric mask 40' forms a second trench 41 having a fourth width W4 between adjacent ones of the polymeric structures 40. The fourth width W4 between adjacent ones of the polymeric structures 40 can range from about 5 nm to about 45 nm (e.g., from about 5 to about 25 nm).

[0049] Next, referring to Figure 6A and 6B , the self-assembled polymeric mask 40' ( Figure 5A and 5B ) is used as a mask for forming a third trench 42 having a fifth width W5 that extends (e.g., vertically downward in the Z direction) and through both the third mask 34 and the second mask 32 to expose the upper surface 31 of the first conductive structure 30. The fifth width W5 of the third trench 42 can be substantially the same as the fourth width W4 between adjacent ones of the polymeric structures 40 of the self-assembled polymeric mask 40' ( Figure 5A and 5B ), and thus, the fifth width W5 can also range from about 5 nm to about 45 nm (e.g., from about 5 nm to about 25 nm). A fourth material removal process (e.g., atomic layer etching (ALE)) can be used to form the third trench 42 and remove the remaining portions of the self-assembled polymeric mask 40' ( Figure 5A and 5B ), the neutral layer mask 38 ( Figure 5A and 5B ) and the fourth mask 36 ( Figure 5A and 5B ) adjacent to the peripheral region P (e.g., on, above the peripheral region P). As can be seen fromFigure 6A and 6B As can be seen, the third trench 42 is defined by a portion of the third mask 34 and the second mask 32 that underlies the self-assembled polymeric mask 40' ( Figure 5A and 5B ) and the polymeric structure 40 and that underlies the fourth mask 36 and that remains after the fourth material removal process.

[0050] After the fourth material removal process is completed and the third trench 42 is formed, a fifth mask 43 can be formed in the third trench 42 and adjacent to the exposed portions of the third mask 34, the second mask 32, and the first conductive structure 30 (e.g., on, over the exposed portions of the third mask 34, the second mask 32, and the first conductive structure 30). The fifth mask 43 can be formed of any suitable sacrificial material (e.g., oxide, silicon oxynitride, silicon nitride). The upper surface of the fifth mask 43 can be planarized using a suitable planarization process (e.g., CMP) to be coplanar with the upper surface of the third mask 34.

[0051] Referring Figure 7A and 7B , a fifth material removal process can be used to remove the remaining portions of the third mask 34 ( Figure 6B ) and the second mask 32 ( Figure 6B ) to form a fourth trench 44 that extends between portions of the fifth mask 43 (e.g., vertically downward in the Z direction) to the upper surface 31 of the first conductive structure 30. The fourth trench 44 can have a sixth width W6 that is substantially equal to the third width W3 of the polymeric structure 40 ( Figure 5B ) used to pattern the fourth trench 44 (i.e., from about 2 nm to about 100 nm, from about 2 nm to about 15 nm). The upper portions of the upper section 27' ( Figure 6B ) of the first insulating structure 27 and the upper portion of the upper section 29' of the third insulating structure 29 can also be removed. The upper portion of the upper section 27' ( Figure 6B ) of the first insulating structure 27 can be further planarized to form a planarized upper section 27'' having an upper surface that is substantially coplanar with the upper surface 31 of the first conductive structure 30. The dimensions of the planarized upper section 27'' are at least partially defined by the second width W2 and the third height H3, and the third height H3 is less than the first height H1 ( Figure 6B ) of the upper section 27' ( Figure 6B ). In some embodiments, the third height H3 is substantially equal to the first height H1 minus the second height H2. In some embodiments, the upper section 29' of the third insulating structure 29 can also be planarized to be coplanar with the upper surface 31 of the first conductive structure 30.

[0052] Referring Figure 8A and 8B , the first conductive structure 30 is formed by removing through the fifth mask 43 ( Figure 7B) to separate the portions of the first conductive structure 30 exposed in the fourth trench 44 into discrete portions. Specifically, an opening 45 is formed through the first conductive structure 30 ([ Figure 7A and 7B ) exposed in the fourth trench 44 of the fifth mask 43([ Figure 7A and 7B ) and at least partially into the underlying semiconductor pillar 23, thereby separating the first conductive structure 30 and creating the first conductive member 30'. In some embodiments, the first conductive members 30' can operate independently of each other and be electrically isolated from each other. The opening 45 exhibits a seventh width W7 that at least partially defines the distance between adjacent ones of the first conductive members 30'. The seventh width W7 of the opening 45 between the first conductive members 30' is substantially equal to the sixth width W6 of the fourth trench 44([ Figure 7B ), and as before, the sixth width W6 is substantially equal to the third width W3 of the polymeric structure 40([ Figure 5B )(i.e., from about 2 nm to about 100 nm, from about 5 nm to about 15 nm). Thus, due to the self-assembled polymeric mask 40'([ Figure 5A and 5B ) formed by the DSA process, substantially uniform nanoscale openings 45 can be formed through portions of the conductive structure 30 to increase (e.g., maximize) the active area of the first conductive members 30' formed therefrom. Similar to the first conductive structure 30 itself, the increase in the active area of the first conductive members 30' can improve (e.g., increase) the current flowing therethrough, resulting in an improvement (e.g., higher) in the operating efficiency of the microelectronic device 100(see Figure 12A and 12B ) that includes the microelectronic device structure 10 according to an embodiment of the present disclosure. Additionally, the uniformity of the size of the openings 45 between the first conductive members 30' reduces (e.g., minimizes) short-circuit conditions between the first conductive members 30', such as may be generated by forming nanoscale openings (e.g., the opening 45) by other processes (e.g., lithography).

[0053] As Figure 8B shown, the intermediate structure 46 includes the first substrate 20, the semiconductor structure 21, the first insulating structure 27, the second insulating structure 28, the third insulating structure 29, and the first conductive member 30'.

[0054] Refer to Figure 9A and 9B, a fourth insulating structure 29” is formed adjacent to (e.g., on, above) the intermediate structure 46 and enters and fills the opening 45 between corresponding ones of the first conductive members 30'. The fourth insulating structure 29” can be formed of the same or different insulating materials as the third insulating structure 29. In some embodiments, the fourth insulating structure 29” is formed of an insulating material 26 (e.g., silicon dioxide, silicon nitride). The intermediate structure 46 on which the fourth insulating structure 29” is formed is inverted and rotated 180 degrees, and the fourth insulating structure 29” is bonded to the second substrate 47 by conventional techniques. The second substrate 47 can comprise any suitable material. In some embodiments, the second substrate 47 is formed of silicon. In at least some embodiments, the fourth insulating structure 29” can be formed adjacent to (e.g., on, above) the second substrate 47 and bonded to the second substrate 47, and thereafter, the intermediate structure 46 is inverted and bonded to the fourth insulating structure 29”, adjacent to the opposite surface of the second substrate 47 (e.g., on, above the opposite surface of the second substrate 47).

[0055] Reference Figure 10A and 10B , a sixth material removal process is completed to remove the first substrate 20 ( Figure 9A and 9B ) and at least a portion of the substrate 22 adjacent to the first insulating structure 27 and the third insulating structure 29 (e.g., on, above the first insulating structure 27 and the third insulating structure 29), thereby exposing the upper surface of the semiconductor pillar 23. As Figure 10B shown, substantially all of the substrate 22 is removed. A first doped region 48 (e.g., source / drain region) is formed in the upper portion of the semiconductor pillar 23, also as Figure 10B shown. The doped region 48 can be used as a channel during the use and operation of the microelectronic device 100 ( Figure 12A and 12B ). Doping can be achieved using suitable processes, such as injecting a suitable dopant (e.g., n-type dopant, p-type dopant) into the upper portion of the semiconductor pillar 23. In some embodiments, the first doped region 48 is individually n-type doped to a concentration in the range of, for example, from about 1x10 15 cm -3 to about 1x10 20 cm -3 . As Figure 10B shown, the first doped region 48 extends from the upper surface of the semiconductor pillar 23 and into the semiconductor pillar 23 (e.g., to a vertical depth of about 20 nm to about 30 nm from the upper surface of the semiconductor pillar 23). This process can be completed before forming a fifth insulating structure 29”' adjacent to the exposed portion of the third insulating structure 29 and the portion of the semiconductor pillar 23 (e.g., on, above the exposed portion of the third insulating structure 29 and the portion of the semiconductor pillar 23), as Figure 10BShown in. The upper surfaces of the fifth insulating structure 29''' and the first doped region 48 can be planarized by any suitable process (such as CMP). In some embodiments, the fifth insulating structure 29''' is formed adjacent to the exposed portion of the third insulating structure 29 and a portion of the semiconductor pillar 23 (such as on, above the exposed portion of the third insulating structure 29 and a portion of the semiconductor pillar 23) before forming the first doped region 48.

[0056] Reference Figure 11A and 11B , the fifth trench 49 is formed through the fifth insulating structure 29''', a portion of the adjacent first doped region 48, and into and at least partially through the semiconductor pillar 23. The second doped region 50 and the third doped region 52 (such as source / drain regions) are formed in the lower portion of the semiconductor pillar 23 by any suitable process (such as an accelerated voltage). Similar to the first doped region 48, the second doped region 50 and the third doped region 52 can be n-type doped or p-type doped to any suitable concentration. In some embodiments, the semiconductor pillar 23 includes a channel region 53 disposed between the first doped region 48 and the second and third doped regions 50, 52, respectively. The channel region 53 can be doped (such as an n-doped region, a p-doped region) or undoped (such as an undoped region).

[0057] Continuing to refer Figure 11A and 11B , a dielectric layer 54 (such as a gate dielectric layer) is formed at least on and along the sidewalls of the fifth trench 49 (such as deposited, conformally deposited). The dielectric layer 54 can be formed of an insulating material and includes an insulating material, such as an insulating oxide material. In other embodiments, the dielectric layer 54 is formed by oxidizing the exposed surface of the semiconductor pillar 23 along the sidewalls of the fifth trench 49. A second conductive structure 56 is formed in the fifth trench 49. In some embodiments, the second conductive structure 56 is substantially surrounded by the dielectric layer 54 within the fifth trench 49. The second conductive structure 56 can include one or more conductive materials, as described above (such as titanium nitride). In some embodiments, the second conductive structure 56 forms a word line (such as an access line).

[0058] In some embodiments, one or more third conductive structures 58 can be formed in the peripheral region P of the microelectronic device structure 10. The third conductive structure 58 facilitates the connection (such as an electrical connection) between the components in the memory cell region M and the components in the peripheral region P of the microelectronic device structure 10. Referring again to Figure 11A , the third conductive structure 58 is formed in the peripheral region P and is disposed substantially perpendicular to the second conductive structure 56. The third conductive structure 58 can include one or more conductive materials, again as described above (such as titanium nitride).

[0059] Then referring to Figure 12A and 12B, the fourth conductive structure 60 is formed adjacent to (e.g., on, over) a portion of the first doped region 48 of the semiconductor pillar 23 and is substantially perpendicular to the second conductive structure 56. As Figure 12A best seen in, the fourth conductive structure 60 extends from the memory cell region M into the peripheral region P to effect electrical connection between components therebetween. Similar to the second and third conductive structures 56, 58 respectively, the fourth conductive structure 60 is formed of and includes one or more conductive materials, such as titanium nitride. In some embodiments, the fourth conductive structure 60 may form bit lines (e.g., digit lines).

[0060] As can be seen from Figure 12B , the semiconductor pillar 23 forms part of a vertical access device 62 (e.g., a vertical transistor). The vertical access device 62 may include a channel region 53 of the semiconductor pillar 23, a source region including one of the first doped region 48 of the semiconductor pillar 23 or the corresponding second and third doped regions 50, 52, and a drain region including the other of the first doped region 48 of the semiconductor pillar 23 or the corresponding second and third doped regions 50, 52. In some embodiments, the first conductive member 30' is arranged to be in electrical communication with the corresponding one of the semiconductor pillars 23. More specifically, in some embodiments, the first conductive member 30' is arranged to be in electrical communication with one of the source region or the drain region of the corresponding one of the semiconductor pillars 23. Additionally, the vertical access device 62 may include a gate electrode including one of the second conductive structures 56 and the corresponding one of the dielectric liners 54, wherein the corresponding ones of the second conductive structure 56 and the dielectric liner 54 are arranged along the sidewall of the semiconductor pillar 23. The corresponding ones of the second conductive structure 56 and the dielectric liner 54 may be used as gate electrodes for a plurality of vertical access devices 62. The fourth conductive structure 60 is arranged to be in electrical communication with the other of the source region or the drain region of the corresponding one of the semiconductor pillars 23 and is opposite to the first conductive member 30'. Similar to the gate electrode, one of the fourth conductive structures 60 may be used as a source / drain line for a plurality of vertical access devices 62. The arrangement of the vertical access devices 62 in the memory cell region M and the third conductive structure 58 in the peripheral region P electrically connected by the fourth conductive structure 60 (e.g., bit lines) at least partially forms the microelectronic device 100 (e.g., a DRAM device). However, the microelectronic device 100 may be a different microelectronic device, such as a static random access memory (SRAM), a flash memory, an erasable programmable read only memory (EPROM), a magnetoresistive random access memory (MRAM), or a phase change memory.

[0061] The methods described herein can be used to form microelectronic devices with significantly fewer process steps by using directed self-assembly (DSA). Additionally, the methods described herein can be used to form microelectronic devices where the active regions of at least some of the conductive structures are increased due to a reduction in the width of the upper section of a first insulating structure between adjacent semiconductor pillars in which at least some of the conductive structures are disposed. Additionally, DSA can be used to form a polymeric mask, which is used, for example, to facilitate separating at least some of the conductive structures into discrete conductive members having substantially uniform nanoscale openings formed therebetween, thereby increasing the active regions of the conductive members. The increase in the active regions of the conductive members permits an improvement (e.g., an increase) in the current flowing therethrough, resulting in an improvement (e.g., a higher) in the operating efficiency of the microelectronic device employing the conductive members with increased active regions. Additionally, the uniformity of the nanoscale openings between the conductive members reduces (e.g., minimizes) shorting between the first conductive members, such as can be produced by forming nanoscale openings by other processes (e.g., lithography).

[0062] A method of forming a microelectronic device includes: forming a first trench extending into a semiconductor structure, the semiconductor structure including a substrate for forming semiconductor pillars between neighbors in the first trench; and forming a first insulating structure in the first trench, each first insulating structure having a second insulating structure therein. The method further includes forming a first conductive structure adjacent to a first end of the semiconductor pillar and a portion of the first insulating structure. The method further includes forming one or more masks adjacent to the first conductive structure and an exposed portion of the first insulating structure, the uppermost of the one or more masks including a neutral layer mask. The method includes: forming a block copolymer adjacent to the neutral layer mask; annealing the block copolymer to form a self-assembled array of a first polymeric structure and a second polymeric structure; and selectively removing the first polymeric structure or the second polymeric structure, the remaining one of the first polymeric structure or the second polymeric structure forming a polymeric mask. The method further includes: forming a second trench in the one or more masks using the polymeric mask; forming a sacrificial material in the second trench; and removing a remaining portion of the one or more masks to form a third trench through the sacrificial material and expose an upper surface of the first conductive structure. The method further includes: removing a portion of the first conductive structure exposed by the third trench to form first conductive members having an opening therebetween; forming a second conductive structure adjacent to at least one sidewall of at least one of the semiconductor pillars; and forming a third conductive structure adjacent to a second end of the semiconductor pillar.

[0063] Another method of forming a microelectronic device forms a semiconductor structure having a substrate and forms first trenches extending into the semiconductor structure in a first direction and disposed parallel to each other in a second direction, and semiconductor pillars are formed and inserted between adjacent ones of the first trenches in the second direction. The method further includes forming an insulating structure in the first trenches, wherein the insulating structure includes: a lower section having a first width defined at least in part in the second direction by a horizontal distance between sidewalls of adjacent semiconductor pillars; an upper section having a second width defined at least in part in the second direction by a horizontal distance between its sidewalls, the first width being greater than the second width; and a shoulder region formed between the sidewalls of the lower section of the insulating structure and the sidewalls of the upper section of the insulating structure. The method further includes: forming a first conductive structure adjacent to a first end of the semiconductor pillars and extending adjacent to the shoulder region of an adjacent insulating structure; and removing a portion of the first conductive structure to form a first conductive member having an opening therebetween. The method further includes: forming a second conductive structure adjacent to one of the sidewalls of at least one of the semiconductor pillars; and forming a third conductive structure adjacent to a second end of the semiconductor pillars.

[0064] A microelectronic device includes: an insulating structure disposed in a first direction and inserted between semiconductor pillars and alternating with the semiconductor pillars in a second direction, each insulating structure having: a lower section having a first width defined at least in part in the second direction by a distance between sidewalls of adjacent semiconductor pillars; an upper section having a second width defined at least in part in the second direction by a distance between its sidewalls, wherein the first width is greater than the second width; and a shoulder region between the sidewalls of the lower section of the insulating structure and the sidewalls of the upper section of the insulating structure. The microelectronic device further includes: one or more vertical access devices, the vertical access devices including: one of the semiconductor pillars having oppositely disposed source / drain regions and a channel region vertically therebetween; a gate electrode adjacent to and in electrical communication with one of the semiconductor pillars; and a first conductive member extending adjacent to one end of one of the semiconductor pillars and adjacent to the shoulder region of an adjacent insulating structure, the first conductive member being in electrical communication with one of the source / drain regions. The microelectronic device further includes a conductive structure in electrical communication with the other of the source / drain regions.

[0065] Figure 13Schematic circuit diagram of a memory cell array including one or more microelectronic devices (e.g., microelectronic device 100) according to an embodiment of the present disclosure. The memory cell array includes word lines W arranged in a matrix and perpendicularly to each other and intersecting at right angles L (e.g., the second conductive structure 56) and bit lines B L (e.g., the fourth conductive structure 60) near the intersection points of the memory cells MC connected. The memory cell MC includes a corresponding access transistor TR (e.g., the vertical access device 62) and a storage capacitor SC.

[0066] The gate electrode (e.g., the second conductive structure 56) of the access transistor TR (e.g., the vertical access device 62) can be used as the word line W of the memory device (e.g., DRAM device) L , and the word line W L (e.g., the second conductive structure 56) can be used as a control line for controlling the selection of the corresponding memory cell MC. One of the source / drain regions of the access transistor TR (e.g., the vertical access device 62) is connected to the bit line B L (e.g., the fourth conductive structure 60) and the other is connected to the storage capacitor SC. Charge accumulates in the storage capacitor SC to store data.

[0067] When data is written into the memory cell MC, a potential for turning on the access transistor TR (e.g., the vertical access device 62) is applied to the word line W L (e.g., the second conductive structure 56), and a low potential or a high potential corresponding to the written data "0" or "1" is applied to the bit line B L (e.g., the fourth conductive structure 60). When data is read from the memory cell MC, a potential for turning on the access transistor TR (e.g., the vertical access device 62) is applied to the word line W L (e.g., the second conductive structure 56). Therefore, the potential drawn from the storage capacitor SC to the bit line B L (e.g., the fourth conductive structure 60) is sensed by a sense amplifier (not shown) connected to the bit line B L (e.g., the fourth conductive structure 60), thereby performing data determination.

[0068] Through the above actions, a microelectronic device (e.g., microelectronic device 100) including an access transistor TR (e.g., vertical access device 62) can be formed. The access transistor TR includes a first doped portion (e.g., first doped region 48), a second semiconductor structure (e.g., semiconductor pillar 23), a second doped portion (e.g., second doped region 50), and a third doped portion (e.g., third doped region 52) that are arranged adjacent to each other. The access transistor TR (e.g., vertical access device 62) can be formed as a metal-oxide-semiconductor field-effect transistor (MOSFET) such that a channel region (e.g., channel region 53) formed in the second semiconductor structure (e.g., semiconductor pillar 23) extends in the vertical direction. An access transistor TR (e.g., vertical access device 62) in which the channel region (e.g., channel region 53) is formed in the vertical direction and the source / drain regions are arranged at the upper and lower ends of the channel region (e.g., channel region 53) in the vertical direction is a vertical transistor. Thus, a structure can be formed in which the access transistor TR (e.g., vertical access device 62) and the storage capacitor SC are arranged in the vertical stacking direction. By arranging the access transistor TR (e.g., vertical access device 62) and the storage capacitor SC in this way, the area occupied by the memory cell MC in the X-Y plane can be reduced, enabling a highly integrated microelectronic device (e.g., microelectronic device 100) to be realized.

[0069] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0070] Example 1. A method of forming a microelectronic device includes: forming a first trench extending into a semiconductor structure, the semiconductor structure including a substrate for forming semiconductor pillars between neighbors in the first trench; forming a first insulating structure in the first trench, each first insulating structure having a second insulating structure therein; forming a first conductive structure adjacent to a first end of the semiconductor pillar and a portion of the first insulating structure; forming one or more masks adjacent to the first conductive structure and an exposed portion of the first insulating structure, an uppermost one of the one or more masks including a neutral layer mask; forming a block copolymer adjacent to the neutral layer mask; annealing the block copolymer to form a self-assembled array of a first polymeric structure and a second polymeric structure; selectively removing the first polymeric structure or the second polymeric structure, a remaining one of the first polymeric structure or the second polymeric structure forming a polymeric mask; forming a second trench in the one or more masks using the polymeric mask; forming a sacrificial material in the second trench; removing a remaining portion of the one or more masks to form a third trench through the sacrificial material and expose an upper surface of the first conductive structure; removing a portion of the first conductive structure exposed by the third trench to form a first conductive member having an opening therebetween; forming a second conductive structure adjacent to at least one sidewall of at least one of the semiconductor pillars; and forming a third conductive structure adjacent to a second end of the semiconductor pillar.

[0071] Example 2. The method according to Example 1, wherein forming the first insulating structure each having a second insulating structure therein in the first trench includes forming the second insulating structure including phosphorous-doped polysilicon.

[0072] Example 3. The method according to Example 1 or Example 2, wherein forming the block copolymer adjacent to the neutral layer mask includes depositing a polystyrene-block-poly(methyl methacrylate) block copolymer adjacent to the neutral layer mask.

[0073] Example 4. The method according to any one of Examples 1 to 3, wherein annealing the block copolymer to form the self-assembled array of the first polymeric structure and the second polymeric structure includes annealing the block copolymer at a temperature from about 240 degrees Celsius to about 280 degrees Celsius.

[0074] Example 5. The method according to any one of Examples 1 to 4, wherein forming the first insulating structure in the first trench includes forming the first insulating structure each including a lower section having a first width and an upper section having a second width, the first width being greater than the second width.

[0075] Example 6. The method according to any one of Examples 1 to 5, wherein forming the first insulating structure in the first trench includes forming the first insulating structure each including a lower section having the first width ranging from about 10 nm to about 40 nm and an upper section having the second width ranging from about 5 nm to about 20 nm.

[0076] Example 7. The method according to any one of Examples 1 to 6, wherein selectively removing the first polymer structure or the second polymer structure includes selectively removing the first polymer structure or the second polymer structure, wherein the remaining first polymer structure or the remaining second polymer structure has a diameter ranging from about 2 nm to about 100 nm.

[0077] Example 8. The method according to any one of Examples 1 to 7, wherein selectively removing the first polymer structure or the second polymer structure, and the remaining one of the first polymer structure or the second polymer structure forms a polymer mask includes: selectively removing the first polymer structure or the second polymer structure, and the remaining one of the first polymer structure or the second polymer structure forms a polymer mask having a fourth trench between the remaining ones of the first polymer structure or the second polymer structure, the fourth trench having a third width ranging from about 5 nm to about 45 nm.

[0078] Example 9. The method according to any one of Examples 1 to 8, wherein removing a portion of the first conductive structure exposed by the third trench to form a first conductive member having an opening therebetween includes removing a portion of the first conductive structure exposed by the third trench to form the first conductive member having an opening for separating the first conductive members from each other, the opening having a fourth width ranging from about 2 nm to about 100 nm.

[0079] Example 10. A method of forming a microelectronic device includes: forming a semiconductor structure having a substrate; forming first trenches extending into the semiconductor structure in a first direction and disposed parallel to each other in a second direction, semiconductor pillars being formed and inserted between adjacent ones of the first trenches in the second direction; forming an insulating structure in the first trenches, the insulating structure including: a lower section having a first width defined at least in part in the second direction by a horizontal distance between sidewalls of adjacent semiconductor pillars; an upper section having a second width defined at least in part in the second direction by a horizontal distance between its sidewalls, the first width being greater than the second width; and a shoulder region formed between the sidewalls of the lower section and the sidewalls of the upper section of the insulating structure; forming a first conductive structure adjacent to a first end of the semiconductor pillars and extending adjacent to the shoulder region of adjacent insulating structures; removing a portion of the first conductive structure to form a first conductive member having an opening therebetween; forming a second conductive structure adjacent to one of the sidewalls of at least one of the semiconductor pillars; and forming a third conductive structure adjacent to a second end of the semiconductor pillars.

[0080] Example 11. The method according to Example 10, wherein forming the semiconductor structure includes forming the semiconductor structure including silicon.

[0081] Example 12. The method according to Example 10 or Example 11, wherein forming the insulating structure in the first trenches includes forming an insulating structure having a lower section in the first trenches, the lower section having a first width in a range from about 10 nanometers to about 40 nanometers.

[0082] Example 13. The method according to any one of Examples 10 to 12, wherein forming the insulating structure in the first trenches includes forming an insulating structure having an upper section in the first trenches, the upper section having a second width in a range from about 5 nanometers to about 20 nanometers.

[0083] Example 14. The method according to Example 13, wherein forming the first conductive structure adjacent to a first end of the semiconductor pillars and extending adjacent to the shoulder region of adjacent insulating structures includes forming a first conductive structure adjacent to a first end of the semiconductor pillars and extending adjacent to a sidewall of the upper section of adjacent insulating structures.

[0084] Example 15. The method according to any one of Examples 10 to 13, wherein forming the first conductive structure adjacent to a first end of the semiconductor pillars and extending adjacent to the shoulder region of adjacent insulating structures includes forming a first conductive structure adjacent to a first end of the semiconductor pillars and extending adjacent to a sidewall of the upper section of adjacent insulating structures.

[0085] Example 16. The method according to any one of Examples 10 to 13 and 15, wherein forming a second conductive structure adjacent to one of the sidewalls of at least one of the semiconductor pillars includes forming a second trench at least partially through the semiconductor pillar and forming the second conductive structure in the second trench.

[0086] Example 17. The method according to any one of Examples 10 to 13, 15 and 16, wherein forming the second conductive structure in the second trench includes forming a dielectric liner in each of the second trenches and forming the second conductive structure on the dielectric liner in the second trenches.

[0087] Example 18. A microelectronic device includes: an insulating structure disposed in a first direction and inserted between semiconductor pillars and alternating with the semiconductor pillars in a second direction, each insulating structure including: a lower section having a first width defined at least in part in the second direction by a distance between sidewalls of adjacent semiconductor pillars; an upper section having a second width defined at least in part in the second direction by a distance between its sidewalls, wherein the first width is greater than the second width; and a shoulder region between the sidewalls of the lower section and the sidewalls of the upper section of the insulating structure; and one or more vertical access devices, the vertical access devices including: one of the semiconductor pillars having oppositely disposed source / drain regions and a channel region vertically between the source / drain regions; a gate electrode adjacent to and in electrical communication with one of the semiconductor pillars; a first conductive member extending adjacent to one end of one of the semiconductor pillars and adjacent to the shoulder region of an adjacent insulating structure, the first conductive member being in electrical communication with one of the source / drain regions; and a conductive structure in electrical communication with the other of the source / drain regions.

[0088] Example 19. The microelectronic device according to Example 18, wherein the first conductive member includes an enlarged active region defined at least in part by a portion of the first conductive member extending adjacent to the shoulder region of the adjacent insulating structure and the sidewalls of its upper section.

[0089] Example 20. The microelectronic device according to Example 18 or Example 19, wherein the microelectronic device includes a dynamic random access memory (DRAM) device.

[0090] The embodiments of the present disclosure described above and illustrated in the accompanying drawings do not limit the scope of the present disclosure, which is covered by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of the present disclosure. In fact, those skilled in the art will understand from the description various modifications of the present disclosure other than those shown and described herein, such as alternative useful combinations of the described elements. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a microelectronic device, comprising: forming a first trench extending into a semiconductor structure including a substrate for forming semiconductor pillars between neighbors in the first trench; forming first insulating structures in the first trenches, each first insulating structure having a second insulating structure therein; forming a first conductive structure adjacent to a first end of the semiconductor pillar and a portion of the first insulating structure; forming one or more masks adjacent to the first conductive structure and the exposed portion of the first insulating structure, an uppermost of the one or more masks comprising a neutral layer mask; forming a block copolymer adjacent to the neutral layer mask; annealing the block copolymer to form a self-assembled array of first and second polymeric structures; selectively removing the first polymerized structure or the second polymerized structure, the remainder of the first polymerized structure or the second polymerized structure forming a polymerized mask; forming a second trench in the one or more masks using the polymeric mask; forming a sacrificial material in the second trench; removing remaining portions of the one or more masks to form a third trench through the sacrificial material and expose an upper surface of the first conductive structure; removing portions of the first conductive structure exposed by the third trench to form a first conductive member having an opening therebetween; forming a second conductive structure adjacent to at least one sidewall of at least one of the semiconductor pillars; and A third conductive structure is formed adjacent to the second end of the semiconductor pillar. 2 . The method of claim 1 , wherein forming the first insulating structures each having a second insulating structure therein in the first trench comprises forming the second insulating structure including phosphorus-doped polysilicon. 3 . The method of claim 1 , wherein forming the block copolymer adjacent to the neutral layer mask comprises depositing a polystyrene-block-poly(methyl methacrylate) block copolymer adjacent to the neutral layer mask.

4. The method of claim 1, wherein annealing the block copolymer to form the self-assembled array of first and second polymeric structures comprises annealing the block copolymer at a temperature of from about 240 degrees Celsius to about 280 degrees Celsius. 5 . The method of claim 1 , wherein forming first insulating structures in the first trenches comprises forming the first insulating structures each including a lower section having a first width and an upper section having a second width, the first width being greater than the second width.

6. The method of any one of claims 1 to 5, wherein forming a first insulating structure in the first trench comprises forming the first insulating structure each including the lower segment having the first width from about 10 nm to about 40 nm and the upper segment having the second width from about 5 nm to about 20 nm.

7. The method of any one of claims 1 to 5, wherein selectively removing the first polymeric structure or the second polymeric structure comprises selectively removing the first polymeric structure or the second polymeric structure, wherein the remaining first polymeric structure or the remaining second polymeric structure has a diameter from about 2 nm to about 100 nm.

8. The method of any one of claims 1 to 5, wherein selectively removing the first polymeric structure or the second polymeric structure or the remaining of the first polymeric structure or the second polymeric structure to form a polymeric mask comprises: Selectively removing the first or second polymeric structures or the remainder of the first or second polymeric structures forms a polymeric mask having fourth trenches between the remainder of the first or second polymeric structures, the fourth trenches having a third width from about 5 nm to about 45 nm.

9. The method of any one of claims 1 to 5, wherein removing portions of the first conductive structure exposed by the third trench to form first conductive members having openings therebetween comprises removing portions of the first conductive structure exposed by the third trench to form first conductive members having openings separating first conductive members from each other, the openings having a fourth width from about 2 nm to about 100 nm.

10. A method of forming a microelectronic device, comprising: forming a semiconductor structure having a substrate; forming first trenches extending into the semiconductor structure in a first direction and disposed parallel to each other in a second direction, semiconductor pillars being formed and inserted between adjacent ones in the first trenches in the second direction; An insulating structure is formed in the first trench, the insulating structure comprising: a lower section exhibiting a first width defined at least in part by a horizontal distance between sidewalls of adjacent semiconductor pillars in the second direction; an upper section exhibiting a second width defined at least in part by a horizontal distance between its sidewalls in the second direction, the first width being greater than the second width; and a shoulder region formed between the sidewall of the lower section of the insulating structure and the sidewall of the upper section of the insulating structure; forming a first conductive structure extending adjacent to the first end of the semiconductor pillar and adjacent to the shoulder region of an adjacent insulating structure; removing portions of the first conductive structure to form a first conductive member having an opening therebetween; forming a second conductive structure adjacent to one of the sidewalls of at least one of the semiconductor pillars; and A third conductive structure is formed adjacent to the second end of the semiconductor pillar. The method of claim 10 , wherein forming the semiconductor structure comprises forming the semiconductor structure to include silicon. 12 . The method of claim 10 , wherein forming an insulating structure in the first trench comprises forming an insulating structure having a lower segment in the first trench, the lower segment having a first width in a range from about 10 nanometers to about 40 nanometers.

13. The method of any one of claims 10 to 12, wherein forming an insulating structure in the first trench comprises forming an insulating structure having an upper section in the first trench, the upper section having a second width in a range from about 5 nanometers to about 20 nanometers.

14. The method of claim 13, wherein forming a first conductive structure extending adjacent to the first end of the semiconductor pillar and adjacent to the shoulder region of an adjacent insulating structure comprises forming a first conductive structure extending adjacent to the first end of the semiconductor pillar and adjacent to a sidewall of the upper section of an adjacent insulating structure.

15. The method of claim 10, wherein forming a first conductive structure extending adjacent to the first end of the semiconductor pillar and adjacent to the shoulder region of an adjacent insulating structure comprises forming a first conductive structure extending adjacent to the first end of the semiconductor pillar and adjacent to a sidewall of the upper section of an adjacent insulating structure.

16. The method of any one of claims 10 to 12, wherein forming a second conductive structure adjacent to one of the sidewalls of at least one of the semiconductor pillars comprises forming a second trench at least partially through the semiconductor pillar and forming the second conductive structure in the second trench. 17 . The method of claim 16 , wherein forming the second conductive structure in the second trenches comprises forming a dielectric liner in each of the second trenches and forming the second conductive structure on the dielectric liner in the second trenches.

18. A microelectronic device comprising: Insulation structures are disposed in the first direction and inserted between the semiconductor pillars and alternate with the semiconductor pillars in the second direction, each insulation structure comprising: a lower section exhibiting a first width defined at least in part by a distance between sidewalls of adjacent semiconductor pillars in the second direction; an upper section exhibiting a second width defined at least in part by a distance between its sidewalls in the second direction, wherein the first width is greater than the second width; and a shoulder region between the sidewall of the lower section of the insulating structure and the sidewall of the upper section of the insulating structure; and One or more vertical access devices, the vertical access devices comprising: one of the semiconductor pillars, the one of the semiconductor pillars having oppositely disposed source / drain regions and a channel region vertically between the source / drain regions; a gate electrode adjacent to and in electrical communication with said one of said semiconductor pillars; a first conductive member extending adjacent one end of said one of said semiconductor pillars and adjacent to said shoulder region of an adjacent insulating structure, said first conductive member being in electrical communication with one of said source / drain regions; and A conductive structure is in electrical communication with the other of the source / drain regions.

19. The microelectronic device of claim 18, wherein the first conductive member includes an enlarged active area defined at least in part by a portion of the first conductive member extending adjacent to the shoulder region of the adjacent insulating structure and the sidewall of the upper segment thereof.

20. The microelectronic device of claim 18, wherein the microelectronic device comprises a dynamic random access memory (DRAM) device.

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