Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device and a method for manufacturing the same, comprising: providing a substrate having multiple gate structures formed thereon; forming a pre-processing trench in the substrate between two adjacent gate structures; forming an expansion layer on the inner wall of the pre-processing trench; etching away the portion of the expansion layer located at the bottom of the pre-processing trench, leaving the remaining expansion layer covering the sidewalls of the pre-processing trench; etching the substrate below the pre-processing trench to form an initial trench based on the pre-processing trench; etching the portion of the initial trench not covered by the expansion layer to form a sigma trench; removing the remaining expansion layer; and forming an epitaxial layer in the sigma trench, the epitaxial layer comprising a buffer layer, an intermediate layer, and a cap layer stacked sequentially from bottom to top, with the buffer layer completely covering the inner wall of the sigma trench. The present application reduces or prevents elements in the intermediate layer from diffusing into the substrate, thereby reducing or even preventing the short channel effect of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In a general epitaxial process (EPI), the epitaxial layer usually includes a buffer layer, an intermediate layer and a cap layer, wherein the buffer layer is formed on the inner wall of the trench in the substrate, the intermediate layer is formed on the buffer layer and fills the trench, and the cap layer is formed on the intermediate layer and is higher than the substrate on both sides of the trench.

[0003] However, during the actual epitaxial growth process, the buffer layer included in the epitaxial layer at the top corner of the epitaxial trench may not completely cover the inner walls of the trench. In other words, the buffer layer does not completely enclose the intermediate layer, and thus fails to isolate the intermediate layer from the substrate. This can cause elements in the intermediate layer (such as boron) to diffuse into the channel region within the substrate, and in severe cases, even cause short channel effects (SCE) in the semiconductor device. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof to reduce or avoid the risk of diffusion of the epitaxial layer and reduce or avoid the short channel effect of the semiconductor device.

[0005] The present application provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate, on which a plurality of gate structures spaced apart from each other are formed, and forming a pre-processed trench in the substrate between two adjacent gate structures;

[0007] forming an expansion layer on the inner wall of the pretreatment groove;

[0008] Etching away a portion of the extension layer located at the bottom of the preprocessing trench so that the remaining extension layer covers the sidewalls of the preprocessing trench, and etching a portion of the substrate below the preprocessing trench to form an initial trench based on the preprocessing trench;

[0009] etching a portion of the initial trench not covered by the extension layer to form a sigma trench;

[0010] removing the remaining expansion layer;

[0011] An epitaxial layer is formed in the sigma trench, wherein the epitaxial layer includes a buffer layer, an intermediate layer and a cap layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

[0012] In one embodiment, the buffer layer includes a first buffer layer close to the substrate and a second buffer layer close to the intermediate layer.

[0013] In one embodiment, the material of the first buffer layer includes germanium silicon material, the materials of the second buffer layer and the intermediate layer include germanium silicon boron material, the germanium element content in the intermediate layer is higher than the germanium element content in the second buffer layer, and the material of the cap layer includes boron silicide.

[0014] In one embodiment, a first wet etching process is used to etch the portion of the initial trench not covered by the extension layer to form the sigma trench, and the etchant used in the first wet etching process includes THMA.

[0015] In one embodiment, a second wet etching process is used to remove the remaining extension layer, and the etchant used in the second wet etching process includes DHF.

[0016] In one embodiment, the extension layer is formed on the inner wall of the pre-processed trench by using an ISSG growth process.

[0017] In one embodiment, the depth of the pre-treatment groove ranges from 5Å to 20Å.

[0018] In one embodiment, the material of the extension layer includes silicon oxide.

[0019] Correspondingly, the present application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.

[0020] In one embodiment, the semiconductor device includes:

[0021] a substrate having a sigma trench provided therein;

[0022] a plurality of mutually spaced gate structures, located on the substrate, with two adjacent gate structures located on the substrate on both sides of the sigma trench;

[0023] An epitaxial layer is located in the sigma trench, and the epitaxial layer includes a buffer layer, an intermediate layer and a cap layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

[0024] The unexpected effects of the present application are: by forming a pretreatment trench and an expansion layer covering the side walls of the pretreatment trench, and forming an initial trench based on the pretreatment trench, the expansion layer is used to protect the side walls covered by it during the subsequent etching process; by forming a sigma trench based on the initial trench and removing the expansion layer, the width of the sigma trench close to the gate structure is increased, providing process space for the subsequently formed epitaxial layer, which is beneficial to improving the thickness and uniformity of the buffer layer included in the epitaxial layer; by making the buffer layer completely cover the inner wall of the sigma trench, the diffusion of elements in the intermediate layer of the epitaxial layer into the substrate is reduced or avoided, thereby reducing or even avoiding the short channel effect of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 It is a structural schematic diagram of a semiconductor device in related technology.

[0027] Figure 2 for Figure 1 Schematic diagram of the electron microscope structure corresponding to the semiconductor device shown.

[0028] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present application.

[0029] Figure 4 This is a structural schematic diagram corresponding to the step of providing a substrate in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0030] Figure 5 This is a structural schematic diagram corresponding to the step of forming a pre-processed trench in a substrate between two adjacent gate structures in a method for manufacturing a semiconductor device provided in one embodiment of the present application.

[0031] Figure 6 This is a structural schematic diagram corresponding to the step of forming an expansion layer on the inner wall of a pre-processed trench in a method for manufacturing a semiconductor device according to one embodiment of the present application.

[0032] Figure 7 A structural schematic diagram corresponding to the step of etching the expansion layer and pre-treating the substrate below the trench to form an initial trench in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0033] Figure 8 A structural schematic diagram corresponding to the step of etching the portion of the initial trench not covered by the expansion layer and forming a sigma trench in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0034] Figure 9 This is a structural schematic diagram corresponding to the step of removing the expansion layer in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0035] Figure 10 This is a structural schematic diagram corresponding to the step of forming an epitaxial layer in a sigma trench in a method for manufacturing a semiconductor device according to one embodiment of the present application.

[0036] Figure 11 for Figure 10 The enlarged structural diagram of the portion of the epitaxial layer located in the top corner area of ​​the sigma trench is shown.

[0037] Among them, the figure marks include: 100-substrate; 101-epitaxial trench; 110-gate structure; 120-Ge-SiB epitaxial layer; 200-substrate; 201-pretreatment trench; 202-initial trench; 203-sigma trench; 210-gate structure; 211-gate dielectric layer; 212-gate; 213-gate sidewall; 220-extension layer; 230-epitaxial layer; 231-buffer layer; 231a-first buffer layer; 231b-second buffer layer; 232-intermediate layer; 233-cap layer; A-top corner area. DETAILED DESCRIPTION

[0038] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0040] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0041] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0042] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Figure 1 Schematic diagram of the structure of an epitaxial layer formed by an epitaxial process in a semiconductor device. Figure 1 A plurality of gate structures 110 spaced apart from each other are formed on a substrate 100 of the semiconductor device. An epitaxial trench 101 is provided in the substrate 100 between two adjacent gate structures 110 , and a germanium silicon boron epitaxial layer 120 is formed in the epitaxial trench 101 .

[0044] In a typical semiconductor device, substrate 100 is typically a silicon (Si) substrate, and gate structure 110 typically includes a gate dielectric layer (not labeled in the figure) formed on substrate 100, a gate electrode (not labeled in the figure) formed on the gate dielectric layer, and sidewall spacers (not labeled in the figure) covering the sidewalls of the gate electrode. Optionally, the gate electrode may be a metal gate or a polysilicon gate, the gate dielectric layer may be made of silicon oxide, and the sidewall spacers may be a stacked structure composed of a silicon oxide layer, a silicon nitride layer, or a combination thereof. For example, the sidewall spacers may be an ONO stacked structure composed of a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers.

[0045] Continue reading Figure 1 The epitaxial trench 101 is a Sigma trench, and the germanium silicon boron epitaxial layer 120 includes an L1 layer, an L2 layer, and an L3 layer stacked sequentially along the surface direction away from the substrate 100. Optionally, the L1 layer includes an L1-1 layer close to the substrate 100 and an L1-2 layer close to the L2 layer. The L1-1 layer is a silicon germanium material layer (SiGe layer), that is, the L1-1 layer does not contain boron; the L1-2 layer and the L2 layer are both germanium silicon boron material layers (SiGeB layers), and the germanium (Ge) content in the L2 layer is higher than the germanium content in the L1-2 layer to increase the stress in the L2 layer; and the L3 layer is a boron silicide layer (SiB layer).

[0046] However, see Figure 1 and Figure 2 In the actual epitaxial process, the top corner of the epitaxial trench 101 (ie Figure 1 and Figure 2 In the epitaxial layer 120 formed by the substrate 100 (the portion encircled by the dotted circle in the figure), the L1 layer (i.e., the stacked structure composed of the L1-1 layer and the L1-2 layer) may not completely cover the substrate 100, so that the L1 layer does not enclose the L2 layer. As a result, the boron element in the L2 layer is easily diffused into the channel (not shown in the figure) in the substrate 100, thereby causing short-channel effects (SCE) in the semiconductor device.

[0047] In order to solve the above problems, the present application provides a semiconductor device and a manufacturing method thereof, so as to reduce or avoid the risk of diffusion of the epitaxial layer, and at the same time reduce or avoid the short channel effect of the semiconductor device.

[0048] Figure 3 This is a flow chart of a method for manufacturing a semiconductor device according to one embodiment of the present application. Figure 3 One embodiment of the present application provides a method for manufacturing a semiconductor device including the following steps S01 to S06.

[0049] Step S01: providing a substrate, on which a plurality of gate structures spaced apart from each other are formed, and forming a pre-processed trench in the substrate between two adjacent gate structures.

[0050] Step S02: forming an expansion layer on the inner wall of the pre-processing groove.

[0051] Step S03: etching away the portion of the extension layer located at the bottom of the preprocessing trench so that the remaining extension layer covers the sidewalls of the preprocessing trench, and etching a portion of the substrate below the preprocessing trench to form an initial trench based on the preprocessing trench.

[0052] It should be noted that the formation of the pretreatment trench in step S01 and the expansion layer in step S02, and the formation of the initial trench based on the pretreatment trench in step S03, are to enable the remaining expansion layer to cover the side wall of the pretreatment trench (it can also be understood that the remaining expansion layer covers the part of the side wall of the initial trench close to the gate structure), providing a process basis for subsequent process steps.

[0053] Step S04: etching the portion of the initial trench not covered by the extension layer to form a sigma trench.

[0054] Step S05: removing the remaining extended layers.

[0055] It should be noted that after removing the remaining extension layer, the width of the sigma trench close to the gate structure increases, providing process space for the subsequent formation of the epitaxial layer.

[0056] Step S06: forming an epitaxial layer in the sigma trench, wherein the epitaxial layer includes a buffer layer, an intermediate layer, and a cap layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

[0057] In the manufacturing method of the semiconductor device as described above, a pretreatment trench and an expansion layer covering the sidewalls of the pretreatment trench are formed, and an initial trench is formed based on the pretreatment trench, so that the expansion layer can be used to protect the sidewalls covered by it during the subsequent etching process; a sigma trench is formed based on the initial trench, and the expansion layer is removed, thereby increasing the width of the sigma trench on the side close to the gate structure, providing process space for the subsequently formed epitaxial layer, which is beneficial to improving the thickness and uniformity of the buffer layer included in the epitaxial layer; by making the buffer layer completely cover the inner wall of the sigma trench, the diffusion of elements in the intermediate layer in the epitaxial layer into the substrate is reduced or avoided, thereby reducing or even avoiding the short channel effect of the semiconductor device.

[0058] Figures 4 to 11 This is a schematic structural diagram corresponding to some process steps in the method for manufacturing a semiconductor device provided in one embodiment of the present application. Figure 4 and Figure 11 The specific details of steps S01 to S06 in the method for manufacturing a semiconductor device provided in an embodiment of the present application are described in detail.

[0059] First, see Figure 4 and Figure 5 , step S01 is performed to provide a substrate 200, on which a plurality of gate structures 210 spaced apart from each other are formed, and a pre-processed trench 201 is formed in the substrate 200 between two adjacent gate structures 210. Optionally, the material of the substrate 200 includes silicon (Si).

[0060] Continue reading Figure 4 In one embodiment, the gate structure 210 includes a gate dielectric layer 211, a gate 212, and a gate spacer 213, wherein the gate dielectric layer 211 is formed on the substrate 200, the gate 212 is formed on the gate dielectric layer 211, and the gate spacer 213 covers the sidewalls of the gate 212 and the sidewalls of the gate dielectric layer 211. Exemplarily, the gate 212 is a metal gate or a polysilicon gate, the material of the gate dielectric layer 211 includes silicon oxide, and the gate spacer 213 can be a stacked structure composed of a silicon oxide layer, a silicon nitride layer, or a combination thereof. For example, the gate spacer 213 can be an ONO stacked structure composed of a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers.

[0061] See Figure 5 In one embodiment, a dry etching process is used to etch the substrate 200 between two adjacent gate structures 210 to form a pre-processed trench 201. Optionally, the depth of the pre-processed trench 201 ranges from 5Å to 20Å.

[0062] It should be emphasized that the depth of the pretreatment groove 201 is relatively shallow compared to the overall thickness of the substrate 200, and the depth of the pretreatment groove 201 is usually set within a thickness range of several angstroms to tens of angstroms to ensure that the formation of the pretreatment groove 201 will not have a significant negative impact on subsequent process steps, thereby reducing or avoiding affecting the yield of semiconductor devices.

[0063] Next, see Figure 6 , step S02 is performed to form an expansion layer 220 on the inner wall of the pre-processing trench 201. In one embodiment, an in-situ steam generation process (ISSG) is used to form the expansion layer 220 on the inner wall of the pre-processing trench 201. Optionally, the material of the expansion layer 220 includes silicon oxide.

[0064] In other embodiments of the present application, other commonly used process methods may be used to form an expansion layer according to actual process requirements. For example, a thermal oxidation growth process may be used to form an expansion layer on the inner wall of a pre-treated groove, or other commonly used process methods may be used to form an expansion layer. In addition, this application will not elaborate on the common knowledge known to those skilled in the art.

[0065] Then, see Figure 7 , execute step S03, etch and remove the portion of the expansion layer 220 located at the bottom of the preprocessing trench 201, so that the remaining expansion layer 220 covers the sidewall of the preprocessing trench 201, and etch the portion of the substrate 200 below the preprocessing trench 201 to form an initial trench 202 based on the preprocessing trench 201.

[0066] It should be noted that during the formation of the initial trench 202, a dry etching process is used to remove the portion of the expansion layer 220 located at the bottom of the pre-processed trench 201, and the substrate 200 below the pre-processed trench 201 is further etched downward to form the initial trench 202. The surface of the remaining expansion layer 220 away from the sidewall is flush with the portion of the sidewall of the initial trench 202 not covered by the expansion layer 220, to ensure smooth processing of subsequent processes.

[0067] Next, see Figure 8 , step S04 is performed to etch the portion of the initial trench 202 not covered by the extension layer 220 to form the sigma trench 203. In one embodiment, a first wet etching process is used to etch the portion of the initial trench 202 not covered by the extension layer 220 to form the sigma trench 203. Optionally, the etchant used in the first wet etching process includes tetramethylammonium hydroxide (THMA).

[0068] It should be emphasized that see Figure 8 The sigma groove 203 is formed based on the initial groove 202. Therefore, the sigma groove 203 formed here includes the entire groove starting from the surface of the substrate 200 (it can also be understood that the sigma groove 203 includes not only the polygonal groove area under the extension layer 220, but also the rectangular groove area where the extension layer 220 is located).

[0069] Then, see Figure 9 , step S05 is performed to remove the remaining extension layer 220. In one embodiment, a second wet etching process is used to remove the remaining extension layer 220. Optionally, the etchant used in the second wet etching process includes DHF (ie, a mixed solution of hydrofluoric acid and deionized water).

[0070] It should be noted that, during the second wet etching process, the gate sidewalls (i.e. Figure 4 The gate spacer 213 in the embodiment can protect the gate dielectric layer 211 to prevent the gate dielectric layer 211 from being damaged during the second wet etching process, thereby ensuring the normal operation of the semiconductor device.

[0071] Continue reading Figure 8 and Figure 9 It should be further emphasized that after the remaining extension layer 220 is removed, the sigma trench 203 includes the entire trench region in the substrate 200 below the gate structure 210 (it can also be understood that the sigma trench 203 includes not only Figure 9 The rectangular trench region in the substrate 200 between two adjacent gate structures 210 also includes a polygonal trench region below the rectangular trench region).

[0072] Next, see Figure 10 and Figure 11 , execute step S06 to form an epitaxial layer 230 in the sigma trench 203, the epitaxial layer 230 includes a buffer layer 231, an intermediate layer 232 and a cap layer 233 stacked in sequence from bottom to top, and the buffer layer 231 completely covers the inner wall of the sigma trench 203.

[0073] Continue reading Figure 10 and Figure 11In one embodiment, the buffer layer 231 includes a first buffer layer 231a on a side close to the substrate 200 and a second buffer layer 231b on a side close to the intermediate layer 232. In one embodiment, the material of the first buffer layer 231a includes a germanium silicon material, such as germanium silicide (SiGe), and the materials of the second buffer layer 231b and the intermediate layer 232 include a germanium silicon boron material (SiGeB). The germanium (Ge) content in the intermediate layer 232 is higher than the germanium content in the second buffer layer 231b to increase the pressure of the intermediate layer 232. The material of the cap layer 233 includes a silicon boron material, such as boron silicide (SiB). In other embodiments of the present application, the specific material of the epitaxial layer 230 and the elements and contents contained in each film layer of the epitaxial layer 230 can be set according to actual process requirements, and this application does not impose any restrictions on this.

[0074] See Figure 11 In the top corner region A of the sigma trench 203, the buffer layer 231 completely covers the inner wall of the sigma trench 203, thereby completely isolating the substrate 200 from the intermediate layer 232. It can be seen that in the epitaxial layer manufactured using the improved semiconductor device manufacturing method according to one embodiment of the present application, because the buffer layer completely isolates the substrate and the intermediate layer, the boron element in the intermediate layer will not diffuse into the trench in the substrate, thereby reducing or avoiding the risk of element diffusion in the epitaxial layer. This further reduces or even avoids the short channel effect caused by the diffusion of elements in the epitaxial layer into the channel, thereby improving the performance and stability of the semiconductor device.

[0075] Accordingly, one embodiment of the present application further provides a semiconductor device manufactured using the above-mentioned method for manufacturing a semiconductor device. Figure 10 and Figure 11 In one embodiment, a semiconductor device includes a substrate 200 and a plurality of mutually spaced gate structures 210 located on the substrate 200; wherein a sigma trench 203 is provided in the substrate 200, two adjacent gate structures 210 are located on the substrate 200 on both sides of the sigma trench 203, and an epitaxial layer 230 is provided in the sigma trench, the epitaxial layer 230 includes a buffer layer 231, an intermediate layer 232 and a cap layer 233 stacked in sequence from bottom to top, and the buffer layer 231 completely covers the inner wall of the sigma trench 203.

[0076] See Figure 11In the top corner region A of the sigma trench 203, the buffer layer 231 completely covers the inner wall of the sigma trench 203, thereby completely isolating the substrate 200 from the intermediate layer 232. Thus, the semiconductor structure described above completely isolates the substrate 200 from the intermediate layer 232 by utilizing the buffer layer 231, thereby ensuring that the boron element in the intermediate layer 232 does not diffuse into the trenches (e.g., the sigma trench 203) within the substrate 200. This reduces or eliminates the risk of element diffusion in the epitaxial layer 230, further reducing or even eliminating the short channel effect caused by element diffusion into the channel in the epitaxial layer 230, thereby improving the performance and stability of the semiconductor device.

[0077] See Figure 4 and Figure 10 In one embodiment, the gate structure 210 includes a gate dielectric layer 211, a gate 212, and a gate spacer 213, wherein the gate dielectric layer 211 is formed on the substrate 200, the gate 212 is formed on the gate dielectric layer 211, and the gate spacer 213 covers the sidewalls of the gate 212 and the sidewalls of the gate dielectric layer 211. Exemplarily, the material of the substrate 200 includes silicon (Si), the gate 212 is a metal gate or a polysilicon gate, the material of the gate dielectric layer 211 includes silicon oxide, and the gate spacer 213 may be a stacked structure composed of a silicon oxide layer, a silicon nitride layer, or a combination thereof. For example, the gate spacer 213 may be an ONO stacked structure composed of a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers.

[0078] Continue reading Figure 10 In one embodiment, the material of the first buffer layer 231a includes a germanium silicon material, such as germanium silicide (SiGe), and the materials of the second buffer layer 231b and the intermediate layer 232 include a germanium silicon boron material (SiGeB). The germanium (Ge) content in the intermediate layer 232 is higher than the germanium content in the second buffer layer 231b to increase the pressure of the intermediate layer 232. The material of the cap layer 233 includes a silicon boron material, such as boron silicide (SiB). In other embodiments of the present application, the specific material of the epitaxial layer 230 and the elements and contents contained in each film layer of the epitaxial layer 230 can be set according to actual process requirements, and this application does not impose any restrictions on this.

[0079] The unexpected effects of the present application are: by forming a pretreatment trench and an expansion layer covering the side walls of the pretreatment trench, and forming an initial trench based on the pretreatment trench, the expansion layer is used to protect the side walls covered by it during the subsequent etching process; by forming a sigma trench based on the initial trench and removing the expansion layer, the width of the sigma trench close to the gate structure is increased, providing process space for the subsequently formed epitaxial layer, which is beneficial to improving the thickness and uniformity of the buffer layer included in the epitaxial layer; by making the buffer layer completely cover the inner wall of the sigma trench, the diffusion of elements in the intermediate layer of the epitaxial layer into the substrate is reduced or avoided, thereby reducing or even avoiding the short channel effect of the semiconductor device.

[0080] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and such modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a plurality of gate structures spaced apart from each other are formed, and forming a pre-processed trench in the substrate between two adjacent gate structures; forming an expansion layer on the inner wall of the pre-treated groove by adopting an in-situ water vapor generation process or a thermal oxidation growth process; Etching away a portion of the extension layer located at the bottom of the preprocessing trench so that the remaining extension layer covers the sidewalls of the preprocessing trench, and etching a portion of the substrate below the preprocessing trench to form an initial trench based on the preprocessing trench; etching a portion of the initial trench not covered by the extension layer to form a sigma trench; removing the remaining expansion layer; An epitaxial layer is formed in the sigma trench, the epitaxial layer including a buffer layer, an intermediate layer and a cap layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench, the buffer layer including a first buffer layer close to the substrate side and a second buffer layer close to the intermediate layer side.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first buffer layer includes germanium silicon material, the materials of the second buffer layer and the intermediate layer include germanium silicon boron material, and the germanium element content in the intermediate layer is higher than the germanium element content in the second buffer layer. The material of the cap layer includes boron silicide.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: A first wet etching process is used to etch a portion of the initial trench not covered with the extension layer to form the sigma trench, and the etchant used in the first wet etching process includes THMA.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: A second wet etching process is used to remove the remaining extension layer, and the etchant used in the second wet etching process includes DHF.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The depth of the pre-treated groove ranges from 5Å to 20Å.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the extension layer includes silicon oxide.

7. A semiconductor device, characterized in that: The semiconductor device is manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. The semiconductor device according to claim 7, wherein: include: a substrate having a sigma trench provided therein; a plurality of mutually spaced gate structures, located on the substrate, with two adjacent gate structures located on the substrate on both sides of the sigma trench; An epitaxial layer is located in the sigma trench, and the epitaxial layer includes a buffer layer, an intermediate layer and a cap layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench. The buffer layer includes a first buffer layer close to the substrate side and a second buffer layer close to the intermediate layer side.

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