Solar cell and its preparation method and photovoltaic module

Abstract

The present application provides a solar cell, a preparation method thereof, and a photovoltaic module, relating to the field of photovoltaic technology. The solar cell includes a silicon wafer, a doped polysilicon layer, and grid lines. The thickness of the silicon wafer in the non-grid line area of the edge portion of the silicon wafer is greater than the thickness of the silicon wafer in the non-grid line area of the middle portion. In the embodiments of the present application, since the non-grid line area of the edge portion has a greater thickness than the non-grid line area of the middle portion, its structural strength is better than that of the middle portion. This makes the silicon wafer and the solar cell not easily warp, crack, or fragment, nor easily damaged due to knocking. During the processing of the solar cell, during the assembly process of the photovoltaic module, and during the subsequent use of the photovoltaic module, the silicon wafer with better reliability can enable the solar cell to have a higher product yield, better performance, and a longer service life.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular, to a solar cell wafer, a preparation method thereof, and a photovoltaic module. Background Art

[0002] During the operation of a solar cell, it is affected by various factors, among which stress is a key factor. The generation of stress mainly stems from the mismatch of the thermal expansion coefficients of materials during the manufacturing process of the cell wafer, the unreasonable design of the cell wafer structure, and the temperature change of the cell wafer in the actual use environment, etc. For example, during the preparation process of a solar cell, various different materials are usually involved, such as silicon wafers, metal electrodes, encapsulation materials, etc. These materials have different thermal expansion coefficients. When undergoing high-temperature processes (such as annealing processes) or when the outdoor environmental temperature changes, due to the different degrees of expansion or contraction of different materials, stress will be generated inside the cell. This stress may cause defects such as cracks and delamination in the cell wafer, affecting the yield of the product.

[0003] Currently, in the related technologies of the cell wafer preparation process, there is a process means of etching away the polysilicon layer in the non-grid line area to improve the cell performance. However, usually during the etching process, the non-grid line area on the entire silicon wafer will be corroded by 2 - 3 μm. Since the existing thickness of the solar cell wafer is relatively thin, this process means will damage the stress of the solar cell wafer to a certain extent, having a negative impact on the long-term stable performance of the cell wafer and the module. For example, during high-temperature processes (such as coating and sintering) of the cell wafer, warping, latent cracks, or even fragmentation may occur; when the cell wafer is subjected to bumps, it is also more likely to crack or break. Summary of the Invention

[0004] The objectives of the present application include providing a solar cell wafer, a preparation method thereof, and a photovoltaic module, which can optimize the stress of the silicon wafer and improve the reliability of the solar cell wafer.

[0005] The embodiments of the present application can be implemented as follows:

[0006] In a first aspect, the present application provides a solar cell wafer. The solar cell wafer is a tunnel oxide passivated contact cell or a back contact cell. The solar cell wafer includes a silicon wafer, a doped polysilicon layer, and grid lines. At least one side of the silicon wafer has a grid line area and a non-grid line area. The doped polysilicon layer covers the grid line area, and the grid lines are connected to the doped polysilicon layer;

[0007] The silicon wafer has a middle part and an edge part. The edge part forms the edge of the silicon wafer and surrounds the middle part. The size of the edge part in its width direction is 1% - 30% of the size of the silicon wafer in the same direction. Wherein, the width direction of the edge part is parallel to the silicon wafer and perpendicular to the edge of the silicon wafer, and the thickness of the silicon wafer at the non-grid line area of the edge part is greater than the thickness of the silicon wafer at the non-grid line area of the middle part.

[0008] In an alternative embodiment, the size of the edge part in its width direction is 1 - 70 mm.

[0009] In an alternative embodiment, trenches are formed in the non-grid line area of the silicon wafer, and the depth of the trenches in the edge part is less than the depth of the trenches in the middle part.

[0010] In an alternative embodiment, the depth of the trenches in the edge part is 0.1 - 3 μm, and the depth of the trenches in the middle part is 1 - 5 μm.

[0011] In an alternative embodiment, the trenches are formed on the back surface of the silicon wafer.

[0012] In a second aspect, the present application provides a method for manufacturing a solar cell wafer according to any one of the foregoing embodiments, including:

[0013] Obtain a silicon wafer;

[0014] Deposit a doped polysilicon layer on the silicon wafer;

[0015] Etch away the doped polysilicon layer and part of the silicon wafer in the non-grid line area, wherein the etching depth of the silicon wafer in the middle part is greater than the etching depth of the silicon wafer in the edge part;

[0016] Fabricate grid lines connected to the doped polysilicon layer.

[0017] In an alternative embodiment, the step of etching away the doped polysilicon layer and part of the silicon wafer in the non-grid line area includes:

[0018] Irradiate the doped polysilicon layer in the non-grid line area with a laser;

[0019] Use a wet etching process to remove the doped polysilicon layer and part of the silicon wafer in the non-grid line area.

[0020] In an alternative embodiment, in the step of irradiating the doped polysilicon layer in the non-grid line area with a laser, the laser energy per unit area in the non-grid line area of the middle part is greater than the laser energy per unit area in the non-grid line area of the edge part.

[0021] In an alternative embodiment, the laser energy per unit area in the non-grid line area of the middle part is 210 mJ / cm 2 ~380 mJ / cm 2; The laser energy per unit area of the non-grid line region of the edge part is 180 mJ / cm 2 ~350 mJ / cm 2 .

[0022] In an alternative embodiment, in the step of irradiating the doped polysilicon layer of the non-grid line region with a laser, the irradiation duration of the non-grid line region in the middle part is longer than that of the non-grid line region in the edge part, and / or the irradiation power of the non-grid line region in the middle part is greater than that of the non-grid line region in the edge part.

[0023] In an alternative embodiment, the step of removing the doped polysilicon layer of the non-grid line region and part of the silicon wafer by a wet etching process includes:

[0024] Etching the non-grid line region in the middle part with a first etching solution, and etching the non-grid line region in the edge part with a second etching solution;

[0025] Wherein, the corrosion resistance of the first etching solution is stronger than that of the second etching solution, and / or the concentration of the first etching solution is greater than that of the second etching solution.

[0026] In an alternative embodiment, in the step of removing the doped polysilicon layer of the non-grid line region and part of the silicon wafer by a wet etching process, the etching duration of the middle part is longer than that of the edge part, and / or the etching temperature of the middle part is higher than that of the edge part.

[0027] In an alternative embodiment, the laser is a green laser.

[0028] In an alternative embodiment, the etching solution used in the wet etching process includes at least one of sodium hydroxide and potassium hydroxide.

[0029] In a third aspect, the present application provides a photovoltaic module, including the solar cell of any one of the foregoing embodiments, or including the solar cell obtained by the preparation method of the solar cell of any one of the foregoing embodiments.

[0030] The beneficial effects of the solar cell, its preparation method and the photovoltaic module provided by the embodiments of the present application include:

[0031] The solar cell provided by the embodiment of the present application is a tunneling oxide passivated contact cell or a back contact cell, which includes a silicon wafer, a doped polysilicon layer, and grid lines. At least one side of the silicon wafer has a grid line area and a non-grid line area. The doped polysilicon layer covers the grid line area, and the grid lines are connected to the doped polysilicon layer. The silicon wafer has a middle part and an edge part. The edge part forms the edge of the silicon wafer and surrounds the middle part. The thickness of the silicon wafer at the non-grid line area of the edge part is greater than the thickness of the silicon wafer at the non-grid line area of the middle part. In the embodiment of the present application, since the non-grid line area of the edge part has a greater thickness than the non-grid line area of the middle part, its structural strength is better than that of the middle part. And the edge part is exactly the position where warping and hidden cracks are likely to occur, and it is also the position where it is easy to be knocked. Therefore, in the embodiment of the present application, strengthening the edge part of the silicon wafer can improve the reliability of the entire silicon wafer and even the entire solar cell, making the silicon wafer and the solar cell not easy to warp, have hidden cracks or break, and not easy to be damaged due to being knocked. During the processing of the solar cell, during the assembly process of the photovoltaic module, and during the subsequent use of the photovoltaic module, the silicon wafer with better reliability can make the solar cell have a higher product yield, better performance, and a longer service life.

[0032] The preparation method of the solar cell provided by the embodiment of the present application can be used to prepare the above-mentioned solar cell. The photovoltaic module provided by the embodiment of the present application includes the above-mentioned solar cell or the solar cell prepared by the above-mentioned preparation method, and thus also has the characteristics of high product yield, good reliability, and long service life. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1 Schematic diagram of the back side of the solar cell in an embodiment of the present application;

[0035] Figure 2 Partial cross-sectional view of the solar cell (TOPCon cell) in an embodiment of the present application;

[0036] Figure 3 Schematic diagram of the silicon wafer in an embodiment of the present application;

[0037] Figure 4 Partial cross-sectional view of the solar cell (BC cell) in another embodiment of the present application;

[0038] Figure 5 Flow chart of a preparation method of a solar cell in an embodiment of the present application;

[0039] Figure 6 Schematic diagram after the preparation of a doped polysilicon layer in an embodiment of the present application;

[0040] Figure 7 Schematic diagram after the preparation of a p-type doped polysilicon layer in an embodiment of the present application;

[0041] Figure 8 Schematic diagram after the preparation of an n-type doped polysilicon layer in an embodiment of the present application;

[0042] Figure 9 Flow chart of etching to remove the doped polysilicon layer and part of the silicon wafer in the non-grid line area in an embodiment of the present application;

[0043] Figure 10 Schematic diagram after etching to remove the doped polysilicon layer in the non-grid line area in an embodiment of the present application;

[0044] Figure 11 Schematic diagram after etching to remove the doped polysilicon layer in the non-grid line area in another embodiment of the present application.

[0045] Icon: 010 - solar cell; 100 - silicon wafer; 101 - middle part; 102 - edge part; 110 - grid line area; 120 - non-grid line area; 200 - grid line; 201 - first grid line; 202 - second grid line; 300 - p-type doped polysilicon layer; 310 - first dielectric layer; 400 - n-type doped polysilicon layer; 410 - second dielectric layer; 500 - tunneling oxide layer; 610 - first passivation layer; 620 - second passivation layer. Detailed implementation manners

[0046] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents the selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0048] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it is not necessary to further define and explain it in subsequent figures.

[0049] In the description of the present application, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship in which the inventive product is usually placed during use. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0050] In addition, if terms such as "first", "second", etc. are used only for distinguishing descriptions, they should not be construed as indicating or implying relative importance.

[0051] It should be noted that, without conflict, the features in the embodiments of the present application may be combined with each other.

[0052] There is a parasitic absorption phenomenon in the polysilicon layer on the back of the solar cell, which affects the photoelectric conversion efficiency of the solar cell 010. Parasitic absorption refers to the phenomenon that photons are absorbed by non-active layers or non-ideal positions, rather than by the active layers (such as perovskite layers, single-crystal or polysilicon layers) designed to generate electrical energy. Polysilicon is composed of many small silicon crystals, and it has many grain boundaries and defects. These regions may cause additional absorption of light with specific wavelengths. In addition, impurities and structural defects in polysilicon can cause scattering and absorption of photon energy. This unnecessary absorption will lead to the loss of photo-generated carriers, thereby reducing the overall conversion efficiency of the solar cell. In related technologies, in order to improve the parasitic absorption problem on the back of the solar cell, the doped polysilicon layer in the non-grid line area on the back of the solar cell is removed. For example, by irradiating all non-grid line areas on the back of the solar cell with a laser, the doped polysilicon layer and the phosphosilicate glass (PSG) film on its surface in the non-grid line area are affected. The PSG film is removed or peeled off from the doped polysilicon layer under the action of the laser (i.e., laser film opening). Subsequently, the doped polysilicon layer in the non-grid line area is completely removed by an etching process, and only the doped polysilicon layer in the grid line area is retained. Although the back etching process in related technologies can improve the parasitic absorption problem of the back polysilicon layer, in the etching process, due to the inability to accurately control the etching depth, in order to ensure that the polysilicon layer in the non-grid line area on the back can be completely removed, the silicon wafer under the polysilicon layer will be etched to a certain extent. Usually, the non-grid line area on the back of the silicon wafer will be uniformly etched by 2-3 μm. And the overall thickness of the solar cell itself is relatively thin (usually less than 150 μm). This etching process makes the reliability of the silicon wafer poor, especially the reliability of the edge part of the silicon wafer is poor. Due to high-temperature processes in subsequent processes (such as coating and sintering), the solar cell is prone to warping, and the risks of hidden cracks and fragmentation will also increase. Moreover, the silicon wafer / solar cell is easily damaged or even fragmented at the edge due to bumping during the manufacturing and assembly processes. Therefore, the preparation method of the solar cell in related technologies will have a greater negative impact on the structural strength of the silicon wafer / solar cell, resulting in negative impacts such as reduced product yield, poor product reliability, and shortened service life.

[0053] In order to improve at least one of the above deficiencies in related technologies, the embodiments of the present application provide a solar cell and its preparation method. By making the thickness of the non-grid line area at the edge part of the silicon wafer greater than that of the non-grid line area in the middle part, the strength of the edge part of the silicon wafer relative to the middle part is improved. By optimizing the stress distribution of the silicon wafer, warping is reduced, and the risks of hidden cracks and fragmentation are reduced. At the same time, the risk of damage due to edge bumping is also reduced. Furthermore, the product yield, reliability, and service life of the solar cell are improved.

[0054] Figure 1 This is a schematic diagram of the back side of a solar cell 010 in an embodiment of the present application. As Figure 1 shown, the back side of the solar cell 010 provided in the embodiment of the present application has a plurality of grid lines 200. These grid lines 200 are made of metal and serve as metal electrodes to collect current. The photo-generated current generated by the solar cell 010 can be transmitted to an external energy storage device or the power grid through the grid lines 200. The type of the solar cell 010 provided in the embodiment of the present application can be a Tunnel Oxide Passivated Contact (TOPCon) cell or a BackContact (BC) cell, or other solar cells that require the removal of the doped polysilicon layer in the non-grid line area 120 (or non-metallized area) on the back side.

[0055] Figure 2 This is a partial cross-sectional view of a solar cell 010 (TOPCon cell) in an embodiment of the present application. As Figure 2 shown, Figure 2 the shown solar cell 010 is a Tunnel Oxide Passivated Contact cell, that is, a TOPCon cell, which includes a silicon wafer 100 and a doped polysilicon layer and grid lines 200 provided on the silicon wafer 100. The silicon wafer 100 has opposite front and back sides in its own thickness direction. The front side corresponds to the light-facing surface of the solar cell 010, and the back side corresponds to the backlight surface of the solar cell 010. In Figure 2 this, the upper surface of the silicon wafer 100 is the front side, and the lower surface of the silicon wafer 100 is the back side.

[0056] In this embodiment, the doped polysilicon layer includes a p-type doped polysilicon layer 300 and an n-type doped polysilicon layer 400. In addition, the solar cell 010 further includes a tunneling oxide layer 500, a first passivation layer 610, and a second passivation layer 620. In this embodiment, the p-type doped polysilicon layer 300 is disposed on the light-facing side of the silicon wafer 100, and the first passivation layer 610 is disposed on the side of the p-type doped polysilicon layer 300 facing away from the silicon wafer 100. The back surface of the silicon wafer 100 has a grid line region 110 and a non-grid line region 120. The tunneling oxide layer 500 and the n-type doped polysilicon layer 400 are sequentially stacked on the grid line region 110 of the back surface, and the second passivation layer 620 is disposed on the non-grid line region 120 and the side of the n-type doped polysilicon layer 400 facing away from the silicon wafer 100. It should be understood that in the embodiment of the present application, the grid line region 110 on the back surface of the silicon wafer 100 is the region covered by the n-type doped polysilicon layer 400, and the non-grid line region 120 is the region on the back surface of the silicon wafer 100 not covered by the n-type doped polysilicon layer 400. The grid lines 200 include a first grid line 201 and a second grid line 202, wherein the first grid line 201 is connected to the p-type doped polysilicon layer 300, and the second grid line 202 is connected to the n-type doped polysilicon layer 400.

[0057] In this embodiment, the silicon wafer 100 is n-type doped, specifically, it can be an n-type single crystal silicon. The materials of the first passivation layer 610 and the second passivation layer 620 are selected from at least one of alumina, silicon oxide, silicon nitride, and silicon oxynitride. The first passivation layer 610 and the second passivation layer 620 can cover the front and back surfaces of the solar cell 010, effectively reducing the surface state density and reducing the recombination of carriers on the surface, thereby improving the open circuit voltage (Voc) and conversion efficiency of the battery. The first passivation layer 610 (such as using SiN x ) can also have an antireflection effect, reducing the reflection loss of incident light, increasing the absorption of light, and thereby improving the short circuit current (Isc). The second passivation layer 620, together with the tunneling oxide layer 500 and the n-type doped polysilicon layer 400, forms a passivated contact structure, which can optimize the transport and collection efficiency of carriers. In addition, the first passivation layer 610 and the second passivation layer 620 can protect the silicon wafer 100 and the doped polysilicon layer from the influence of the external environment (such as moisture, pollutants), improving the long-term stability of the solar cell 010.

[0058] The tunneling oxide layer 500 can effectively reduce the recombination rate on the back side and increase the open-circuit voltage (Voc) of the battery. As the interface layer between the silicon wafer 100 and the n-type doped polysilicon layer 400, the tunneling oxide layer 500 can optimize the interface characteristics, reduce interface defects, and improve the carrier transport efficiency. The material of the tunneling oxide layer 500 can be selected as SiO2. The tunneling oxide layer 500 allows electrons to pass through by quantum tunneling effect while blocking holes, thereby achieving selective transport of carriers. The tunneling oxide layer 500 is usually thin, for example, with a thickness of 1 nm to 2 nm.

[0059] Figure 3 This is a schematic diagram of the silicon wafer 100 in an embodiment of the present application. Combining Figure 2 and Figure 3 , in the embodiment of the present application, the silicon wafer 100 has a middle part 101 and an edge part 102. The edge part 102 forms the edge of the silicon wafer 100 and surrounds the middle part 101. The thickness of the silicon wafer 100 at the non-grid line area 120 in the edge part 102 is greater than the thickness of the silicon wafer 100 at the non-grid line area 120 in the middle part 101. It can be understood that the area occupied by the non-grid line area 120 is usually larger than the area occupied by the grid line area 110. The thickness of the silicon wafer 100 at the non-grid line area 120 has a significant impact on the structural strength of the silicon wafer 100. Generally, the edge part 102 of the silicon wafer 100 is more likely to warp and is more prone to being knocked than the middle part 101. Therefore, the edge part 102 is the weak position of the silicon wafer 100 and is prone to warping and hidden cracks. In the embodiment of the present application, since the thickness of the non-grid line area 120 in the edge part 102 of the silicon wafer 100 is greater than the thickness of the non-grid line area 120 in the middle part 101, the edge part 102 of the silicon wafer 100 has higher structural strength relative to the middle part 101. This form of silicon wafer 100 is not easy to warp and can also reduce the risk of the silicon wafer 100 being fragmented due to being knocked. Since the solar cell 010 is not easy to warp and has good strength, it is convenient for subsequent processing and assembly of the cell and is not easy to be damaged, which is beneficial to improving the yield of the product. After being assembled into a photovoltaic module and put into use, since the solar cell 010 has good reliability, its service life will also be improved.

[0060] Such as Figure 3As shown, the middle part 101 of the silicon wafer 100 is the part enclosed by the dashed line, and the part between the dashed line and the edge of the silicon wafer 100 is the edge part 102 of the silicon wafer 100. Optionally, both the middle part 101 of the silicon wafer 100 and the silicon wafer 100 are rectangular; optionally, the middle part 101 of the silicon wafer 100 and the silicon wafer 100 are of similar shapes (i.e., having the same aspect ratio). In other alternative embodiments, the middle part 101 of the silicon wafer 100 can also be selected as other shapes according to needs, such as circular, elliptical, triangular, trapezoidal or other irregular shapes, as long as there is a gap between the edge of the middle part 101 of the silicon wafer 100 and the edge of the silicon wafer 100.

[0061] Optionally, the dimension of the edge part 102 in its width direction (W1 and W2 in the figure) is 1% - 30% of the dimension of the silicon wafer 100 in the same direction, such as any one of the ratio values of 1%, 2%, 5%, 10%, 15%, 20%, 25%, 30% of the dimension of the silicon wafer 100 in the same direction or a value between any two ratio values. Wherein, the width direction of the edge part 102 is parallel to the silicon wafer 100 and perpendicular to the edge of the silicon wafer 100. In this embodiment, since the edge part 102 surrounds the middle part 101, there will be different directions in the width direction of the edge part 102. As Figure 3 shown, for the edge parts 102 on the left and right sides, its width direction is the left - right direction, parallel to the width direction of the silicon wafer 100. The width of the edge part 102 here ( Figure 3 shown as W1) accounts for 1% - 30% of the width of the silicon wafer 100 ( Figure 3 shown as L1). For the edge parts 102 on the upper and lower sides, its width direction is the up - down direction, parallel to the length direction of the silicon wafer 100. The width of the edge part 102 here ( Figure 3 shown as W2) accounts for 1% - 30% of the length of the silicon wafer 100 ( Figure 3 shown as L2).

[0062] Optionally, the dimension of the edge part 102 in its width direction is 1 - 70 mm. For example, the width of the edge part 102 is any one of the point values of 1 mm, 2 mm, 5 mm, 10 mm, 15 mm, 20 mm, 30 mm, 40 mm, 50 mm, 60 mm, 70 mm or a value between any two points.

[0063] In this embodiment, trenches are formed in the non-grid-line area 120 on the back surface of the silicon wafer 100. This is formed by over-etching to ensure complete removal of the doped polysilicon layer on the back surface (specifically, the n-type doped polysilicon layer 400 in this embodiment) during the wet etching process. In alternative other embodiments, some of the silicon wafer 100 in the non-grid-line area 120 may not be etched and no trenches are formed; for example, the non-grid-line area 120 in the edge portion 102 of the silicon wafer 100 may not be etched (i.e., the etching just reaches the surface of the silicon wafer 100). It can be understood that when the silicon wafer 100 is not etched, its thickness can be uniform, and by adjusting the etching depth of the silicon wafer 100 in the non-grid-line area 120, that is, adjusting the trench depth ( Figure 2 as shown in D), the thickness of the silicon wafer 100 at the non-grid-line area 120 can be adjusted.

[0064] In the embodiments of the present application, the depth of the trenches in the edge portion 102 is less than the depth of the trenches in the middle portion 101. Therefore, the thickness of the silicon wafer 100 in the non-grid-line area 120 of the edge portion 102 is greater than the thickness of the silicon wafer 100 in the non-grid-line area 120 of the middle portion 101. Optionally, the depth of the trenches in the edge portion 102 is 0.1 - 3 μm, such as any point value among 0.1 μm, 0.2 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm or a value between any two point values; the depth of the trenches in the middle portion 101 is 1 - 5 μm, such as any point value among 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm or a value between any two point values. It can be understood that if the trench depth is designed too deep, it is easy to cause the problem of reduced strength of the silicon wafer 100, and if the trench depth is designed too shallow, it is easy to have the problem of incomplete removal of the doped polysilicon layer. In alternative other embodiments, the depth of the trenches can also be selected outside the above range according to the actual product requirements. For example, when using a thicker silicon wafer 100, the depth of the trenches can be considered to be increased.

[0065] The above Figure 2 embodiments are introduced taking the TOPCon cell as an example. The solar cell wafer 010 provided in the embodiments of the present application can also be a back contact cell (i.e., a BC cell). Figure 4 This is a partial cross-sectional view of the solar cell wafer 010 (i.e., a BC cell) in another embodiment of the present application. As Figure 4 shown, the solar cell wafer 010 includes a silicon wafer 100, a doped polysilicon layer provided on the silicon wafer 100, and grid lines 200. In Figure 4Among them, the front side of the silicon wafer 100 faces upward, corresponding to the light-facing side of the solar cell 010, and the back side of the silicon wafer 100 faces downward, corresponding to the backlight side of the solar cell 010. The doped polysilicon layer includes a p-type doped polysilicon layer 300 and an n-type doped polysilicon layer 400. The solar cell 010 further includes a first dielectric layer 310, a second dielectric layer 410, a first passivation layer 610, and a second passivation layer 620. The first passivation layer 610 is disposed on the front side of the silicon wafer 100. The first dielectric layer 310 and the p-type doped polysilicon layer 300 are sequentially stacked on a part of the grid line region 110 on the back side of the silicon wafer 100, and the second dielectric layer 410 and the n-type doped polysilicon layer 400 are sequentially stacked on another part of the grid line region 110 on the back side of the silicon wafer 100. The second passivation layer 620 is disposed on the side of the p-type doped polysilicon layer 300 facing away from the silicon wafer 100, the side of the n-type doped polysilicon layer 400 facing away from the silicon wafer 100, and the non-grid line region 120 on the back side of the silicon wafer 100.

[0066] In Figure 4 In the illustrated embodiment, the grid lines 200 specifically include a first grid line 201 and a second grid line 202, wherein the first grid line 201 is connected to the p-type doped polysilicon layer 300, and the second grid line 202 is connected to the n-type doped polysilicon layer 400. In this embodiment, the characteristic of the back contact battery is that no grid lines 200 are provided on the light-facing side, and all the grid lines 200 (including the first grid line 201 and the second grid line 202) are provided on the back side of the battery, which means that there are no grid lines 200 on the light-facing side of the battery to block sunlight. Therefore, the entire area of the light-facing side of the solar cell 010 can receive sunlight, which makes it have a high photoelectric conversion efficiency and increases the photocurrent. And, since the grid lines 200 are all located on the backlight side, the front side of the battery can be made more concise, flat, and have a high aesthetic degree, which is suitable for application scenarios with high aesthetic requirements, such as building integrated photovoltaics (BIPV) systems. In Figure 4 In the illustrated embodiment, the non-grid line region 120 on the back side of the silicon wafer 100 also forms a groove, and the depth of the groove is Figure 4 as shown in D in

[0067] Figure 5 This is a flowchart of a method for manufacturing the solar cell 010 in an embodiment of the present application. As Figure 5 shown, the method for manufacturing the solar cell 010 provided in the embodiment of the present application can be used to manufacture the solar cell 010 provided in the above embodiment of the present application. The method for manufacturing the solar cell 010 includes the following steps:

[0068] Step S100, obtaining a silicon wafer 100.

[0069] In the embodiment of the present application, the obtained silicon wafer 100 is an n-type doped single crystal silicon. For making Figure 2Taking the TOPCon cell shown as an example, optionally, the front surface of the silicon wafer 100 can be textured to form a textured surface, thereby reducing light reflection loss, improving light absorption efficiency, reducing surface recombination, and thus improving cell performance. Optionally, the surface of the silicon wafer 100 can be etched with an alkaline solution (such as sodium hydroxide solution) to form a textured surface.

[0070] Step S200, depositing a doped polysilicon layer on the silicon wafer 100.

[0071] Taking Figure 2 the TOPCon cell shown as an example, it is necessary to deposit a p-type doped polysilicon layer 300 on the front surface of the silicon wafer 100, deposit an n-type doped polysilicon layer 400 on the front surface of the silicon wafer 100, and, before depositing the n-type doped polysilicon layer 400, it is also necessary to first fabricate a tunneling oxide layer 500 on the back surface of the silicon wafer 100. Optionally, the doped polysilicon layer can be fabricated by chemical vapor deposition (CVD) process; the tunneling oxide layer 500 can be fabricated by thermal oxidation process or chemical vapor deposition process. For example, first place the silicon wafer 100 in a chemical vapor deposition equipment, introduce a silicon source (such as high-purity SiH4) to grow an intrinsic polysilicon layer on the front surface of the silicon wafer 100, and then place the above structure in a boron diffusion furnace tube, introduce BCl3 for boron diffusion to convert the intrinsic polysilicon layer into a p-type doped polysilicon layer 300. Place the previously fabricated structure in a CVD equipment, introduce high-purity oxygen to grow a tunneling oxide layer 500 on the back surface of the silicon wafer 100, then introduce a silicon source (such as high-purity SiH4), grow an intrinsic polysilicon layer on the surface of the tunneling oxide layer 500, and then place the above structure in a phosphorus diffusion furnace tube, introduce POCl3 for phosphorus diffusion to convert the intrinsic polysilicon layer into an n-type doped polysilicon layer 400. It can be understood that the process gases used in the above doping process can be selected according to the n-type doping element and p-type doping element to be doped, and are not limited to BCl3 and POCl3. After the doped polysilicon layer is prepared, the structure shown in Figure 6 is obtained.

[0072] Taking Figure 4 the BC cell shown as an example, a first dielectric layer 310 and a p-type doped polysilicon layer 300 can be sequentially deposited on the back surface of the silicon wafer 100. Specifically, it can be realized by chemical vapor deposition process. Specifically, first place the silicon wafer 100 in a chemical vapor deposition equipment, introduce high-purity oxygen to grow a first dielectric layer 310 on the back surface of the silicon wafer 100, then introduce a silicon source (such as high-purity SiH4) to grow an intrinsic polysilicon layer on the first dielectric layer 310, and then place the above structure in a boron diffusion furnace tube, introduce BCl3 for boron diffusion to convert the intrinsic polysilicon layer into a p-type doped polysilicon layer 300, and obtain the structure shown in Figure 7The structure shown. After that, a part of the first dielectric layer 310 and the p-type doped polysilicon layer 300 can be removed by laser to expose a part of the back surface of the silicon wafer 100, and then a second dielectric layer 410 and an n-type doped polysilicon layer 400 are sequentially grown on the exposed surface of the silicon wafer 100. Specifically, the steps of growing the second dielectric layer 410 and the n-type doped polysilicon layer 400 include: placing the previously prepared structure in a chemical vapor deposition device, introducing high-purity oxygen to grow the second dielectric layer 410 on the exposed back surface of the silicon wafer 100, and then introducing a silicon source (such as high-purity SiH4) to grow an intrinsic polysilicon layer on the second dielectric layer 410. Subsequently, the above structure is placed in a phosphorus diffusion furnace tube, and POCl3 is introduced for phosphorus diffusion to convert the intrinsic polysilicon layer into an n-type doped polysilicon layer 400, obtaining the structure as shown in Figure 8 The structure shown. It can be understood that the process gases used in the above doping process can be selected according to the n-type doping element and p-type doping element to be doped, and are not limited to POCl3 and BCl3.

[0073] Step S300, etching away the doped polysilicon layer in the non-grid line region 120 and a part of the silicon wafer 100, wherein the etching depth of the silicon wafer 100 in the middle part 101 is greater than the etching depth of the silicon wafer 100 in the edge part 102.

[0074] Figure 9 is a flowchart of etching away the doped polysilicon layer in the non-grid line region 120 and a part of the silicon wafer 100 in an embodiment of the present application. As shown in Figure 9 In the embodiment of the present application, step S300 specifically includes:

[0075] Step S310, irradiating the doped polysilicon layer in the non-grid line region 120 with a laser.

[0076] It can be understood that in the process of preparing the doped polysilicon layer (including the p-type doped polysilicon layer 300 and the n-type doped polysilicon layer 400), a phosphosilicate glass (PSG) film will be formed on the surface of the n-type doped polysilicon layer 400, and a borosilicate glass (BSG) will be formed on the surface of the p-type doped polysilicon layer 300. By irradiating all the non-grid line regions 120 on the back surface of the solar cell 010 with a laser, the doped polysilicon layer in the non-grid line region 120 and the PSG film (and / or BSG film) on its surface are affected. The PSG film can be melted or vaporized or peeled off from the doped polysilicon layer under the action of the laser to achieve laser film opening. Laser film opening can facilitate the subsequent complete removal of the doped polysilicon layer in the non-grid line region 120 by wet etching, and only the doped polysilicon layer in the grid line region 110 is retained.

[0077] In order to achieve that the etching depth of the silicon wafer 100 in the final middle part 101 is greater than that of the silicon wafer 100 in the edge part 102, non-uniform laser irradiation can be used in step S310. For example, in the step of irradiating the doped polysilicon layer in the non-grid line area 120 with laser, the laser energy per unit area of the non-grid line area 120 in the middle part 101 is greater than that of the non-grid line area 120 in the edge part 102. Through the above non-uniform laser irradiation, the doped polysilicon layer and PSG film (and / or BSG film) in the non-grid line area 120 of the middle part 101 are more affected by the laser, can generate more heat, and melt and vaporize more, so that in the subsequent etching process, it is easier to be corroded than the doped polysilicon layer in the edge part 102.

[0078] Optionally, the laser energy per unit area of the non-grid line area 120 in the middle part 101 is 210 mJ / cm 2 ~380 mJ / cm 2 , for example, 210 mJ / cm 2 , 230 mJ / cm 2 , 250 mJ / cm 2 , 270 mJ / cm 2 , 290 mJ / cm 2 , 310 mJ / cm 2 , 330 mJ / cm 2 , 350 mJ / cm 2 , 370 mJ / cm 2 , 380 mJ / cm 2 Any point value or value between any two points in. The laser energy per unit area of the non-grid line area 120 in the edge part 102 is 180 mJ / cm 2 ~350 mJ / cm 2 , for example, 180 mJ / cm 2 , 200 mJ / cm 2 , 220 mJ / cm 2 , 240 mJ / cm 2 , 260 mJ / cm 2 , 280 mJ / cm 2 , 300 mJ / cm 2 , 320 mJ / cm 2 , 340 mJ / cm 2 , 350 mJ / cm 2 Any point value or value between any two points in.

[0079] It can be understood that the difference in the laser energy per unit area received by the middle part 101 and the edge part 102 can be achieved by irradiating the same-power laser for different durations; it can also be achieved by irradiating lasers with different powers for the same duration; or the laser powers for irradiating the middle part 101 and the edge part 102 are different, and the irradiation durations are also different. Therefore, in an optional embodiment of the present application, the irradiation duration of the non-grid line area 120 of the middle part 101 is greater than that of the non-grid line area 120 of the edge part 102, and / or, the irradiation power of the non-grid line area 120 of the middle part 101 is greater than that of the non-grid line area 120 of the edge part 102.

[0080] It can be understood that the scanning speed, frequency, power, and spot size of the laser can all directly affect the energy of the laser action; in an optional embodiment, the initial frequency of the laser can be 600K, and the scanning speed can be 45 - 60 m / s. Optionally, the laser used in step S310 can be a green laser. Optionally, by improving the control algorithm and hardware performance of the scanning galvanometer, it can dynamically adjust the scanning speed and angle of the laser beam according to the preset energy distribution pattern during the scanning process. For example, when scanning to the edge part 102, the scanning speed is appropriately increased to reduce the action time of the laser on the edge part 102, thereby reducing the laser energy received by the edge part 102; in the middle part 101, the scanning speed is reduced so that more energy accumulates in the middle part 101.

[0081] Step S320, using a wet etching process to remove the doped polysilicon layer and part of the silicon wafer 100 in the non-grid line area 120.

[0082] It can be understood that the non-grid line area 120 irradiated by the laser can be etched away, while the non-grid line area 120 not irradiated by the laser will not be etched. To ensure that the doped polysilicon layer in the non-grid line area 120 is completely removed to expose the silicon wafer 100, the back surface of the silicon wafer 100 (especially in the non-grid line area 120 of the middle part 101) is usually also corroded to a certain extent to form grooves. If in step S310, the middle part 101 and the edge part 102 have been unevenly irradiated by the laser, for example, the laser energy per unit area of the non-grid line area 120 of the middle part 101 is greater than that of the non-grid line area 120 of the edge part 102, then when using the wet etching process with the same technical parameters for the middle part 101 and the edge part 102, deeper grooves will be generated in the non-grid line area 120 of the middle part 101 of the silicon wafer 100, which also makes the thickness of the silicon wafer 100 in the non-grid line area 120 of the middle part 101 less than that of the silicon wafer 100 in the non-grid line area 120 of the edge part 102.

[0083] In other embodiments, non-uniform etching can also be achieved by using different wet etching processes in the middle part 101 and the edge part 102. For example, the non-gate line area 120 of the middle part 101 is etched using a first etching solution, and the non-gate line area 120 of the edge part 102 is etched using a second etching solution; wherein the corrosiveness of the first etching solution is stronger than the corrosiveness of the second etching solution, and / or the concentration of the first etching solution is greater than the concentration of the second etching solution. The above-mentioned comparison of the strength of the corrosiveness should be judged based on the corrosiveness of the etching solution to the doped polysilicon layer; for example, at the same concentration, the alkalinity of the effective component of the first etching solution is stronger than the alkalinity of the effective component in the second etching solution (for example, the first etching solution uses a strong base, and the second etching solution uses a weak base). In an optional embodiment, a mold can be used to form a barrier between the edge portion 102 and the middle portion 101, so that the first etching liquid is confined to the middle portion 101 and the second etching liquid is confined to the edge portion 102, thereby etching the non-grid line area 120 of the middle portion 101 with the first etching liquid and etching the non-grid line area 120 of the edge portion 102 with the second etching liquid. In another optional embodiment, a temporary mask can be used to cover the edge portion 102, and the non-grid line area 120 of the middle portion 101 can be etched with the first etching liquid; then, the temporary mask of the edge portion 102 is removed, and a temporary mask is laid on the middle portion 101 instead, and the non-grid line area 120 of the edge portion 102 is etched with the second etching liquid; then, the temporary mask of the middle portion 101 is removed.

[0084] In other optional embodiments, different etching times can be used to achieve non-uniform etching for the etching of the non-gate line area 120 of the middle part 101 and the edge part 102. For example, the etching time of the middle part 101 is longer than the etching time of the edge part 102. In this case, the non-gate line area 120 of the middle part 101 of the silicon wafer 100 will be corroded deeper than the non-gate line area 120 of the edge part 102. Optionally, the etching time of the non-gate line area 120 of the middle part 101 and the non-gate line area 120 of the edge part 102 should be selected based on relevant factors such as the parameters of the etching solution, the thickness of the doped polysilicon layer, and the depth to which the silicon wafer 100 is allowed to be etched. For example, the etching time of the middle part 101 is 3 minutes to 5 minutes, and the etching time of the edge part 102 is 2 minutes to 4 minutes. In an optional embodiment, all non-gridline areas 120 on the back of the solar cell 010 can be etched for a first time (e.g., 2 minutes to 4 minutes); then, a mold is used to form a barrier between the edge portion 102 and the middle portion 101 to confine the etching liquid to the middle portion 101, and the non-gridline areas 120 in the middle portion 101 are further etched for a second time (e.g., 30 seconds to 180 seconds). In another optional embodiment, all non-gridline areas 120 on the back of the solar cell 010 can be etched for a first time (e.g., 2 minutes to 4 minutes), and then, a temporary mask is used to cover the edge portion 102; then, the non-gridline areas 120 in the middle portion 101 are further etched for a second time (e.g., 30 seconds to 180 seconds) using an etching liquid. During this process, due to the presence of the temporary mask, the non-gridline areas 120 in the edge portion 102 will not be etched; finally, the temporary mask is removed.

[0085] In other optional embodiments, different process temperatures can be used to etch the non-gate line area 120 of the middle portion 101 and the edge portion 102 to achieve non-uniform etching. For example, the etching temperature of the middle portion 101 is greater than the etching temperature of the edge portion 102. It can be understood that, generally speaking, the higher the temperature, the better the thermodynamic and kinetic conditions of the chemical reaction, the easier the reaction is to proceed, and the faster the reaction rate. Therefore, when the etching temperature of the middle portion 101 is greater than the etching temperature of the edge portion 102, the non-gate line area 120 of the middle portion 101 of the silicon wafer 100 will be corroded deeper than the non-gate line area 120 of the edge portion 102. For example, the etching temperature of the edge portion 102 is room temperature, and the etching temperature of the middle portion 101 is 30°C to 60°C. A heating device can be used to synchronously heat the middle portion 101 of the silicon wafer 100 during the etching process; or the middle portion 101 of the silicon wafer 100 can be heated first to increase the temperature of the middle portion 101 to the target etching temperature, and then the doped polysilicon layer on the silicon wafer 100 can be wet-etched.

[0086] When fabricating the solar cell 010 (TOPCon cell) as shown in Figure 2 , in the wet etching process, in addition to removing the doped polysilicon layer in the non-grid line region 120, the tunneling oxide layer 500 in the non-grid line region 120 is also removed, resulting in the structure as shown in Figure 10 .

[0087] When fabricating the solar cell 010 (BC cell) as shown in Figure 4 , a part of the n-type doped polysilicon layer 400 and a corresponding part of the second dielectric layer 410 can be removed through the wet etching process to expose the non-grid line region 120 of the silicon wafer 100; a part of the p-type doped polysilicon layer 300 and a corresponding part of the first dielectric layer 310 can also be removed to expose the non-grid line region 120 of the silicon wafer 100; or, a part of the n-type doped polysilicon layer 400 and its corresponding part of the second dielectric layer 410, and a part of the p-type doped polysilicon layer 300 and a corresponding part of the first dielectric layer 310 can be removed to expose the non-grid line region 120 of the silicon wafer 100. Finally, the structure as shown in Figure 11 can be obtained.

[0088] In the embodiment of the present application, grooves are formed in the non-grid line regions 120 of both the middle part 101 and the edge part 102 of the silicon wafer 100 through the wet etching process. Among them, the groove depth of the non-grid line region 120 in the middle part 101 of the silicon wafer 100 is 1 μm to 5 μm, and the groove depth of the non-grid line region 120 in the edge part 102 of the silicon wafer 100 is 0.1 μm to 3 μm. Since the non-grid line region 120 in the middle part 101 of the silicon wafer 100 is etched deeper, the thickness of the non-grid line region 120 in the middle part 101 of the silicon wafer 100 is smaller than the thickness of the non-grid line region 120 in the edge part 102. This "thick edge and thin middle" structure is beneficial to improving the warping problem of the silicon wafer 100 and brings convenience to subsequent processing and assembly; moreover, the relatively thick edge thickness can effectively reduce the risk of damage to the solar cell 010 due to bumping. Optionally, the etching solution used in the wet etching process contains at least one of sodium hydroxide and potassium hydroxide.

[0089] Step S400, fabricating the grid lines 200 connected to the doped polysilicon layer.

[0090] In the embodiment of the present application, the first grid line 201 is connected to the p-type doped polysilicon layer 300, and the second grid line 202 is connected to the n-type doped polysilicon layer 400.

[0091] To fabricate as shown in Figure 2Taking the solar cell 010 (TOPCon cell) shown as an example, before fabricating the first grid line 201 and the second grid line 202, a first passivation layer 610 can be prepared on the side of the p-type doped polysilicon layer 300 facing away from the silicon wafer 100, and a second passivation layer 620 can be prepared on the non-grid line area 120 on the back side of the silicon wafer 100 and on the side of the n-type doped polysilicon layer 400 facing away from the silicon wafer 100; then the first grid line 201 and the second grid line 202 are fabricated, obtaining the solar cell 010 as shown in Figure 2 the solar cell 010 shown.

[0092] Taking the fabrication of the solar cell 010 (BC cell) as shown in Figure 4 as an example, before fabricating the first grid line 201 and the second grid line 202, a first passivation layer 610 can be prepared on the front side of the silicon wafer 100, and a second passivation layer 620 can be prepared on the non-grid line area 120 on the back side of the silicon wafer 100 and on the sides of the p-type doped polysilicon layer 300 and the n-type doped polysilicon layer 400 facing away from the silicon wafer 100; then the first grid line 201 and the second grid line 202 are fabricated, obtaining the solar cell 010 as shown in Figure 4 the solar cell 010 shown.

[0093] Optionally, the first passivation layer 610 and the second passivation layer 620 can be prepared by a chemical vapor deposition process or an atomic layer deposition process; the first passivation layer 610 and the second passivation layer 620 can be a single-layer structure formed by a single material (such as an alumina layer, a silica layer, a silicon oxynitride layer, or a silicon nitride layer), or a composite layer structure formed by multiple materials.

[0094] During the process of fabricating the grid line 200, the second grid line 202 can be printed on the second passivation layer 620 corresponding to the area of the n-type doped polysilicon layer 400; thereafter, the first grid line 201 is printed on the first passivation layer 610 corresponding to the area of the p-type doped polysilicon layer 300; finally, the first grid line 201 and the second grid line 202 are sintered. Ultimately, the solar cell 010 as shown in Figure 2 or Figure 4 the solar cell 010 shown can be obtained.

[0095] The embodiment of the present application also provides a photovoltaic module (not shown in the figure), which includes the solar cell 010 provided in the above embodiment of the present application, or includes the solar cell 010 fabricated by the fabrication method provided in the above embodiment of the present application.

[0096] In summary, the embodiments of the present application provide a solar cell 010, a preparation method thereof, and a photovoltaic module. The solar cell 010 provided by the embodiments of the present application is a tunnel oxide passivated contact cell or a back contact cell, which includes a silicon wafer 100, a doped polysilicon layer, and grid lines 200. At least one side of the silicon wafer 100 has a grid line region 110 and a non-grid line region 120. The doped polysilicon layer covers the grid line region 110, and the grid lines 200 are connected to the doped polysilicon layer. The silicon wafer 100 has a middle part 101 and an edge part 102. The edge part 102 forms the edge of the silicon wafer 100 and surrounds the middle part 101. The thickness of the silicon wafer 100 at the non-grid line region 120 of the edge part 102 is greater than the thickness of the silicon wafer 100 at the non-grid line region 120 of the middle part 101. In the embodiments of the present application, since the non-grid line region 120 of the edge part 102 has a greater thickness than the non-grid line region 120 of the middle part 101, its structural strength is better than that of the middle part 101. And the edge part 102 is exactly the position where warping and hidden cracks are likely to occur, and it is also the position where it is easy to be knocked. Therefore, in the embodiments of the present application, strengthening the edge part 102 of the silicon wafer 100 can improve the reliability of the entire silicon wafer 100 and even the entire solar cell 010, making the silicon wafer 100 and the solar cell 010 not easy to warp, have hidden cracks or break, and not easy to be damaged due to knocking. During the processing of the solar cell 010, during the assembly process of the photovoltaic module, and during the subsequent use process of the photovoltaic module, the silicon wafer 100 with better reliability can make the solar cell 010 have a higher product yield, better performance, and a longer service life.

[0097] The preparation method of the solar cell 010 provided by the embodiments of the present application can be used to prepare the above-mentioned solar cell 010. The photovoltaic module provided by the embodiments of the present application includes the above-mentioned solar cell 010 or the solar cell 010 prepared by the above-mentioned preparation method. Therefore, it also has the characteristics of high product yield, good reliability, and long service life.

[0098] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application.

Claims

1. A solar cell, characterized in that, The solar cell (010) is a tunnel oxide passivated contact cell or a back contact cell. The solar cell (010) includes a silicon wafer (100), a doped polysilicon layer, and grid lines (200). At least one side of the silicon wafer (100) has a grid line region (110) and a non-grid line region (120). The doped polysilicon layer covers the grid line region (110), and the grid lines (200) are connected to the doped polysilicon layer; The silicon wafer (100) has a middle part (101) and an edge part (102). The edge part (102) forms the edge of the silicon wafer (100) and surrounds the middle part (101). The dimension of the edge part (102) in its width direction is 1% - 30% of the dimension of the silicon wafer (100) in the same direction. Wherein, the width direction of the edge part (102) is parallel to the silicon wafer (100) and perpendicular to the edge of the silicon wafer (100). The thickness of the silicon wafer (100) at the non-grid line region (120) in the edge part (102) is greater than the thickness of the silicon wafer (100) at the non-grid line region (120) in the middle part (101).

2. The solar cell according to claim 1, wherein, The dimension of the edge part (102) in its width direction is 1 - 70 mm.

3. The solar cell according to claim 1, characterized in that, Grooves are formed in the non-grid line region (120) of the silicon wafer (100). The depth of the grooves in the edge part (102) is less than the depth of the grooves in the middle part (101).

4. The solar cell according to claim 3, characterized in that, The depth of the grooves in the edge part (102) is 0.1 - 3 μm, and the depth of the grooves in the middle part (101) is 1 - 5 μm.

5. The solar cell according to claim 3, wherein The grooves are formed on the back surface of the silicon wafer (100).

6. The method for preparing a solar cell according to any one of claims 1-5, characterized in that, Including: Obtaining the silicon wafer; Depositing the doped polysilicon layer on the silicon wafer; Etching to remove the doped polysilicon layer in the non-grid line region and part of the silicon wafer, wherein the etching depth of the silicon wafer in the middle part is greater than the etching depth of the silicon wafer in the edge part; Fabricating grid lines connected to the doped polysilicon layer.

7. The manufacturing method of the solar cell according to claim 6, characterized in that, The step of etching to remove the doped polysilicon layer in the non-grid line region and part of the silicon wafer includes: Irradiating the doped polysilicon layer in the non-grid line region with a laser; Removing the doped polysilicon layer in the non-grid line region and part of the silicon wafer by a wet etching process.

8. The manufacturing method of the solar cell according to claim 7, characterized in that, In the step of irradiating the doped polysilicon layer in the non-grid line region with a laser, the laser energy per unit area in the non-grid line region of the middle part is greater than the laser energy per unit area in the non-grid line region of the edge part.

9. The method for preparing a solar cell according to claim 8, wherein, The laser energy per unit area of the non-grid line region of the middle part is 210 mJ / cm 2 ~380 mJ / cm 2 ; the laser energy per unit area of the non-grid line region of the edge part is 180 mJ / cm 2 ~350 mJ / cm 2 .

10. The manufacturing method of the solar cell according to claim 8, characterized in that, In the step of irradiating the doped polysilicon layer in the non-grid line region with a laser, the irradiation duration in the non-grid line region of the middle part is greater than the irradiation duration in the non-grid line region of the edge part, and / or, the irradiation power in the non-grid line region of the middle part is greater than the irradiation power in the non-grid line region of the edge part.

11. The manufacturing method of the solar cell according to claim 7, characterized in that, The step of removing the doped polysilicon layer in the non-grid line region and part of the silicon wafer by a wet etching process includes: Etch the non-grid line area of the middle part with the first etching solution, and etch the non-grid line area of the edge part with the second etching solution; Wherein, the corrosiveness of the first etching solution is stronger than that of the second etching solution, and / or, the concentration of the first etching solution is greater than that of the second etching solution.

12. The method for preparing a solar cell according to claim 7, wherein In the step of removing the doped polysilicon layer in the non-grid line area and part of the silicon wafer by wet etching process, the etching duration of the middle part is longer than that of the edge part, and / or, the etching temperature of the middle part is higher than that of the edge part.

13. The preparation method of the solar cell according to any one of claims 7-12, characterized in that, The laser is a green laser.

14. The manufacturing method of a solar cell according to any one of claims 7-12, characterized in that, The etching solution used in the wet etching process contains at least one of sodium hydroxide and potassium hydroxide.

15. A photovoltaic module, characterized in that, Including the solar cell described in any one of claims 1-5, or, the solar cell prepared by the preparation method of the solar cell described in any one of claims 6-14.

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