Method of manufacturing display device

Abstract

A method of manufacturing a display device is provided. The method includes aligning a metal layer disposed on a transfer substrate and a display substrate facing each other; attaching a light emitting element including a metal protruding portion bonded to the metal layer to an overcoat layer of the display substrate by moving the transfer substrate relative to the display substrate; and separating the metal protruding portion from the light emitting element by moving the transfer substrate relative to the display substrate.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0195515, filed with the Korean Intellectual Property Office on December 28, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a method of manufacturing a display device. Background art

[0004] A display device displays an image by combining light emitted from a plurality of light - emitting elements. To manufacture a display device, a series of processes may be performed: manufacturing a plurality of light - emitting elements, transferring the light - emitting elements, and then providing the light - emitting elements on a display substrate. Deterioration in reliability in the process of transferring a plurality of light - emitting elements and / or in the process of providing the light - emitting elements on the display substrate is a problem.

[0005] It is to be understood that this background art section is intended to provide useful background for understanding the technology in part. However, this background art section may also include concepts, ideas, or cognitions that are not known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0006] Embodiments provide a method of manufacturing a display device in which reliability is improved.

[0007] According to an aspect of the present disclosure, there is provided a method of manufacturing a display device. The method may include: aligning a metal layer provided on a transfer substrate and a display substrate to face each other; attaching a light - emitting element including a metal protrusion portion joined to the metal layer to an outer coating of the display substrate by moving the transfer substrate relative to the display substrate; and separating the metal protrusion portion from the light - emitting element by moving the transfer substrate relative to the display substrate.

[0008] During the process of separating the metal protrusion portion from the light - emitting element, the joining between the metal protrusion portion and the metal layer may be maintained.

[0009] During the process of separating the metal protrusion portion from the light - emitting element, the attachment between the light - emitting element and the outer coating may be maintained.

[0010] The light - emitting element may further include: a light - emitting stack structure including a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer. The light - emitting element may further include a first bonding electrode electrically connected to the first semiconductor layer, a second bonding electrode electrically connected to the second semiconductor layer, and an insulating film covering at least a part of the outer peripheral surface of the light - emitting stack structure.

[0011] Before separating the metal protrusion from the light-emitting element, the metal protrusion may be in a state in which the metal protrusion is joined to an insulating film covering the surface of the light-emitting stack structure.

[0012] Each of the first bonding electrode and the second bonding electrode may protrude in a direction in which the metal protrusion protrudes from the surface of the light-emitting stack structure.

[0013] The metal protrusion may protrude much more than the first bonding electrode and the second bonding electrode in a direction in which the metal protrusion protrudes.

[0014] The bonding force between the metal protrusion and the insulating film may be weaker than the adhesive force between the light-emitting element and the outer coating.

[0015] The bonding force between the metal protrusion and the insulating film may be weaker than the bonding force between the metal protrusion and the metal layer.

[0016] The bonding force between the metal protrusion and the metal layer may be weaker than the adhesive force between the light-emitting element and the outer coating.

[0017] Each of the first bonding electrode and the second bonding electrode may be spaced apart from the metal protrusion.

[0018] The method may further include: before aligning the metal layer provided on the transfer substrate and the display substrate facing each other, aligning the metal layer provided on the transfer substrate and the metal protrusion included in the light-emitting element formed on the surface of the growth substrate in physical contact with each other; joining the metal protrusion and the metal layer to each other; and separating the light-emitting element from the growth substrate.

[0019] Separating the light-emitting element from the growth substrate may include irradiating a first laser to an area where the growth substrate and the light-emitting element are in physical contact with each other.

[0020] Joining the metal protrusion and the metal layer to each other may include: irradiating a second laser to an area where the metal protrusion and the metal layer are in physical contact with each other.

[0021] Joining the metal protrusion and the metal layer to each other may include: allowing the metal layer and the metal protrusion to form an alloy in an area where the metal protrusion and the metal layer are in physical contact with each other.

[0022] According to another aspect of the present disclosure, a method of manufacturing a display device is provided. The method may include: aligning a metal layer disposed on a transfer substrate and a display substrate facing each other; attaching a light-emitting element including a metal protrusion portion joined to the metal layer to an outer coating of the display substrate by moving the transfer substrate relative to the display substrate; and separating the metal protrusion portion from the metal layer by moving the transfer substrate relative to the display substrate. The light-emitting element may further include: a light-emitting stack structure including a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; a first bonding electrode electrically connected to the first semiconductor layer; and a second bonding electrode electrically connected to the second semiconductor layer. The metal protrusion portion may include at least one of a first metal protrusion portion overlapping with the first bonding electrode and a second metal protrusion portion overlapping with the second bonding electrode.

[0023] During the process of separating the metal protrusion portion from the metal layer, the attachment between the light-emitting element and the outer coating may be maintained.

[0024] The bonding force between the metal protrusion portion and the metal layer may be weaker than the adhesion force between the light-emitting element and the outer coating.

[0025] The method may further include: before aligning the metal layer disposed on the transfer substrate and the display substrate facing each other, aligning the metal layer disposed on the transfer substrate and the metal protrusion portion included in the light-emitting element formed on the surface of the growth substrate in physical contact with each other; joining the metal protrusion portion and the metal layer to each other; and separating the light-emitting element from the growth substrate.

[0026] Joining the metal protrusion portion and the metal layer to each other may include: allowing the metal layer and the metal protrusion portion to form an alloy in a region where the metal protrusion portion and the metal layer are in physical contact with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0028] In the drawings, for clarity of illustration, dimensions may be exaggerated. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or there can also be one or more intervening elements. The same reference numerals always denote the same elements.

[0029] Figure 1 is a schematic block diagram showing a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is a schematic block diagram showing any one of the sub-pixels among the sub-pixels included in the Figure 1 display device shown in

[0031] Figure 3 is a schematic plan view showing the display panel constituting the Figure 1 display device shown in

[0032] Figure 4 is a schematic cross-sectional view showing an embodiment of the Figure 3 display panel shown in

[0033] Figure 5 is a schematic cross-sectional view showing another embodiment of the Figure 3 display panel shown in

[0034] Figure 6 is a schematic plan view showing any one of the pixels among the pixels included in the Figure 3 display panel shown in

[0035] Figure 7 and Figure 8 is a schematic cross-sectional view showing the Figure 6 pixel shown in

[0036] Figure 9 is a flowchart showing a method of manufacturing a display device according to an embodiment of the present disclosure.

[0037] Figures 10 to 16 is a schematic view showing the Figure 9 method shown in

[0038] Figure 17 is a flowchart showing a method of manufacturing a display device according to another embodiment of the present disclosure.

[0039] Figures 18 to 24 is a schematic view showing the Figure 17 method shown in

[0040] Figure 25 is a schematic block diagram showing a display system according to an embodiment of the present disclosure.

[0041] Figures 26 to 29 is a schematic perspective view showing an application example of the Figure 25 display system shown in Detailed Description

[0042] In the following, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operations according to the present disclosure are described, and descriptions of other parts are omitted so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the embodiments described herein, but may be implemented in various different forms. More precisely, the embodiments described herein are provided to thoroughly and completely describe the disclosed content and to effectively convey the idea of the present disclosure to those of ordinary skill in the art.

[0043] As used herein, the singular forms "a", "an" and "the" are intended to include the plural meanings as well, unless the context clearly indicates otherwise.

[0044] In this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or directly coupled to the other element, or indirectly connected or indirectly coupled to the other element, with one or more intervening elements interposed therebetween. It will be understood that when a component "comprises", "has" or "includes" an element, unless otherwise described to the contrary, it should be understood that the component does not exclude another element, but may also include another element. It will be understood that for the purposes of the present disclosure, "at least one of X, Y and Z" can be understood as only X, only Y, only Z, or any combination of two or more items among X, Y and Z (e.g., XYZ or YZ). Similarly, for the purposes of the present disclosure, "at least one selected from the group consisting of X, Y and Z" can be understood as only X, only Y, only Z, or any combination of two or more items among X, Y and Z (e.g., XYZ or YZ).

[0045] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element.

[0046] Spatial relative terms such as "below", "above", etc. may be used herein for convenience of description to describe the relationship between one element and another as shown in the drawings. It will be understood that, in addition to the orientations described herein and depicted in the drawings, the spatial relative terms and the configurations shown are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "above" can encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0047] In addition, embodiments of the present disclosure are described with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes as illustrated can be anticipated due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing techniques. The regions shown in the drawings are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0048] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0049] It will be understood that the term "connected to" or "coupled to" can include a physical connection or physical coupling, or an electrical connection or electrical coupling.

[0050] The terms "facing" and "oriented towards" mean that a first element can be directly or indirectly opposite a second element. In the case where a third element is interposed between the first element and the second element, the first element and the second element can be understood to be indirectly opposite each other although still facing each other.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0052] Figure 1 is a schematic block diagram showing a display device according to an embodiment of the present disclosure.

[0053] Referring to Figure 1 , the display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0054] The display panel DP may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through a first gate line GL1 to an m-th gate line GLm. The sub-pixels SP may be connected to the data driver 130 through a first data line DL1 to an n-th data line DLn.

[0055] The sub-pixel SP can generate light of two or more colors. For example, each of the sub-pixels SP can generate light such as red, green, blue, cyan, magenta, yellow, white, etc.

[0056] Two or more of the sub-pixels among the sub-pixels SP can form a pixel PXL. For example, as Figure 1 shown, the pixel PXL can include three sub-pixels. The pixel PXL can emit various colors of light with various brightness levels according to the combination of light emitted from the sub-pixels included in the pixel PXL.

[0057] The gate driver 120 can be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 can output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0058] The gate driver 120 can be disposed on one side of the display panel DP. However, the embodiment is not limited thereto. For example, the gate driver 120 can be divided into two or more drivers that are physically and / or logically separated, and these drivers can be disposed on one side of the display panel DP and the other side of the display panel DP opposite to the one side. Therefore, in some embodiments, the gate driver 120 can be disposed at the periphery of the display panel DP in various forms.

[0059] The data driver 130 can be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS can include a source start pulse, a source shift clock, a source output enable signal, etc.

[0060] The data driver 130 can receive a voltage from the voltage generator 140. The data driver 130 can apply a data signal having a gray-scale voltage corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn by using the received voltage. In the case where a gate signal is applied to each of the first gate line GL1 to the m-th gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data line DL1 to the n-th data line DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Therefore, an image can be displayed on the display panel DP.

[0061] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0062] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate a voltage and provide the generated voltage to components of the display device DD. The voltage generator 140 may generate a voltage by receiving an input voltage from outside the display device DD and adjusting the received voltage.

[0063] The voltage generator 140 may generate a first power voltage and a second power voltage. The generated first power voltage and second power voltage may be provided to the sub-pixel SP through a power line PL. In other embodiments, at least one of the first power voltage and the second power voltage may be provided from outside the display device DD.

[0064] The voltage generator 140 may provide various voltages and / or signals. For example, the voltage generator 140 may provide one or more initialization voltages applied to the sub-pixel SP. For example, in a sensing operation for sensing the electrical characteristics of transistors and / or light-emitting elements of the sub-pixel SP, a predetermined or selected reference voltage may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate a reference voltage and transmit the reference voltage to the data driver 130. For example, in a display operation for displaying an image on the display panel DP, a common pixel control signal may be applied to the sub-pixel SP, and the voltage generator 140 may generate a pixel control signal. In an embodiment, the voltage generator 140 may provide a pixel control signal to the sub-pixel SP through a pixel control line PXCL. In Figure 1 it is shown that the pixel control line PXCL is connected between the voltage generator 140 and the display panel DP. However, the embodiment is not limited thereto. For example, the pixel control line PXCL may be connected between the gate driver 120 and the display panel DP. The pixel control signal may be transmitted from the gate driver 120 to the sub-pixel SP through the pixel control line PXCL.

[0065] The controller 150 may control the overall operation of the display device DD. The controller 150 may receive input image data IMG and a control signal CTRL corresponding to the input image data IMG from outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0066] The controller 150 may convert the input image data IMG to be suitable for the display device DD or the display panel DP, and thus output the image data DATA. In an embodiment, the controller 150 may align the input image data IMG in units of rows to be suitable for the sub-pixels SP, and thus output the image data DATA.

[0067] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted in one integrated circuit. As Figure 1 shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. The data driver 130, the voltage generator 140, and the controller 150 may be components functionally divided in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component different from the driver integrated circuit DIC.

[0068] Figure 2 is a schematic block diagram showing any one of the sub-pixels included in the Figure 1 display device shown in Figure 2 In Figure 1 shown, the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP shown in

[0069] Refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0070] The light-emitting element LD may be connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. The first power supply voltage node VDDN may be connected to Figure 1 one of the power lines PL shown in

[0071] to receive the first power supply voltage. The second power supply voltage node VSSN may be connected to the other of the power lines PL to receive the second power supply voltage. The first power supply voltage may have a voltage level higher than the voltage level of the second power supply voltage.

[0072] The sub-pixel circuit SPC can be connected to Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm shown in Figure 1 and the j-th data line DLj among the first data line DL1 to the n-th data line DLn shown in Figure 1 . In response to the gate signal received through the i-th gate line GLi, the sub-pixel circuit SPC can control the light-emitting element LD to emit light according to the data signal received through the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC can also be connected to

[0073] the pixel control line PXCL shown in

[0074] The sub-pixel circuit SPC can further control the light-emitting element LD in response to the control signal received through the pixel control line PXCL.

[0075] Figure 3 is a schematic plan view showing the display panel of the display device shown in Figure 1

[0076] Referring to Figure 3 , the display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be provided at the periphery of the display area DA.

[0077] The display panel DP can include sub-pixels SP provided in the display area DA. The sub-pixels SP can be arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP can be arranged in a matrix form along the first direction DR1 and the second direction DR2. In another example, the sub-pixels SP can be arranged in a zigzag form along the first direction DR1 and the second direction DR2. In some embodiments, the arrangement of the sub-pixels SP can vary. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0078] Two or more of the sub-pixels SP can constitute a pixel PXL. In Figure 3 ​In [the figure], it is shown that pixel PXL includes three sub-pixels SP1, SP2, and SP3. However, the embodiments are not limited thereto. For example, pixel PXL may include two sub-pixels. Hereinafter, for ease of description, it is assumed that pixel PXL includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0079] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of one of various colors such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for clear and simple description, it is assumed that the first sub-pixel SP1 is configured to generate red light, the second sub-pixel SP2 is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0080] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include at least one light-emitting element configured to generate light. In an embodiment, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of the same color. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate blue light. In other embodiments, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate red, green, and blue light, respectively.

[0081] A self-emitting display panel (such as a light-emitting diode display panel (LED display panel) using micron-scale or nano-scale light-emitting diodes as light-emitting elements and an organic light-emitting display panel (OLED panel) using organic light-emitting diodes as light-emitting elements) may be used as the display panel DP.

[0082] Components for controlling the sub-pixel SP may be provided in the non-display area NDA. Wires connected to the sub-pixel SP (e.g., Figure 1 the first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL shown in [the figure]) may be provided in the non-display area NDA.

[0083] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 shown in [the figure] may be provided in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 may be provided in the non-display area NDA. The data driver 130, the voltage generator 140, and the controller 150 may be implemented into Figure 1in a driver integrated circuit (DIC) different from the display panel DP as shown, and the driver integrated circuit DIC can be connected to lines provided in the non-display area NDA. In other embodiments, the gate driver 120, data driver 130, voltage generator 140, and controller 150 can be implemented in one integrated circuit different from the display panel DP.

[0084] In an embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including linear edges and / or curved edges. For example, the display area DA can have a shape such as a polygon, circle, semi-circle, or ellipse.

[0085] In an embodiment, the display panel DP can have a flat display surface. In other embodiments, the display panel DP can at least partially have a rounded display surface. In an embodiment, the display panel DP can be bendable, foldable, or rollable. The display panel DP and / or the substrate of the display panel DP can include a flexible material.

[0086] Figure 4 is a schematic cross-sectional view showing Figure 3 an embodiment of the display panel shown in

[0087] Referring to Figure 4 , the display panel DP can include a base substrate SUB, a pixel circuit layer PCL, a display panel layer DPL, and a light conversion layer LCL that can be stacked on top of each other in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The third direction DR3 can be, for example, the thickness direction of the base substrate SUB.

[0088] The base substrate SUB can be made of an insulating material such as glass or resin. For example, the base substrate SUB can include a glass substrate. In another example, the base substrate SUB can include a polyimide (PI) substrate. In yet another example, the base substrate SUB can include a silicon wafer substrate formed using semiconductor processes.

[0089] In an embodiment, the base substrate SUB can be made of a flexible material for bendability or foldability and have a single-layer structure or a multi-layer structure. For example, the flexible material can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0090] The pixel circuit layer PCL may be disposed on the base substrate SUB. The pixel circuit layer PCL may include an insulating layer and semiconductor patterns and conductive patterns that may be disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as circuit elements, wires, etc.

[0091] The circuit elements of the pixel circuit layer PCL may include Figure 3 the sub-pixel circuits ( Figure 2 SPCs) of each of the sub-pixels SP shown in

[0092] In other words, the circuit elements of the pixel circuit layer PCL may be provided as transistors and one or more capacitors of the sub-pixel circuit SPC.

[0093] The display panel layer DPL may be disposed on the pixel circuit layer PCL. The display panel layer DPL may include light-emitting elements of the sub-pixels SP.

[0094] The light conversion layer LCL may be disposed on the display panel layer DPL. The light conversion layer LCL may include a light conversion pattern having color conversion particles and / or light scattering particles. For example, the color conversion particles may include quantum dots. The quantum dots may change the wavelength (or color) of the light emitted from the display panel layer DPL. In an embodiment, the light conversion pattern may be omitted.

[0095] The light conversion layer LCL may further include a color filter layer including color filters. The color filters may allow light having a specific wavelength (or specific color) to selectively transmit through the color filters. In an embodiment, the color filter layer may be omitted.

[0096] A window for protecting the exposed surface (or top surface) of the display panel DP may be disposed on the light conversion layer LCL. The window may protect the display panel DP from external impacts. The window may be joined to the light conversion layer LCL by an optically transparent adhesive (or bonding) member. The window may have a multi-layer structure selected from a glass substrate, a plastic film, and a plastic substrate. Such a multi-layer structure may be formed by a continuous process or a bonding process using an adhesive layer. All or part of the window may be flexible.

[0097] Figure 5 is a schematic cross-sectional view showing Figure 3 another embodiment of the display panel shown in

[0098] Reference Figure 5, the display panel DP' may include a base substrate SUB, a pixel circuit layer PCL, a display panel layer DPL, an input sensing layer ISL, and a light conversion layer LCL. The base substrate SUB, the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL may be configured to be substantially the same as or similar to the base substrate SUB, the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL described with reference to Figure 4 Therefore, redundant descriptions will be omitted.

[0099] The input sensing layer ISL may sense an input of a user with respect to the top surface (or display surface) of the display panel DP'. The input sensing layer ISL may include components adapted to sense an external object such as a user's hand or a pen. For example, the input sensing layer ISL may include touch electrodes.

[0100] Figure 6 is a schematic plan view showing any one of the pixels included in the display panel shown in Figure 3 .

[0101] With reference to Figure 6 , the pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in a first direction DR1. However, the arrangement of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 included in the pixel PXL is not limited thereto and may be variously changed in some embodiments. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in a zigzag pattern.

[0102] A first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 may be respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first anode electrode AE1 may be disposed to be connected to the anode electrode ( Figure 2 shown in Figure 2 ) of the sub-pixel circuit (SPC shown in Figure 2 ) of the first sub-pixel SP1. The second anode electrode AE2 may be disposed to be connected to the anode electrode ( Figure 2 ) of the sub-pixel circuit (SPC shown in Figure 2 ) of the second sub-pixel SP2. The third anode electrode AE3 may be disposed to be connected to the anode electrode ( Figure 2 ) of the sub-pixel circuit (SPC shown in

[0103] The cathode electrode CE can be spaced apart from the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The cathode electrode CE and the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be disposed at the same height. The cathode electrode CE can be spaced apart from the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 in the second direction DR2. In an embodiment, the cathode electrode CE can extend in the first direction DR1 to serve as the cathode electrode for the pixel PXL and other pixels adjacent to the pixel PXL. Although not shown in the drawings, the cathode electrode CE can extend in the second direction DR2 in addition to the first direction DR1 to serve as the cathode electrode for Figure 3 all the sub-pixels SP shown in

[0104] The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be disposed on the first anode electrode AE1, the second anode electrode AE2, the third anode electrode AE3, and the cathode electrode CE. The first light-emitting element LD1 can be electrically connected to the first anode electrode AE1 and the cathode electrode CE. The first light-emitting element LD1 can be disposed as the light-emitting element ( Figure 2 LD shown in Figure 2 ) of the sub-pixel circuit ( Figure 2 SPC shown in Figure 2 ) connected to the first sub-pixel SP1. The second light-emitting element LD2 can be electrically connected to the second anode electrode AE2 and the cathode electrode CE. The second light-emitting element LD2 can be disposed as the light-emitting element ( Figure 2 ) of the sub-pixel circuit ( Figure 2 SPC shown in

[0105] ) connected to the second sub-pixel SP2. The third light-emitting element LD3 can be electrically connected to the third anode electrode AE3 and the cathode electrode CE. The third light-emitting element LD3 can be disposed as the light-emitting element (

[0106] Figure 7 ) of the sub-pixel circuit ( Figure 6 SPC shown in

[0107] ) connected to the third sub-pixel SP3. Figure 6 and Figure 7, the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL can be sequentially disposed on the base substrate SUB.

[0108] The pixel circuit layer PCL may include an insulating layer, a semiconductor pattern, and a conductive pattern that can be stacked on each other on the base substrate SUB. The insulating layer may include a buffer layer BFL, one or more interlayer insulating layers ILD, and one or more passivation layers PSV1, PSV2, and PSV3. The semiconductor pattern and the conductive pattern may be located between the insulating layers. The conductive pattern may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0109] As described in the reference Figure 2 , the sub-pixel circuit ( Figure 2 SPC shown in) of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a transistor and one or more capacitors. The semiconductor pattern and the conductive pattern of the pixel circuit layer PCL may be used as the transistor and the capacitor of the sub-pixel circuit SPC. In addition, the conductive pattern of the pixel circuit layer PCL may also be used as a line, for example, Figure 1 the first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL shown in.

[0110] The buffer layer BFL may be disposed on the base substrate SUB. The buffer layer BFL may prevent impurities from diffusing into the semiconductor pattern and the conductive pattern included in the pixel circuit layer PCL. The buffer layer BFL may include an inorganic insulating material. For example, the buffer layer BFL may include silicon nitride, silicon oxide, silicon oxynitride, and / or aluminum oxide.

[0111] The transistor T_SP may be disposed on the buffer layer BFL. The transistor T_SP may include a semiconductor pattern SCP, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1 may be either a source electrode or a drain electrode, and the second terminal ET2 may be the other of the source electrode and the drain electrode.

[0112] The semiconductor pattern SCP may be disposed on the buffer layer BFL. The semiconductor pattern SCP may include a first contact region connected to the first terminal ET1 and a second contact region connected to the second terminal ET2. The region between the first contact region and the second contact region may be a channel region. The channel region may overlap with the gate electrode GE of the transistor T_SP. The channel region is a semiconductor pattern that is substantially undoped with impurities. Each of the first contact region and the second contact region is a semiconductor pattern doped with impurities and may be a region having relatively high conductivity. The semiconductor pattern SCP may include at least one of, for example, amorphous silicon semiconductor, single crystal silicon semiconductor, polycrystalline silicon semiconductor, low temperature polycrystalline silicon semiconductor, and oxide semiconductor.

[0113] The sequentially stacked interlayer insulating layers ILD may be disposed over the semiconductor pattern SCP. The interlayer insulating layers ILD may include an inorganic insulating material and / or an organic insulating material. For example, each of the interlayer insulating layers ILD may independently include silicon nitride, silicon oxide, silicon oxynitride, and / or aluminum oxide.

[0114] The interlayer insulating layers ILD may electrically isolate the conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers ILD. For example, the interlayer insulating layer ILD may include a gate insulating layer GI disposed on the semiconductor pattern SCP. The gate insulating layer GI may be disposed between the semiconductor pattern SCP and the gate electrode GE such that the gate electrode GE and the semiconductor pattern SCP are spaced apart. In an embodiment, the gate insulating layer GI may be completely disposed on the semiconductor pattern SCP and the buffer layer BFL to cover the semiconductor pattern SCP and the buffer layer BFL. When the number of required layers in the conductive pattern and / or semiconductor pattern increases, the number of interlayer insulating layers ILD may increase.

[0115] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap with the channel region of the semiconductor pattern SCP.

[0116] The first terminal ET1 and the second terminal ET2 may be disposed on the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 may be connected to the semiconductor pattern SCP through contact holes passing through the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 may be respectively connected to the first contact region and the second contact region of the semiconductor pattern SCP.

[0117] The first passivation layer PSV1 may be disposed on the interlayer insulating layer ILD. The passivation layers PSV1, PSV2, and PSV3 may be designated as a protective layer or a via layer. The first passivation layer PSV1 may protect the components disposed below the first passivation layer PSV1 and provide a flat top surface.

[0118] The connection pattern CP may be disposed on the first passivation layer PSV1. The connection pattern CP may be connected to the first terminal ET1 of the transistor T_SP while passing through the first passivation layer PSV1.

[0119] The second passivation layer PSV2 may be disposed on the connection pattern CP and the first passivation layer PSV1. The second passivation layer PSV2 may protect the components disposed thereunder and provide a flat top surface.

[0120] The first anode electrode AE1 and the cathode electrode CE may be disposed on the pixel circuit layer PCL. The first anode electrode AE1 may be electrically connected to the connection pattern CP through a contact hole passing through the second passivation layer PSV2. Thus, the first anode electrode AE1 may be electrically connected to the transistor T_SP. The cathode electrode CE may be spaced apart from the first anode electrode AE1. A common voltage may be applied to the cathode electrode CE.

[0121] The first bank BNK1 may be disposed on the first anode electrode AE1 and the cathode electrode CE. The first bank BNK1 may have a first opening OP1 exposing portions of the first anode electrode AE1 and the cathode electrode CE. The first bank BNK1 may be disposed as a pixel defining layer defining a region in which the first light emitting element LD1 is located.

[0122] The first bank BNK1 may be configured to include a light blocking material to prevent light mixing between adjacent sub-pixels. In an embodiment, the first bank BNK1 may include an organic insulating material. For example, the first bank BNK1 may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0123] The first reflective electrode RFE1 may be disposed on the exposed portion of the first anode electrode AE1 and the side surface of the first bank BNK1 adjacent to the first anode electrode AE1. The second reflective electrode RFE2 may be disposed on the exposed portion of the cathode electrode CE and the side surface of the first bank BNK1 adjacent to the cathode electrode CE. The first reflective electrode RFE1 and the second reflective electrode RFE2 may include a conductive material suitable for reflecting light. Thus, the first reflective electrode RFE1 and the second reflective electrode RFE2 may be used to improve the light emission efficiency of the light emitted from the first light emitting element LD1. The first reflective electrode RFE1 and the second reflective electrode RFE2 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0124] On the first reflective electrode RFE1, the second reflective electrode RFE2, and the second passivation layer PSV2, the outer coating OCL may be disposed in the first opening OP1 of the first bank BNK1. The outer coating OCL may be used to fix the first light-emitting element LD1 so that it does not move. In some embodiments, the outer coating OCL may include an adhesive (or bonding) material. Thus, the outer coating OCL may be used to protect the components disposed below the outer coating OCL from foreign substances such as dust or moisture.

[0125] The first light-emitting element LD1 may be attached to the outer coating OCL in the first opening OP1. In an embodiment, the first light-emitting element LD1 may be partially buried in the outer coating OCL. In other embodiments, the outer coating OCL may be only partially disposed in the region adjacent to the lower portion of the first light-emitting element LD1, and thus, the first light-emitting element LD1 may not be partially buried in the outer coating OCL.

[0126] The first light-emitting element LD1 may include a light-emitting stack structure EST, a first bonding electrode BDE1, a second bonding electrode BDE2, and an insulating film 15.

[0127] The light-emitting stack structure EST may include a first semiconductor layer 11, a second semiconductor layer 12 disposed below the first semiconductor layer 11, and an active layer 13 between the first semiconductor layer 11 and the second semiconductor layer 12. In an embodiment, the light-emitting stack structure EST may further include a auxiliary layer 14 disposed below the second semiconductor layer 12.

[0128] The first semiconductor layer 11 may provide holes to the active layer 13. The first semiconductor layer 11 may include at least one P-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and is a P-type semiconductor layer doped with a P-type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba). However, the material constituting the first semiconductor layer 11 is not limited thereto. In addition, various materials may constitute the first semiconductor layer 11. In an embodiment, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a P-type dopant.

[0129] The second semiconductor layer 12 may be spaced apart from the first semiconductor layer 11. The second semiconductor layer 12 may supply electrons to the active layer 13. The second semiconductor layer 12 may include at least one N-type semiconductor layer. For example, the second semiconductor layer 12 may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and is an N-type semiconductor layer doped with an N-type dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer 12 is not limited thereto. In addition, various materials may constitute the second semiconductor layer 12. In an embodiment, the second semiconductor layer 12 may include a gallium nitride (GaN) semiconductor material doped with an N-type dopant. In some embodiments, the second semiconductor layer 12 together with the auxiliary layer 14 may constitute an N-type semiconductor layer.

[0130] The active layer 13 may be between the first semiconductor layer 11 and the second semiconductor layer 12, and provide a region where electrons and holes recombine. When electrons and holes recombine in the active layer 13, light having an energy level changed to a low energy level and having a wavelength corresponding to the low energy level may be generated. The active layer 13 may be formed in a single quantum well structure or a multi quantum well structure. In the case where the active layer 13 is formed in a multi quantum well structure, units including a barrier layer, a strain enhancing layer, and a well layer may be repeatedly stacked with each other to form the active layer 13. However, the embodiment of the active layer 13 is not limited thereto.

[0131] The auxiliary layer 14 may include a gallium nitride (GaN) semiconductor material that is substantially undoped with impurities or doped with a relatively low concentration of impurities. The auxiliary layer 14 together with the second semiconductor layer 12 may constitute an N-type semiconductor layer.

[0132] The first bonding electrode BDE1 may be connected to the first semiconductor layer 11, and the second bonding electrode BDE2 may be connected to the second semiconductor layer 12. The first bonding electrode BDE1 may not be in physical contact with the second semiconductor layer 12, the active layer 13, and the second bonding electrode BDE2, and the second bonding electrode BDE2 may not be in physical contact with the first semiconductor layer 11 and the active layer 13. In an embodiment, the first bonding electrode BDE1 and the second bonding electrode BDE2 may protrude from the light-emitting stack structure EST in the same direction. For example, the first bonding electrode BDE1 and the second bonding electrode BDE2 may protrude in the third direction DR3.

[0133] The insulating film 15 may cover at least a portion of the outer peripheral surface of the light-emitting stack structure EST. For example, the insulating film 15 may completely cover other surfaces except the bottom surface of the auxiliary layer 14. In addition, the insulating film 15 may be configured to expose the first bonding electrode BDE1 and the second bonding electrode BDE2 protruding from the light-emitting stack structure EST. The insulating film 15 may be used to prevent a short circuit that may occur when the active layer 13 comes into contact with another conductive material other than the first semiconductor layer 11 and the second semiconductor layer 12. In an embodiment, the insulating film 15 may include a transparent insulating material.

[0134] The third passivation layer PSV3 may be disposed on the first reflective electrode RFE1, the second reflective electrode RFE2, the first light-emitting element LD1, and the outer coating OCL. The third passivation layer PSV3 may protect the components disposed below the third passivation layer PSV3 and provide a flat top surface. At least one of the first passivation layer PSV1 and the second passivation layer PSV2 and the third passivation layer PSV3 may include the same material, but the embodiments are not limited thereto.

[0135] The third passivation layer PSV3 may have a second opening OP2, a third opening OP3, a fourth opening OP4, and a fifth opening OP5. The second opening OP2 may expose the top surface of the first bonding electrode BDE1. The third opening OP3 may expose the top surface of the second bonding electrode BDE2. The fourth opening OP4 may expose the top surface of the first reflective electrode RFE1. The fifth opening OP5 may expose the top surface of the second reflective electrode RFE2.

[0136] The first transparent electrode ITO1 and the second transparent electrode ITO2 may be disposed on the third passivation layer PSV3. The first transparent electrode ITO1 may electrically connect the first bonding electrode BDE1 exposed by the second opening OP2 to the first reflective electrode RFE1 exposed by the fourth opening OP4. The second transparent electrode ITO2 may electrically connect the second bonding electrode BDE2 exposed by the third opening OP3 to the second reflective electrode RFE2 exposed by the fifth opening OP5. Accordingly, the first bonding electrode BDE1 may be electrically connected to the first anode electrode AE1. The second bonding electrode BDE2 may be electrically connected to the cathode electrode CE through the second transparent electrode ITO2 and the second reflective electrode RFE2.

[0137] In an embodiment, the first transparent electrode ITO1 and the second transparent electrode ITO2 may be substantially transparent or semi-transparent to meet a predetermined or selected light transmittance. For example, the first transparent electrode ITO1 and the second transparent electrode ITO2 may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first transparent electrode ITO1 and the second transparent electrode ITO2 are not limited thereto.

[0138] The capping layer CPL may be disposed over the third passivation layer PSV3. The capping layer CPL may be used to protect components (such as the first transparent electrode ITO1, the second transparent electrode ITO2, and the first light-emitting element LD1) disposed below the capping layer CPL from external moisture, humidity, etc. The capping layer CPL may include, for example, silicon nitride, silicon oxide, silicon oxynitride, and / or aluminum oxide.

[0139] In the foregoing, the pixel circuit layer PCL and the display panel layer DPL of the first sub-pixel SP1 have been described. Figure 6 Each of the second sub-pixel SP2 and the third sub-pixel SP3 shown therein may also be configured to be the same as or similar to the first sub-pixel SP1.

[0140] The light conversion layer LCL may be disposed on the capping layer CPL. The light conversion layer LCL may include a second bank BNK2, a reflective layer RFL, a fourth passivation layer PSV4, a first light conversion pattern CCP1, a low refractive index layer LRL, and a color filter layer CFL.

[0141] The second bank BNK2 may be disposed on the capping layer CPL. The second bank BNK2 may overlap with the first bank BNK1. The second bank BNK2 may have a sixth opening OP6 overlapping with the first opening OP1.

[0142] The second bank BNK2 may be configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In an embodiment, the second bank BNK2 may include an organic material. For example, the second bank BNK2 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0143] The reflective layer RFL may be disposed on a side surface of the second bank BNK2 adjacent to the sixth opening OP6. The reflective layer RFL is configured to reflect incident light and thus can improve the light emission efficiency. The reflective layer RFL may include a material suitable for reflecting light. The reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0144] On the capping layer CPL, a fourth passivation layer PSV4 is disposed in the sixth opening OP6. The fourth passivation layer PSV4 may protect components disposed below the fourth passivation layer PSV4 and provide a flat surface. At least one of the first passivation layer PSV1, the second passivation layer PSV2, and the third passivation layer PSV3 and the fourth passivation layer PSV4 may include the same material, but the embodiments are not limited thereto.

[0145] On the fourth passivation layer PSV4, a first light conversion pattern CCP1 may be disposed in the sixth opening OP6.

[0146] The first light conversion pattern CCP1 may include color conversion particles and / or light scattering particles. The color conversion particles may convert incident light into light of another color by changing the wavelength of the incident light. In addition, the color conversion particles may scatter the incident light. In an embodiment, the color conversion particles may be quantum dots. The light scattering particles may scatter the incident light.

[0147] The first sub-pixel SP1 may be a red sub-pixel. In the case where the first light-emitting element LD1 emits blue light, the first light conversion pattern CCP1 may include first color conversion particles QD1 configured to convert blue light into red light. In the case where the first light-emitting element LD1 emits red light, the first light conversion pattern CCP1 may include light scattering particles. Therefore, the light scattering particles included in the first light conversion pattern CCP1 may vary according to the color of the light emitted by the first light-emitting element LD1.

[0148] The low refractive index layer LRL may be disposed on the second bank BNK2, the reflective layer RFL, and the first light conversion pattern CCP1. The low refractive index layer LRL may have a refractive index lower than that of each of the first light conversion pattern CCP1 and the first color filter CF1. The low refractive index layer LRL may be configured to refract or totally reflect light according to the incident angle of the corresponding light. For example, the low refractive index layer LRL may provide the light passing through the first light conversion pattern CCP1 to the first light conversion pattern CCP1 again. Therefore, the light conversion efficiency of the first light conversion pattern CCP1 can be improved.

[0149] The color filter layer CFL may be disposed on the low refractive index layer LRL. The color filter layer CFL may include a first color filter CF1 and a light blocking pattern LBP. The first color filter CF1 may overlap with the first light conversion pattern CCP1. The first color filter CF1 may allow light in a desired wavelength range to selectively transmit through the first color filter CF1. In the case where the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. The light blocking pattern LBP may include at least one of various light blocking materials.

[0150] Figure 8 is a schematic cross-sectional view taken along Figure 6 the line B-B' shown in

[0151] Reference Figure 6 and Figure 8 , the pixel circuit layer PCL, the display panel layer DPL, and the light conversion layer LCL may be disposed on the base substrate SUB.

[0152] The pixel circuit layer PCL and the display panel layer DPL may be the same as those described in reference Figure 7 . In the pixel circuit layer PCL, sub-pixel circuits corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be provided. In the display panel layer DPL, a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be provided respectively. The first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may overlap with the first opening OP1 of the first bank BNK1. The first light emitting element LD1 may be connected between the cathode electrode CE and the transistor T_SP included in the sub-pixel circuit of the first sub-pixel SP1. The second light emitting element LD2 may be connected between the cathode electrode CE and the transistor included in the sub-pixel circuit of the second sub-pixel SP2. The third light emitting element LD3 may be connected between the cathode electrode CE and the transistor included in the sub-pixel circuit of the third sub-pixel SP3. Hereinafter, redundant descriptions will be omitted.

[0153] The light conversion layer LCL may be disposed on the display panel layer DPL. The light conversion layer LCL may be the same as the description in reference Figure 7 . Hereinafter, descriptions of the overlapping portions will be omitted.

[0154] The second bank BNK2 may have a sixth opening OP6. It can be seen that the emission areas EMA and non-emission areas NEMA of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be defined by the second bank BNK2. The area overlapping with the second bank BNK2 may be the non-emission area NEMA. The area overlapping with the sixth opening OP6 of the second bank BNK2 may be the emission areas EMA of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0155] On the capping layer CPL, a fourth passivation layer PSV4 may be disposed in the sixth opening OP6. On the fourth passivation layer PSV4, a first light conversion pattern CCP1, a second light conversion pattern CCP2, and a third light conversion pattern CCP3 may be disposed in the sixth opening OP6.

[0156] In an embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be configured to emit blue light. The first light conversion pattern CCP1 may include first color conversion particles QD1 configured to convert blue light into red light. The second light conversion pattern CCP2 may include second color conversion particles QD2 configured to convert blue light into green light. The third light conversion pattern CCP3 may include light scattering particles SCT that scatter blue light to improve light emission efficiency. Accordingly, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In an embodiment, at least one of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the third light conversion pattern CCP3 may further include color conversion particles configured to convert blue light into white light.

[0157] In an embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be configured to emit red, green, and blue light, respectively. Each of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the third light conversion pattern CCP3 may include light scattering particles SCT. Accordingly, the particles included in the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the third light conversion pattern CCP3 may vary according to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0158] In some embodiments, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the third light conversion pattern CCP3 may be omitted.

[0159] The low refractive index layer LRL may be disposed on the second bank BNK2, the reflective layer RFL, and the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the third light conversion pattern CCP3. The low refractive index layer LRL may have a refractive index lower than that of each of the first light conversion pattern CCP1, the second light conversion pattern CCP2, the third light conversion pattern CCP3, and the first color filter CF1, the second color filter CF2, and the third color filter CF3. In an embodiment, the low refractive index layer LRL may be omitted in the region corresponding to the third sub-pixel SP3.

[0160] The color filter layer CFL may be disposed on the low refractive index layer LRL. The color filter layer CFL may include the first color filter CF1, the second color filter CF2, the third color filter CF3, and the light blocking pattern LBP.

[0161] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may allow light in a desired wavelength range to selectively transmit through the first color filter CF1, the second color filter CF2, and the third color filter CF3. When the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. When the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 may include a green color filter. When the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter.

[0162] The light blocking pattern LBP may be disposed between the color filters CF1, CF2, and CF3. It can be seen that the emission regions (or light emitting regions) EMA and the non-emission regions NEMA of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be defined by the light blocking pattern LBP. The region overlapping with the light blocking pattern LBP may correspond to the non-emission region NEMA. The region not overlapping with the light blocking pattern LBP may correspond to the emission region EMA.

[0163] In an embodiment, the light blocking pattern LBP may include at least one of various light blocking materials. In an embodiment, each of the light blocking patterns LBP may be provided in a multi-layer form overlapping at least two of the first color filter CF1, the second color filter CF2, and the third color filter CF3. For example, each of the light blocking patterns LBP may be formed by the first color filter CF1, the second color filter CF2, and the third color filter CF3 overlapping each other. In another example, the light blocking pattern LBP between the first color filter CF1 and the second color filter CF2 among the light blocking patterns LBP may be formed into a multi-layer in which the first color filter CF1 and the second color filter CF2 overlap, and the light blocking pattern LBP between the second color filter CF2 and the third color filter CF3 among the light blocking patterns LBP may be formed into a multi-layer in which the second color filter CF2 and the third color filter CF3 overlap. The light blocking pattern LBP between the first color filter CF1 and the third color filter CF3 of adjacent pixels may be formed into a multi-layer in which the first color filter CF1 and the third color filter CF3 overlap. Accordingly, each of the first color filter CF1 to the third color filter CF3 may extend into the non-emission region NEMA to form the light blocking pattern LBP.

[0164] Figure 9 is a flowchart showing a method of manufacturing a display device according to an embodiment of the present disclosure.

[0165] Refer to Figure 9 , a method of manufacturing a display device according to an embodiment of the present disclosure may include a first step S1, a second step S2, a third step S3, a fourth step S4, a fifth step S5, and a sixth step S6. Hereinafter, the first step S1, the second step S2, the third step S3, the fourth step S4, the fifth step S5, and the sixth step S6 will be described with reference to Figures 10 to 16 .

[0166] Figures 10 to 16 is a schematic diagram showing Figure 9 the method shown in

[0167] Refer to Figure 10 , before the first step S1, a growth substrate SUB” and a light-emitting element LD formed on the surface of the growth substrate SUB” may be provided.

[0168] The growth substrate SUB” may be a substrate for forming the light-emitting element LD. For example, the growth substrate SUB” may be a silicon wafer substrate.

[0169] The light-emitting element LD may include a light-emitting stack structure EST, a first bonding electrode BDE1, a second bonding electrode BDE2, an insulating film 15, and a metal protrusion SAC.

[0170] The light-emitting stack structure EST may include a first semiconductor layer 11, a second semiconductor layer 12, and an active layer 13. In some embodiments, the light-emitting stack structure EST may further include a auxiliary layer 14. The auxiliary layer 14, the second semiconductor layer 12, the active layer 13, and the first semiconductor layer 11 may be stacked on top of each other in a direction away from the growth substrate SUB”. The first semiconductor layer 11, the second semiconductor layer 12, the active layer 13, and the auxiliary layer 14 may be substantially the same as or similar to the first semiconductor layer 11, the second semiconductor layer 12, the active layer 13, and the auxiliary layer 14 already described with reference to Figure 7 and thus redundant descriptions will be omitted.

[0171] The first bonding electrode BDE1 may be connected to the first semiconductor layer 11, and the second bonding electrode BDE2 may be connected to the second semiconductor layer 12. The first bonding electrode BDE1 may not be in physical contact with the second semiconductor layer 12, the active layer 13, and the second bonding electrode BDE2, and the second bonding electrode BDE2 may not be in physical contact with the first semiconductor layer 11 and the active layer 13. In an embodiment, the first bonding electrode BDE1 and the second bonding electrode BDE2 may protrude from the light-emitting stack structure EST in the same direction. For example, the first bonding electrode BDE1 and the second bonding electrode BDE2 may protrude in a direction away from the growth substrate SUB”.

[0172] The insulating film 15 may cover at least a portion of the outer peripheral surface of the light-emitting stack structure EST. For example, the insulating film 15 may completely cover the outer circumference of the light-emitting stack structure EST except for the surface in contact with the growth substrate SUB”, the surface connected to the first bonding electrode BDE1, and the surface connected to the second bonding electrode BDE2. In addition, the insulating film 15 may be configured to expose the first bonding electrode BDE1 and the second bonding electrode BDE2 protruding from the light-emitting stack structure EST. The insulating film 15 may be used to prevent an electrical short circuit that may occur when the active layer 13 comes into contact with another conductive material other than the first semiconductor layer 11 and the second semiconductor layer 12. In an embodiment, the insulating film 15 may include a transparent insulating material.

[0173] The metal protrusion SAC may be disposed on the insulating film 15 covering the surface of the light-emitting stack structure EST. The metal protrusion SAC may protrude from the surface of the light-emitting stack structure EST in a direction away from the growth substrate SUB”. In an embodiment, the metal protrusion SAC may include various metal materials and / or an alloy of at least two metal materials selected therefrom.

[0174] The metal protruding portion SAC can protrude in the same direction as the first bonding electrode BDE1 and the second bonding electrode BDE2. In other words, each of the first bonding electrode BDE1 and the second bonding electrode BDE2 can protrude in the direction in which the metal protruding portion SAC protrudes from the surface of the light-emitting stack structure EST. In an embodiment, the metal protruding portion SAC can protrude much more than the first bonding electrode BDE1 and the second bonding electrode BDE2 with respect to the direction in which the metal protruding portion SAC protrudes.

[0175] The metal protruding portion SAC may not be in physical contact with the first bonding electrode BDE1 and the second bonding electrode BDE2. That is, each of the first bonding electrode BDE1 and the second bonding electrode BDE2 can be spaced apart from the metal protruding portion SAC.

[0176] In an embodiment, the method of forming the growth substrate SUB” and the light-emitting element LD formed on the surface of the growth substrate SUB” is not limited. For example, various semiconductor manufacturing methods can be applied, such as growing an epitaxial layer on a silicon wafer, without limitation.

[0177] For ease of description, only one light-emitting element LD is shown in Figure 10 . However, the embodiment is not limited thereto. For example, a plurality of light-emitting elements LD can be provided on the surface of the growth substrate SUB”, and the parts described with reference to Figures 11 to 16 can be applied substantially the same or similarly to the plurality of light-emitting elements LD. Hereinafter, only one light-emitting element LD will be shown even in Figures 11 to 16 . Figures 10 to 16 The light-emitting element LD shown in Figures 6 to 8 can correspond to any one of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 already described with reference to

[0178] Referring to Figure 11 , a transfer substrate SUB' can be provided. The transfer substrate SUB' can be a substrate for transferring the light-emitting element LD. In an embodiment, a metal layer ML can be provided on the surface of the transfer substrate SUB'. The metal layer ML can include various metal materials and / or an alloy of at least two metal materials selected therefrom.

[0179] The transfer substrate SUB' and the growth substrate SUB'' can be aligned with each other (first step S1). Accordingly, the metal layer ML provided on the transfer substrate SUB' and the metal protruding portion SAC included in the light-emitting element LD formed on the surface of the growth substrate SUB'' can be in contact with each other. The first bonding electrode BDE1 and the second bonding electrode BDE2 of the light-emitting element LD can protrude less than the metal protruding portion SAC. Accordingly, the first bonding electrode BDE1 and the second bonding electrode BDE2 can be spaced apart from the metal layer ML, and the contact reliability between the metal protruding portion SAC and the metal layer ML can be ensured.

[0180] The metal protruding portion SAC and the metal layer ML can be bonded to each other (second step S2). This can be performed by applying sufficient heat to the region where the metal protruding portion SAC and the metal layer ML are in contact with each other. For example, the second laser L2 can be irradiated onto the region where the metal protruding portion SAC and the metal layer ML are in contact with each other. The metal protruding portion SAC and the metal layer ML can form an alloy in the region where the metal protruding portion SAC and the metal layer ML are in contact with each other, such that the metal protruding portion SAC and the metal layer ML can be bonded to each other.

[0181] The light-emitting element LD can be separated from the growth substrate SUB'' (third step S3). This can be performed by irradiating the first laser L1 onto the region where the growth substrate SUB'' and the light-emitting element LD are in contact with each other.

[0182] Reference Figure 12 , after performing the first step S1, the second step S2, and the third step S3 described with reference to Figure 11 , the light-emitting element LD can be bonded and fixed to the metal layer ML through the metal protruding portion SAC. That is, the metal-to-metal bonding between the metal protruding portion SAC and the metal layer ML can be used to fix the light-emitting element LD to the transfer substrate SUB'. Accordingly, the light-emitting element LD can be more effectively fixed to the transfer substrate SUB'.

[0183] In the present disclosure, the light-emitting element LD can be bonded and fixed to the metal layer ML through the metal protruding portion SAC. That is, the metal-to-metal bonding between the metal protruding portion SAC and the metal layer ML can be used to fix the light-emitting element LD to the transfer substrate SUB'. Accordingly, the light-emitting element LD can be more effectively fixed to the transfer substrate SUB'.

[0184] In addition, a metal layer ML on which alignment marks can be easily formed (for example, marks having a specific shape formed in the metal layer ML for easy identification thereof) can be provided on the transfer substrate SUB', and thus the reliability of alignment in the alignment step (fourth step S4) to be described later can be easily ensured.

[0185] Reference Figure 13 , the light-emitting element LD fixed to the transfer substrate SUB' can be transferred so that the metal layer ML on the transfer substrate SUB' and the display substrate DSUB are aligned facing each other (fourth step S4). The light-emitting element LD can be aligned to be located on the outer coating OCL of the display substrate DSUB using the alignment marks and the like described above.

[0186] The display substrate DSUB may include a base substrate SUB and various components provided on the base substrate SUB. The base substrate SUB may be made of an insulating material such as glass or resin. For example, the base substrate SUB may include a glass substrate. In another example, the base substrate SUB may include a polyimide (PI) substrate.

[0187] Various components for supplying various signals (or voltages) to the light-emitting element LD or improving the light emission efficiency and reliability of the light-emitting element LD may be provided on the base substrate SUB. For example, the pixel circuit layer PCL, the anode electrode AE, the cathode electrode CE, the first bank BNK1, the first reflective electrode RFE1, the second reflective electrode RFE2, and the outer coating OCL may be provided on the base substrate SUB. The pixel circuit layer PCL, the anode electrode AE, the cathode electrode CE, the first bank BNK1, the first reflective electrode RFE1, the second reflective electrode RFE2, and the outer coating OCL may be substantially the same as or similar to the pixel circuit layer PCL, the first anode electrode AE1, the cathode electrode CE, the first bank BNK1, the first reflective electrode RFE1, the second reflective electrode RFE2, and the outer coating OCL already referred to Figure 7 and Figure 8 described. Thus, redundant descriptions will be omitted.

[0188] Reference Figure 14 , by moving the transfer substrate SUB' relative to the display substrate DSUB, the light-emitting element LD can be attached to the outer coating OCL (fifth step S5). For example, the transfer substrate SUB' may be moved in the direction toward the display substrate DSUB, and thus, the light-emitting element LD may be partially buried in the outer coating OCL. In some embodiments, the outer coating OCL may be only partially provided in the region adjacent to the lower portion of the light-emitting element LD, and thus, the light-emitting element LD may not be partially buried in the outer coating OCL.

[0189] Reference Figure 15 , by moving the transfer substrate SUB' relative to the display substrate DSUB, the metal protrusion SAC can be separated from the light-emitting element LD (sixth step S6). For example, the transfer substrate SUB' may be moved in the direction away from the display substrate DSUB.

[0190] The bonding between the metal protrusion SAC and the metal layer ML can be maintained. That is, in the case of performing the sixth step S6, the metal protrusion SAC and the metal layer ML can be in a state where the metal protrusion SAC and the metal layer ML are bonded to each other. In addition, the attachment between the light-emitting element LD and the outer coating OCL can be maintained. That is, in the case of performing the sixth step S6, the light-emitting element LD can maintain a position that is substantially equal to the position where the light-emitting element LD has been attached to the outer coating OCL in the fifth step S5.

[0191] In an embodiment, the bonding force between the metal protrusion SAC and the insulating film 15 can be weaker than the adhesive force between the light-emitting element LD and the outer coating OCL. In the case of performing the sixth step S6, the metal protrusion SAC can be effectively separated from the light-emitting element LD. In addition, the attachment between the light-emitting element LD and the outer coating OCL can be effectively maintained.

[0192] In an embodiment, the bonding force between the metal protrusion SAC and the insulating film 15 can be weaker than the bonding force between the metal protrusion SAC and the metal layer ML. In the case of performing the sixth step S6, the bonding between the metal protrusion SAC and the metal layer ML can be effectively maintained, and thus the metal protrusion SAC can be effectively separated from the light-emitting element LD.

[0193] In an embodiment, the bonding force between the metal protrusion SAC and the metal layer ML can be weaker than the adhesive force between the light-emitting element LD and the outer coating OCL. In the case of performing the sixth step S6, the light-emitting element LD can maintain a position that is substantially equal to the position where the light-emitting element LD has been attached to the outer coating OCL in the fifth step S5.

[0194] Reference Figure 16 , after performing the sixth step S6, various components for connecting the light-emitting element LD to the anode electrode AE and the cathode electrode CE can also be formed. For example, a third passivation layer PSV3, a first transparent electrode ITO1, a second transparent electrode ITO2, and a capping layer CPL can also be formed. The third passivation layer PSV3, the first transparent electrode ITO1, the second transparent electrode ITO2, and the capping layer CPL can be substantially the same as or similar to the third passivation layer PSV3, the first transparent electrode ITO1, the second transparent electrode ITO2, and the capping layer CPL described with reference to Figure 7 and Figure 8 . Therefore, redundant descriptions will be omitted.

[0195] A display substrate DSUB including a base substrate SUB, a pixel circuit layer PCL, and a display panel layer DPL can be formed. Although in Figure 16is not shown in the figure, but the light conversion layer LCL described with reference to Figure 7 and Figure 8 can be further formed on the display panel layer DPL.

[0196] Figure 17 is a flowchart showing a method of manufacturing a display device according to another embodiment of the present disclosure.

[0197] Referring to Figure 17 , a method of manufacturing a display device according to another embodiment of the present disclosure may include a first step S1', a second step S2', a third step S3', a fourth step S4', a fifth step S5' and a sixth step S6'. Hereinafter, the first step S1', the second step S2', the third step S3', the fourth step S4', the fifth step S5' and the sixth step S6' will be described with reference to Figures 18 to 24 .

[0198] Figures 18 to 24 is a schematic diagram showing the method shown in Figure 17 .

[0199] Referring to Figure 18 , before the first step S1', a growth substrate SUB” and a light-emitting element LD' formed on the surface of the growth substrate SUB” may be provided.

[0200] The growth substrate SUB” may be a substrate for forming the light-emitting element LD'. For example, the growth substrate SUB” may be a silicon wafer substrate.

[0201] The light-emitting element LD' may include a light-emitting stack structure EST, a first bonding electrode BDE1', a second bonding electrode BDE2', an insulating film 15 and a metal protrusion SAC'.

[0202] The light-emitting stack structure EST may be substantially the same as or similar to the light-emitting stack structure EST described with reference to Figure 10 . The light-emitting stack structure EST may include a first semiconductor layer 11, a second semiconductor layer 12 and an active layer 13. In some embodiments, the light-emitting stack structure EST may further include an auxiliary layer 14. Hereinafter, redundant descriptions will be omitted.

[0203] The first bonding electrode BDE1' can be connected to the first semiconductor layer 11, and the second bonding electrode BDE2' can be connected to the second semiconductor layer 12. The first bonding electrode BDE1' may not be in physical contact with the second semiconductor layer 12, the active layer 13, and the second bonding electrode BDE2', and the second bonding electrode BDE2' may not be in physical contact with the first semiconductor layer 11 and the active layer 13. In an embodiment, the first bonding electrode BDE1' and the second bonding electrode BDE2' may protrude from the light-emitting stack structure EST in the same direction. For example, the first bonding electrode BDE1' and the second bonding electrode BDE2' may protrude in a direction away from the growth substrate SUB".

[0204] The insulating film 15 may cover at least a part of the outer peripheral surface of the light-emitting stack structure EST. For example, the insulating film 15 may completely cover other surfaces of the outer periphery of the light-emitting stack structure EST except for the surface in contact with the growth substrate SUB", the surface connected to the first bonding electrode BDE1', and the surface connected to the second bonding electrode BDE2'. The insulating film 15 may be configured to expose the first bonding electrode BDE1' and the second bonding electrode BDE2' protruding from the light-emitting stack structure EST. The insulating film 15 may be used to prevent an electrical short circuit that may occur when the active layer 13 comes into contact with another conductive material other than the first semiconductor layer 11 and the second semiconductor layer 12. In an embodiment, the insulating film 15 may include a transparent insulating material.

[0205] The metal protrusion SAC' may include at least one of a first metal protrusion SAC1' overlapping with the first bonding electrode BDE1' and a second metal protrusion SAC2' overlapping with the second bonding electrode BDE2'. For example, as Figure 18 shown, the metal protrusion SAC' may include the first metal protrusion SAC1' and the second metal protrusion SAC2'.

[0206] The first metal protrusion SAC1' may be disposed on the first bonding electrode BDE1'. The second metal protrusion SAC2' may be disposed on the second bonding electrode BDE2'. In an embodiment, the first metal protrusion SAC1' may be in direct contact with the first bonding electrode BDE1', and the second metal protrusion SAC2' may be in direct contact with the second bonding electrode BDE2'. In an embodiment, the first metal protrusion SAC1' and the second metal protrusion SAC2' may include various metal materials and / or alloys of at least two metal materials selected therefrom.

[0207] The first metal protruding portion SAC1' and the second metal protruding portion SAC2' may protrude in a direction away from the growth substrate SUB". The first metal protruding portion SAC1' and the second metal protruding portion SAC2' may protrude much more than the first bonding electrode BDE1' and the second bonding electrode BDE2'. The uppermost surfaces of the first metal protruding portion SAC1' and the second metal protruding portion SAC2' may be located at the same height.

[0208] In an embodiment, the method of forming the growth substrate SUB" and the light-emitting element LD' formed on the surface of the growth substrate SUB" is not limited. For example, various semiconductor manufacturing methods can be applied, such as growing an epitaxial layer on a silicon wafer, without limitation.

[0209] For ease of description, only one light-emitting element LD' is shown in Figure 18 . However, the embodiment is not limited thereto. For example, a plurality of light-emitting elements LD' may be provided on the surface of the growth substrate SUB", and the parts described with reference to Figures 19 to 24 may be applied substantially the same or similarly to the plurality of light-emitting elements LD'. Hereinafter, even in Figures 19 to 24 , only one light-emitting element LD' will be shown. Figures 18 to 24 The light-emitting element LD' shown in Figures 6 to 8 may correspond to any one of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 described with reference to

[0210] Referring to Figure 19 , a transfer substrate SUB' may be provided. The transfer substrate SUB' may be a substrate for transferring the light-emitting element LD'. In an embodiment, a metal layer ML may be provided on the surface of the transfer substrate SUB'. The metal layer ML may include various metal materials and / or an alloy of at least two metal materials selected therefrom.

[0211] The transfer substrate SUB' and the growth substrate SUB" may be aligned with each other (first step S1'). Accordingly, the metal layer ML provided on the transfer substrate SUB' and the metal protruding portion SAC' included in the light-emitting element LD' formed on the surface of the growth substrate SUB" may be in contact with each other.

[0212] The metal protrusion SAC' and the metal layer ML can be joined to each other (second step S2'). This can be performed by applying sufficient heat to the region where the metal protrusion SAC' and the metal layer ML are in contact with each other. For example, the second laser L2 can be irradiated onto the region where the metal protrusion SAC' and the metal layer ML are in contact with each other. The metal layer ML and the metal protrusion SAC' can form an alloy in the region where the metal protrusion SAC' and the metal layer ML are in contact with each other, such that the metal protrusion SAC' and the metal layer ML can be joined to each other.

[0213] The light-emitting element LD' can be separated from the growth substrate SUB” (third step S3'). This can be performed by irradiating the first laser L1 onto the region where the growth substrate SUB” and the light-emitting element LD' are in contact with each other.

[0214] Reference Figure 20 , after performing the first step S1', the second step S2', and the third step S3' that have been described with reference to Figure 19 , the metal protrusion SAC' of the light-emitting element LD' can be joined to the metal layer ML. Accordingly, the light-emitting element LD' can be fixed to the transfer substrate SUB', and the light-emitting element LD' fixed to the transfer substrate SUB' can be transferred.

[0215] Reference Figure 21 , the light-emitting element LD' fixed to the transfer substrate SUB' can be transferred so that the metal layer ML provided on the transfer substrate SUB' and the display substrate DSUB are aligned facing each other (fourth step S4'). The light-emitting element LD' can be aligned to be located on the outer coating OCL of the display substrate DSUB.

[0216] The display substrate DSUB can be substantially the same as or similar to the display substrate DSUB that has been described with reference to Figure 13 . Accordingly, redundant descriptions will be omitted.

[0217] Reference Figure 22 , by moving the transfer substrate SUB' relative to the display substrate DSUB, the light-emitting element LD' can be attached to the outer coating OCL' (fifth step S5'). For example, the transfer substrate SUB' can be moved in the direction toward the display substrate DSUB, and accordingly, the light-emitting element LD' can be partially buried in the outer coating OCL. In some embodiments, the outer coating OCL can be only partially provided in the region adjacent to the lower portion of the light-emitting element LD', and accordingly, the light-emitting element LD' may not be partially buried in the outer coating OCL.

[0218] Reference Figure 23, by moving the transfer substrate SUB' relative to the display substrate DSUB, the metal protrusion SAC' of the light-emitting element LD' can be separated from the metal layer ML (sixth step S6'). For example, the transfer substrate SUB' can be moved in a direction away from the display substrate DSUB.

[0219] The attachment between the light-emitting element LD' and the outer coating OCL can be maintained. That is, in the case of performing the sixth step S6', the light-emitting element LD' can be maintained at a position that is substantially equal to the position where the light-emitting element LD' has been attached to the outer coating OCL in the fifth step S5'.

[0220] In an embodiment, the bonding force between the metal protrusion SAC' and the metal layer ML can be weaker than the adhesion force between the light-emitting element LD' and the outer coating OCL. In the case of performing the sixth step S6', the metal protrusion SAC' can be effectively separated from the metal layer ML. In addition, the attachment between the light-emitting element LD' and the outer coating OCL can be effectively maintained.

[0221] Reference Figure 24 , after performing the sixth step S6', various components for connecting the light-emitting element LD' to the anode electrode AE and the cathode electrode CE can also be formed. For example, a third passivation layer PSV3, a first transparent electrode ITO1, a second transparent electrode ITO2, and a capping layer CPL can also be formed.

[0222] The third passivation layer PSV3 can be disposed on the first reflective electrode RFE1, the second reflective electrode RFE2, the light-emitting element LD', and the outer coating OCL. The third passivation layer PSV3 can protect the components disposed below the third passivation layer PSV3 and provide a flat top surface. At least one of the first passivation layer PSV1 and the second passivation layer PSV2 and the third passivation layer PSV3 can include the same material, but the embodiment is not limited thereto.

[0223] The third passivation layer PSV3 can have a second opening OP2, a third opening OP3, a fourth opening OP4, and a fifth opening OP5. The second opening OP2 can expose the top surface of the first metal protrusion SAC1'. In some embodiments, in the case of omitting the first metal protrusion SAC1', the second opening OP2 can expose the top surface of the first bonding electrode BDE1'. The third opening OP3 can expose the top surface of the second metal protrusion SAC2'. In some embodiments, in the case of omitting the second metal protrusion SAC2', the third opening OP3 can expose the top surface of the second bonding electrode BDE2'. The fourth opening OP4 can expose the top surface of the first reflective electrode RFE1. The fifth opening OP5 can expose the top surface of the second reflective electrode RFE2.

[0224] The first transparent electrode ITO1 and the second transparent electrode ITO2 may be disposed on the third passivation layer PSV3. The first transparent electrode ITO1 may electrically connect the first metal protrusion SAC1' exposed by the second opening OP2 to the first reflective electrode RFE1 exposed by the fourth opening OP4. The second transparent electrode ITO2 may electrically connect the second metal protrusion SAC2' exposed by the third opening OP3 to the second reflective electrode RFE2 exposed by the fifth opening OP5. Accordingly, the first metal protrusion SAC1' may be electrically connected to the anode electrode AE through the first transparent electrode ITO1 and the first reflective electrode RFE1. The second metal protrusion SAC2' may be electrically connected to the cathode electrode CE through the second transparent electrode ITO2 and the second reflective electrode RFE2.

[0225] In an embodiment, the first transparent electrode ITO1 and the second transparent electrode ITO2 may be substantially transparent or semi-transparent to meet a predetermined or selected light transmittance. For example, the first transparent electrode ITO1 and the second transparent electrode ITO2 may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the materials of the first transparent electrode ITO1 and the second transparent electrode ITO2 are not limited thereto.

[0226] The capping layer CPL may be disposed over the third passivation layer PSV3. The capping layer CPL may be used to protect components (such as the first transparent electrode ITO1 and the second transparent electrode ITO2 and the light-emitting element LD') disposed below the capping layer CPL from external moisture, humidity, etc. The capping layer CPL may include, for example, silicon nitride, silicon oxide, silicon oxynitride, and / or aluminum oxide.

[0227] Thus, a display substrate DSUB including a base substrate SUB, a pixel circuit layer PCL, and a display panel layer DPL may be formed. Although not shown in Figure 24 , a light conversion layer LCL that has been described with reference to Figure 7 and Figure 8 may be further formed on the display panel layer DPL.

[0228] Figure 25 is a schematic block diagram showing a display system according to an embodiment of the present disclosure.

[0229] Referring to Figure 25 , the display system 1000 may include a processor 1100 and a display device 1200.

[0230] The processor 1100 may perform various tasks and various calculations. In an embodiment, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 via a bus system to control the components of the display system 1000.

[0231] The processor 1100 may send the image data IMG and the control signal CTRL to the display device 1200. The display device 1200 may display an image based on the image data IMG and the control signal CTRL. The display device 1200 may be configured to be the same as or similar to the display device DD described in the reference Figure 1 The image data IMG and the control signal CTRL may be respectively set to the input image data IMG and the control signal CTRL shown in Figure 1 .

[0232] The display system 1000 may include a computing system for providing an image display function, such as a smart watch, a mobile phone, a smartphone, a portable computer, a tablet personal computer (PC), a watch phone, an in-vehicle display, smart glasses, a portable multimedia player (PMP), a navigation system, or an ultra-mobile computer (UMPC). The display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0233] Figures 26 to 29 is a schematic perspective view showing an application example of the display system shown in Figure 25 .

[0234] Referring to Figure 26 , Figure 25 the display system 1000 shown in may be applied to a smart watch 2000 including a display portion 2100 and a band portion 2200.

[0235] The smart watch 2000 may be a wearable electronic device. For example, the smart watch 2000 may have a structure in which the band portion 2200 is worn on a user's wrist. The display system 1000 and / or the display device 1200 may be applied to the display portion 2100 such that image data including time information may be provided to the user.

[0236] Referring to Figure 27 , Figure 25 the display system 1000 shown in may be applied to an in-vehicle display system 3000. The in-vehicle display system 3000 may include a computing system provided inside / outside a vehicle to provide image data.

[0237] For example, the display system 1000 and / or the display device 1200 can be applied to at least one of the information entertainment panel 3100, the cluster 3200, the co-pilot display 3300, the head-up display 3400, the side mirror display 3500, and the reading seat display 3600 provided in a vehicle.

[0238] Reference Figure 28 , Figure 25 As shown in, the display system 1000 can be applied to smart glasses 4000. The smart glasses 4000 are wearable electronic devices that can be worn on a user's face. For example, the smart glasses 4000 can be wearable devices for augmented reality (AR).

[0239] The smart glasses 4000 can include a frame 4100 and a lens part 4200. The frame 4100 can include a housing 4110 that supports the lens part 4200 and leg parts 4120 that allow the user to wear the smart glasses 4000. The leg parts 4120 can be connected to the housing 4110 by hinges to fold or unfold relative to the housing 4110.

[0240] A battery, a touchpad, a microphone, a camera, etc. can be built into the frame 4100. In addition, a projector for outputting light, a processor for controlling optical signals, etc. can be built into the frame 4100.

[0241] The lens part 4200 can be an optical member that allows light to transmit through it or allows light to be reflected by it. For example, the lens part 4200 can include glass, transparent synthetic resin, etc.

[0242] In order for the user's eyes to recognize visual information, the lens part 4200 can allow an image caused by an optical signal sent from the projector of the frame 4100 to be reflected by the rear surface of the lens part 4200 (e.g., the surface facing the user's eyes). For example, the user can recognize information including time, data, etc. displayed on the lens part 4200. The projector and / or the lens part 4200 can be a type of display device. The display device 1200 can be applied to the projector and / or the lens part 4200.

[0243] Reference Figure 29 , Figure 25 As shown in, the display system 1000 can be applied to a head-mounted display device 5000.

[0244] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality (VR) or mixed reality (MR).

[0245] The head-mounted display device 5000 may include a head-mounted band 5100 and a display housing box 5200. The head-mounted band 5100 may be connected to the display housing box 5200. The head-mounted band 5100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 5000 to the user's head. The horizontal band may be configured to surround the side portions of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, the embodiments are not limited thereto. For example, the head-mounted band 5100 may be implemented in the form of a spectacle frame, a helmet, or the like.

[0246] The display housing box 5200 may accommodate the display system 1000 and / or the display device 1200.

[0247] According to the present disclosure, a method of manufacturing a display device may include the steps of: providing a light-emitting element from a transfer substrate to a display substrate using a metal layer provided on the transfer substrate and a light-emitting element including a metal protrusion joined to the metal layer. Accordingly, the reliability of the step of providing the light-emitting element to the display substrate may be improved.

[0248] Exemplary embodiments have been disclosed herein, and although specific terms have been used, they have been used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to those of ordinary skill in the art at the time of filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a display device, the method comprising: aligning a metal layer disposed on a transfer substrate and a display substrate to face each other; attaching a light emitting element including a metal protrusion bonded to the metal layer to an outer coating of the display substrate by moving the transfer substrate relative to the display substrate; as well as The metal protruding portion is separated from the light emitting element by moving the transfer substrate relative to the display substrate.

2. The method according to claim 1, wherein: The bond between the metal protrusion and the metal layer is maintained during separation of the metal protrusion from the light emitting element.

3. The method according to claim 1, wherein: During separation of the metal protrusion from the light emitting element, the attachment between the light emitting element and the outer coating is maintained.

4. The method according to claim 1, wherein: The light emitting element further comprises: A light emitting stacked structure comprising a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; a first bonding electrode electrically connected to the first semiconductor layer; a second bonding electrode electrically connected to the second semiconductor layer; and an insulating film covering at least a portion of an outer peripheral surface of the light emitting stack structure, Here, before the metal protrusion is separated from the light emitting element, the metal protrusion is in a state where the metal protrusion is bonded to the insulating film covering the surface of the light emitting stacked structure.

5. The method according to claim 4, wherein: Each of the first bonding electrode and the second bonding electrode protrudes in a direction in which the metal protruding portion protrudes from the surface of the light emitting stack structure, and The metal protruding portion protrudes more than the first bonding electrode and the second bonding electrode with respect to the direction in which the metal protruding portion protrudes.

6. The method according to claim 4, wherein: The bonding force between the metal protrusion and the insulating film is weaker than the bonding force between the light emitting element and the overcoat layer. wherein the bonding force between the metal protrusion and the insulating film is weaker than the bonding force between the metal protrusion and the metal layer, and The bonding force between the metal protrusion and the metal layer is weaker than the bonding force between the light emitting element and the outer coating layer.

7. The method according to claim 4, wherein: Each of the first bonding electrode and the second bonding electrode is spaced apart from the metal protruding portion.

8. The method according to claim 1, further comprising: Before aligning the metal layer disposed on the transfer substrate and the display substrate to face each other: aligning the metal layer disposed on the transfer substrate and the metal protrusion included in the light emitting element formed on the surface of the growth substrate in physical contact with each other; joining the metal protrusion and the metal layer to each other; as well as separating the light emitting element from the growth substrate, Wherein, separating the light emitting element from the growth substrate comprises: irradiating a first laser onto a region where the growth substrate and the light emitting element are in physical contact with each other.

9. The method according to claim 8, wherein: Joining the metal protrusion and the metal layer to each other includes allowing the metal layer and the metal protrusion to form an alloy in a region where the metal protrusion and the metal layer are in physical contact with each other.

10. A method for manufacturing a display device, the method comprising: aligning a metal layer disposed on a transfer substrate and a display substrate to face each other; attaching a light emitting element including a metal protrusion bonded to the metal layer to an outer coating of the display substrate by moving the transfer substrate relative to the display substrate; as well as The metal protrusion is separated from the metal layer by moving the transfer substrate relative to the display substrate, wherein: The light emitting element further comprises: A light emitting stacked structure comprising a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; a first bonding electrode electrically connected to the first semiconductor layer; and a second bonding electrode electrically connected to the second semiconductor layer, and The metal protruding portion includes at least one of a first metal protruding portion overlapping the first bonding electrode and a second metal protruding portion overlapping the second bonding electrode.

Images