Display device and method of dispersing static electricity for display device

Abstract

A display device and a method of dispersing static electricity for the display device are disclosed. A display device according to an exemplary embodiment of the present disclosure includes: a substrate including a display area and a non-display area; a semiconductor layer disposed in the display area on the substrate; a connection line disposed in the non-display area on the substrate; a gate insulating layer disposed on the semiconductor layer and the connecting line; a gate line disposed on the gate insulating layer and connected to the connection line; at least one insulating layer disposed on the gate line; and a light emitting element disposed on the at least one insulating layer. In the present disclosure, the connection lines are made of a metal oxide and are disposed on the same layer as the semiconductor layer, and the connection lines between adjacent gate lines are partially removed and thus broken. Accordingly, damage to the display panel can be suppressed by dispersing static electricity generated during processing.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0195714, filed with the Korean Intellectual Property Office on December 28, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of suppressing static electricity. Background art

[0004] Currently, in the comprehensive information age, the field of display devices that visually express electrical information signals has developed rapidly. In addition, continuous research has been conducted to improve the performance of various display devices, such as reduced thickness, light weight, and low power consumption.

[0005] Typical display devices may include a liquid crystal display (LCD) device, an electro - wetting display (EWD) device, an organic light - emitting display (OLED) device, etc.

[0006] An electroluminescent display device including an OLED is a self - emissive display device and, unlike an LCD, does not require a separate light source. Therefore, an electroluminescent display device can be manufactured in a light and thin form. In addition, electroluminescent display devices are advantageous in terms of power consumption because they are driven at a low voltage. In addition, electroluminescent display devices have excellent color rendering capabilities, high response speeds, wide viewing angles, and high contrast ratios (CR). Therefore, the use of electroluminescent display devices is expected in various fields. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a display device capable of dispersing static electricity generated during processing.

[0008] Another object to be achieved by the present disclosure is to provide a display device capable of dispersing static electricity and minimizing the reflectance of a display panel.

[0009] Still another object to be achieved by the present disclosure is to provide a display device capable of simplifying a process and dispersing static electricity.

[0010] The objects of the present disclosure are not limited to the above - mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0011] A display device according to an exemplary embodiment of the present disclosure includes: a substrate including a display area and a non-display area; a semiconductor layer disposed on the substrate in the display area; a connection line disposed on the substrate in the non-display area; a gate insulating layer disposed on the semiconductor layer and the connection line; a gate line disposed on the gate insulating layer and connected to the connection line; at least one insulating layer disposed on the gate line; and a light-emitting element disposed on the at least one insulating layer. Herein, the connection line is made of a metal oxide and disposed on the same layer as the semiconductor layer, and the connection line between adjacent gate lines is partially removed and thus disconnected.

[0012] A display device according to another exemplary embodiment of the present disclosure includes: a substrate including a display area and a non-display area; a gate line disposed on the substrate; a first connection line disposed in a direction crossing the gate line and connected to the gate line; an interlayer insulating layer disposed on the gate line; a second connection line disposed on the interlayer insulating layer and connected to the first connection line; at least one insulating layer disposed on the second connection line; and a light-emitting element disposed on the at least one insulating layer. Herein, each of the first connection line and the second connection line between adjacent gate lines is partially removed and thus disconnected.

[0013] Other detailed matters of the exemplary embodiments are included in the detailed description and the drawings.

[0014] According to an exemplary embodiment of the present disclosure, a connection line is disposed between gate lines or data lines to disperse static electricity. Accordingly, damage to the display panel can be suppressed. Accordingly, the reliability of the display device can be improved.

[0015] According to an exemplary embodiment of the present disclosure, a connection line is disposed on the same layer as the semiconductor layer under the gate line. Accordingly, static electricity can be dispersed from the formation of the gate line to the formation of the anode.

[0016] According to an exemplary embodiment of the present disclosure, a connection line is made of a transparent metal oxide. Accordingly, the reflectance of the display panel can be minimized. Accordingly, low power consumption can be achieved.

[0017] According to an exemplary embodiment of the present disclosure, a connection line is made of a transparent metal oxide. Accordingly, when forming the anode, the connection line can be patterned. Accordingly, the process can be simplified.

[0018] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. Description of the Drawings

[0019] The above aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 3 is a plan view of a display panel according to a first exemplary embodiment of the present disclosure;

[0023] Figure 4 is Figure 3 an enlarged view of region A of

[0024] Figure 5 is a cross-sectional view of a sub-pixel;

[0025] Figure 6 is a plan view of a part of a display panel according to a second exemplary embodiment of the present disclosure;

[0026] Figure 7 is Figure 6 an enlarged view of region B of

[0027] Figure 8 is along Figure 7 a cross-sectional view taken along line I-I' of

[0028] Figures 9A to 9G shows the process of manufacturing Figure 7 a display panel according to a second exemplary embodiment of the present disclosure;

[0029] Figures 10A to 10G sequentially shows the process of manufacturing Figure 8 a display panel according to a second exemplary embodiment of the present disclosure;

[0030] Figure 11 is a plan view of a display panel according to a third exemplary embodiment of the present disclosure;

[0031] Figure 12 is Figure 11 an enlarged view of region C of

[0032] Figure 13A is along Figure 12 a cross-sectional view taken along line II-II' of

[0033] Figure 13B is along Figure 12A cross-sectional view taken along line III-III';

[0034] Figures 14A to 14F is a diagram showing the process of manufacturing Figure 12 a display panel according to a third exemplary embodiment of the present disclosure;

[0035] Figures 15A to 15F is a diagram sequentially showing the process of manufacturing Figure 13B a display panel according to a third exemplary embodiment of the present disclosure;

[0036] Figure 16 is a plan view showing a part of a display panel according to a fourth exemplary embodiment of the present disclosure;

[0037] Figure 17 is along Figure 16 a cross-sectional view taken along line IV-IV';

[0038] Figure 18 is a plan view showing a part of a display panel according to a fifth exemplary embodiment of the present disclosure;

[0039] Figure 19 is along Figure 18 a cross-sectional view taken along line V-V'; and

[0040] Figure 20 is a plan view showing a part of a display panel according to a sixth exemplary embodiment of the present disclosure. Detailed Description

[0041] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying Figure One drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0042] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having", and "consisting of" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular generally includes the plural unless otherwise clearly stated.

[0043] Even if not explicitly stated, components are construed to include ordinary error ranges.

[0044] When terms such as "on", "above", "below", and "next to" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used together with the terms "immediately" or "directly".

[0045] When an element or layer is disposed "on" another element or layer, the other layer or the other element may be directly disposed on the other element or directly disposed therebetween.

[0046] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component to be mentioned below may be the second component.

[0047] Throughout the specification, like reference numerals generally denote like elements.

[0048] For ease of description, the dimensions and thicknesses of each component shown in the drawings are shown, but the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0049] The features of the various embodiments of the present disclosure may be partially or completely adhered to or combined with each other and may be interlocked and operated in technically different ways, and the embodiments may be implemented independently of each other or in association with each other.

[0050] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings.

[0051] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0052] Referring to Figure 1 , a display device 100 according to an exemplary embodiment of the present disclosure may include an image processor 151, a timing controller 152, a data driver 153, a gate driver 154, and a display panel 110.

[0053] The image processor 151 may output a data signal DATA and a data enable signal DE by the data signal DATA supplied from the outside.

[0054] In addition to the data enable signal DE, the image processor 151 may also output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0055] The timing controller 152 receives a data enable signal DE or a data signal DATA from the image processor 151, as well as drive signals including a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. The timing controller 152 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 154 and a data timing control signal DDC for controlling the operation timing of the data driver 153 based on the drive signals.

[0056] The data driver 153 may sample and latch the data signal DATA supplied from the timing controller 152 in response to the data timing control signal DDC supplied from the timing controller 152. Then, the data driver 153 may convert the data signal DATA into a gamma reference voltage to output it. For example, the data driver 153 may output the data signal DATA through data lines DL1 to DLn.

[0057] The gate driver 154 may output a gate signal in response to the gate timing control signal GDC supplied from the timing controller 152 while converting the level of the gate voltage. The gate driver 154 may output the gate signal through gate lines GL1 to GLm.

[0058] The display panel 110 may display an image when the sub-pixel P emits light in response to the data signal DATA and the gate signal supplied from the data driver 153 and the gate driver 154. Details of the sub-pixel P will be described with reference to Figure 2 and Figure 5 The detailed structure of the sub-pixel P will be described.

[0059] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0060] Referring to Figure 2 According to an exemplary embodiment of the present disclosure, a sub-pixel of a display device may include a switching transistor ST, a driving transistor DT, a compensation circuit 135, and a light-emitting element 130.

[0061] The light-emitting element 130 may operate to emit light according to a driving current formed by the driving transistor DT.

[0062] The switching transistor ST may perform a switching operation in response to a gate signal supplied through the gate line 116 so that a data signal supplied through the data line 117 is stored as a data voltage in a capacitor.

[0063] In addition, the driving transistor DT may operate in response to the data voltage stored in the capacitor so that a constant driving current flows between the high-potential power line VDD and the low-potential power line GND.

[0064] The compensation circuit 135 is configured to compensate for the threshold voltage of the driving transistor DT and the like. The compensation circuit 135 may include one or more transistors and capacitors. The configuration of the compensation circuit 135 may vary according to the compensation method.

[0065] For example, Figure 2 A sub-pixel having a 2T (transistor) 1C (capacitor) structure including a switching transistor ST, a driving transistor DT, a capacitor, and a light-emitting element 130 is shown. However, if the compensation circuit 135 is added, the sub-pixel may have various structures, such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0066] Figure 3 is a plan view of a display panel according to a first exemplary embodiment of the present disclosure.

[0067] Figure 4 is Figure 3 an enlarged view of region A of

[0068] Figure 5 is a cross-sectional view of a sub-pixel.

[0069] Referring to Figure 3 , a display device according to a first exemplary embodiment of the present disclosure may include a display panel 110, a flexible film, and a printed circuit board.

[0070] For example, the display panel 110 may include a substrate 111 and a package substrate 160.

[0071] The display panel 110 is configured to display an image to a user.

[0072] The display panel 110 may include a display element configured to display an image, a driving element configured to operate the display element, and lines configured to send various signals to the display element and the driving element. The display element may be defined in different ways according to the type of the display panel 110. For example, when the display panel 110 is an organic light-emitting display panel, the display element may be an organic light-emitting element including an anode, an organic light-emitting layer, and a cathode.

[0073] Hereinafter, the display panel 110 is assumed to be an organic light-emitting display panel. However, the display panel 110 is not limited to an organic light-emitting display panel.

[0074] The display panel 110 may include a display area AA and a non-display area NA.

[0075] The display area AA is an area where the display panel 110 displays an image.

[0076] The display area AA may include a plurality of sub-pixels that constitute a plurality of pixels, and a circuit for driving the plurality of sub-pixels. The plurality of sub-pixels may be the smallest units that constitute the display area AA. A display element may be provided in each of the plurality of sub-pixels. The plurality of sub-pixels may constitute a pixel. For example, each of the plurality of sub-pixels may include an organic light-emitting element including an anode, an organic light-emitting layer, and a cathode. However, the present disclosure is not limited thereto. In addition, the circuit for driving the plurality of sub-pixels may include driving elements, lines, etc. For example, the circuit may include thin-film transistors, storage capacitors, gate lines, data lines, etc., but is not limited thereto.

[0077] The non-display area NA is an area where an image is not displayed.

[0078] Figure 3 It is shown that the non-display area NA surrounds the display area AA having a quadrilateral shape. However, the shapes and arrangements of the display area AA and the non-display area NA are not limited to Figure 3 the example shown.

[0079] That is to say, the display area AA and the non-display area NA may be adapted to the design of the electronic device equipped with the display device. For example, the display area AA may have other shapes, such as a pentagonal shape, a hexagonal shape, a circular shape, an oval shape, etc.

[0080] In addition, the display device may include various additional components configured to generate various signals or drive the pixels in the display area AA. The additional components for driving the pixels may include an inverter circuit, a multiplexer, an electrostatic discharge (ESD) circuit, etc. The display device may also include additional components related to functions other than the function of driving the pixels. For example, the display device may include additional components for providing a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, a haptic feedback function, etc. The additional components may be located in the non-display area NA and / or in an external circuit connected to the connection interface.

[0081] For example, the gate driver 154, the electrostatic discharge element ESD, and the data driver 153 required to perform the display function may be provided in the non-display area NA. The gate driver 154 and the electrostatic discharge element ESD may be formed simultaneously with the thin-film transistors provided in the display area AA. The data driver 153 may be attached to one side of the display panel 110, but is not limited thereto.

[0082] In order to implement a narrow bezel structure, the gate driver 154 may be directly formed on the substrate 111, particularly on the left and right sides of the non-display area NA. When the gate driver 154 is directly formed on the substrate 111, static electricity may be introduced through the gate line 116.

[0083] The data driver 153 having a more complex structure than the gate driver 154 can be manufactured separately and then can be mounted on the substrate 111 or connected to the substrate 111 through connecting elements such as FPCBs. Figure 3 It shows the data driver 153 mounted on the substrate 111. In this case, static electricity can be introduced through the data line 117.

[0084] In addition, a flexible film is used to supply signals to a plurality of sub-pixels and circuits provided in the display area AA. The flexible film can be electrically connected to the display panel 110. The flexible film can be provided at one end of the non-display area NA of the display panel 110 to supply a power voltage, a data voltage, etc. to a plurality of sub-pixels and circuits provided in the display area AA. A driving IC such as a data driver IC can be provided on the flexible film.

[0085] A printed circuit board can be provided at one end of the flexible film and connected to the flexible film. The printed circuit board is configured to supply signals to the driving IC. The printed circuit board can supply various signals to the driving IC, such as a driving signal, a data signal, etc.

[0086] As described above, during processing, static electricity can be introduced through the gate line 116 or the data line 117.

[0087] Therefore, in the first exemplary embodiment of the present disclosure, an electrostatic discharge element ESD can also be provided to suppress static electricity from being introduced into the display area AA from the outside through the data line 117 or the driving current line. The electrostatic discharge element ESD can be provided at the ends of the data line 117 and the driving current line. For example, the electrostatic discharge element ESD can be provided on the upper side of the display area AA where the data driver 153 is provided. In addition, the electrostatic discharge element ESD can be provided adjacent to the display area AA. The electrostatic discharge element ESD can be configured as a thin film transistor. Therefore, when a thin film transistor is formed in the display area AA, the electrostatic discharge element ESD can also be formed simultaneously.

[0088] A ground line GND can be provided to surround the display area AA and the gate driver 154 and ESD provided therearound. The ground line GND can be provided to branch at the data driver 153. A dam can be provided outside the ground line GND.

[0089] Meanwhile, if the gate lines 116 are separated from each other as in the prior art, they may be vulnerable to static electricity. The same is true for the data lines 117. In addition, WOLED TVs and monitors (MNTs) need to have a reduced reflectance, high resolution, high aperture ratio, and high PPI, but due to the increased pattern density, they may be vulnerable to static electricity and reflectance.

[0090] Thus, in a first exemplary embodiment of the present disclosure, connection lines may be disposed between the gate lines 116 (or data lines 117) to disperse static electricity.

[0091] Details of the connection lines will be further described with reference to Figure 4 and Figure 5 Description of the details of the connection lines will be provided.

[0092] Referring to Figures 3 to 5 , the substrate 111 may be divided into a display area AA and a non-display area NA outside the display area AA.

[0093] Thin film transistors 120 and light emitting elements 130 may be disposed in the display area AA of the substrate 111.

[0094] The non-display area NA of the substrate 111 may include a pad area PA.

[0095] A gate pad GP and a data pad DP may be disposed in the pad area PA.

[0096] The substrate 111 is used to support and protect the components of the display device disposed thereon.

[0097] Recently, the flexible substrate 111 may be used by using a flexible material such as plastic.

[0098] The flexible substrate 111 may be in the form of a film including one of the following groups, the group including polyester-based polymers, silicon-based polymers, acrylic polymers, polyolefin-based polymers, and copolymers thereof.

[0099] A light-shielding layer (not shown) may be disposed on the substrate 111.

[0100] The light-shielding layer may be made of a metal material having a light-shielding function to block external light from being introduced into the semiconductor layer 124.

[0101] For example, the light-shielding layer may be configured as a single layer or multiple layers, and the single layer or multiple layers are made of any one opaque metal or an alloy thereof such as aluminum (Al), chromium (Cr), tungsten (W), titanium (Ti), neodymium (Nd), nickel (Ni), molybdenum (Mo), and copper (Cu).

[0102] A buffer layer 112 may be disposed on the substrate 111 on which the light-shielding layer is disposed.

[0103] The buffer layer 112 is a functional layer for protecting various electrodes and lines from the influence of impurities (e.g., moisture, oxygen, alkali ions, etc.) introduced from the substrate 111 or below it. The buffer layer 112 may have a multilayer structure composed of a first buffer layer 112a and a second buffer layer 112b. However, the present disclosure is not limited thereto.

[0104] For example, the buffer layer 112 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer structure thereof, but is not limited thereto. Depending on the type of the thin film transistor 120, the buffer layer 112 can be omitted.

[0105] The buffer layer 112 can include contact holes that expose a part of the light-shielding layer.

[0106] The thin film transistor 120 can be disposed on the buffer layer 112.

[0107] The thin film transistor 120 in the display area AA can be a driving transistor. For convenience, Figure 5 only the driving transistor 120 is shown. Other switching transistors, sensing transistors, compensation circuits, etc. can be included in the display device.

[0108] In this case, the driving transistor 120 can send the current that has been transmitted through the power line to the anode 131 in response to a signal received from the switching transistor. Then, the driving transistor 120 can control the light emission by the current sent to the anode 131.

[0109] For this purpose, the driving transistor 120 can include a gate electrode 121, a semiconductor layer 124, a source electrode 122, and a drain electrode 123.

[0110] The switching transistor can be turned on by a gate pulse supplied through the gate line 116 and can send the data voltage supplied through the data line 117 to the gate electrode 121 of the driving transistor 120.

[0111] The semiconductor layer 124 can be disposed on the second buffer layer 112b.

[0112] The semiconductor layer 124 can be made of polycrystalline silicon (p-Si). In this case, a predetermined region thereof can be doped with impurities. In addition, the semiconductor layer 124 can be made of amorphous silicon (a-Si) or various organic semiconductor materials such as pentacene. In addition, the semiconductor layer 124 can be made of an oxide semiconductor.

[0113] Oxide semiconductors have excellent mobility and uniformity. Oxide semiconductors can be made from: quaternary metal oxides such as indium tin gallium zinc oxide (InSnGaZnO)-based materials, ternary metal oxides such as indium gallium zinc oxide (InGaZnO)-based materials, indium tin zinc oxide (InSnZnO)-based materials, indium aluminum zinc oxide (InAlZnO)-based materials, tin gallium zinc oxide (SnGaZnO)-based materials, aluminum gallium zinc oxide (AlGaZnO)-based materials, and tin aluminum zinc oxide (SnAlZnO)-based materials, binary metal oxides such as indium zinc oxide (InZnO)-based materials, tin zinc oxide (SnZnO)-based materials, aluminum zinc oxide (AlZnO)-based materials, zinc magnesium oxide (ZnMgO)-based materials, tin magnesium oxide (SnMgO)-based materials, indium oxide (InO)-based materials, tin oxide (SnO)-based materials, indium gallium oxide (InGaO)-based materials, zinc oxide (ZnO)-based materials, indium magnesium oxide (InMgO)-based materials, etc. The composition ratio of each element is not limited.

[0114] The semiconductor layer 124 may include a source region and a drain region containing p-type or n-type impurities, and a channel region between the source region and the drain region. The semiconductor layer 124 may also include a low-concentration doped region between the channel region and the source region and the drain region adjacent to the channel region. However, the present disclosure is not limited thereto.

[0115] The source region and the drain region are doped with a high concentration of impurities and may be connected to the source electrode 122 and the drain electrode 123 of the thin film transistor 120, respectively.

[0116] p-type impurities or n-type impurities can be used as impurity ions. The p-type impurity may be one of boron (B), aluminum (Al), gallium (Ga), and indium (In). The n-type impurity may be one of phosphorus (P), arsenic (As), and antimony (Sb).

[0117] According to the structure of the NMOS or PMOS thin film transistor, the channel region may be doped with n-type impurities or p-type impurities.

[0118] A gate insulating layer 115a may be provided on the semiconductor layer 124. For example, the gate insulating layer 115a may be made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), or may be made of an organic insulating material.

[0119] A gate electrode 121 and a gate line 116 may be provided on the gate insulating layer 115a.

[0120] In addition, a gate pad GP may be provided on the gate insulating layer 115a in the non-display area NA. For example, the gate pad GP may be provided at one end of each gate line 116 extending to the pad area PA.

[0121] The gate electrode 121, the gate line 116, and the gate pad GP may be made of various conductive materials such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or an alloy thereof.

[0122] In addition, an interlayer insulating layer 115b may be provided on the gate electrode 121, the gate line 116, and the gate pad GP.

[0123] For example, the interlayer insulating layer 115b may be made of silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer structure thereof.

[0124] In a first exemplary embodiment of the present disclosure, a first contact hole 170a exposing a part of the gate line 116 may be formed by selectively removing a part of the interlayer insulating layer 115b. The first contact hole 170a may be located in the non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the first contact hole 170a may be provided in the non-display area NA between the display area AA and the gate pad GP.

[0125] Although not shown in detail in the figure, at least one of the insulating layers such as the buffer layer 112, the gate insulating layer 115a, and the interlayer insulating layer 115b may extend to the non-display area NA including the pad area PA.

[0126] A source electrode 122, a drain electrode 123, and a data line 117 may be provided on the interlayer insulating layer 115b.

[0127] A data pad DP may be provided on the interlayer insulating layer 115b in the non-display area NA. For example, the data pad DP may be provided at one end of each data line 117 extending to the pad area PA.

[0128] In addition, a connection line 175 connecting the gate line 116 through the first contact hole 170a may be provided in the non-display area NA. For example, the connection line 175 may be provided in the non-display area NA between the display area AA and the gate pad GP.

[0129] The source electrode 122, the drain electrode 123, the data line 117, the data pad DP, and the connection line 175 may be configured by a single layer or multiple layers made of various conductive materials, such as metal materials such as aluminum (Al), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0130] A protective layer 115f may be provided on the thin film transistor 120 configured as described above.

[0131] In addition, a planarization layer 115 may be provided on the protective layer 115f.

[0132] The planarization layer 115 may be an outer coating.

[0133] The planarization layer 115 may have a multilayer structure composed of at least two layers. For example, the planarization layer 115 may include a first planarization layer 115c and a second planarization layer 115d. In this case, for example, the first planarization layer 115c may be provided to cover the thin film transistor 120 and expose a part of the drain electrode 123 of the thin film transistor 120. However, the present disclosure is not limited thereto. The planarization layer 115 may be configured by a single layer.

[0134] The planarization layer 115 may extend to a non-display area NA other than the disk area PA.

[0135] The planarization layer 115 may have a thickness of about 2 μm, but is not limited thereto.

[0136] According to the positions of the components of the thin film transistor 120, the thin film transistor 120 may be divided into an inverted staggered structure and a coplanar structure. For example, in a thin film transistor having an inverted staggered structure, the gate electrode may be located on a side opposite to the source electrode and the drain electrode with respect to the semiconductor layer. As Figure 5 shown, in the thin film transistor 120 having a coplanar structure, the gate electrode 121 may be located on the same side as the source electrode 122 and the drain electrode 123 with respect to the semiconductor layer 124.

[0137] Although Figure 5 the thin film transistor 120 having a coplanar structure is shown, the present disclosure is not limited thereto. The display device according to an exemplary embodiment of the present disclosure may include a thin film transistor having an inverted staggered structure. In addition, some thin film transistors 120 may have a coplanar structure, while some other thin film transistors 120 may have an inverted staggered structure.

[0138] A connection electrode 125 for electrically connecting the thin film transistor 120 and the light emitting element 130 may be provided on the first planarization layer 115c. In addition, although Figure 5 not shown, various metal layers (for example, signal lines) serving as lines / electrodes may be provided on the first planarization layer 115c.

[0139] In addition, a color filter CF may be provided on the first planarization layer 115c, but the present disclosure is not limited thereto. Depending on the type of the light emitting element 130, the color filter CF may be omitted.

[0140] The color filter CF in each sub-pixel may be one of red, green, and blue. The color filter CF may not be provided in the sub-pixel for realizing white. The arrangement of red, green, and blue may vary, and a black matrix that can absorb external light may be provided between the color filters CF.

[0141] In the bottom emission method, the color filter CF may be located below the electrode 131.

[0142] In addition, a second planarization layer 115d may be provided on the first planarization layer 115c and the connection electrode 125. In the display device according to the first exemplary embodiment of the present disclosure, since the number of various signal lines increases as the display panel 110 has a higher resolution, the planarization layer 115 is composed of two layers. Therefore, when all the lines are placed on one layer, it becomes more difficult to ensure a minimum gap. Therefore, an additional layer is provided. The additional layer (second planarization layer 115d) may provide sufficient margin for the line arrangement, which makes it easier to design the layout of the lines / electrodes. If a dielectric material is used for the planarization layer 115 configured by multiple layers, the planarization layer 115 may be used to generate capacitance between the metal layers. However, as described above, the planarization layer 115 may be configured by a single layer.

[0143] The second planarization layer 115d may be provided to expose a part of the connection electrode 125. The drain electrode 123 of the thin film transistor 120 may be electrically connected to the anode 131 of the light emitting element 130 through the connection electrode 125.

[0144] The light emitting element 130 composed of the anode 131, the organic layer 132, and the cathode 133 may be provided on the second planarization layer 115d.

[0145] Herein, in the first exemplary embodiment of the present disclosure, the second contact hole 170b for exposing a part of the protective layer 115f may be formed by selectively removing a part of the planarization layer 115. The second contact hole 170b may be located on the connection line 175 between adjacent gate lines 116.

[0146] In addition, in the first exemplary embodiment of the present disclosure, the third contact hole 170c for exposing a part of the connection line 175 may be formed by selectively removing a part of the protective layer 115f. For example, the third contact hole 170c may expose the upper surface of the connection line 175 between adjacent gate lines 116.

[0147] The anode 131 may be provided on the second planarization layer 115d.

[0148] The anode 131 is an electrode for supplying holes to the organic layer 132 and can be connected to the thin film transistor 120 through a contact hole formed in the planarization layer 115.

[0149] Meanwhile, the display device can be implemented by a top emission method or a bottom emission method. In the top emission method, a reflective layer made of an opaque conductive material having a high reflectivity, such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof, can be added below the anode 131. Accordingly, the light emitted from the organic layer 132 is reflected by the anode 131 and guided upward, i.e., in the direction toward the cathode 133. In the bottom emission method, the anode 131 can be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like. Hereinafter, the display panel 110 of the present disclosure will be described as a bottom emission display panel.

[0150] The gate pad terminal GPT and the data pad terminal DPT can be disposed on the second planarization layer 115d in the non-display area NA. For example, the gate pad terminal GPT can be electrically connected to the gate pad GP through a gate pad contact hole GPH. In addition, the data pad terminal DPT can be connected to the data pad DP through a data pad contact hole DPH.

[0151] Meanwhile, in the first exemplary embodiment of the present disclosure, after the anode 131 is formed (patterned), the upper surface of the connection line 175 exposed by the third contact hole 170c can be removed through an additional etching process. Accordingly, the connection line 175 between adjacent gate lines 116 can be disconnected.

[0152] The bank 115e can be disposed on the anode 131 and the second planarization layer 115d.

[0153] The bank 115e disposed on the anode 131 and the second planarization layer 115d can divide the actually light-emitting area, i.e., the light-emitting area, to define sub-pixels.

[0154] For example, after a photoresist is formed on the anode 131, the bank 115e can be formed by photolithography.

[0155] To form the organic layer 132 of the light-emitting element 130, a fine metal mask (FMM) can be used as a deposition mask.

[0156] To suppress damage that may be caused by contact with the deposition mask disposed on the bank 115e and maintain a predetermined distance between the bank 115e and the deposition mask, spacers can be disposed on the bank 115e. The spacers can be made of one of polyimide, photoacryl, and benzocyclobutene (BCB) as a transparent organic material.

[0157] In this text, the bank 115e in the light-emitting region can be removed to expose a part of the anode 131.

[0158] The bank 115e can extend to a part of the non-display region NA other than the disk region PA, but is not limited thereto.

[0159] In addition, for example, the bank 115e can have a thickness of about 1 μm, but is not limited thereto.

[0160] An organic layer 132 can be provided between the anode 131 and the cathode 133.

[0161] The organic layer 132 is for light emission and includes at least one of a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer, an electron transport layer (ETL), and an electron injection layer (EIL). Some components can be omitted according to the structure or characteristics of the display device. In this text, as the light-emitting layer, an electroluminescent light-emitting layer and an inorganic light-emitting layer can be applied.

[0162] The hole injection layer is provided on the anode 131 to facilitate the injection of holes.

[0163] The hole transport layer is provided on the hole injection layer to facilitate the transport of holes to the light-emitting layer.

[0164] The light-emitting layer is provided on the hole transport layer and contains a material that emits light of a specific color to emit light of a specific color. The light-emitting material can be a phosphorescent material or a fluorescent material.

[0165] The electron injection layer can also be provided on the electron transport layer. The electron injection layer is an organic layer that facilitates the injection of electrons from the cathode 133 and can be omitted according to the structure and characteristics of the display device.

[0166] In addition, an electron blocking layer and / or a hole blocking layer that blocks the flow of holes or electrons can also be provided adjacent to the light-emitting layer. In this case, when electrons are injected into the light-emitting layer, the phenomenon of electrons moving from the light-emitting layer through the adjacent hole-transparent layer can be suppressed. In addition, when holes are injected into the light-emitting layer, the phenomenon of holes moving from the light-emitting layer through the adjacent electron-transparent layer can be suppressed. Therefore, the light-emitting efficiency can be improved.

[0167] The cathode 133 can be provided on the organic layer 132.

[0168] The cathode 133 is used to supply electrons to the organic layer 132. Since the cathode 133 needs to supply electrons, the cathode 133 can be made of a metal material, which is a conductive material with a low work function, such as magnesium or silver-magnesium, but is not limited thereto.

[0169] Although not shown in the figure, a cover layer can also be provided on the cathode 133.

[0170] The cover layer can be used to protect the light-emitting element 130 and help the light generated from the organic layer 132 to be effectively emitted toward the outside.

[0171] An inorganic layer 140 can be provided on the cathode 133. However, the present disclosure is not limited thereto. The inorganic layer 140 may not be provided.

[0172] For example, the inorganic layer 140 can be made of an inorganic insulating material.

[0173] The inorganic layer 140 can delay the penetration of moisture from above and suppress defects caused by dents or foreign matters.

[0174] In the present disclosure, in order to delay the penetration of moisture, the inorganic layer 140 can be made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof, but is not limited thereto.

[0175] The encapsulation substrate 160 can be provided on the inorganic layer 140 through an adhesive layer 165. However, the present disclosure is not limited thereto. An encapsulation structure including multiple layers of a sealing member and a reinforcing substrate can be provided on the inorganic layer 140.

[0176] For example, the adhesive layer 165 can be used to delay the lateral penetration of moisture.

[0177] For example, in addition to an isobutyl rubber resin, the adhesive layer 165 can further contain a moisture absorbent such as an getter. The moisture absorbent can include calcium oxide.

[0178] The moisture absorbent can be particles having moisture absorption performance and can absorb moisture and oxygen from the outside. Therefore, the moisture absorbent can minimize the penetration of moisture and oxygen into the display area AA.

[0179] For example, the adhesive layer 165 can have a thickness of 40 μm to 60 μm.

[0180] The adhesive layer 165 can extend to a non-display area NA other than the disc area PA. For example, the adhesive layer 165 can be provided to cover the connection line 175.

[0181] The encapsulation substrate 160 can be provided on the adhesive layer 165.

[0182] The encapsulation substrate 160 can protect the light-emitting element 130 together with the adhesive layer 165. The encapsulation substrate 160 can protect the light-emitting element 130 from the effects of external moisture, oxygen, impact, etc.

[0183] For example, the encapsulation substrate 160 can be used to suppress the penetration of moisture through the front surface.

[0184] For example, the encapsulation substrate 160 may be made of steel such as stainless steel (SUS) or invar alloy, but is not limited thereto. In the present disclosure, invar alloy is one of alloys of nickel and iron and has a very low coefficient of thermal expansion and is thus relatively stable against temperature changes.

[0185] For example, the encapsulation substrate 160 may have a thickness of 70 μm to 80 μm.

[0186] The encapsulation substrate 160 may extend to a non-display area NA other than the disk area PA. For example, the encapsulation substrate 160 may be arranged to cover the connection line 175.

[0187] In the first exemplary embodiment of the present disclosure, the connection lines 175 are arranged between the gate lines 116 to disperse static electricity. Accordingly, damage to the display panel 110 during processing can be suppressed. Accordingly, the reliability of the display device can be improved.

[0188] Meanwhile, the connection lines of the present disclosure may be arranged on the same layer as the semiconductor layer under the gate lines. In this case, static electricity can be dispersed from the formation of the gate lines to the formation of the anodes. Details thereof will be described with reference to the drawings.

[0189] Figure 6 is a plan view of a part of a display panel according to a second exemplary embodiment of the present disclosure.

[0190] Figure 7 is Figure 6 an enlarged view of area B of

[0191] Figure 8 is Figure 7 a cross-sectional view taken along line I-I' of

[0192] According to Figures 6 to 8 the second exemplary embodiment of the display panel 210 is substantially the same as Figure 3 and Figure 4 the first exemplary embodiment, except that the connection lines 280 are arranged on the same layer as the semiconductor layer under the gate lines 116. Accordingly, redundant descriptions thereof will be omitted. The same components will be denoted by the same reference numerals. Hereinafter, descriptions of the same reference numerals may be made with reference to Figures 1 to 5 .

[0193] Referring to Figures 6 to 8 , the substrate 111 may be divided into a display area AA and a non-display area NA outside the display area AA.

[0194] Thin film transistors 120 and light emitting elements 130 may be provided in the display area AA of the substrate 111.

[0195] The non-display area NA of the substrate 111 may include a disk area PA.

[0196] A gate disk GP and a data disk DP may be provided in the disk area PA.

[0197] A light-shielding layer (not shown) may be provided on the substrate 111.

[0198] A buffer layer 112 may be provided on the substrate 111 on which the light-shielding layer is provided.

[0199] For example, the buffer layer 112 may have a multi-layer structure composed of a first buffer layer 112a and a second buffer layer 112b, but is not limited thereto.

[0200] A thin film transistor 120 may be provided on the buffer layer 112.

[0201] A semiconductor layer 124 may be provided on the second buffer layer 112b.

[0202] The semiconductor layer 124 may be made of an oxide semiconductor.

[0203] For example, the semiconductor layer 124 may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but is not limited thereto.

[0204] In addition, a connection line 280 may be provided in the non-display area NA. For example, the connection line 280 may be provided in a direction intersecting the gate line 116. In addition, for example, the connection line 280 may be provided in the non-display area NA between the display area AA and the gate disk GP in a direction intersecting the gate line 116. For example, the connection line 280 may be provided in a longitudinal direction (parallel) along the data line 117 from the first gate line 116 to the last gate line 116.

[0205] For example, the connection line 280 may be provided on the same layer as the semiconductor layer 124. In addition, the connection line 280 may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but is not limited thereto.

[0206] A gate insulating layer 115a may be provided on the semiconductor layer 124 and the connection line 280.

[0207] In a second exemplary embodiment of the present disclosure, a first contact hole 270a exposing a portion of the connection line 280 may be formed by selectively removing a portion of the gate insulating layer 115a. The first contact hole 270a may be located in a non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the first contact hole 270a may be provided in the non-display area NA between the display area AA and the gate pad GP.

[0208] A gate electrode 121 and a gate line 116 may be provided on the gate insulating layer 115a. For example, the gate line 116 may extend in a second direction intersecting the connection line 280 to a pad area PA of the non-display area NA.

[0209] In addition, a gate pad GP may be provided on the gate insulating layer 115a in the non-display area NA. For example, the gate pad GP may be provided at one end of each gate line 116 extending to the pad area PA.

[0210] In a second exemplary embodiment of the present disclosure, the gate line 116 may be electrically connected to the connection line 280 through the first contact hole 270a. Accordingly, all the gate lines 116 may be connected to each other through the connection line 280. In addition, even when static electricity is generated during subsequent processing, the static electricity may be dispersed through the connected gate lines 116.

[0211] In addition, an interlayer insulating layer 115b may be provided on the gate electrode 121, the gate line 116, and the gate pad GP.

[0212] In a second exemplary embodiment of the present disclosure, a second contact hole 270b exposing a portion of the connection line 280 may be formed by selectively removing a portion of the interlayer insulating layer 115b. The second contact hole 270b may be located in a non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the second contact hole 270b may be located in the non-display area NA between the display area AA and the gate pad GP. For example, the second contact hole 270b may be located on the connection line 280 between the gate lines 116. For example, the second contact hole 270b may have a sufficient lateral width to expose a portion of the connection line 280. Accordingly, the connection line 280 may be reliably disconnected through a process of disconnecting the connection line 280, which will be described below.

[0213] A source electrode 122, a drain electrode 123, and a data line 117 may be provided on the interlayer insulating layer 115b.

[0214] In the non-display area NA, a data pad DP may be provided on the interlayer insulating layer 115b. For example, the data pad DP may be provided at one end of each data line 117 extending to the pad area PA.

[0215] A protective layer 115f can be provided on the thin film transistor 120 configured as described above.

[0216] In addition, a planarization layer 115 can be provided on the protective layer 115f.

[0217] The planarization layer 115 can be an outer coating.

[0218] The planarization layer 115 can extend to a non-display area NA other than the disk area PA.

[0219] A light-emitting element 130 composed of an anode 131, an organic layer 132, and a cathode 133 can be provided on the planarization layer 115.

[0220] In this document, in the second exemplary embodiment of the present disclosure, a third contact hole 270c exposing a part of the protective layer 115f can be formed by selectively removing a part of the planarization layer 115. For example, the third contact hole 270c can be located on the second contact hole 270b. For example, the third contact hole 270c can be located on a connection line 280 between adjacent gate lines 116.

[0221] For example, the third contact hole 270c can have a lateral width greater than that of the second contact hole 270b.

[0222] In the second exemplary embodiment of the present disclosure, a fourth contact hole 270d exposing a part of the connection line 280 can be formed by selectively removing a part of the protective layer 115f exposed by the third contact hole 270c. For example, the fourth contact hole 270d can be located on the second contact hole 270b. Therefore, for example, the fourth contact hole 270d can expose the upper surface of the connection line 280 between adjacent gate lines 116.

[0223] For example, the fourth contact hole 270d can have a lateral width greater than that of the second contact hole 270b.

[0224] The anode 131 can be provided on the second planarization layer 115d.

[0225] In the bottom emission method, the anode 131 can be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. However, the present disclosure is not limited thereto. A top emission method can also be applied.

[0226] A gate disk terminal GPT and a data disk terminal DPT can be provided on the second planarization layer 115d in the non-display area NA. For example, the gate disk terminal GPT can be electrically connected to the gate disk GP through a gate disk contact hole GPH, and the data disk terminal DPT can be connected to the data disk DP through a data disk contact hole DPH.

[0227] In the second exemplary embodiment of the present disclosure, when forming (patterning) the anode 131, a portion of the connection line 280 exposed by the second contact hole 270b, the third contact hole 270c, and the fourth contact hole 270d may be removed by the same etching process. Accordingly, the connection line 280 between adjacent gate lines 116 may be disconnected.

[0228] A bank 115e may be provided on the anode 131 and the second planarization layer 115d.

[0229] The bank 115e may extend to a portion of the non-display area NA other than the disk area PA, but is not limited thereto.

[0230] An organic layer 132 may be provided between the anode 131 and the cathode 133.

[0231] The cathode 133 may be provided on the organic layer 132.

[0232] An inorganic layer 140 may be provided on the cathode 133.

[0233] The encapsulation substrate 160 may be provided on the inorganic layer 140 through an adhesive layer 165.

[0234] The adhesive layer 165 may extend to the non-display area NA other than the disk area PA. For example, the adhesive layer 165 may be provided to cover the connection line 280.

[0235] The encapsulation substrate 160 may be provided on the adhesive layer 165.

[0236] The encapsulation substrate 160 may extend to the non-display area NA other than the disk area PA. For example, the encapsulation substrate 160 may be provided to cover the connection line 280.

[0237] In the second exemplary embodiment of the present disclosure, the connection line 280 may be provided on the same layer as the semiconductor layer 124 under the gate line 116 to disperse static electricity. Accordingly, static electricity generated during the process from the formation of the gate line 116 to the formation of the anode 131 may be more effectively dispersed. Accordingly, the reliability of the display device may be further improved.

[0238] In addition, in the second exemplary embodiment of the present disclosure, the connection line 280 is made of a transparent metal oxide to minimize the reflectance of the display panel. Accordingly, low power consumption may be achieved. In particular, the second exemplary embodiment of the present disclosure may contribute to improving the quality of WOLED TVs and monitors (MNTs).

[0239] In addition, in the second exemplary embodiment of the present disclosure, the connection line 280 is made of the same transparent metal oxide as the anode 131. Therefore, when the anode 131 is formed, the connection line 280 can be patterned. Thus, the process can be simplified.

[0240] Hereinafter, a process of manufacturing a display device according to the second exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0241] Figures 9A to 9G is a diagram showing a process of manufacturing a display panel according to the second exemplary embodiment of the present disclosure Figure 7 of.

[0242] Figures 10A to 10G is a diagram sequentially showing a process of manufacturing a display panel according to the second exemplary embodiment of the present disclosure Figure 8 of.

[0243] Figures 9A to 9G and Figures 10A to 10G shows an example of a process of manufacturing a display panel according to the second exemplary embodiment of the present disclosure. The same components will be denoted by the same reference numerals. Hereinafter, the description of the same reference numerals may be referred to Figures 1 to 8 .

[0244] First, referring to Figure 9A and Figure 10A , a buffer layer 112 may be provided on a substrate 111, and the substrate 111 is divided into a display area AA and a non-display area NA.

[0245] Then, a semiconductor layer 124 may be provided on the buffer layer 112.

[0246] The semiconductor layer 124 may be made of an oxide semiconductor.

[0247] For example, the semiconductor layer 124 may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but is not limited thereto.

[0248] In addition, a connection line pattern 285 may be provided in the non-display area NA. For example, the connection line pattern 285 may be provided in a direction intersecting the gate line 116. For example, the connection line pattern 285 may be provided in the non-display area NA between the display area AA and the gate pad GP in a first direction intersecting the gate line 116. For example, the connection line pattern 285 may be provided (parallel) in a longitudinal direction from the first gate line 116 to the last gate line 116 along the data line 117.

[0249] The connection line pattern 285 may be made of the same transparent metal oxide as the semiconductor layer 124. The transparent metal oxide may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but is not limited thereto.

[0250] Thereafter, referring to Figure 9B and Figure 10B , a gate insulating layer 115a may be provided on the semiconductor layer 124 and the connection line pattern 285.

[0251] Then, a first contact hole 270a exposing a part of the connection line pattern 285 may be formed by selectively removing a part of the gate insulating layer 115a.

[0252] In this document, the first contact hole 270a may be located in the non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the first contact hole 270a may be located in the non-display area NA between the display area AA and the gate pad GP.

[0253] Then, referring to Figure 9C and Figure 10C , a gate electrode 121 and a gate line 116 may be provided on the gate insulating layer 115a.

[0254] For example, the gate line 116 may extend to the pad area PA of the non-display area NA in a second direction intersecting the connection line pattern 285.

[0255] In addition, a gate pad GP may be provided on the gate insulating layer 115a in the non-display area NA. For example, the gate pad GP may be provided at one end of each gate line 116 extending to the pad area PA.

[0256] In the second exemplary embodiment of the present disclosure, the gate line 116 may be connected to the connection line pattern 285 through the first contact hole 270a. Therefore, all the gate lines 116 may be connected to each other through the connection line pattern 285. In addition, even when static electricity is generated during subsequent processing, the static electricity may be dispersed through the connected gate lines 116.

[0257] Thereafter, referring to Figure 9D and Figure 10D , an interlayer insulating layer 115b may be provided on the gate electrode 121, the gate line 116, and the gate pad GP.

[0258] Then, a second contact hole 270b that exposes a part of the connection line pattern 285 may be formed by selectively removing a part of the interlayer insulating layer 115b. The second contact hole 270b may be located in the non-display area NA adjacent to the display area AA, but is not limited thereto. In addition, for example, the second contact hole 270b may be located in the non-display area NA between the display area AA and the gate pad GP. In addition, for example, the second contact hole 270b may be located on the connection line pattern 285 between the gate lines 116.

[0259] Thereafter, referring to Figure 9E 、 Figure 9F and Figure 10E a source electrode 122, a drain electrode 123, and a data line 117 may be provided on the interlayer insulating layer 115b.

[0260] In addition, a data pad DP may be provided on the interlayer insulating layer 115b in the non-display area NA. For example, the data pad DP may be provided at one end of each data line 117 extending to the pad area PA.

[0261] Then, a protective layer 115f may be provided.

[0262] In addition, a planarization layer 115 may be provided on the protective layer 115f.

[0263] The planarization layer 115 may extend to the non-display area NA except for the pad area PA.

[0264] Thereafter, in the second exemplary embodiment of the present disclosure, a third contact hole 270c that exposes a part of the protective layer 115f may be formed by selectively removing a part of the planarization layer 115. For example, the third contact hole 270c may be located on the second contact hole 270b. For example, the third contact hole 270c may be located on the connection line pattern 285 between adjacent gate lines 116.

[0265] Then, a fourth contact hole 270d that exposes a part of the connection line pattern 285 may be formed by selectively removing a part of the protective layer 115f exposed by the third contact hole 270c. For example, the fourth contact hole 270d may be located on the second contact hole 270b. Therefore, for example, the fourth contact hole 270d may expose the upper surface of the connection line pattern 285 between adjacent gate lines 116.

[0266] Herein, the third contact hole 270c and the fourth contact hole 270d may be formed sequentially, but the present disclosure is not limited thereto. The third contact hole 270c and the fourth contact hole 270d may be formed simultaneously.

[0267] Thereafter, referring to Figure 9G 、 Figure 10FAnd Figure 10G An anode 131 may be disposed on the second planarization layer 115d.

[0268] In the bottom emission method, the anode 131 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like.

[0269] A gate pad terminal GPT and a data pad terminal DPT may be disposed on the second planarization layer 115d in the non-display area NA. For example, the gate pad terminal GPT may be electrically connected to the gate pad GP through a gate pad contact hole GPH, and the data pad terminal DPT may be connected to the data pad DP through a data pad contact hole DPH.

[0270] In the present disclosure, in the second exemplary embodiment, when forming (patterning) the anode 131, a part of the connection line pattern 285 exposed by the second contact hole 270b, the third contact hole 270c, and the fourth contact hole 270d may be removed by the same etching process. Accordingly, the connection line pattern 285 between adjacent gate lines 116 may be disconnected to form a connection line 280.

[0271] Then, a bank 115e may be disposed on the anode 131 and the second planarization layer 115d.

[0272] The bank 115e may extend to a part of the non-display area NA other than the pad area PA and may fill the space between the disconnected connection lines 280.

[0273] Meanwhile, according to the present disclosure, a first connection line connecting the gate lines to each other and a second connection line connecting the first connection lines are provided. Accordingly, static electricity may be dispersed. Details thereof will be described with reference to the accompanying drawings.

[0274] Figure 11 is a plan view of a display panel according to a third exemplary embodiment of the present disclosure.

[0275] Figure 12 is Figure 11 an enlarged view of region C of

[0276] Figure 13A is Figure 12 a cross-sectional view taken along line II-II' of

[0277] Figure 13B is Figure 12 a cross-sectional view taken along line III-III' of

[0278] According to Figures 11 to 13A and Figure 13B the third exemplary embodiment of the display panel 310 is the same asFigure 6 and Figure 8 is substantially the same as the second exemplary embodiment, except that the connection lines 375 and 380 are composed of a first connection line 375 that connects the gate lines 116 to each other and a second connection line 380 that connects the first connection line 375. Therefore, its redundant description will be omitted. The same components will be denoted by the same reference numerals. Hereinafter, the description of the same reference numerals may be referred to Figures 1 to 8 .

[0279] Referring to Figures 11 to 13A and Figure 13B , the substrate 111 may be divided into a display area AA and a non-display area NA outside the display area AA.

[0280] Thin film transistors 120 and light emitting elements 130 may be provided in the display area AA of the substrate 111.

[0281] The non-display area NA of the substrate 111 may include a disc area PA.

[0282] A gate disc GP and a data disc DP may be provided in the disc area PA.

[0283] A buffer layer 112 may be provided on the substrate 111.

[0284] A semiconductor layer 124 may be provided on the buffer layer 112.

[0285] A gate insulating layer 115a may be provided on the semiconductor layer 124.

[0286] A gate electrode 121 and a gate line 116 may be provided on the gate insulating layer 115a. For example, the gate line 116 may extend to the disc area PA of the non-display area NA.

[0287] In addition, a gate disc GP may be provided on the gate insulating layer 115a in the non-display area NA. For example, the gate disc GP may be provided at one end of each gate line 116 extending to the disc area PA.

[0288] In the third exemplary embodiment of the present disclosure, a first connection line 375 may be provided on the gate insulating layer 115a in a direction intersecting the gate line 116.

[0289] For example, the first connection line 375 may be provided (parallel) in the longitudinal direction of the data line 117 from the first gate line 116 to the last gate line 116. Therefore, all the gate lines 116 may be connected to each other through the first connection line 375. In addition, even when static electricity is generated during a subsequent data line process, the static electricity may be dispersed through the connected gate lines 116.

[0290] In addition, an interlayer insulating layer 115b may be provided on the gate electrode 121, the gate line 116, the gate pad GP, and the first connection line 375.

[0291] In the third exemplary embodiment of the present disclosure, a first contact hole 370a exposing a part of the first connection line 375 may be formed by selectively removing a part of the interlayer insulating layer 115b. The first contact hole 370a may be located in a non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the first contact hole 370a may be located in the non-display area NA between the display area AA and the gate pad GP. For example, the first contact hole 370a may be located on the first connection line 375 between adjacent gate lines 116. For example, the first contact hole 370a may be provided at both ends of the first connection line 375 between adjacent gate lines 116.

[0292] In addition, in the third exemplary embodiment of the present disclosure, a second contact hole 370b exposing a part of the first connection line 375 may be formed by selectively removing another part of the interlayer insulating layer 115b. The second contact hole 370b may be located in a non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the second contact hole 370b may be located in the non-display area NA between the display area AA and the gate pad GP. For example, the second contact hole 370b may be located on the first connection line 375 between the gate lines 116. For example, the second contact hole 370b may be provided between the first contact holes 370a at both ends of the first connection line 375 between adjacent gate lines 116.

[0293] In addition, for example, the second contact hole 370b may have a sufficient lateral width to expose another part of the first connection line 375. Therefore, by the process of disconnecting the first connection line 375 to be described below, the first connection line 375 can be reliably disconnected.

[0294] A source electrode 122, a drain electrode 123, and a data line 117 may be provided on the interlayer insulating layer 115b.

[0295] A data pad DP may be provided on the interlayer insulating layer 115b in the non-display area NA. For example, the data pad DP may be provided at one end of each data line 117 extending to the pad area PA.

[0296] In the third exemplary embodiment of the present disclosure, a second connection line 380 connecting both ends of the first connection line 375 may be provided on the interlayer insulating layer 115b. For example, the second connection line 380 may be electrically connected to both ends of the first connection line 375 through first contact holes 370a at both ends. For example, the second connection line 380 in the non-display area NA may be made of the same material on the same layer as the data line 117 in the display area AA, but is not limited thereto.

[0297] In the third exemplary embodiment of the present disclosure, when forming (patterning) the data line 117, another part of the first connection line 375 exposed by the second contact hole 370b may be removed through an etching process. Accordingly, the first connection line 375 between adjacent gate lines 116 may be disconnected.

[0298] For example, the second connection line 380 may bypass and connect the disconnected first connection line 375.

[0299] A protective layer 115f may be provided on the thin film transistor 120 configured as described above.

[0300] In addition, a planarization layer 115 may be provided on the protective layer 115f.

[0301] The planarization layer 115 may be an overcoat layer.

[0302] The planarization layer 115 may extend to the non-display area NA except for the disk area PA.

[0303] A light-emitting element 130 including an anode 131, an organic layer 132, and a cathode 133 may be provided on the planarization layer 115.

[0304] Here, in the third exemplary embodiment of the present disclosure, a third contact hole 370c exposing a part of the protective layer 115f may be formed by selectively removing a part of the planarization layer 115. For example, the third contact hole 370c may be located on the second connection line 380 positioned on one side of the first connection line 375. For example, the third contact hole 370c may be located on the second connection line 380 between adjacent gate lines 116. For example, the third contact hole 370c may have a sufficient lateral width to expose a part of the second connection line 380.

[0305] In a third exemplary embodiment of the present disclosure, a fourth contact hole 370d exposing a part of the second connection line 380 may be formed by selectively removing a part of the protective layer 115f exposed through the third contact hole 370c. For example, the fourth contact hole 370d may expose the upper surface of the second connection line 380 between adjacent gate lines 116. For example, the fourth contact hole 370d may have a sufficient lateral width to expose a part of the second connection line 380. Therefore, the second connection line 380 can be reliably disconnected through a process of disconnecting the second connection line 380 to be described below.

[0306] For example, the third contact hole 370c may have a larger lateral width than the fourth contact hole 370d, but is not limited thereto.

[0307] The anode 131 may be disposed on the planarization layer 115.

[0308] In the non-display area NA, a gate pad terminal GPT and a data pad terminal DPT may be disposed on the planarization layer 115. For example, the gate pad terminal GPT may be electrically connected to the gate pad GP through a gate pad contact hole GPH, and the data pad terminal DPT may be connected to the data pad DP through a data pad contact hole DPH.

[0309] In a third exemplary embodiment of the present disclosure, after forming (patterning) the anode 131, a part of the second connection line 380 exposed through the fourth contact hole 370d may be removed through an additional etching process. Therefore, the second connection line 380 between adjacent gate lines 116 may be disconnected.

[0310] A bank 115e may be disposed on the anode 131 and the planarization layer 115.

[0311] The bank 115e may extend to a part of the non-display area NA other than the pad area PA, but is not limited thereto.

[0312] In a third exemplary embodiment of the present disclosure, the first connection line 375 connecting the gate lines 116 to each other and the second connection line 380 connecting the first connection lines 375 are provided to dissipate static electricity. Therefore, static electricity generated during the process from the formation of the gate lines 116 to the formation of the anode 131 can be effectively dissipated. Therefore, the reliability of the display device can be improved.

[0313] Hereinafter, a process of manufacturing a display device according to a third exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0314] Figures 14A to 14F is a diagram showing a process of manufacturing Figure 12 a display panel according to a third exemplary embodiment of the present disclosure.

[0315] Figures 15A to 15F sequentially shows the process of manufacturing Figure 13B a display panel according to a third exemplary embodiment of the present disclosure.

[0316] Figures 14A to 14F and Figures 15A to 15F shows an example of the process of manufacturing a display panel according to a third exemplary embodiment of the present disclosure. The same components will be denoted by the same reference numerals. Hereinafter, the description of the same reference numerals may refer to Figures 1 to 8 .

[0317] Referring to Figure 14A and Figure 15A , a buffer layer 112 may be provided on the substrate 111, and the substrate 111 is divided into a display area AA and a non-display area NA.

[0318] Then, a semiconductor layer 124 may be provided on the buffer layer 112.

[0319] Thereafter, a gate insulating layer 115a may be provided on the semiconductor layer 124.

[0320] A gate electrode 121 and a gate line 116 may be provided on the gate insulating layer 115a. For example, the gate line 116 may extend to the disk area PA of the non-display area NA.

[0321] In addition, a gate disk GP may be provided on the gate insulating layer 115a in the non-display area NA. For example, the gate disk GP may be provided at one end of each gate line 116 extending to the disk area PA.

[0322] In the third exemplary embodiment of the present disclosure, a first connection line pattern 376 may be provided on the gate insulating layer 115a in a direction intersecting the gate line 116.

[0323] For example, the first connection line pattern 376 may be provided (parallel) in the longitudinal direction (from the first gate line 116 to the last gate line 116) along the data line 117. Thus, all the gate lines 116 may be connected to each other through the first connection line pattern 376. In addition, even when static electricity is generated during subsequent data line processing, the static electricity may be dispersed through the connected gate lines 116.

[0324] Then, referring to Figure 14B and Figure 15B , an interlayer insulating layer 115b may be provided on the gate electrode 121, the gate line 116, the gate disk GP, and the first connection line pattern 376.

[0325] Thereafter, a first contact hole 370a exposing a part of the first connection line pattern 376 may be formed by selectively removing a part of the interlayer insulating layer 115b. The first contact hole 370a may be located in the non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the first contact hole 370a may be located in the non-display area NA between the display area AA and the gate pad GP. For example, the first contact hole 370a may be located on the first connection line pattern 376 between adjacent gate lines 116. For example, the first contact hole 370a may be provided at both ends of the first connection line pattern 376 between adjacent gate lines 116.

[0326] In addition, a second contact hole 370b exposing another part of the first connection line pattern 376 may be formed by selectively removing another part of the interlayer insulating layer 115b. The second contact hole 370b may be located in the non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the second contact hole 370b may be located in the non-display area NA between the display area AA and the gate pad GP. For example, the second contact hole 370b may be located on the first connection line pattern 376 between adjacent gate lines 116. For example, the second contact hole 370b may be provided between the first contact holes 370a at both ends between adjacent gate lines 116. For example, the second contact hole 370b may have a sufficient lateral width to expose another part of the first connection line pattern 376.

[0327] Then, referring to Figure 14C and Figure 15C , a source electrode 122, a drain electrode 123, and a data line 117 may be provided on the interlayer insulating layer 115b.

[0328] A data pad DP may be provided on the interlayer insulating layer 115b in the non-display area NA. For example, the data pad DP may be provided at one end of each data line 117 extending to the pad area PA.

[0329] A second connection line pattern 385 connecting both ends of the first connection line pattern 376 may be provided on the interlayer insulating layer 115b in the non-display area NA. For example, the second connection line pattern 385 may be electrically connected to both ends of the first connection line pattern 376 through the first contact holes 370a at both ends. For example, the second connection line pattern 385 may be provided on the same layer as the data line 117 at the same time, but is not limited thereto.

[0330] In the third exemplary embodiment of the present disclosure, when forming (patterning) the data line 117, another part of the first connection line pattern 376 exposed by the second contact hole 370b may be removed through an etching process. Accordingly, the first connection line pattern 376 between adjacent gate lines 116 may be disconnected to form a first connection line 375.

[0331] For example, the second connection line pattern 385 may bypass and connect the disconnected first connection line 375.

[0332] Then, referring to Figure 14D and Figure 15D , the protective layer 115f may be provided.

[0333] In addition, a planarization layer 115 may be provided on the protective layer 115f.

[0334] The planarization layer 115 may extend to the non-display area NA other than the disk area PA.

[0335] Thereafter, in the third exemplary embodiment of the present disclosure, a third contact hole 370c exposing a part of the protective layer 115f may be formed by selectively removing a part of the planarization layer 115. For example, the third contact hole 370c may be located on the second connection line pattern 385 positioned on one side of the first connection line 375. For example, the third contact hole 370c may be located on the second connection line pattern 385 between adjacent gate lines 116. For example, the third contact hole 370c may have a sufficient lateral width to expose a part of the second connection line pattern 385.

[0336] Then, referring to Figure 14E and Figure 15E , a fourth contact hole 370d exposing a part of the second connection line pattern 385 may be formed by selectively removing a part of the protective layer 115f exposed by the third contact hole 370c. For example, the fourth contact hole 370d may expose the upper surface of the second connection line pattern 385 between adjacent gate lines 116. For example, the fourth contact hole 370d may have a sufficient lateral width to expose a part of the second connection line pattern 385.

[0337] For example, the third contact hole 370c may have a larger lateral width than the fourth contact hole 370d, but is not limited thereto.

[0338] Herein, the third contact hole 370c and the fourth contact hole 370d may be formed sequentially, but the present disclosure is not limited thereto. The third contact hole 370c and the fourth contact hole 370d may be formed simultaneously.

[0339] Thereafter, referring to Figure 14F and Figure 15F , an anode 131 may be provided on the planarization layer 115.

[0340] In the non-display area NA, gate pad terminals GPT and data pad terminals DPT may be provided on the planarization layer 115. For example, the gate pad terminal GPT may be electrically connected to the gate pad GP through a gate pad contact hole GPH, and the data pad terminal DPT may be connected to the data pad DP through a data pad contact hole DPH.

[0341] In the third exemplary embodiment of the present disclosure, after forming (patterning) the anode 131, a part of the second connection line pattern 385 exposed by the fourth contact hole 370d may be removed by an additional etching process. Accordingly, the second connection line pattern 385 between adjacent gate lines 116 may be disconnected to form the second connection line 380.

[0342] Then, a bank 115e may be provided on the anode 131 and the planarization layer 115.

[0343] The bank 115e may extend to a part of the non-display area NA other than the pad area PA, and may fill the space between the second connection lines 380 that are disconnected from each other.

[0344] Meanwhile, according to the present disclosure, connection lines for connecting the gate lines to each other are provided. Accordingly, static electricity may be dispersed. Details thereof will be described with reference to the drawings.

[0345] Figure 16 is a plan view of a part of a display panel according to a fourth exemplary embodiment of the present disclosure.

[0346] Figure 17 is along Figure 16 a cross-sectional view taken along line IV-IV'.

[0347] Figure 16 and Figure 17 The display panel 410 according to the fourth exemplary embodiment of Figures 11 to 13A and Figure 13B is substantially the same as the third exemplary embodiment of Figures 1 to 13A and Figure 13B , except that the display panel 410 includes a connection line 475. Accordingly, redundant descriptions thereof will be omitted. The same components will be denoted by the same reference numerals. Hereinafter, descriptions of the same reference numerals may be made with reference to

[0348] Referring to Figure 16 and Figure 17 , the connection line 475 may be provided on the gate insulating layer 115a in the non-display area NA in a direction crossing the gate lines 116.

[0349] For example, the connection line 475 may be provided (parallel) in the longitudinal direction from the first gate line 116 to the last gate line 116 along the data line 117.

[0350] Meanwhile, in a fourth exemplary embodiment of the present disclosure, a first contact hole 470a exposing a part of the protective layer 115f can be formed by selectively removing a part of the planarization layer 115. Here, for example, the first contact hole 470a can be located on a connection line 475 between adjacent gate lines 116. In addition, for example, the first contact hole 470a can have a sufficient lateral width to expose a part of the connection line 475. Further, in the fourth exemplary embodiment of the present disclosure, a second contact hole 470b exposing a part of the connection line 475 can be formed by selectively removing a part of the protective layer 115f exposed by the first contact hole 470a. For example, the second contact hole 470b can expose the upper surface of the connection line 475 between adjacent gate lines 116. For example, the second contact hole 470b can have a sufficient lateral width to expose a part of the connection line 475.

[0351] In the fourth exemplary embodiment of the present disclosure, after forming (patterning) the anode 131, a part of the connection line 475 exposed by the second contact hole 475b can be removed by an additional etching process. Accordingly, the connection line 475 between adjacent gate lines 116 can be disconnected.

[0352] Figure 18 is a plan view of a part of a display panel according to a fifth exemplary embodiment of the present disclosure.

[0353] Figure 19 is along Figure 18 taken cross-sectional view along line V-V'.

[0354] Figure 18 and Figure 19 The display panel 510 according to the fifth exemplary embodiment of Figure 16 and Figure 17 is substantially the same as the fourth exemplary embodiment of Figures 1 to 7 , except that a second connection line 580 is provided on the first connection line 575. Accordingly, redundant descriptions thereof will be omitted. The same components will be denoted by the same reference numerals. Hereinafter, the description of the same reference numerals can be referred to

[0355] Referring to Figure 18 and Figure 19 , the first connection line 575 can be provided on the gate insulating layer 115a in a non-display area NA in a direction crossing the gate lines 116. For example, the first connection line 575 can be provided (parallel) in a longitudinal direction from the first gate line 116 to the last gate line 116 along the data line 117.

[0356] In a fifth exemplary embodiment of the present disclosure, a second connection line 580 having an island shape is further provided on the first connection line 575.

[0357] Specifically, for example, an interlayer insulating layer 115b may be provided on the first connection line 575.

[0358] In a fifth exemplary embodiment of the present disclosure, a first contact hole 570a exposing a part of the first connection line 575 may be formed by selectively removing a part of the interlayer insulating layer 115b. For example, the first contact hole 570a may be located on the first connection line 575 between adjacent gate lines 116. For example, the first contact hole 570a may be provided at both ends of the first connection line 575 between adjacent gate lines 116.

[0359] Furthermore, in a fifth exemplary embodiment of the present disclosure, a second contact hole 570b exposing a part of the first connection line 575 may be formed by selectively removing another part of the interlayer insulating layer 115b. For example, the second contact hole 570b may be located on the first connection line 575 between adjacent gate lines 116. For example, the second contact hole 570b may be provided between the first contact holes 570a at both ends between adjacent gate lines 116. For example, the second contact hole 570b may have a sufficient lateral width to expose a part of the first connection line 575.

[0360] In a fifth exemplary embodiment of the present disclosure, a second connection line 580 electrically connected to the first connection line 575 through the first contact hole 570a may be provided on the interlayer insulating layer 115b. For example, the second connection line 580 may be electrically connected to the first connection line 575 through the first contact holes 570a at both ends.

[0361] Furthermore, in a fifth exemplary embodiment of the present disclosure, a third contact hole 570c exposing a part of the protective layer 115f may be formed by selectively removing a part of the planarization layer 115. For example, the third contact hole 570c may be located on the second connection line 580 between adjacent gate lines 116. For example, the third contact hole 570c may have a sufficient lateral width to expose a part of the second connection line 580. For example, the third contact hole 570c may be located on the second contact hole 570b.

[0362] In the fifth exemplary embodiment of the present disclosure, a fourth contact hole 570d exposing a part of the second connection line 580 may be formed by selectively removing a part of the protective layer 115f exposed through the third contact hole 570c. For example, the fourth contact hole 570d may expose the upper surface of the second connection line 580 between adjacent gate lines 116. For example, the fourth contact hole 570d may have a sufficient lateral width to expose a part of the second connection line 580. For example, the fourth contact hole 570d may be located on the second contact hole 570b and the third contact hole 570c.

[0363] In the fifth exemplary embodiment of the present disclosure, after forming (patterning) the anode 131, a part of the second connection line 580 exposed through the fourth contact hole 570d and a part of the underlying first connection line 575 may be removed by an additional etching process. Accordingly, each of the first connection line 575 and the second connection line 580 between adjacent gate lines 116 may be disconnected.

[0364] Meanwhile, the first exemplary embodiment to the fifth exemplary embodiment of the present disclosure may be applicable to static electricity in the data lines. An example in which the second exemplary embodiment is applicable to the data lines will be described in detail with reference to the drawings.

[0365] Figure 20 is a plan view of a part of a display panel according to a sixth exemplary embodiment of the present disclosure.

[0366] Figure 20 The display panel 610 according to the sixth exemplary embodiment is substantially the same as Figures 6 to 8 the second exemplary embodiment, except that the connection line 680 is applicable to the data line 117. Accordingly, redundant descriptions thereof will be omitted. The same components will be denoted by the same reference numerals. Hereinafter, the description of the same reference numerals may be made with reference to Figures 1 to 8 .

[0367] Referring to Figure 20 , the substrate 111 may be divided into a display area AA and a non-display area NA outside the display area AA.

[0368] The non-display area NA of the substrate 111 may include a disk area PA.

[0369] A gate disk GP and a data disk DP may be provided in the disk area PA.

[0370] A semiconductor layer 124 may be provided on the buffer layer 112.

[0371] The semiconductor layer 124 may be made of an oxide semiconductor.

[0372] For example, the semiconductor layer 124 may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but is not limited thereto.

[0373] In addition, the connection line 680 may be provided in the non-display area NA. For example, the connection line 680 may be provided in a direction intersecting the data line 117. In addition, for example, the connection line 680 may be provided in the non-display area NA between the display area AA and the gate pad GP in a second direction intersecting the data line 117. For example, the connection line 680 may be provided (parallel) in the longitudinal direction from the first data line 117 to the last data line 117 along the gate line 116.

[0374] For example, the connection line 680 may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but is not limited thereto.

[0375] The gate insulating layer 115a may be provided on the semiconductor layer 124 and the connection line 680.

[0376] In the sixth exemplary embodiment of the present disclosure, the first contact hole 670a exposing a part of the connection line 680 may be formed by selectively removing a part of the gate insulating layer 115a. The first contact hole 670a may be located in the non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the first contact hole 670a may be provided in the non-display area NA between the display area AA and the gate pad GP.

[0377] The gate electrode 121 and the gate line 116 may be provided on the gate insulating layer 115a.

[0378] In addition, the interlayer insulating layer 115b may be provided on the gate electrode 121, the gate line 116, and the gate pad GP.

[0379] In the sixth exemplary embodiment of the present disclosure, the second contact hole 670b exposing a part of the connection line 680 may be formed by selectively removing a part of the interlayer insulating layer 115b. The second contact hole 670b may be located in the non-display area NA adjacent to the display area AA, but is not limited thereto. For example, the second contact hole 670b may be located in the non-display area NA between the display area AA and the gate pad GP. For example, the second contact hole 670b may be located on the connection line 680 between the data lines 117. For example, the second contact hole 670b may have a sufficient lateral width to expose a part of the connection line 680. Therefore, the connection line 680 can be reliably disconnected by a process of disconnecting the connection line 680 to be described below.

[0380] The source electrode 122, the drain electrode 123, and the data line 117 may be provided on the interlayer insulating layer 115b.

[0381] In the sixth exemplary embodiment of the present disclosure, the data line 117 may be electrically connected to the connection line 680 through the first contact hole 670a. Accordingly, all the data lines 117 may be connected to each other through the connection line 680. In addition, even when static electricity is generated during subsequent processing, the static electricity may be dispersed through the connected data lines 117.

[0382] The protective layer 115f may be provided on the thin film transistor 120.

[0383] In addition, the planarization layer 115 may be provided on the protective layer 115f.

[0384] Herein, in the sixth exemplary embodiment of the present disclosure, the third contact hole 670c exposing a part of the protective layer 115f may be formed by selectively removing a part of the planarization layer 115. For example, the third contact hole 670c may be located on the second contact hole 670b. For example, the third contact hole 670c may be located on the connection line 680 between adjacent data lines 117.

[0385] For example, the third contact hole 670c may have a larger lateral width than the second contact hole 670b.

[0386] In the sixth exemplary embodiment of the present disclosure, the fourth contact hole 670d exposing a part of the connection line 680 may be formed by selectively removing a part of the protective layer 115f exposed by the third contact hole 670c. For example, the fourth contact hole 670d may be located on the second contact hole 670b. Accordingly, for example, the fourth contact hole 670d may expose the upper surface of the connection line 680 between adjacent data lines 117.

[0387] For example, the fourth contact hole 670d may have a larger lateral width than the second contact hole 670b.

[0388] The anode 131 may be provided on the planarization layer 115.

[0389] In the bottom emission method, the anode 131 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. However, the present disclosure is not limited thereto. The top emission method may also be applied.

[0390] In the sixth exemplary embodiment of the present disclosure, when forming (patterning) the anode 131, a part of the connection line 680 exposed by the second contact hole 670b, the third contact hole 670c, and the fourth contact hole 670d may be removed by the same etching process. Accordingly, the connection line 680 between adjacent data lines 117 may be disconnected.

[0391] In the sixth exemplary embodiment of the present disclosure, the connection line 680 may be disposed on the same layer as the semiconductor layer 124 under the data line 117 to disperse static electricity. Accordingly, the static electricity generated during the process from the formation of the data line 117 to the formation of the anode 131 may be dispersed. Accordingly, the reliability of the display device may be improved.

[0392] In addition, in the sixth exemplary embodiment of the present disclosure, the connection line 680 is made of a transparent metal oxide to minimize the reflectance of the display panel. Accordingly, low power consumption may be achieved.

[0393] In addition, in the sixth exemplary embodiment of the present disclosure, the connection line 680 is made of the same transparent metal oxide as the anode 131. Accordingly, when forming the anode 131, the connection line 680 may be patterned. Accordingly, the process may be simplified.

[0394] The exemplary embodiment of the present disclosure may be described as follows:

[0395] According to an aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area; a semiconductor layer disposed on the substrate in the display area; a connection line disposed on the substrate in the non-display area; a gate insulating layer disposed on the semiconductor layer and the connection line; a gate line disposed on the gate insulating layer and connected to the connection line; at least one insulating layer disposed on the gate line; and a light-emitting element disposed on the at least one insulating layer; wherein the connection line may be made of a metal oxide and disposed on the same layer as the semiconductor layer, and the connection line between adjacent gate lines may be partially removed and thus disconnected.

[0396] The display device may further include: a first contact hole exposing a part of the connection line by removing a part of the gate insulating layer, wherein the first contact hole is located between the non-display area between the display area and the gate pad.

[0397] The gate line may be connected to the connection line through the first contact hole.

[0398] The at least one insulating layer may include an interlayer insulating layer disposed on the gate line, and the display device may further include: a second contact hole exposing a part of the connection line by selectively removing a part of the interlayer insulating layer.

[0399] The second contact hole may be located on a connection line between adjacent gate lines, and an exposed portion of the connection line under the second contact hole may be removed.

[0400] The connection line may be disposed in a direction intersecting the gate line.

[0401] The display device may further include: a data line disposed on the gate line in a direction parallel to the connection line, and the at least one insulating layer may include a protective layer and a planarization layer disposed on the data line.

[0402] The display device may further include: a third contact hole that exposes a part of the protective layer by selectively removing a part of the planarization layer, and the third contact hole may be located on the second contact hole.

[0403] The display device may further include: a fourth contact hole that exposes a part of the connection line by selectively removing a part of the protective layer exposed by the third contact hole, and the fourth contact hole may be located on the second contact hole.

[0404] The third contact hole may be located on a connection line between adjacent gate lines, and the fourth contact hole may expose an upper surface of the connection line between adjacent gate lines.

[0405] The third contact hole and the fourth contact hole may have a larger lateral width than the second contact hole.

[0406] The light-emitting element may include an anode, and the connection line may not be disconnected before the anode can be patterned, and in the case where the anode can be patterned, a part of the connection line exposed by the fourth contact hole may be removed to disconnect the connection line between adjacent gate lines.

[0407] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area; a gate line disposed on the substrate; a first connection line disposed in a direction intersecting the gate line and connected to the gate line; an interlayer insulating layer disposed on the gate line; a second connection line disposed on the interlayer insulating layer and connected to the first connection line; at least one insulating layer disposed on the second connection line; and a light-emitting element disposed on the at least one insulating layer, and each of the first connection line and the second connection line between adjacent gate lines may be partially removed and thus disconnected.

[0408] The display device may further include: a first contact hole that exposes a part of the first connection line by removing a part of the interlayer insulating layer, and the first contact hole may be located between the non-display area between the display area and the gate pad.

[0409] The first contact holes may be provided at both ends of a first connection line between adjacent gate lines, and a second connection line may be connected to the first connection line through the first contact holes at both ends.

[0410] The display device may further include: second contact holes, which may expose another part of the first connection line by selectively removing another part of the interlayer insulating layer.

[0411] The second contact holes may be located on the first connection line between adjacent gate lines, and the second contact holes may be provided between the first contact holes at both ends between adjacent gate lines.

[0412] The display device may further include: data lines, which are provided on the gate lines in a direction parallel to the first connection line, and at least one insulating layer may include a protective layer and a planarization layer provided on the data lines.

[0413] The display device may further include: third contact holes, which may expose a part of the protective layer by selectively removing a part of the planarization layer, and the third contact holes may be located on the second connection line positioned on one side of the first connection line.

[0414] The display device may further include: fourth contact holes, which may expose a part of the second connection line by selectively removing a part of the protective layer exposed by the third contact holes, and the fourth contact holes may expose the upper surface of the second connection line between adjacent gate lines.

[0415] Before the data lines may be patterned, the first connection line may not be disconnected, and in the case where the data lines may be patterned, the other part of the first connection line exposed by the second contact holes may also be removed to disconnect the first connection line between adjacent gate lines.

[0416] The light-emitting element may include an anode, and before the anode may be patterned, the second connection line may not be disconnected, and in the case where the anode may be patterned, the part of the second connection line exposed by the fourth contact holes may also be removed to disconnect the second connection line between adjacent gate lines.

[0417] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate including a display area and a non-display area; a semiconductor layer disposed in the display region on the substrate; A connecting line, which is arranged in the non-display area on the substrate; A gate insulating layer, which is disposed on the semiconductor layer and the connecting line; a gate line disposed on the gate insulating layer and connected to the connection line; at least one insulating layer disposed on the gate line; as well as a light emitting element disposed on the at least one insulating layer, The connection line is made of metal oxide and is disposed on the same layer as the semiconductor layer, and the connection line between adjacent gate lines is partially removed and disconnected.

2. The display device according to claim 1, further comprising: a first contact hole, wherein the first contact hole is formed by removing a portion of the gate insulating layer so as to expose a portion of the connection line; Wherein, the first contact hole is located in the non-display area between the display area and the gate plate.

3. The display device according to claim 2, wherein: The gate line is connected to the connection line through the first contact hole.

4. The display device according to claim 1, wherein: The at least one insulating layer includes an interlayer insulating layer disposed on the gate line, and The display device further includes a second contact hole, which is formed by selectively removing a portion of the interlayer insulating layer to expose a portion of the connecting line.

5. The display device according to claim 4, wherein: The second contact hole is located on a connection line between adjacent gate lines, and Wherein, the exposed portion of the connecting line below the second contact hole is removed.

6. The display device according to claim 1, wherein: The connection line is disposed in a direction crossing the gate line.

7. The display device according to claim 4, further comprising: a data line disposed on the gate line in a direction parallel to the connection line, Wherein, the at least one insulating layer includes a protection layer and a planarization layer disposed on the data line.

8. The display device according to claim 7, further comprising: a third contact hole, the third contact hole being formed by selectively removing a portion of the planarization layer so as to expose a portion of the protection layer, Wherein, the third contact hole is located on the second contact hole.

9. The display device according to claim 8, further comprising: a fourth contact hole formed by selectively removing a portion of the protective layer exposed through the third contact hole so as to expose a portion of the connection line, Wherein, the fourth contact hole is located on the second contact hole.

10. The display device according to claim 9, wherein: The third contact hole is located on the connection line between adjacent gate lines, and The fourth contact hole exposes the upper surface of the connection line between adjacent gate lines.

11. The display device according to claim 9, wherein: The third contact hole and the fourth contact hole have a greater lateral width than the second contact hole.

12. The display device according to claim 10, wherein: The light emitting element includes an anode, and The connecting wire is not disconnected before the anode is patterned, and Wherein, when the anode is patterned, the portion of the connection line exposed through the fourth contact hole is also removed to disconnect the connection line between adjacent gate lines.

13. A display device, comprising: A substrate including a display area and a non-display area; A gate line is disposed on the substrate; a first connection line disposed in a direction crossing the gate line and connected to the gate line; an interlayer insulating layer disposed on the gate line; a second connection line disposed on the interlayer insulating layer and connected to the first connection line; at least one insulating layer disposed on the second connecting line; as well as a light emitting element disposed on the at least one insulating layer, Wherein, each of the first connection line and the second connection line between adjacent gate lines is partially removed and disconnected.

14. The display device according to claim 13, further comprising: a first contact hole, wherein the first contact hole is formed by removing a portion of the interlayer insulating layer so as to expose a portion of the first connection line; Wherein, the first contact hole is located in the non-display area between the display area and the gate plate.

15. The display device according to claim 14, wherein: The first contact holes are disposed at both ends of the first connection line between adjacent gate lines, and The second connection line is connected to the first connection line through the first contact holes on the two ends.

16. The display device according to claim 14, further comprising: A second contact hole is formed by selectively removing another portion of the interlayer insulating layer to expose another portion of the first connection line.

17. The display device according to claim 16, wherein: The second contact hole is located on the first connection line between adjacent gate lines, and Wherein, the second contact hole is disposed between the first contact holes on both ends of the first connection line between adjacent gate lines.

18. The display device according to claim 17, further comprising: a data line disposed on the gate line in a direction parallel to the first connection line, Wherein, the at least one insulating layer includes a protection layer and a planarization layer disposed on the data line.

19. The display device according to claim 18, further comprising: a third contact hole, the third contact hole being formed by selectively removing a portion of the planarization layer so as to expose a portion of the protection layer, The third contact hole is located on the second connection line located at one side of the first connection line.

20. The display device according to claim 19, further comprising: a fourth contact hole formed by selectively removing a portion of the protective layer exposed through the third contact hole so as to expose a portion of the second connection line, in, The fourth contact hole exposes the upper surface of the second connection line between adjacent gate lines.

21. The display device according to claim 20, wherein: Before the data line is patterned, the first connection line is not disconnected, and Wherein, when the data line is patterned, another portion of the first connection line exposed through the second contact hole is also removed to disconnect the first connection line between adjacent gate lines.

22. The display device according to claim 20, wherein: The light emitting element includes an anode, and Before the anode is patterned, the second connection line is not disconnected, and Wherein, when the anode is patterned, the portion of the second connection line exposed through the fourth contact hole is also removed to disconnect the second connection line between adjacent gate lines.

23. A method for dispersing static electricity for a display device, the display device comprising a connection line disposed in a non-display area, the connection line being made of a metal oxide and disposed on the same layer as a semiconductor layer of the display device, the method comprising: Forming one or more contact holes that expose a portion of the connection line by selectively removing a portion of an interlayer insulating layer, a gate insulating layer, a planarizing layer, or a protective layer of the display device; and removing the exposed portion of the connecting line.

24. The method according to claim 23, wherein: The one or more contact holes include a first contact hole formed by selectively removing a portion of the interlayer insulating layer, a second contact hole formed by selectively removing a portion of the planarization layer to expose a portion of the protective layer, and a third contact hole formed by selectively removing a portion of the protective layer exposed by the second contact hole.

25. The method according to claim 23, wherein: The one or more contact holes include a first contact hole formed by selectively removing a portion of the gate insulating layer, a second contact hole formed by selectively removing a portion of the interlayer insulating layer, a third contact hole formed by selectively removing a portion of the planarization layer to expose a portion of the protective layer, and a fourth contact hole formed by selectively removing a portion of the protective layer exposed by the third contact hole.

26. The method of claim 23, wherein: The one or more contact holes include a first contact hole formed by selectively removing a portion of the interlayer insulating layer, a second contact hole formed by selectively removing another portion of the interlayer insulating layer, a third contact hole formed by selectively removing a portion of the planarization layer to expose a portion of the protective layer, and a fourth contact hole formed by selectively removing a portion of the protective layer exposed by the third contact hole.

27. The method according to claim 23, wherein: The one or more contact holes include a first contact hole formed by selectively removing a portion of the planarization layer to expose a portion of the protection layer, and a second contact hole formed by selectively removing a portion of the protection layer exposed by the first contact hole.

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