Gate driving circuit and driving method thereof, display panel and display device

Abstract

The invention discloses a gate driving circuit and a driving method thereof, a display panel and a display device. The gate drive circuit comprises a multi-stage cascaded shift register unit, the shift register unit comprises a shift output circuit (1) and a control circuit (2), the shift output circuit (1) is used for converting an input signal into an output signal of shift output, and the shift output circuit (1) comprises a plurality of signal ends; the control circuit (2) is connected with at least part of signal ends, a gating signal end (SM) and a driving signal end (Gate) in the at least one shift output circuit (1); wherein the signal ends, connected with the control circuit (2) and located on the shift output circuit (1), of the control circuit (2) comprise one or more control signal ends (CN), the control circuit (2) is used for responding to signals on the gating signal end (SM) and the control signal ends (CN) so as to input a first driving signal or a second driving signal to the driving signal end (Gate), the first driving signal is the same as the output signal, and the second driving signal is the same as the output signal. The second driving signal is an invalid level signal.

Description

Gate drive circuit and driving method thereof, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gate driving circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] In related technologies, a display panel can only adjust the refresh rate of all its pixel driver circuits. When the display panel displays an image with a high refresh rate requirement in some areas and a low refresh rate requirement in others, the display panel can only increase the refresh rate of all pixel driver circuits to meet the image requirements. However, this configuration results in higher energy consumption for the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a gate driving circuit is provided, wherein the shift register unit includes:

[0006] A shift output circuit, the shift output circuit is used to convert an input signal into an output signal of a shift output, the shift output circuit includes a plurality of signal terminals;

[0007] a control circuit connected to at least part of the signal terminals, the selection signal terminal, and the drive signal terminal of at least one of the shift output circuits;

[0008] Among them, the signal terminals connected to the control circuit and located in the shift output circuit include one or more control signal terminals, and the control circuit is used to respond to the signals on the selection signal terminal and the control signal terminal to input a first drive signal or a second drive signal to the drive signal terminal, the first drive signal is the same as the output signal, and the second drive signal is an invalid level signal.

[0009] In an exemplary embodiment of the present disclosure, the signal on the control signal terminal and the output signal output by the shift output circuit of this stage have pulse signals that at least partially overlap.

[0010] In an exemplary embodiment of the present disclosure, the control signal terminal includes one or more first control signal terminals;

[0011] The control circuit comprises:

[0012] a gating circuit connected to the gating signal terminal and the first node, and configured to transmit a signal from the gating signal terminal to the first node in response to a control signal;

[0013] The regulating circuit is connected to the first node, the first control signal terminal, and the driving signal terminal. The regulating circuit is used to respond to the signals of the first node and the first control signal terminal to input the first driving signal or the second driving signal to the driving signal terminal.

[0014] In an exemplary embodiment of the present disclosure, the control signal terminal further includes one or more second control signal terminals;

[0015] The gating circuit is connected to the second control signal terminal, and is configured to respond to a signal on the second control signal terminal to transmit the signal on the gating signal terminal to the first node.

[0016] In an exemplary embodiment of the present disclosure, the first control signal terminal is formed by a signal terminal in the shift output circuit of the current stage;

[0017] And / or, the gating circuit is connected to a plurality of second control signal terminals, and the plurality of second control signal terminals connected to the gating circuit are formed by signal terminals in two adjacent stages of the shift output circuits.

[0018] In an exemplary embodiment of the present disclosure, the shift output circuit includes a signal output terminal, and the signal output terminal is used to output the output signal;

[0019] The gating circuit is connected to a plurality of second control signal terminals, wherein the plurality of second control signal terminals connected to the gating circuit include a first sub-control signal terminal and a second sub-control signal terminal, wherein the first sub-control signal terminal is formed by a signal output terminal of a shift output circuit of the current stage, and the second sub-control signal terminal is formed by a signal output terminal of a shift output circuit of an adjacent stage;

[0020] The gating circuit is configured to transmit the signal of the gating signal terminal to the first node in response to signals on the first sub-control signal terminal and the second sub-control signal terminal.

[0021] In an exemplary embodiment of the present disclosure, the first control signal terminal is formed by a signal output terminal in the shift output circuit of this stage;

[0022] The regulating circuit comprises:

[0023] a NAND gate, a first input terminal connected to the first control signal terminal, and a second input terminal connected to the first node;

[0024] The first inverter has an input end connected to the output end of the NAND gate and an output end connected to the driving signal end.

[0025] In an exemplary embodiment of the present disclosure, the second sub-control signal terminal is formed by the signal output terminal of the adjacent previous stage shift output circuit;

[0026] Alternatively, the second sub-control signal terminal is formed by a signal output terminal of an adjacent next-stage shift output circuit.

[0027] In an exemplary embodiment of the present disclosure, the gate driving circuit is used for a display panel, and the display panel includes a plurality of rows of pixel driving circuits;

[0028] When the second sub-control signal terminal is formed by the signal output terminal of the adjacent previous stage shift output circuit, the driving signal terminal of the first stage shift register unit is not connected to the pixel driving circuit;

[0029] When the second sub-control signal terminal is formed by the signal output terminal of the adjacent next-stage shift output circuit, the driving signal terminal of the last-stage shift register unit is not connected to the pixel driving circuit.

[0030] In an exemplary embodiment of the present disclosure, the regulating circuit includes:

[0031] The latch circuit is connected to the first node and is used to latch the voltage of the first node input by the selection signal terminal.

[0032] In an exemplary embodiment of the present disclosure, the regulating circuit further includes:

[0033] The first reset circuit is connected to the first node, the reset signal terminal, and the first power terminal, and is used for transmitting the signal of the first power terminal to the first node in response to the signal of the reset signal terminal.

[0034] In an exemplary embodiment of the present disclosure, when the second sub-control signal terminal is formed by the signal output terminal of the adjacent previous-stage shift output circuit, the gating circuit includes:

[0035] a first transistor, wherein a first electrode is connected to the selection signal terminal, a gate is connected to the first sub-control signal terminal, and a conduction level of the first transistor is opposite to the effective level polarity of the signal output terminal;

[0036] a second transistor, wherein a first electrode is connected to the second electrode of the first transistor, a second electrode is connected to the first node, a gate is connected to the second sub-control signal terminal, and a conduction level of the second transistor is the same as the effective level polarity of the signal output terminal;

[0037] a first capacitor, wherein a first electrode is connected to the first node and a second electrode is connected to a stable voltage terminal;

[0038] When the second sub-control signal terminal is formed by the signal output terminal of the adjacent next-stage shift output circuit, the gating circuit includes:

[0039] a first transistor, wherein a first electrode is connected to the selection signal terminal, a gate is connected to the second sub-control signal terminal, and a conduction level of the first transistor is opposite to an effective level polarity of the signal output terminal;

[0040] a second transistor, wherein a first electrode is connected to the second electrode of the first transistor, a second electrode is connected to the first node, a gate is connected to the first sub-control signal terminal, and a conduction level of the second transistor is the same as the effective level polarity of the signal output terminal;

[0041] The first capacitor has a first electrode connected to the first node and a second electrode connected to a stable voltage terminal.

[0042] In an exemplary embodiment of the present disclosure, the regulating circuit further includes:

[0043] a latch circuit connected to the first node and configured to latch a voltage inputted from the selection signal terminal to the first node;

[0044] The latch circuit comprises:

[0045] a second inverter, an input end of which is connected to the first node;

[0046] a third inverter, an input end of which is connected to the output end of the second inverter, and an output end of which is connected to the second input end of the NAND gate;

[0047] a fourth switching circuit, connected to the first node and the output end of the third inverter, for shutting off the first node and the output end of the third inverter during at least a portion of the time period when the selection signal end inputs a signal to the first node, and for turning on the first node and the output end of the third inverter during at least another portion of the time period when the selection signal end inputs a signal to the first node.

[0048] In an exemplary embodiment of the present disclosure, the second inverter includes:

[0049] a third P-type transistor, having a first electrode connected to the first high-level power supply terminal, a second electrode connected to the second node, and a gate connected to the first node;

[0050] a fourth N-type transistor, having a first electrode connected to the second low-level power supply terminal, a second electrode connected to the second node, and a gate connected to the first node;

[0051] The third inverter comprises:

[0052] a fifth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second input terminal of the NAND gate, and a gate connected to the second node;

[0053] a sixth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the second input terminal of the NAND gate, and a gate connected to the second node;

[0054] When the second sub-control signal terminal is formed by the signal output terminal of the adjacent previous stage shift output circuit, the fourth switch circuit includes:

[0055] a seventh transistor, having a first electrode connected to the second input terminal of the NAND gate, a second electrode connected to the first node, and a gate connected to the signal output terminal of the adjacent previous stage shift output circuit;

[0056] an eighth transistor, having a first electrode connected to the second input terminal of the NAND gate, a second electrode connected to the first node, and a gate connected to the first clock signal terminal;

[0057] When the second sub-control signal terminal is formed by the signal output terminal of the adjacent next-stage shift output circuit, the fourth switch circuit includes:

[0058] a seventh transistor, having a first electrode connected to the second input terminal of the NAND gate, a second electrode connected to the first node, and a gate connected to the signal output terminal of the shift output circuit of this stage;

[0059] An eighth transistor has a first electrode connected to the second input terminal of the NAND gate, a second electrode connected to the first node, and a gate connected to the first clock signal terminal.

[0060] In an exemplary embodiment of the present disclosure, the NAND gate includes:

[0061] a ninth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the first input terminal of the NAND gate;

[0062] a tenth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the second input terminal of the NAND gate;

[0063] an eleventh N-type transistor, having a first electrode connected to the third node and a gate connected to the first input terminal of the NAND gate;

[0064] a twelfth N-type transistor, having a first electrode connected to the second electrode of the eleventh N-type transistor, a second electrode connected to the second power supply terminal, and a gate connected to the second input terminal of the NAND gate;

[0065] The first inverter comprises:

[0066] a thirteenth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the drive signal terminal, and a gate connected to the output terminal of the NAND gate;

[0067] A fourteenth N-type transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the drive signal terminal, and a gate connected to the output terminal of the NAND gate.

[0068] In an exemplary embodiment of the present disclosure, the first reset circuit includes:

[0069] A fifteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the first node, and a gate connected to the reset signal terminal.

[0070] In an exemplary embodiment of the present disclosure, the shift output circuit includes:

[0071] a first output circuit connected to the fourth node, the first power supply terminal, and the signal output terminal of the shift output circuit, the first output circuit being configured to transmit the signal of the first power supply terminal to the signal output terminal in response to the signal of the fourth node;

[0072] a second output circuit connected to the fifth node, the second power supply terminal, and the signal output terminal of the shift output circuit, the second output circuit being configured to transmit the signal of the second power supply terminal to the signal output terminal in response to the signal of the fifth node, and the signal output terminal being configured to output the output signal;

[0073] The gating circuit is connected to a plurality of second control signal terminals, wherein the plurality of second control signal terminals connected to the gating circuit include a third sub-control signal terminal and a fourth sub-control signal terminal, the fourth node of the shift output circuit of the current stage forms the third sub-control signal terminal, and the fifth node of the shift output circuit of the next adjacent stage forms the fourth sub-control signal terminal;

[0074] The gating circuit is connected to a plurality of gating signal terminals, wherein the plurality of gating signal terminals connected to the gating circuit include a first gating signal terminal and a second gating signal terminal;

[0075] The gating circuit is also connected to a third control signal terminal, and is used to respond to signals from the third control signal terminal and the third sub-control signal terminal to transmit the signal from the first gating signal terminal to the first node, and to respond to signals from the third control signal terminal and the fourth sub-control signal terminal to transmit the signal from the second gating signal terminal to the first node.

[0076] In an exemplary embodiment of the present disclosure, the regulation circuit is connected to a plurality of first control signal terminals, wherein the plurality of first control signal terminals connected to the regulation circuit include a fifth sub-control signal terminal and a sixth sub-control signal terminal, wherein the fifth sub-control signal terminal is formed by a fourth node in the current-stage shift output circuit, and the sixth sub-control signal terminal is formed by a fifth node in the current-stage shift output circuit;

[0077] The regulating circuit comprises:

[0078] a first switch circuit connected to the sixth sub-control signal terminal, the first node, and the sixth node, and configured to transmit the signal of the sixth sub-control signal terminal to the sixth node in response to the signal of the first node;

[0079] a second switch circuit, connected to the fifth sub-control signal terminal, the first node, and the seventh node, and configured to transmit the signal of the fifth sub-control signal terminal to the seventh node in response to the signal of the first node;

[0080] The third output circuit is connected to the sixth node, the seventh node, the first power supply terminal, and the second power supply terminal, and is used to transmit the power signal of the second power supply terminal to the drive signal terminal in response to the signal of the sixth node, and is used to transmit the power signal of the first power supply terminal to the drive signal terminal in response to the signal of the seventh node.

[0081] In an exemplary embodiment of the present disclosure, the second output circuit is further connected to an eighth node, and the second output circuit is further configured to transmit the signal of the eighth node to the fifth node in response to a signal of the eighth node;

[0082] The regulating circuit further includes:

[0083] The third switch circuit is connected to the sixth node and the eighth node, and is configured to respond to a signal from the eighth node and transmit the signal from the eighth node to the sixth node.

[0084] In an exemplary embodiment of the present disclosure, the gating circuit includes:

[0085] a sixteenth transistor, a first electrode connected to the first selection signal terminal, and a gate connected to the third control signal terminal;

[0086] a seventeenth transistor, having a first electrode connected to the second electrode of the sixteenth transistor, a second electrode connected to the first node, and a gate connected to the third sub-control signal terminal;

[0087] an eighteenth transistor, a first electrode connected to the second selection signal terminal, and a gate connected to the third control signal terminal;

[0088] a nineteenth transistor, having a first electrode connected to the second electrode of the eighteenth transistor, a second electrode connected to the first node, and a gate connected to the fourth sub-control signal terminal;

[0089] a second capacitor, a first electrode connected to the first node, and a second electrode connected to the seventh node;

[0090] The first switching circuit includes:

[0091] a twentieth transistor, having a first electrode connected to the sixth sub-control signal terminal, a second electrode connected to the sixth node, and a gate connected to the first node;

[0092] The second switching circuit includes:

[0093] a twenty-first transistor, having a first electrode connected to the fifth sub-control signal terminal, a second electrode connected to the seventh node, and a gate connected to the first node;

[0094] The third switch circuit includes:

[0095] a twenty-fourth transistor, having a first electrode connected to the eighth node, a second electrode connected to the sixth node, and a gate connected to the eighth node;

[0096] The third output circuit includes:

[0097] a twenty-second transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the drive signal terminal, and a gate connected to the seventh node;

[0098] a twenty-third transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the drive signal terminal, and a gate connected to the sixth node;

[0099] A third capacitor has a first electrode connected to the seventh node and a second electrode connected to the first power supply terminal.

[0100] In an exemplary embodiment of the present disclosure, the shift output circuit includes:

[0101] a first input circuit connected to the second power supply terminal, the first clock signal terminal, and the ninth node, and configured to transmit the signal of the second power supply terminal to the ninth node in response to the signal of the first clock signal terminal;

[0102] a second input circuit connected to the signal input terminal, the first clock signal terminal, the tenth node, and the eleventh node, and configured to transmit the signal of the signal input terminal to the tenth node and the eleventh node in response to the signal of the first clock signal terminal;

[0103] a first output circuit connected to the twelfth node, the thirteenth node, the fourth node, the second clock signal terminal, the first power terminal, and the signal output terminal, the first output circuit being configured to transmit the signal of the second clock signal terminal to the thirteenth node in response to the signal of the twelfth node, to transmit the signal of the thirteenth node to the fourth node in response to the signal of the second clock signal terminal, and to transmit the power signal of the first power terminal to the signal output terminal in response to the signal of the fourth node, wherein the twelfth node is connected to the ninth node;

[0104] a second output circuit connected to the eighth node, the fifth node, the second power supply terminal, and the signal output terminal, the second output circuit being configured to transmit the signal of the eighth node to the fifth node in response to a signal of the eighth node, and to transmit the signal of the second power supply terminal to the signal output terminal in response to a signal of the fifth node, the eighth node being connected to the eleventh node, and the tenth node being connected to the fifth node;

[0105] a first pull-up circuit connected to the tenth node, the first power supply terminal, and the fourth node, and configured to transmit a signal from the first power supply terminal to the fourth node in response to a signal from the tenth node;

[0106] a second pull-up circuit connected to the tenth node, the first clock signal terminal, and the ninth node, and configured to transmit the signal of the first clock signal terminal to the ninth node in response to the signal of the tenth node;

[0107] a coupling circuit connected to the ninth node, the first power supply terminal, the fourteenth node, the eighth node, and the second clock signal terminal, configured to transmit a signal from the first power supply terminal to the fourteenth node in response to a signal from the ninth node, to transmit a signal from the second clock signal terminal to the fourteenth node in response to a signal from the eighth node, and to couple a signal on the fourteenth node to the eighth node;

[0108] The signal input end of the first-stage shift output circuit is connected to the initial signal, and the signal input ends of other shift output circuits are connected to the signal output ends of the adjacent upper-stage shift output circuit.

[0109] In an exemplary embodiment of the present disclosure, the shift output circuit further includes:

[0110] a first isolation circuit connected to the ninth node, the twelfth node, and a second power supply terminal, and configured to connect the ninth node and the twelfth node in response to a signal from the second power supply terminal;

[0111] a second isolation circuit connected to the tenth node, the eleventh node, the second power supply terminal, the fifth node, and the eighth node, and configured to connect the tenth node and the fifth node, and connect the eleventh node and the eighth node in response to a signal from the second power supply terminal;

[0112] The second reset circuit is connected to the first power supply terminal, the reset signal terminal, and the tenth node, and is configured to transmit the signal from the first power supply terminal to the tenth node in response to the signal from the reset signal terminal.

[0113] In an exemplary embodiment of the present disclosure, the first input circuit includes:

[0114] a twenty-fifth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the ninth node, and a gate connected to the first clock signal terminal;

[0115] The second input circuit includes:

[0116] A twenty-sixth transistor, having a first electrode connected to the signal input terminal, a second electrode connected to the tenth node, and a gate connected to the first clock signal terminal;

[0117] a twenty-seventh transistor, having a first electrode connected to the signal input terminal, a second electrode connected to the eleventh node, and a gate connected to the first clock signal terminal;

[0118] The first output circuit includes:

[0119] a twenty-eighth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the thirteenth node, and a gate connected to the twelfth node;

[0120] a twenty-ninth transistor, having a first electrode connected to the thirteenth node, a second electrode connected to the fourth node, and a gate connected to the second clock signal terminal;

[0121] a 30th transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the signal output terminal, and a gate connected to the fourth node;

[0122] a fourth capacitor, a first electrode connected to the twelfth node, and a second electrode connected to the thirteenth node;

[0123] a fifth capacitor, a first electrode of which is connected to the fourth node, and a second electrode of which is connected to the first power supply terminal;

[0124] The second output circuit includes:

[0125] a thirty-first transistor, having a first electrode connected to the fifth node, a second electrode connected to the eighth node, and a gate connected to the eighth node;

[0126] a thirty-second transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the signal output terminal, and a gate connected to the fifth node;

[0127] a sixth capacitor, a first electrode of which is connected to the signal output terminal, and a second electrode of which is connected to the second power supply terminal;

[0128] The first pull-up circuit comprises:

[0129] a thirty-third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth node, and a gate connected to the tenth node;

[0130] The second pull-up circuit includes:

[0131] a thirty-fourth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the ninth node, and a gate connected to the tenth node;

[0132] The coupling circuit comprises:

[0133] a thirty-fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourteenth node, and a gate connected to the ninth node;

[0134] a thirty-sixth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the fourteenth node, and a gate connected to the eighth node;

[0135] a seventh capacitor, a first electrode connected to the fourteenth node, and a second electrode connected to the eighth node;

[0136] The first isolation circuit includes:

[0137] a thirty-seventh transistor, having a first electrode connected to the ninth node, a second electrode connected to the twelfth node, and a gate connected to the second power supply terminal;

[0138] The second isolation circuit includes:

[0139] a thirty-eighth transistor, having a first electrode connected to the tenth node, a second electrode connected to the fifth node, and a gate connected to the second power supply terminal;

[0140] a thirty-ninth transistor, having a first electrode connected to the eleventh node, a second electrode connected to the eighth node, and a gate connected to the second power supply terminal;

[0141] The second reset circuit includes:

[0142] The fortieth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the tenth node, and a gate connected to the reset signal terminal.

[0143] According to one aspect of the present disclosure, a gate drive circuit driving method is provided for driving the above-mentioned gate drive circuit, the driving method comprising:

[0144] Utilizing the shift output circuit to shift output the output signal;

[0145] The control circuit is controlled by a selection signal to output a first drive signal or a second drive signal, the first drive signal is the same as the output signal, and the second drive signal is an invalid level signal.

[0146] According to one aspect of the present disclosure, a display panel is provided, comprising the above-mentioned gate driving circuit.

[0147] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0148] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0149] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0150] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0151] FIG2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG1 ;

[0152] FIG3 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit disclosed herein;

[0153] FIG4 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0154] FIG5 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0155] FIG6 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0156] FIG7 is a timing diagram of a signal output terminal of a shift output circuit in an exemplary embodiment of the gate driving circuit disclosed herein;

[0157] FIG8 is a timing diagram of each node in a driving method of the shift register unit disclosed in the present invention;

[0158] FIG9 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0159] FIG10 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0160] FIG11 is a timing diagram of each node in a driving method of the shift register unit shown in FIG10 . DETAILED DESCRIPTION

[0161] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0162] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0163] This exemplary embodiment first provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a structural diagram of an exemplary embodiment of the pixel driving circuit disclosed in the present invention, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0164] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. A first electrode of the fourth transistor T4 is connected to a data signal terminal Da, a second electrode of the fourth transistor T4 is connected to a first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to a first gate driving signal terminal G1; a first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to a first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to an enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to a node N, a second electrode of the second transistor T2 is connected to a second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to a second gate driving signal terminal G2; a first electrode of the sixth transistor T6 is connected to a second electrode of the driving transistor T3, and a second electrode of the sixth transistor T6 is connected to a seventh transistor T7 The second electrode of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to the node N, the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be connected to a light-emitting unit OLED and is used to drive the light-emitting unit OLED to emit light. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The first transistor T1 and the second transistor T2 can be N-type transistors, for example, N-type metal oxide transistors. N-type transistors have low leakage current, thereby preventing leakage of node N through the first transistor T1 and the second transistor T2 during the light-emitting phase. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors. For example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon transistors. P-type transistors have high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal may output the same or different voltage signals depending on actual conditions.

[0165] As shown in Figure 2, G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a reset phase t1, a data writing phase t2, and a light-emitting phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the node N, and the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED. In the data writing phase t2: the second gate drive signal terminal G2 outputs a high-level signal, the first gate drive signal terminal G1 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a data signal to write the compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting phase t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I=(μWCox / 2L)(Vgs-Vth) 2

[0166] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0167] It should be understood that in other exemplary embodiments, the second reset signal terminal Re2 and the first gate drive signal terminal G1 may also share the same signal terminal, and the seventh transistor T7 may write the second initial signal to the first electrode of the light-emitting unit OLED in the data writing phase t2.

[0168] As shown in Figure 3, it is a structural diagram of another exemplary embodiment of the pixel driving circuit of the present invention. The difference between this pixel driving circuit and the pixel driving circuit shown in Figure 1 is that the first transistor T1 is connected to the output end of the driving transistor T3. The driving method of the pixel driving circuit may also include: a reset stage t1, a data writing stage t2, and a light-emitting stage t3. In the reset stage t1: the first reset signal terminal Re1 and the second gate driving signal terminal G2 output a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1, the seventh transistor T7, and the second transistor T2 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2, and the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED. During the data writing phase t2, the second gate drive signal terminal G2 outputs a high-level signal, the first gate drive signal terminal G1 and the first reset signal terminal Re1 output low-level signals, the fourth transistor T4 and the second transistor T2 are turned on, the first transistor T1 is turned off, and the data signal terminal Da outputs a data signal to write the compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. During the light-emitting phase t3, the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C.

[0169] As can be seen from the pixel driving circuit shown in Figure 1, if the first transistor T1 and the second transistor T2 are not conducting during the reset phase t1 and the data writing phase t2, the voltage at node N will not be refreshed, and node N will maintain the voltage of the previous frame. As can be seen from the pixel driving circuit shown in Figure 2, if the second transistor T2 is not conducting during the reset phase t1 and the data writing phase t2, the voltage at node N will not be refreshed, and node N will maintain the voltage of the previous frame. This exemplary embodiment can achieve the refresh rate of the pixel driving circuit in a local area of ​​the display panel by controlling the gate drive signals of the first transistor T1 and the second transistor T2.

[0170] Accordingly, this exemplary embodiment provides a gate driving circuit, which can provide a gate driving signal to the first transistor T1 or the second transistor T2 .

[0171] In this exemplary embodiment, the gate drive circuit includes a multi-stage cascaded shift register unit, as shown in FIG4 , which is a structural diagram of an exemplary embodiment of the shift register unit disclosed in the present invention. The shift register unit includes: a shift output circuit 1 and a control circuit 2, wherein the shift output circuit 1 is used to convert an input signal into an output signal of a shift output, and the shift output circuit 1 includes multiple signal terminals; the control circuit 2 is connected to at least part of the signal terminals, the selection signal terminal SM, and the drive signal terminal Gate in at least one of the shift output circuits 1; wherein the signal terminals connected to the control circuit 2 and located in the shift output circuit 1 include one or more control signal terminals CN, and the control circuit 2 is used to respond to the signals on the selection signal terminal SM and the control signal terminal CN to input a first drive signal or a second drive signal to the drive signal terminal Gate, wherein the first drive signal is the same as the output signal, and the second drive signal is an invalid level signal.

[0172] The gate drive circuit provided in this exemplary embodiment utilizes a select signal terminal SM and a control signal terminal CN to drive the control circuit to output a first drive signal or a second drive signal according to different requirements. The first drive signal can control the pixel drive circuit to scan normally, while the second drive signal can control the pixel drive circuit to not scan. This gate drive circuit can thus control the refresh rate of a portion of the pixel drive circuit in a display panel.

[0173] In this exemplary embodiment, the signal at the control signal terminal CN and the output signal output by the shift output circuit 1 at this stage have pulse signals that at least partially overlap. The control signal terminal CN can promptly drive the control circuit 2 to output the first drive signal or the second drive signal when the shift output circuit at this stage outputs a valid pulse signal. The shift register unit can output the corresponding drive signal during the scanning period of the pixel drive circuit according to the scanning requirements of the pixel drive circuit. The polarity of the pulse signal at the control signal terminal CN can be the same as or opposite to the polarity of the output signal output by the shift output circuit 1 at this stage.

[0174] In this exemplary embodiment, as shown in FIG5 , there is shown a schematic diagram of the structure of an exemplary embodiment of the shift register unit of the present disclosure. The control signal terminal CN includes one or more first control signal terminals CN1; the control circuit 2 includes: a gating circuit 21 and a regulating circuit 22. The gating circuit 21 is connected to the gating signal terminal SM and the first node N1, and is configured to respond to a control signal to transmit the signal of the gating signal terminal SM to the first node N1; the regulating circuit 22 is connected to the first node N1, the first control signal terminal CN1, and the drive signal terminal Gate, and is configured to respond to the signal of the first node N1 and the first control signal terminal CN1 to input the first drive signal or the second drive signal to the drive signal terminal Gate.

[0175] In this exemplary embodiment, as shown in FIG5 , the first control signal terminal CN1 may be formed by a signal terminal in the shift output circuit 1 of the same stage. For example, the first control signal terminal CN1 may be formed by a signal output terminal of the shift output circuit 1. In addition, the first control signal terminal CN1 may also be formed by other signal terminals in the shift output circuit 1 of the same stage.

[0176] In this exemplary embodiment, as shown in Figure 5, the control signal terminal CN also includes one or more second control signal terminals CN2; the selection circuit 21 is connected to the second control signal terminal CN2, and the selection circuit 21 is used to respond to the signal on the second control signal terminal CN2 to transmit the signal of the selection signal terminal SM to the first node N1.

[0177] In this exemplary embodiment, as shown in FIG5 , the gating circuit 21 may be connected to a plurality of second control signal terminals CN2 , and the plurality of second control signal terminals CN2 connected to the gating circuit 21 may be formed by signal terminals in two adjacent stages of the shift output circuit 1 .

[0178] In this exemplary embodiment, as shown in FIG6 , there is shown a schematic diagram of the structure of an exemplary embodiment of the shift register unit disclosed in the present invention. The shift output circuit 1 includes a signal output terminal OUT(n), and the signal output terminal OUT(n) is used to output the output signal; the selection circuit 21 is connected to a plurality of second control signal terminals CN2, and the plurality of second control signal terminals CN2 connected to the selection circuit 21 include a first sub-control signal terminal CN21 and a second sub-control signal terminal CN22, wherein the first sub-control signal terminal CN21 is formed by the signal output terminal OUT(n) of the shift output circuit 1 at this stage, and the second sub-control signal terminal CN22 is formed by the signal output terminal OUT(n-1) of the shift output circuit 1 at the adjacent previous stage; and the first control signal terminal CN1 is formed by the signal output terminal OUT(n) of the shift output circuit 1 at this stage. The selection circuit 21 is used to respond to the signals on the first sub-control signal terminal CN21 and the second sub-control signal terminal CN22 to transmit the signal of the selection signal terminal SM to the first node N1; the regulation circuit 22 includes: a NAND gate 222 and a first inverter 223, the first input terminal in1 of the NAND gate 222 is connected to the first control signal terminal CN1, and the second input terminal in2 is connected to the first node N1; the signal input terminal of the first inverter 223 is connected to the output terminal of the NAND gate 222, and the output terminal is connected to the drive signal terminal Gate.

[0179] In this exemplary embodiment, as shown in FIG6 , the regulating circuit 22 may further include a latch circuit 221 , which is connected to the first node N1 and configured to latch the voltage inputted from the selection signal terminal MS to the first node N1 .

[0180] In this exemplary embodiment, as shown in Figure 6, the regulation circuit 22 may further include: a first reset circuit 224, the first reset circuit 224 is connected to the first node N1, the reset signal terminal Re, and the first power supply terminal VGH, and is used to respond to the signal of the reset signal terminal Re and transmit the signal of the first power supply terminal VGH to the first node N1.

[0181] In this exemplary embodiment, as shown in FIG6 , the gating circuit 21 includes: a first transistor T1, a second transistor T2, and a first capacitor C1. The first electrode of the first transistor T1 is connected to the gating signal terminal SM, and the gate is connected to the first sub-control signal terminal CN21. The conduction level of the first transistor T1 is opposite to the effective level of the signal output terminal OUT(n). The first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the second electrode is connected to the first node N1, and the gate is connected to the second sub-control signal terminal CN22. The conduction level of the second transistor T2 is the same as the effective level of the signal output terminal OUT(n). The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to a stable voltage terminal. For example, the second electrode of the first capacitor C1 can be connected to the second power supply terminal VGL. In this exemplary embodiment, the effective level can be understood as the level that turns on the target circuit. For example, the shift output circuit is used to turn on the N-type transistor in the pixel driving circuit through a high-level signal. The effective level of the signal output terminal is a high level. Accordingly, the first power supply terminal VGH can be a high-level power supply terminal, the second power supply terminal VGL can be a low-level power supply terminal, the first transistor T1 can be a P-type transistor, and the second transistor T2 can be an N-type transistor.

[0182] In this exemplary embodiment, as shown in FIG6 , the latch circuit 221 includes: a second inverter PI2, a third inverter PI3, and a fourth switch circuit K4. The input of the second inverter PI2 is connected to the first node N1; the input of the third inverter PI3 is connected to the output of the second inverter PI2, and the output of the third inverter PI3 is connected to the second input in2 of the NAND gate 222. The fourth switch circuit K4 is connected to the first node N1 and the output of the third inverter PI3, and is configured to shut off the first node N1 and the output of the third inverter PI3 during at least a portion of the time period when the selection signal terminal MS inputs a signal to the first node N1, and to conduct the first node and the output of the third inverter PI3 during at least a portion of the other time periods when the selection signal terminal MS inputs a signal to the first node. The fourth switch circuit K4 can prevent the voltage at the output of the third inverter PI3 from affecting the voltage of the first node N1 when the selection signal terminal MS inputs a signal to the first node N1, while maintaining the voltage of the first node N1 through the output of the third inverter PI3 during other time periods.

[0183] In this exemplary embodiment, as shown in FIG6 , the second inverter PI2 may include: a third P-type transistor T3 and a fourth N-type transistor T4, wherein the third P-type transistor T3 has a first electrode connected to the high-level first power supply terminal VGH, a second electrode connected to the second node N2, and a gate connected to the first node N1; a fourth N-type transistor T4 has a first electrode connected to the low-level second power supply terminal VGL, a second electrode connected to the second node N2, and a gate connected to the first node N1. The third inverter PI3 may include: a fifth P-type transistor T5 and a sixth N-type transistor T6, wherein the fifth P-type transistor T5 has a first electrode connected to the first power supply terminal VGH, a second electrode connected to the second input terminal in2 of the NAND gate 222, and a gate connected to the second node N2; and a sixth N-type transistor T6 has a first electrode connected to the second power supply terminal VGL, a second electrode connected to the second input terminal in2 of the NAND gate 222, and a gate connected to the second node N2. The fourth switch circuit K4 may include: a seventh transistor T7 and an eighth transistor T8, wherein the first electrode of the seventh transistor T7 is connected to the second input terminal in2 of the NAND gate 222, the second electrode is connected to the first node N1, and the gate is connected to the signal output terminal OUT(n-1) of the adjacent previous-stage shift output circuit 1; the first electrode of the eighth transistor T8 is connected to the second input terminal in2 of the NAND gate 222, the second electrode is connected to the first node N1, and the gate is connected to the first clock signal terminal CLK.

[0184] In this exemplary embodiment, as shown in Figure 6, the NAND gate 222 includes: a ninth P-type transistor T9, a tenth P-type transistor T10, an eleventh N-type transistor T11, and a twelfth N-type transistor T12. The first electrode of the ninth P-type transistor T9 is connected to the first power supply terminal VGH, the second electrode is connected to the third node N3, and the gate is connected to the first input terminal in1 of the NAND gate 222; the first electrode of the tenth P-type transistor T10 is connected to the first power supply terminal VGH, the second electrode is connected to the third node N3, and the gate is connected to the second input terminal in2 of the NAND gate 222; the first electrode of the eleventh N-type transistor T11 is connected to the third node N3, and the gate is connected to the first input terminal in1 of the NAND gate 222; the first electrode of the twelfth N-type transistor T12 is connected to the second electrode of the eleventh N-type transistor T11, the second electrode is connected to the second power supply terminal VGL, and the gate is connected to the second input terminal in2 of the NAND gate 222. The first inverter 223 includes a thirteenth P-type transistor T13 and a fourteenth N-type transistor T14. The thirteenth P-type transistor T13 has a first electrode connected to the first power supply terminal VGH, a second electrode connected to the drive signal terminal Gate, and a gate connected to the output terminal of the NAND gate 222. The fourteenth N-type transistor T14 has a first electrode connected to the second power supply terminal VGL, a second electrode connected to the drive signal terminal Gate, and a gate connected to the output terminal OUT of the NAND gate 222. The first reset circuit 224 includes a fifteenth transistor T15. The fifteenth transistor T15 has a first electrode connected to the first power supply terminal VGH, a second electrode connected to the first node N1, and a gate connected to the reset signal terminal Re.

[0185] FIG7 shows a timing diagram of the signal output terminals of the shift output circuit in an exemplary embodiment of the gate drive circuit disclosed herein. OUT(n) represents the timing of the signal output terminals of the shift output circuit at the current stage, and OUT(n-1) represents the timing of the signal output terminals of the shift output circuit at the previous stage.

[0186] As shown in Figures 6 and 7, in the first time period t1, OUT(n-1) outputs a high level, OUT(n) outputs a low level, the first transistor T1 and the second transistor T2 are turned on, and the selection signal terminal MS can input a selection signal to the first node N1 in the first time period t1. When the pixel driving circuit connected to the driving signal terminal Gate needs to maintain a high refresh rate, the selection signal terminal MS inputs a high level signal to the first node N1 in the first time period t1. When the signal output terminal OUT(n) outputs a high level signal, the output terminal of the NAND gate outputs a low level signal, and the output terminal of the first inverter outputs a high level signal. When the signal output terminal OUT(n) outputs a low level signal, the output terminal of the NAND gate outputs a high level signal, and the output terminal of the first inverter normally outputs a low level signal. When the pixel driving circuit connected to the driving signal terminal Gate needs to change to a low refresh rate, the selection signal terminal MS inputs a low level signal to the first node N1 in the first time period t1. Regardless of whether the signal output terminal OUT(n) outputs a high level signal or a low level signal, the output terminal of the NAND gate outputs a high level signal, and the output terminal of the first inverter outputs a low level signal. This exemplary embodiment can control the refresh frequency of the pixel driving circuit by controlling the polarity of the signal input from the selection signal terminal MS to the first node N1.

[0187] It should be understood that in other exemplary embodiments, the adjustment circuit 22 can also have other structures. For example, the adjustment circuit 22 can replace the NAND gate and the first inverter in the shift register unit shown in Figure 6 with an AND gate, wherein the first input of the AND gate is connected to the signal output terminal OUT(n), the second input is connected to the first node N1, and the output is connected to the drive signal terminal Gate. When the pixel driving circuit connected to the drive signal terminal needs to maintain a high refresh rate, a high level is written to the first node N1. When the signal output terminal OUT(n) outputs a high level, the drive signal terminal Gate outputs a high level. When the signal output terminal OUT(n) outputs a low level, the drive signal terminal Gate normally outputs a low level. When the pixel driving circuit connected to the drive signal terminal needs to change to a low refresh rate, a low level is written to the first node N1. Regardless of whether the signal output terminal OUT(n) outputs a high level or a low level, the drive signal terminal Gate outputs a low level.

[0188] In this exemplary embodiment, the driving signal terminal Gate can be connected to one or more rows of pixel driving circuits. The multiple stages of cascaded shift register units can provide a strobe signal terminal via the same signal line. Since the strobe circuit is used to write the signal of the strobe signal terminal to the first node N1 in response to the first sub-control signal terminal CN21 and the second sub-control signal terminal CN22, the strobe signals input to different rows of shift register units on the same signal line will not interfere with each other.

[0189] In this exemplary embodiment, the driving signal end of the first-stage shift register unit may not be connected to the pixel driving circuit. This setting can make the gate driving signal driving capability received by each row of pixel driving circuits more uniform, thereby improving the display uniformity of the display panel.

[0190] In this exemplary embodiment, as shown in FIG6 , the shift output circuit 1 may include: a first input circuit 13 , a second input circuit 14 , a first output circuit 11 , a second output circuit 12 , a first pull-up circuit 15 , a second pull-up circuit 16 , and a coupling circuit 17 .The first input circuit 13 is connected to the second power supply terminal VGL, the first clock signal terminal CLK, and the ninth node N9, and is used to transmit the signal of the second power supply terminal VGL to the ninth node N9 in response to the signal of the first clock signal terminal CLK; the second input circuit 14 is connected to the signal input terminal IN, the first clock signal terminal CLK, the tenth node N10, and the eleventh node N11, and is used to transmit the signal of the signal input terminal IN to the tenth node N10 and the eleventh node N11 in response to the signal of the first clock signal terminal CLK; the first output circuit 11 is connected to the twelfth node N12, the thirteenth node N13, the fourth node N4, the second clock signal terminal CLB, the first power supply terminal VG H, signal output terminal OUT(n), the first output circuit 11 is used to transmit the signal of the second clock signal terminal CLB to the thirteenth node N13 in response to the signal of the twelfth node N12, and to transmit the signal of the thirteenth node N13 to the fourth node N4 in response to the signal of the second clock signal terminal CLB, and to transmit the power signal of the first power supply terminal VGH to the signal output terminal OUT(n) in response to the signal of the fourth node N4, wherein the twelfth node N12 is connected to the ninth node N9; the second output circuit 12 is connected to the eighth node N8, the fifth node N5, the second power supply terminal VGL, and the signal output terminal OUT(n), The second output circuit 12 is used to transmit the signal of the eighth node N8 to the fifth node N5 in response to the signal of the eighth node N8, and to transmit the signal of the second power supply terminal VGL to the signal output terminal OUT(n) in response to the signal of the fifth node N5, the eighth node N8 is connected to the eleventh node N11, and the tenth node N10 is connected to the fifth node N5; the first pull-up circuit 15 is connected to the tenth node N10, the first power supply terminal VGH, and the fourth node N4, and is used to transmit the signal of the first power supply terminal VGH to the fourth node N4 in response to the signal of the tenth node N10; the second pull-up circuit 16 is connected to the tenth node N10 , the first clock signal terminal CLK, the ninth node N9, and is used to transmit the signal of the first clock signal terminal CLK to the ninth node N9 in response to the signal of the tenth node N10; the coupling circuit 17 is connected to the ninth node N9, the first power supply terminal VGH, the fourteenth node N14, the eighth node N8, and the second clock signal terminal CLB, and is used to transmit the signal of the first power supply terminal VGH to the fourteenth node N14 in response to the signal of the ninth node N9, and is used to transmit the signal of the second clock signal terminal CLB to the fourteenth node N14 in response to the signal of the eighth node N8, and is used to couple the signal on the fourteenth node N14 to the eighth node N8.

[0191] In this exemplary embodiment, the signal input terminal IN of the first stage shift output circuit 1 can be connected to the initial signal terminal, and the signal input terminals IN of other shift output circuits 1 are connected to the signal output terminals OUT(n) of the adjacent previous stage shift output circuit 1 .

[0192] In this exemplary embodiment, as shown in FIG6 , the shift output circuit 1 further includes: a first isolation circuit 18, a second isolation circuit 19, and a second reset circuit 110. The first isolation circuit 18 is connected to the ninth node N9, the twelfth node N12, and the second power supply terminal VGL, and is configured to connect the ninth node N9 and the twelfth node N12 in response to a signal from the second power supply terminal VGL. The second isolation circuit 19 is connected to the tenth node N10, the eleventh node N11, the second power supply terminal VGL, the fifth node N5, and the eighth node N8, and is configured to connect the tenth node N10 and the fifth node N5, and the eleventh node N11 and the eighth node N8 in response to a signal from the second power supply terminal VGL. The second reset circuit 110 is connected to the first power supply terminal VGH, the reset signal terminal Re, and the tenth node N10, and is configured to transmit the signal from the first power supply terminal VGH to the tenth node N10 in response to a signal from the reset signal terminal Re.

[0193] In this exemplary embodiment, as shown in FIG6 , the first input circuit 13 includes a twenty-fifth transistor T25, wherein a first electrode of the twenty-fifth transistor T25 is connected to the second power supply terminal VGL, a second electrode of the twenty-fifth transistor T25 is connected to the ninth node N9, and a gate of the transistor is connected to the first clock signal terminal CLK. The second input circuit 14 includes a twenty-sixth transistor T26 and a twenty-seventh transistor T27, wherein a first electrode of the twenty-sixth transistor T26 is connected to the signal input terminal IN, a second electrode of the transistor T26 is connected to the tenth node N10, and a gate of the transistor T27 is connected to the first clock signal terminal CLK. The second input circuit 14 includes a twenty-sixth transistor T26 and a twenty-seventh transistor T27, wherein a first electrode of the twenty-sixth transistor T26 is connected to the signal input terminal IN, a second electrode of the transistor T26 is connected to the tenth node N10, and a gate of the transistor T27 is connected to the first clock signal terminal CLK.

[0194] In this exemplary embodiment, as shown in Figure 6, the first output circuit 11 includes: a twenty-eighth transistor T28, a twenty-ninth transistor T29, a thirtieth transistor T30, a fourth capacitor C4, and a fifth capacitor C5. The first electrode of the twenty-eighth transistor T28 is connected to the second clock signal terminal CLB, the second electrode is connected to the thirteenth node N13, and the gate is connected to the twelfth node N12; the first electrode of the twenty-ninth transistor T29 is connected to the thirteenth node N13, the second electrode is connected to the fourth node N4, and the gate is connected to the second clock signal terminal CLB; the first electrode of the thirtieth transistor T30 is connected to the first power supply terminal VGH, the second electrode is connected to the signal output terminal OUT(n), and the gate is connected to the fourth node N4; the first electrode of the fourth capacitor C4 is connected to the twelfth node N12, and the second electrode is connected to the thirteenth node N13; the first electrode of the fifth capacitor C5 is connected to the fourth node N4, and the second electrode is connected to the first power supply terminal VGH.

[0195] In this exemplary embodiment, as shown in Figure 6, the second output circuit 12 includes: a thirty-first transistor T31, a thirty-second transistor T32, and a sixth capacitor C6, the first electrode of the thirty-first transistor T31 is connected to the fifth node N5, the second electrode is connected to the eighth node N8, and the gate is connected to the eighth node N8; the first electrode of the thirty-second transistor T32 is connected to the second power supply terminal VGL, the second electrode is connected to the signal output terminal OUT(n), and the gate is connected to the fifth node N5; the first electrode of the sixth capacitor C6 is connected to the signal output terminal OUT(n), and the second electrode is connected to the second power supply terminal VGL.

[0196] In this exemplary embodiment, as shown in FIG6 , the first pull-up circuit 15 includes a 33rd transistor T33, wherein a first electrode of the 33rd transistor T33 is connected to the first power supply terminal VGH, a second electrode is connected to the fourth node N4, and a gate is connected to the tenth node N10. The second pull-up circuit 16 includes a 34th transistor T34, wherein a first electrode of the 34th transistor T34 is connected to the first clock signal terminal CLK, a second electrode is connected to the ninth node N9, and a gate is connected to the tenth node N10. The coupling circuit 17 includes a 35th transistor T35, a 36th transistor T36, and a seventh capacitor C7. The 35th transistor T35 has a first electrode connected to the first power supply terminal VGH, a second electrode connected to the fourteenth node N14, and a gate connected to the ninth node N9. The 36th transistor T36 has a first electrode connected to the second clock signal terminal CLB, a second electrode connected to the fourteenth node N14, and a gate connected to the eighth node N8. The seventh capacitor C7 has a first electrode connected to the fourteenth node N14 and a second electrode connected to the eighth node N8. The first isolation circuit 18 includes a 37th transistor T37, wherein a first electrode of the 37th transistor T37 is connected to the 9th node N9, a second electrode is connected to the 12th node N12, and a gate is connected to the second power supply terminal VGL. The second isolation circuit 19 includes a 38th transistor T38 and a 39th transistor T39, wherein a first electrode of the 38th transistor T38 is connected to the 10th node N10, a second electrode is connected to the 5th node N5, and a gate is connected to the second power supply terminal VGL. The 39th transistor T39 has a first electrode connected to the 11th node N11, a second electrode is connected to the 8th node N8, and a gate is connected to the second power supply terminal VGL. The second reset circuit 110 includes a 40th transistor T40, wherein a first electrode of the 40th transistor T40 is connected to the first power supply terminal VGH, a second electrode is connected to the 10th node N10, and a gate is connected to the reset signal terminal Re.

[0197] Figure 8 shows the timing diagram of each node in a driving method for a shift register unit disclosed herein. CLK is the timing diagram for the first clock signal terminal, CLB is the timing diagram for the second clock signal terminal, IN is the timing diagram for the signal input terminal, and OUT(n) is the timing diagram for the signal output terminal.

[0198] In this exemplary embodiment, the 25th to 40th transistors may be P-type transistors, the first power supply terminal VGH is a high-level signal terminal, and the second power supply terminal VGL is a low-level signal terminal. The first isolation circuit and the second isolation circuit are normally turned on.

[0199] The shift register unit driving method may include eight stages: a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t8. In the first stage t1, the first clock signal terminal CLK outputs a low-level signal, the second clock signal terminal CLB outputs a high-level signal, the signal input terminal IN outputs a high-level signal, the twenty-fifth transistor T25 and the twenty-eighth transistor T28 are turned on, a low-level signal is written to the twelfth node N12 and the thirteenth node N13, the twenty-ninth transistor T29 is turned off under the action of the second clock signal terminal CLB, the fourth node N4 maintains the high-level signal of the previous stage, the thirtieth transistor T30 is turned off, and at the same time, the twenty-sixth transistor T26 and the twenty-seventh transistor T27 are turned on, the high-level signal of the signal input terminal IN is written to the fifth node N5 and the eighth node N8, the thirty-second transistor T32 is turned off, and the signal output terminal OUT(n) maintains the low level of the previous stage under the action of the sixth capacitor C6. In the second phase t2, the first clock signal terminal CLK and the signal input terminal IN output a high level, the second clock signal terminal CLB outputs a low level, and the twelfth node N12 maintains the low level of the previous phase under the action of the fourth capacitor C4, thereby turning on the 28th transistor T28 to transmit the low level of the second clock signal terminal CLB to the fourth node N4. The 30th transistor T30, under the action of the fourth node N4, turns on to transmit the high level of the first power supply terminal VGH to the signal output terminal OUT(n). In the third phase t3, the first clock signal terminal CLK outputs a low level signal, the second clock signal terminal CLB outputs a high level signal, the signal input terminal IN outputs a high level signal, the fourth node N4 maintains the low level of the previous phase, the 30th transistor T30 turns on, and the first power supply terminal VGH inputs a high level signal to the signal output terminal OUT(n). The driving conditions in the fourth phase t4 and the sixth phase t6 are similar to those in the second phase t2, and the driving conditions in the fifth phase t5 are similar to those in the third phase t3. In the seventh stage t7: the first clock signal terminal CLK outputs a low-level signal, the second clock signal terminal CLB outputs a high-level signal, the signal input terminal IN outputs a low-level signal, the fifth node N5 and the eighth node N8 are written with the low-level signal of the signal input terminal IN, the ninth node N9 is written with the low-level signal of the second power supply terminal VGL, the thirty-fourth transistor T34, the thirty-fifth transistor T35, and the thirty-sixth transistor T36 are turned on, the fourteenth node N14 is written with a high-level signal, and under the coupling effect of the seventh capacitor C7, the eighth node N8 and the fifth node N5 are pulled high, the fifth node N5 cannot fully turn on the thirty-second transistor T32, and thus the signal output terminal OUT(n) maintains the high level of the previous stage.In the eighth stage t8: the first clock signal terminal CLK outputs a high-level signal, the second clock signal terminal CLB outputs a low-level signal, the signal input terminal IN outputs a low-level signal, the second clock signal terminal CLB changes from a high level to a low level, and accordingly, the fourteenth node N14 changes from a high level to a low level. Under the coupling action of the seventh capacitor C7, the eighth node N8 and the fifth node N5 are pulled low, the thirty-second transistor T32 is turned on, and the signal output terminal OUT(n) outputs a low level. At the same time, under the action of the first pull-up circuit and the second pull-up circuit, the ninth node N9 and the fourth node N4 are pulled high.

[0200] The reset signal terminal Re may input a valid signal when the display panel is powered on to turn on the second reset circuit 110 and the first reset circuit 224 to reset the tenth node N10 and the first node N1 respectively.

[0201] In this exemplary embodiment, the gate of the seventh transistor T7 in the fourth switch circuit K4 is connected to the signal output terminal OUT(n-1) in the adjacent previous stage shift output circuit 1, and the gate of the eighth transistor T8 in the fourth switch circuit K4 is connected to the first clock signal terminal CLK in the shift output circuit 1, so that the latch circuit can turn off the first node and the output terminal of the third inverter during at least a portion of the period when the selection signal terminal inputs a signal to the first node, and turn on the first node and the output terminal of the third inverter during at least another portion of the period when the selection signal terminal inputs a signal to the first node.

[0202] As shown in FIG9 , a schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed herein is shown. The second sub-control signal terminal CN22 can also be formed by the signal output terminal OUT(n+1) of the adjacent next-stage shift output circuit 1. The selection circuit 21 includes: a first transistor T1, a second transistor T2, and a first capacitor C1. The first electrode of the first transistor T1 is connected to the selection signal terminal SM, and the gate is connected to the second sub-control signal terminal CN22. The conduction level of the first transistor T1 is opposite to the effective level of the signal output terminal OUT(n); the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the second electrode is connected to the first node N1, and the gate is connected to the first sub-control signal terminal CN21. The conduction level of the second transistor T2 is the same as the effective level of the signal output terminal OUT(n); the first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to a stable voltage terminal. For example, the second electrode of the first capacitor C1 can be connected to the second power supply terminal VGL. The effective level of the signal output terminal OUT(n) can be a high level. The first transistor T1 can be a P-type transistor, and the second transistor T2 can be an N-type transistor.

[0203] In this exemplary embodiment, as shown in FIG9 , the gate drive circuit is used in a display panel that includes multiple rows of pixel drive circuits. The drive signal terminal of the final shift register unit may not be connected to the pixel drive circuit. This arrangement ensures that the gate drive signal received by the pixel drive circuit has a relatively uniform drive capability, thereby improving the display uniformity of the display panel.

[0204] In this exemplary embodiment, as shown in FIG9 , the fourth switch circuit includes: a seventh transistor T7 and an eighth transistor T8 . The first electrode of the seventh transistor T7 is connected to the output terminal of the third inverter, the second electrode is connected to the first node, and the gate is connected to the signal output terminal OUT(n) of the shift output circuit of this stage. The first electrode of the eighth transistor T8 is connected to the output terminal of the third inverter, the second electrode is connected to the first node, and the gate is connected to the first clock signal terminal CLK. This arrangement can also enable the latch circuit to shut off the first node and the output terminal of the third inverter during at least a portion of the time period when the selection signal terminal inputs a signal to the first node, and to conduct the first node and the output terminal of the third inverter during at least a portion of the other time period when the selection signal terminal inputs a signal to the first node.

[0205] As shown in Figure 10, it is a schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed in the present invention. In this exemplary embodiment, the shift output circuit 1 includes: a first output circuit 11 and a second output circuit 12. The first output circuit 11 is connected to the fourth node N4, the first power supply terminal VGH, and the signal output terminal OUT(n) of the shift output circuit 1. The first output circuit 11 is used to transmit the signal of the first power supply terminal VGH to the signal output terminal OUT(n) in response to the signal of the fourth node N4; the second output circuit 12 is connected to the fifth node N5, the second power supply terminal VGL, and the signal output terminal OUT(n) of the shift output circuit 1. The second output circuit 12 is used to transmit the signal of the second power supply terminal VGL to the signal output terminal OUT(n) in response to the signal of the fifth node N5. The signal output terminal OUT(n) is used to output the output signal. The gating circuit 21 is connected to a plurality of second control signal terminals CN2, wherein the plurality of second control signal terminals CN2 connected to the gating circuit 21 include a third sub-control signal terminal CN23 and a fourth sub-control signal terminal CN24, the fourth node N4 of the shift output circuit 1 at this stage forms the third sub-control signal terminal CN23, and the fifth node N5(n+1) of the shift output circuit 1 at the adjacent next stage forms the fourth sub-control signal terminal CN24; the gating circuit 21 is connected to a plurality of gating signal terminals SM, wherein the plurality of gating signal terminals SM connected to the gating circuit 21 include a first gating signal terminal SM1 and a second gating signal terminal SM2; the gating circuit 21 is also connected to a third control signal terminal CN3, and the gating circuit 21 is used to respond to signals of the third control signal terminal CN3 and the third sub-control signal terminal CN23 to transmit the signal of the first gating signal terminal SM1 to the first node N1, and to respond to signals of the third control signal terminal CN3 and the fourth sub-control signal terminal CN24 to transmit the signal of the second gating signal terminal SM2 to the first node N1.

[0206] In this exemplary embodiment, as shown in Figure 10, the regulation circuit 22 is connected to multiple first control signal terminals CN1, and the multiple first control signal terminals CN1 connected to the regulation circuit 22 include a fifth sub-control signal terminal CN15 and the sixth sub-control signal terminal CN16. The fifth sub-control signal terminal CN15 is formed by the fourth node N4 in the current stage shift output circuit 1, and the sixth sub-control signal terminal CN16 is formed by the fifth node N5 in the current stage shift output circuit 1. The regulation circuit 22 includes: a first switching circuit 225, a second switching circuit 226, and a third output circuit 227. The first switching circuit 225 is connected to the sixth sub-control signal terminal CN16, the first node N1, and the sixth node N6, and is used to transmit the signal of the sixth sub-control signal terminal CN16 to the sixth node N6 in response to the signal of the first node N1; the second switching circuit 226 is connected to the fifth sub-control signal terminal CN15, the first node N1, and the seventh node N7, and is used to transmit the signal of the fifth sub-control signal terminal CN15 to the seventh node N7 in response to the signal of the first node N1; the third output circuit 227 is connected to the sixth node N6, the seventh node N7, the first power supply terminal VGH, and the second power supply terminal VGL, and is used to transmit the power signal of the second power supply terminal VGL to the drive signal terminal Gate in response to the signal of the sixth node N6, and is used to transmit the power signal of the first power supply terminal VGH to the drive signal terminal Gate in response to the signal of the seventh node N7.

[0207] In this exemplary embodiment, the second output circuit 12 is further connected to the eighth node N8 and is further configured to transmit the signal of the eighth node N8 to the fifth node N5 in response to the signal of the eighth node N8. The regulating circuit 22 further includes a third switch circuit 228, which is connected to the sixth node N6 and the eighth node N8 and is configured to transmit the signal of the eighth node N8 to the sixth node N6 in response to the signal of the eighth node N8.

[0208] In this exemplary embodiment, the gating circuit 21 includes: a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, and a second capacitor C2. The first electrode of the sixteenth transistor T16 is connected to the first gating signal terminal SM1, and the gate is connected to the third control signal terminal CN3; the first electrode of the seventeenth transistor T17 is connected to the second electrode of the sixteenth transistor T16, the second electrode is connected to the first node N1, and the gate is connected to the third sub-control signal terminal CN23; the first electrode of the eighteenth transistor T18 is connected to the second gating signal terminal SM2, and the gate is connected to the third control signal terminal CN3; the first electrode of the nineteenth transistor T19 is connected to the second electrode of the eighteenth transistor T18, the second electrode is connected to the first node N1, and the gate is connected to the fourth sub-control signal terminal CN24; the first electrode of the second capacitor C2 is connected to the first node N1, and the second electrode is connected to the seventh node N7. The first switch circuit 225 includes a 20th transistor T20, wherein a first electrode of the 20th transistor T20 is connected to the sixth sub-control signal terminal CN16, a second electrode is connected to the sixth node N6, and a gate is connected to the first node N1. The second switch circuit 226 includes a 21st transistor T21, wherein a first electrode of the 21st transistor T21 is connected to the fifth sub-control signal terminal CN15, a second electrode is connected to the seventh node N7, and a gate is connected to the first node N1. The third switch circuit 228 includes a 24th transistor T24, wherein a first electrode of the 24th transistor T24 is connected to the eighth node N8, a second electrode is connected to the sixth node N6, and a gate is connected to the eighth node N8. The third output circuit 227 includes: a twenty-second transistor T22, a twenty-third transistor T23, and a third capacitor C3. The first electrode of the twenty-second transistor T22 is connected to the first power supply terminal VGH, the second electrode is connected to the drive signal terminal Gate, and the gate is connected to the seventh node N7; the first electrode of the twenty-third transistor T23 is connected to the second power supply terminal VGL, the second electrode is connected to the drive signal terminal Gate, and the gate is connected to the sixth node N6; the first electrode of the third capacitor C3 is connected to the seventh node N7, and the second electrode is connected to the first power supply terminal VGH.

[0209] In this exemplary embodiment, the multi-stage cascaded shift register units may provide a first selection signal terminal through a first signal line, a second selection signal terminal through a second signal line, and a third control signal terminal through a third signal line.

[0210] In this exemplary embodiment, the sixteenth to twenty-fourth transistors may be P-type transistors, the first power supply terminal VGH is a high-level signal terminal, and the second power supply terminal VGL is a low-level signal terminal.

[0211] FIG11 is a timing diagram of each node in a driving method of the shift register unit shown in FIG10 . N4 is the timing diagram of the fourth node, N5(n+1) is the timing diagram of the fifth node in the adjacent previous-stage shift output circuit, CN3 is the timing diagram of the third control signal terminal, MS1 is the timing diagram of the first selection signal terminal, MS2 is the timing diagram of the second selection signal terminal, and OUT(n) is the timing diagram of the signal output terminal in the current-stage shift output circuit.

[0212] When the display panel does not switch its refresh rate, the display panel can output a valid pulse signal via the third control signal terminal CN3 during a first phase t1 before the start of a frame refresh. At this time, the fifth node N5 in all shift register units is at a low level, the fourth node N4 is at a high level, the nineteenth transistor T19 and the eighteenth transistor T18 are turned on, the low-level signal of the second selection signal terminal MS2 is written to the first node N1, the twenty-first transistor T21 and the twentieth transistor T20 are turned on, the fifth node N5 is connected to the sixth node N6, the fourth node N4 is connected to the seventh node N7, and the drive signal terminal Gate outputs the same signal as the signal output terminal OUT(n). In this exemplary embodiment, the first phase t1 can be located at the end of the blank period between frames.

[0213] When a local area of ​​the display panel needs to switch from a high refresh frequency to a low refresh frequency, the display panel can output a second valid level pulse through the third control signal terminal CN3 in the second stage t2 at the end of the high refresh period. For the shift register unit at this stage, the signal output terminal of the shift output circuit outputs a low level signal, the fourth node N4 is at a high level, the fifth node N5 (n+1) in the adjacent next-stage shift output circuit is at a low level, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, the first node N1 is written with a high level signal of the second selection signal terminal, the twentieth transistor T20 and the twenty-first transistor T21 are turned off, the sixth node N6 maintains the low level of the previous stage, the seventh node N7 maintains the high level of the previous stage, and the driving signal terminal Gate continues to output a low level, that is, the pixel driving circuit corresponding to the shift register unit at this stage is switched to a low refresh frequency. For other shift register units, if the signal output terminal of the shift output circuit outputs a high-level signal at this time, the fourth node N4 is at a low level, the fifth node N5(n+1) in the adjacent next-stage shift output circuit is at a high level, the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, the low-level signal of the first selection signal terminal MS1 is written to the first node N1, the twentieth transistor T20 and the twenty-first transistor T21 are turned on, the sixth node N6 is written to the high-level signal, the seventh node is written to the low-level signal, and the drive signal terminal Gate outputs a high-level signal, i.e., the other shift register units can output normally. In addition, when the signal output terminal switches from a high level to a low level, the drive signal terminal Gate can also switch to output a low level, i.e., this driving method does not affect the output of the drive signal of other shift register units to maintain a high refresh rate.

[0214] When a local area of ​​the display panel needs to switch from a low refresh frequency to a high refresh frequency, the display panel can output a third valid level pulse through the third control signal terminal CN3 in the third stage t3 at the end of the low refresh period. For the shift register unit at this level, the signal output terminal of the shift output circuit outputs a low level signal, the fourth node N4 is at a high level, the fifth node N5 (n+1) in the adjacent next-level shift output circuit is at a low level, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, the first node N1 is written with a low level signal of the second selection signal terminal, the twentieth transistor T20 and the twenty-first transistor T21 are turned on, the sixth node N6 is connected to the fifth node N5, the fourth node N4 is connected to the seventh node N7, and the driving signal terminal outputs the same signal as the signal output terminal, that is, the pixel driving circuit corresponding to the shift register unit at this level is switched to a high refresh frequency. For other shift register units, if the signal output end of the shift output circuit outputs a high-level signal at this time, the fourth node N4 is at a low level, the fifth node N5(n+1) in the adjacent next-level shift output circuit is at a high level, the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, the first node N1 is written with a high-level signal of the first selection signal end MS1, the twentieth transistor T20 and the twenty-first transistor T21 are turned off, the sixth node N6 maintains the low level of the previous stage, the seventh node N7 maintains the high level of the previous stage, and the driving signal end Gate outputs a low-level signal, that is, this driving method will not affect the output of the driving signal maintaining a low refresh frequency by other shift register units.

[0215] As shown in FIG10 , the structure of the shift output circuit 1 may be the same as that of the shift output circuit shown in FIG6 , and will not be described in detail here.

[0216] According to one aspect of the present disclosure, a gate drive circuit driving method is provided, the driving method comprising:

[0217] Utilizing the shift output circuit to shift output the output signal;

[0218] The control circuit is controlled by a selection signal to output a first drive signal or a second drive signal, the first drive signal is the same as the output signal, and the second drive signal is an invalid level signal.

[0219] According to one aspect of the present disclosure, a display panel is provided, comprising the above-mentioned gate driving circuit.

[0220] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0221] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0222] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

[0223] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A gate drive circuit, wherein: The gate driving circuit includes a multi-stage cascaded shift register unit, wherein the shift register unit includes: A shift output circuit, the shift output circuit is used to convert an input signal into an output signal of a shift output, and the shift output circuit includes a plurality of signal terminals; A control circuit connected to at least part of the signal terminals, the selection signal terminal, and the drive signal terminal of at least one of the shift output circuits; Among them, the signal terminals connected to the control circuit and located in the shift output circuit include one or more control signal terminals, and the control circuit is used to respond to the signals on the selection signal terminal and the control signal terminal to input the first drive signal or the second drive signal to the drive signal terminal, the first drive signal is the same as the output signal, and the second drive signal is an invalid level signal.

2. The gate drive circuit according to claim 1, wherein: The signal on the control signal terminal and the output signal output by the shift output circuit at this stage have pulse signals that at least partially overlap.

3. The gate driving circuit according to claim 1, wherein: The control signal terminals include one or more first control signal terminals; The control circuit comprises: A gating circuit, the gating circuit being connected to the gating signal terminal and the first node, and the gating circuit being used for transmitting the signal of the gating signal terminal to the first node in response to a control signal; The regulating circuit is connected to the first node, the first control signal terminal, and the driving signal terminal. The regulating circuit is used to respond to the signals of the first node and the first control signal terminal to input the first driving signal or the second driving signal to the driving signal terminal.

4. The gate driving circuit according to claim 3, wherein: The control signal terminal also includes one or more second control signal terminals; The gating circuit is connected to the second control signal terminal, and is used for responding to a signal on the second control signal terminal to transmit the signal on the gating signal terminal to the first node.

5. The gate driving circuit according to claim 4, wherein: The first control signal terminal is formed by the signal terminal in the shift output circuit of this stage; And / or, the gating circuit is connected to a plurality of the second control signal terminals, and the plurality of the second control signal terminals connected to the gating circuit are formed by signal terminals in two adjacent stages of the shift output circuits.

6. The gate drive circuit according to claim 4 or 5, wherein: The shift output circuit comprises a signal output terminal, and the signal output terminal is used to output the output signal; The gating circuit is connected to a plurality of the second control signal terminals, wherein the plurality of the second control signal terminals connected to the gating circuit include a first sub-control signal terminal and a second sub-control signal terminal, wherein the first sub-control signal terminal is formed by a signal output terminal of a shift output circuit of the current stage, and the second sub-control signal terminal is formed by a signal output terminal of a shift output circuit of an adjacent stage; The gating circuit is used for transmitting the signal of the gating signal terminal to the first node in response to the signals on the first sub-control signal terminal and the second sub-control signal terminal.

7. The gate drive circuit according to any one of claims 3 to 6, wherein: The first control signal terminal is formed by the signal output terminal in the shift output circuit of this stage; The regulating circuit comprises: A NAND gate, a first input terminal connected to the first control signal terminal, and a second input terminal connected to the first node; The first inverter has an input end connected to the output end of the NAND gate and an output end connected to the driving signal end.

8. The gate driving circuit according to claim 6, wherein: The second sub-control signal terminal is formed by the signal output terminal of the adjacent previous stage shift output circuit; Alternatively, the second sub-control signal terminal is formed by a signal output terminal of an adjacent next-stage shift output circuit.

9. The gate driving circuit according to claim 8, wherein: The gate driving circuit is used for a display panel, and the display panel includes a plurality of rows of pixel driving circuits; When the second sub-control signal terminal is formed by the signal output terminal of the adjacent previous stage shift output circuit, the driving signal terminal of the first stage shift register unit is not connected to the pixel driving circuit; When the second sub-control signal terminal is formed by the signal output terminal of the adjacent next-stage shift output circuit, the driving signal terminal of the last-stage shift register unit is not connected to the pixel driving circuit.

10. The gate drive circuit according to any one of claims 3 to 9, wherein: The regulating circuit comprises: The latch circuit is connected to the first node and is used to latch the voltage of the first node input by the selection signal terminal.

11. The gate drive circuit according to any one of claims 3 to 10, wherein: The regulating circuit also includes: The first reset circuit is connected to the first node, the reset signal terminal, and the first power terminal, and is used for transmitting the signal of the first power terminal to the first node in response to the signal of the reset signal terminal.

12. The gate drive circuit according to claim 8 or 9, wherein: When the second sub-control signal terminal is formed by the signal output terminal of the adjacent previous stage shift output circuit, the gating circuit includes: a first transistor, wherein a first electrode is connected to the selection signal terminal, a gate is connected to the first sub-control signal terminal, and a conduction level of the first transistor is opposite to an effective level polarity of the signal output terminal; a second transistor, wherein a first electrode is connected to the second electrode of the first transistor, a second electrode is connected to the first node, a gate is connected to the second sub-control signal terminal, and a conduction level of the second transistor has the same polarity as an effective level of the signal output terminal; A first capacitor, a first electrode of which is connected to the first node, and a second electrode of which is connected to a stable voltage terminal; When the second sub-control signal terminal is formed by the signal output terminal of the adjacent next-stage shift output circuit, the gating circuit includes: a first transistor, wherein a first electrode is connected to the selection signal terminal, a gate is connected to the second sub-control signal terminal, and a conduction level of the first transistor is opposite to an effective level polarity of the signal output terminal; a second transistor, wherein a first electrode is connected to the second electrode of the first transistor, a second electrode is connected to the first node, a gate is connected to the first sub-control signal terminal, and a conduction level of the second transistor has the same polarity as an effective level of the signal output terminal; The first capacitor has a first electrode connected to the first node and a second electrode connected to a stable voltage terminal.

13. The gate drive circuit according to any one of claims 8, 9 and 12, wherein: The first control signal terminal is formed by the signal output terminal in the shift output circuit of this stage; The regulating circuit comprises: A NAND gate, a first input terminal connected to the first control signal terminal, and a second input terminal connected to the First node; A first inverter, an input end of which is connected to the output end of the NAND gate, and an output end of which is connected to the driving signal end; a latch circuit, connected to the first node, and used to latch the voltage of the first node input by the selection signal terminal; The latch circuit comprises: a second inverter, an input end of which is connected to the first node; A third inverter, an input end of which is connected to the output end of the second inverter, and an output end of which is connected to the second input end of the NAND gate; a fourth switch circuit, connecting the first node and the output end of the third inverter, and used for shutting off the first node and the output end of the third inverter during at least a portion of the time period when the selection signal end inputs a signal to the first node, and for turning on the first node and the output end of the third inverter during at least another portion of the time period when the selection signal end inputs a signal to the first node.

14. The gate driving circuit according to claim 13, wherein: The second inverter comprises: A third P-type transistor, a first electrode connected to the first power supply terminal of a high level, a second electrode connected to the second node, and a gate connected to the first node; a fourth N-type transistor, wherein a first electrode is connected to the second power supply terminal of a low level, a second electrode is connected to the second node, and a gate is connected to the first node; The third inverter comprises: a fifth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second input terminal of the NAND gate, and a gate connected to the second node; a sixth N-type transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the second input terminal of the NAND gate, and a gate connected to the second node; When the second sub-control signal terminal is formed by the signal output terminal of the adjacent previous stage shift output circuit, the fourth switch circuit includes: a seventh transistor, wherein a first electrode is connected to the second input terminal of the NAND gate, a second electrode is connected to the first node, and a gate is connected to the signal output terminal of the adjacent previous stage shift output circuit; An eighth transistor, a first electrode connected to the second input terminal of the NAND gate, a second electrode connected to the A first node, the gate of which is connected to a first clock signal terminal; When the second sub-control signal terminal is formed by the signal output terminal of the adjacent next-stage shift output circuit, the fourth switch circuit includes: a seventh transistor, wherein a first electrode is connected to the second input terminal of the NAND gate, a second electrode is connected to the first node, and a gate is connected to the signal output terminal of the shift output circuit at this stage; An eighth transistor has a first electrode connected to the second input terminal of the NAND gate, a second electrode connected to the first node, and a gate connected to the first clock signal terminal.

15. The gate driving circuit according to claim 7, wherein: The NAND gate comprises: a ninth P-type transistor, wherein the first electrode is connected to the first power supply terminal, the second electrode is connected to the third node, and the gate is connected to the first input terminal of the NAND gate; a tenth P-type transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the second input terminal of the NAND gate; an eleventh N-type transistor, a first electrode connected to the third node, and a gate connected to the first input terminal of the NAND gate; a twelfth N-type transistor, having a first electrode connected to the second electrode of the eleventh N-type transistor, a second electrode connected to the second power supply terminal, and a gate connected to the second input terminal of the NAND gate; The first inverter comprises: a thirteenth P-type transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the drive signal terminal, and a gate connected to the output terminal of the NAND gate; A fourteenth N-type transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the drive signal terminal, and a gate connected to the output terminal of the NAND gate.

16. The gate driving circuit according to claim 11, wherein: The first reset circuit comprises: The fifteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the first node, and a gate connected to the reset signal terminal.

17. The gate drive circuit according to any one of claims 4 to 6, wherein: The shift output circuit comprises: a first output circuit connected to the fourth node, the first power supply terminal, and the signal output terminal of the shift output circuit, wherein the first output circuit is used to transmit the signal of the first power supply terminal to the signal output terminal in response to the signal of the fourth node; a second output circuit connected to the fifth node, the second power supply terminal, and the signal output terminal of the shift output circuit, the second output circuit being used to transmit the signal of the second power supply terminal to the signal output terminal in response to the signal of the fifth node, and the signal output terminal being used to output the output signal; The gating circuit is connected to a plurality of the second control signal terminals, wherein the plurality of the second control signal terminals connected to the gating circuit include a third sub-control signal terminal and a fourth sub-control signal terminal, the fourth node of the shift output circuit of the current stage forms the third sub-control signal terminal, and the fifth node of the shift output circuit of the next adjacent stage forms the fourth sub-control signal terminal; The gating circuit is connected to a plurality of gating signal terminals, wherein the plurality of gating signal terminals connected to the gating circuit include a first gating signal terminal and a second gating signal terminal; The gating circuit is also connected to a third control signal terminal, and is used to respond to signals from the third control signal terminal and a third sub-control signal terminal to transmit the signal from the first gating signal terminal to the first node, and to respond to signals from the third control signal terminal and a fourth sub-control signal terminal to transmit the signal from the second gating signal terminal to the first node.

18. The gate driving circuit according to claim 17, wherein: The regulating circuit is connected to a plurality of the first control signal terminals, wherein the plurality of the first control signal terminals connected to the regulating circuit include a fifth sub-control signal terminal and a sixth sub-control signal terminal, wherein the fifth sub-control signal terminal is formed by a fourth node in the shift output circuit of the current stage, and the sixth sub-control signal terminal is formed by a fifth node in the shift output circuit of the current stage; The regulating circuit comprises: a first switch circuit, connected to the sixth sub-control signal terminal, the first node, and the sixth node, and configured to transmit the signal of the sixth sub-control signal terminal to the sixth node in response to the signal of the first node; a second switch circuit, connected to the fifth sub-control signal terminal, the first node, and the seventh node, and configured to transmit the signal of the fifth sub-control signal terminal to the seventh node in response to the signal of the first node; The third output circuit is connected to the sixth node, the seventh node, the first power supply terminal, and the second power supply terminal, and is used to transmit the power signal of the second power supply terminal to the drive signal terminal in response to the signal of the sixth node, and is used to transmit the power signal of the first power supply terminal to the drive signal terminal in response to the signal of the seventh node.

19. The gate driving circuit according to claim 18, wherein: The second output circuit is also connected to an eighth node, and the second output circuit is further used to transmit the signal of the eighth node to the fifth node in response to the signal of the eighth node; The regulating circuit also includes: The third switch circuit is connected to the sixth node and the eighth node, and is used for responding to the signal of the eighth node and transmitting the signal of the eighth node to the sixth node.

20. The gate driving circuit according to claim 19, wherein: The gating circuit comprises: A sixteenth transistor, a first electrode connected to the first selection signal terminal, and a gate connected to the third control signal terminal; a seventeenth transistor, a first electrode connected to the second electrode of the sixteenth transistor, a second electrode connected to the first node, and a gate connected to the third sub-control signal terminal; An eighteenth transistor, a first electrode of which is connected to the second selection signal terminal, and a gate of which is connected to the third control signal terminal; a nineteenth transistor, a first electrode connected to the second electrode of the eighteenth transistor, a second electrode connected to the first node, and a gate connected to the fourth sub-control signal terminal; a second capacitor, a first electrode of which is connected to the first node, and a second electrode of which is connected to the seventh node; The first switch circuit comprises: a twentieth transistor, having a first electrode connected to the sixth sub-control signal terminal, a second electrode connected to the sixth node, and a gate connected to the first node; The second switch circuit comprises: A twenty-first transistor, having a first electrode connected to the fifth sub-control signal terminal, a second electrode connected to the seventh node, and a gate connected to the first node; The third switch circuit comprises: A twenty-fourth transistor, having a first electrode connected to the eighth node, a second electrode connected to the sixth node, and a gate connected to the eighth node; The third output circuit comprises: A twenty-second transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the driving signal terminal, and a gate connected to the seventh node; A twenty-third transistor, a first electrode connected to the second power supply terminal, a second electrode connected to the driving signal terminal, and a gate connected to the sixth node; A third capacitor has a first electrode connected to the seventh node and a second electrode connected to the first power supply terminal.

21. The gate drive circuit according to any one of claims 1 to 20, wherein: The shift output circuit comprises: a first input circuit connected to the second power supply terminal, the first clock signal terminal, and the ninth node, and configured to transmit the signal of the second power supply terminal to the ninth node in response to the signal of the first clock signal terminal; a second input circuit connected to the signal input terminal, the first clock signal terminal, the tenth node, and the eleventh node, and configured to transmit the signal of the signal input terminal to the tenth node and the eleventh node in response to the signal of the first clock signal terminal; a first output circuit, connected to the twelfth node, the thirteenth node, the fourth node, the second clock signal terminal, the first power supply terminal, and the signal output terminal, the first output circuit being used to transmit the signal of the second clock signal terminal to the thirteenth node in response to the signal of the twelfth node, to transmit the signal of the thirteenth node to the fourth node in response to the signal of the second clock signal terminal, and to transmit the power supply signal of the first power supply terminal to the signal output terminal in response to the signal of the fourth node, wherein the twelfth node is connected to the ninth node; a second output circuit, connected to the eighth node, the fifth node, the second power supply terminal, and the signal output terminal, the second output circuit being used to transmit the signal of the eighth node to the fifth node in response to the signal of the eighth node, and being used to transmit the signal of the second power supply terminal to the signal output terminal in response to the signal of the fifth node, the eighth node being connected to the eleventh node, and the tenth node being connected to the fifth node; a first pull-up circuit connected to the tenth node, the first power supply terminal, and the fourth node, and configured to transmit a signal from the first power supply terminal to the fourth node in response to a signal from the tenth node; a second pull-up circuit, connected to the tenth node, the first clock signal terminal, and the ninth node, and configured to transmit the signal of the first clock signal terminal to the ninth node in response to the signal of the tenth node; A coupling circuit is connected to the ninth node, the first power supply terminal, the fourteenth node, the eighth node, and the second clock signal terminal, and is used to respond to the signal of the ninth node and transmit the signal of the first power supply terminal to the transmitting to the fourteenth node, for transmitting the signal of the second clock signal terminal to the fourteenth node in response to the signal of the eighth node, and for coupling the signal on the fourteenth node to the eighth node; The signal input end of the first-stage shift output circuit is connected to the initial signal, and the signal input ends of other shift output circuits are connected to the signal output ends of the adjacent previous-stage shift output circuit.

22. The gate driving circuit according to claim 21, wherein: The shift output circuit also includes: a first isolation circuit, connected to the ninth node, the twelfth node, and the second power supply terminal, and configured to connect the ninth node and the twelfth node in response to a signal from the second power supply terminal; a second isolation circuit, connected to the tenth node, the eleventh node, the second power supply terminal, the fifth node, and the eighth node, and configured to connect the tenth node with the fifth node, and connect the eleventh node with the eighth node in response to a signal from the second power supply terminal; The second reset circuit is connected to the first power supply terminal, the reset signal terminal, and the tenth node, and is used for transmitting the signal of the first power supply terminal to the tenth node in response to the signal of the reset signal terminal.

23. The gate driving circuit according to claim 22, wherein: The first input circuit comprises: A twenty-fifth transistor, a first electrode connected to the second power supply terminal, a second electrode connected to the ninth node, and a gate connected to the first clock signal terminal; The second input circuit comprises: A twenty-sixth transistor, a first electrode connected to the signal input terminal, a second electrode connected to the tenth node, and a gate connected to the first clock signal terminal; A twenty-seventh transistor, a first electrode connected to the signal input terminal, a second electrode connected to the eleventh node, and a gate connected to the first clock signal terminal; The first output circuit comprises: A twenty-eighth transistor, a first electrode connected to the second clock signal terminal, a second electrode connected to the thirteenth node, and a gate connected to the twelfth node; A twenty-ninth transistor, a first electrode connected to the thirteenth node, a second electrode connected to the fourth node, and a gate connected to the second clock signal terminal; A thirtieth transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the signal input terminal An output terminal, the gate of which is connected to the fourth node; a fourth capacitor, wherein a first electrode is connected to the twelfth node, and a second electrode is connected to the thirteenth node; a fifth capacitor, a first electrode of which is connected to the fourth node, and a second electrode of which is connected to the first power supply terminal; The second output circuit comprises: A thirty-first transistor, having a first electrode connected to the fifth node, a second electrode connected to the eighth node, and a gate connected to the eighth node; A thirty-second transistor, a first electrode connected to the second power supply terminal, a second electrode connected to the signal output terminal, and a gate connected to the fifth node; a sixth capacitor, a first electrode of which is connected to the signal output terminal, and a second electrode of which is connected to the second power supply terminal; The first pull-up circuit comprises: A thirty-third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourth node, and a gate connected to the tenth node; The second pull-up circuit comprises: A thirty-fourth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the ninth node, and a gate connected to the tenth node; The coupling circuit comprises: A thirty-fifth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the fourteenth node, and a gate connected to the ninth node; A thirty-sixth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the fourteenth node, and a gate connected to the eighth node; a seventh capacitor, a first electrode of which is connected to the fourteenth node, and a second electrode of which is connected to the eighth node; The first isolation circuit comprises: A thirty-seventh transistor, having a first electrode connected to the ninth node, a second electrode connected to the twelfth node, and a gate connected to the second power supply terminal; The second isolation circuit comprises: A thirty-eighth transistor, a first electrode connected to the tenth node, a second electrode connected to the fifth node point, the gate is connected to the second power supply terminal; A thirty-ninth transistor, having a first electrode connected to the eleventh node, a second electrode connected to the eighth node, and a gate connected to the second power supply terminal; The second reset circuit comprises: The fortieth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the tenth node, and a gate connected to the reset signal terminal.

24. A gate drive circuit driving method, wherein: Used to drive the gate drive circuit according to any one of claims 1 to 23, the driving method comprising: Utilizing the shift output circuit to shift output the output signal; The control circuit is controlled by a selection signal to output a first drive signal or a second drive signal, the first drive signal is the same as the output signal, and the second drive signal is an invalid level signal.

25. A display panel, wherein: The display panel comprises the gate driving circuit according to any one of claims 1-23.

26. A display device, wherein: The display device comprises the display panel according to claim 25.

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