Wafer processing method based on laser invisibility

Abstract

The invention provides a wafer processing method based on laser invisibility, which comprises the following steps of: A, implementing a first round of laser invisibility processing, and obtaining a plurality of first cutting marks which are distributed side by side at intervals and a plurality of areas among the first marks in a wafer; c, subsequent laser invisible processing is carried out, a plurality of subsequent cutting marks distributed side by side at intervals and a plurality of areas between the subsequent cutting marks are obtained in the wafer, the subsequent cutting marks comprise a plurality of second cutting marks located in the first areas between the first cutting marks, the areas between the subsequent cutting marks comprise a plurality of areas between the second cutting marks and a plurality of areas between the third cutting marks, and the third cutting marks are located between the second areas between the second cutting marks and the third areas between the third cutting marks; and each second cutting mark divides the first inter-mark area into a second inter-mark area and a third inter-mark area. According to the invention, the stripping difficulty of the wafer can be reduced, and the loss layer of the wafer can be thinned, so that the production cost of the wafer is reduced; as the laser focus does not need to be repeatedly moved along the cutting mark, the number of times that the laser focus moves along the cutting mark can be reduced, the probability that defects occur in the wafer is reduced, and therefore the production yield of the wafer is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device production, and particularly to a wafer processing method based on laser stealth. Background Art

[0002] Laser stealth is a semiconductor processing method. Taking the laser stealth of silicon carbide as an example, the laser stealth processing method will cause complex physical and chemical modifications in the silicon carbide wafer. Existing laser stealth processes often lead to an increase in the thickness of the wafer loss layer and an increase in the probability of internal defects, which increases the production cost of the wafer and reduces the production yield of the wafer. Changing the process parameters of laser stealth may cause the cracks generated by laser cutting to not meet the requirements for slicing, making it difficult to peel the wafer. Summary of the Invention

[0003] In view of this, the present invention provides a wafer processing method based on laser stealth, which can make the wafer easier to peel and slice, reduce wafer loss, and improve wafer yield.

[0004] The wafer processing method based on laser stealth of the present invention includes:

[0005] A. Implement the first-round laser stealth processing to obtain a plurality of first cut marks arranged side by side at intervals and a plurality of first inter-mark regions in the wafer;

[0006] C. Implement subsequent laser stealth processing to obtain a plurality of subsequent cut marks arranged side by side at intervals and a plurality of subsequent inter-mark regions in the wafer,

[0007] The subsequent cut marks include a plurality of second cut marks respectively located in a plurality of first inter-mark regions, and the subsequent inter-mark regions include a plurality of second inter-mark regions and a third inter-mark region. Each second cut mark divides the first inter-mark region into a second inter-mark region and a third inter-mark region.

[0008] The present invention obtains all the required scribe lines after at least two rounds of laser stealth machining. These scribe lines include the first scribe lines obtained by performing step A and step C and subsequent scribe lines. At the same time, these scribe lines also divide the wafer into multiple second inter-scribe regions and multiple third inter-scribe regions. Compared with the first inter-scribe region, the width dimensions of the second inter-scribe region and the third inter-scribe region are both narrowed. Compared with two adjacent first scribe lines or two adjacent subsequent scribe lines, any subsequent scribe line is closer to and easier to interact with the adjacent first scribe line, and cracks are more likely to expand at the scribe line. There is no need to increase the power of the laser source to increase the energy of the laser acting on the scribe line, nor is it necessary to repeatedly move the laser focus along the scribe line to reduce the difficulty of peeling the wafer; since there is no need to increase the power of the laser source, the present invention can thin the loss layer of the wafer, thereby reducing the production cost of the wafer; since there is no need to repeatedly move the laser focus along the scribe line, the present invention can reduce the number of times the laser focus moves along the scribe line, and the probability of defects occurring inside the wafer decreases, thereby improving the production yield of the wafer.

[0009] In some embodiments, each second scribe line equally divides the first inter-scribe region, and the second inter-scribe region and the third inter-scribe region have the same width.

[0010] In some embodiments,

[0011] Step A includes:

[0012] A1. Control the laser source to perform a scribe movement relative to the wafer along the scribe line direction, so that the laser focus translates relative to the wafer along the scribe line direction;

[0013] A2. Control the laser source to perform a trace movement relative to the wafer along the trace direction perpendicular to the scribe line direction and the wafer axis, so that the laser focus position translates relative to the wafer along the trace direction. The stroke of the trace movement is equal to the single-round scribe line pitch and equal to the width of the first inter-scribe region;

[0014] A3. Repeat steps A1 and A2 several times;

[0015] The wafer processing method based on laser stealth further includes:

[0016] B. Control the laser source to perform a misalignment movement relative to the wafer along the misalignment direction perpendicular to the scribe line direction and the wafer axis, so that the laser focus position translates relative to the wafer along the trace direction. The stroke of the misalignment movement is one-half of the single-round scribe line pitch;

[0017] Step C includes:

[0018] C1. Control the laser source to perform a scribe movement relative to the wafer along the scribe line direction, so that the laser focus translates relative to the wafer along the scribe line direction;

[0019] C2, control the laser source to move relative to the wafer in a moving direction perpendicular to the cutting direction and the axial direction of the wafer, so that the laser focus position is translated relative to the wafer in the moving direction, and the moving stroke is equal to the single-round cutting line spacing and equal to the width of the first inter-mark area;

[0020] C3. Repeat steps C1 and C2 several times.

[0021] In some embodiments, the laser source moves along the cutting direction relative to the wafer at a cutting speed ranging from 150 mm / s to 250 mm / s.

[0022] In some embodiments, the single wheel cut line spacing is 500 , the displacement travel is 250 .

[0023] In some embodiments, step A and step C are performed over the entire area of ​​the back side of the wafer;

[0024] The wafer processing method based on laser stealth also includes:

[0025] D. Compensation laser invisible processing is performed in the low light transmittance range on the back side of the wafer to obtain multiple compensation cuts spaced side by side in the wafer, and the multiple compensation cuts overlap with the multiple subsequent cuts in the low light transmittance range one by one; or, the multiple compensation cuts overlap with the multiple first cuts in the low light transmittance range one by one.

[0026] In some embodiments, the width of the low light transmission range in the length direction of the cutting surface is X1, the diameter of the wafer is X, and the width of the highest light transmission range of the wafer is Y, X1 = X-(2Y±10) .

[0027] In some embodiments, the laser source is controlled to configure the power P 全 Generate laser and perform steps A and C, 40W≤P 全 ≤50W.

[0028] In some embodiments, the laser source is controlled to compensate for the configuration power P 补 Generate laser and execute step D, 30W≤P 补 ≤40W.

[0029] In some embodiments, the laser stealth-based wafer processing method further comprises:

[0030] S. Use the back of the wafer as the laser incident surface to make the laser focus position fall into the wafer, and control the distance between the laser focus position and the back of the wafer to be between 150 ~250 .

[0031] In some embodiments, step A is first performed to obtain N first notches and N−1 first inter-notch regions, and then step C is performed, where N is the expected number of first notches to be obtained. Description of the Drawings

[0032] Figure 1 Schematic diagram of the distribution of wafer notches obtained after processing a wafer by the wafer processing method based on laser stealth of the present invention;

[0033] Figure 2 Schematic diagram of the distribution of first notches obtained after processing a wafer by the wafer processing method based on laser stealth of the present invention;

[0034] Figure 3 Schematic diagram of the distribution of second notches obtained after processing a wafer by the wafer processing method based on laser stealth of the present invention;

[0035] Figure 4 Schematic diagram of the distribution of compensation notches obtained after processing a wafer by the wafer processing method based on laser stealth of the present invention;

[0036] Figure 5 Schematic diagram of generating notches of the wafer processing method based on laser stealth of the present invention;

[0037] Figure 6 Schematic diagram of the resistivity distribution in the wafer.

[0038] Reference Signs: 100, wafer; 101, carbon surface; 102, low light transmission range; 103, silicon surface; 104, cutting surface; 20, first notch; 30, first inter-notch region; 40, second notch; 51, second inter-notch region; 52, third inter-notch region; 60, compensation notch; 70, laser beam; 71, laser focus. Detailed Embodiments

[0039] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0041] The present invention provides a wafer processing method based on laser stealth. This method uses laser irradiation to modify the irradiated positions inside the wafer 100 and generate cut marks. The purpose of obtaining the cut marks is to facilitate the subsequent peeling and segmentation of the wafer 100. To improve the modification efficiency and the quality of the cut marks, the laser is incident through the carbon surface 101 of the wafer 100, and the position where the laser focus 71 is located is modified to generate a light spot. As the laser focus 71 moves, a series of light spots generated by the laser focus 71 in the wafer 100 are arranged along the moving trajectory of the laser focus 71 to form a cut mark. The moving speed of the laser focus 71 is called the cutting speed of the laser stealth processing. The lower the cutting speed, the denser the light spots arranged along the moving trajectory of the laser focus 71, the better the cutting effect, and the easier it is to peel the wafer 100.

[0042] Due to the thermal expansion of the wafer 100 accompanied by laser stealth, too low a cutting speed will exacerbate the thermal expansion of the wafer 100. The wafers 100 obtained by the existing laser stealth processing technology have problems such as low yield, high probability of internal defects in the wafers 100, large thickness of the damaged layer of the wafers 100, and high production cost of the wafers 100. The influencing factors leading to internal defects include cutting power and cutting times. The cutting power is the power of the laser source used to generate the laser beam 70, and the cutting times refer to the number of times the laser focus 71 moves along the moving trajectory corresponding to the cut mark during the process of obtaining a single cut mark. The factors leading to a large thickness of the damaged layer of the wafers 100 include cutting power. Although the industry has recognized that reducing the cutting power and the cutting times is beneficial to improving the yield, reducing internal defects in the wafers 100, controlling and reducing the thickness of the damaged layer of the wafers 100, but lower cutting power and fewer cutting times will cause the cut marks to not extend to form cracks meeting the segmentation requirements, thus making it more difficult to peel and segment the wafers 100.

[0043] In view of this, the wafer processing method based on laser stealth of the present invention includes the following steps:

[0044] Step A: Implement the first round of laser stealth processing to obtain multiple first cut marks 20 arranged side by side at intervals and multiple first inter-mark regions 30 in the wafer 100;

[0045] Step C: Implement subsequent laser stealth processing to obtain multiple subsequent cut marks arranged side by side at intervals and multiple subsequent inter-mark regions in the wafer 100,

[0046] The subsequent cut marks include multiple second cut marks 40 respectively located in multiple first inter-mark regions 30. The subsequent inter-mark regions include multiple second inter-mark regions 51 and a third inter-mark region 52. Each second cut mark 40 divides the first inter-mark region 30 into a second inter-mark region 51 and a third inter-mark region 52.

[0047] After implementing Step A, the multiple first cut marks 20 and multiple first inter-mark regions 30 obtained are as Figure 2As shown; multiple second notches 40, multiple second notch regions 51, and multiple third notch regions 52 obtained after implementing step C are as Figure 1 and Figure 3 shown; as Figure 1 shown, multiple first notches 20 and multiple second notches 40 are arranged side by side and alternately spaced. Each second notch 40 divides the first notch region 30 where it is located into a second notch region 51 and a third notch region 52. The second notch region 51 and the third notch region 52 within each first notch region 30 are respectively located on both sides of the second notch 40 within the first notch region 30.

[0048] Both the first notch 20 and the second notch 40 are used to extend cracks. After the wafer 100 is peeled and formed into multiple strip-shaped peeled products, the multiple second notch regions 51 and the multiple third notch regions 52 respectively correspond to the multiple strip-shaped peeled products. The fracture surface of each strip-shaped peeled product during the peeling process is formed by the cracks extended from the first notch 20 and the second notch 40. The multiple strip-shaped peeled products can be divided into two groups. In one group of strip-shaped peeled products, the width of the strip-shaped peeled product is the width of the second notch region 51. In the other group of strip-shaped peeled products, the width of the strip-shaped peeled product is the width of the third notch region 52.

[0049] The width of each first notch region 30 is equal to the distance between two adjacent first notches 20 that define the first notch region 30; for the same first notch region 30, the width of its second notch region 51 is equal to the distance from the second notch 40 to the first notch 20 on one side of the second notch 40, and the width of its third notch region 52 is equal to the distance from the second notch 40 to the first notch 20 on the other side of the second notch 40.

[0050] Optionally, referring to Figures 1 to 3 , multiple first notches 20 are arranged parallel to each other and at equal intervals, and multiple second notches 40 are arranged parallel to each other and at equal intervals; the number of first notch regions 30, the number of second notch regions 51, and the number of third notch regions 52 are all equal, that is, the sum of the number of second notch regions 51 and the number of third notch regions 52 is twice the number of first notch regions 30. With such a setting, the total number of multiple strip-shaped peeled products obtained after the wafer 100 is peeled is equal to the sum of the number of second notch regions 51 and the number of third notch regions 52, and each strip-shaped peeled product is a structure with a uniform width dimension.

[0051] In some embodiments, each second notch 40 equally divides the first notch interval region 30, and the second notch interval region 51 and the third notch interval region 52 have the same width. With such a setting, the multiple strip-shaped chip products obtained after the chip 100 is peeled and segmented have a uniform width. The width of each strip-shaped chip product is equal to the width of each second notch interval region 51 and also equal to the width of each third notch interval region 52. The width of each first notch interval region 30 is twice the width of each strip-shaped chip product. With such a setting, it can be ensured that the cracks extended by the first notch 20 and the cracks extended by the second notch 40 can meet the standards and are thus easy to peel. In other embodiments, the second notch interval region 51 and the third notch interval region 52 can also be set to have unequal widths.

[0052] In some embodiments, step A includes:

[0053] Step A1: Control the laser source to perform a notching movement relative to the chip 100 along the notch direction, so that the laser focus 71 translates relative to the chip 100 along the notch direction;

[0054] Step A2: Control the laser source to perform a trace movement relative to the chip 100 along the trace direction perpendicular to the notch direction and the axial direction of the chip 100, so that the position of the laser focus 71 translates relative to the chip 100 along the trace direction. The stroke of the trace movement is equal to the single-round notch row spacing and equal to the width of the first notch interval region 30;

[0055] Step A3: Repeat steps A1 and A2 several times;

[0056] The chip processing method based on laser stealth further includes:

[0057] Step B: Control the laser source to perform a misalignment movement relative to the chip 100 along the misalignment direction perpendicular to the notch direction and the axial direction of the chip 100, so that the position of the laser focus 71 translates relative to the chip 100 along the trace direction. The stroke of the misalignment movement is one-half of the single-round notch row spacing;

[0058] Step C includes:

[0059] Step C1: Control the laser source to perform a notching movement relative to the chip 100 along the notch direction, so that the laser focus 71 translates relative to the chip 100 along the notch direction;

[0060] Step C2: Control the laser source to perform a trace movement relative to the chip 100 along the trace direction perpendicular to the notch direction and the axial direction of the chip 100, so that the position of the laser focus 71 translates relative to the chip 100 along the trace direction. The stroke of the trace movement is equal to the single-round notch row spacing and equal to the width of the first notch interval region 30;

[0061] Step C3: Repeat steps C1 and C2 several times.

[0062] The cutting direction and the moving direction are both perpendicular to the axial direction of the wafer 100. The first cut 20, the second cut 40, and all subsequent cuts except the second cut 40 extend in the cutting direction, that is, the first cut 20, the second cut 40, and all subsequent cuts except the second cut 40 are parallel to each other, and each cut is composed of a number of light spots arranged in a straight line along the cutting direction. Optionally, in some embodiments, the cutting surface 104 of the wafer 100 is parallel to the axial direction of the wafer 100, the cutting direction is perpendicular to the cutting surface 104, the moving direction is parallel to the cutting surface 104, the first cut 20, the second cut 40, and all subsequent cuts except the second cut 40 are perpendicular to the cutting surface 104, see Figures 1 to 3 After the bow structure is removed from the wafer 100, a cutting surface 104 is formed by the remaining cross section.

[0063] Each time step A1 is performed once, a first cut mark 20 is obtained, and step A2 is performed to prepare for the next first cut mark 20; each time step C1 is performed once, a second cut mark 40 is obtained, and step C2 is performed to prepare for the next second cut mark 40. The line spacing of a single round of cuts is equal to the distance between any two adjacent first cut marks 20, and is also equal to the distance between any two adjacent second cut marks 40. Repeating steps A1 and A2 several times can generate multiple first cut marks 20 distributed side by side in the wafer 100. Repeating steps C1 and C2 several times can generate multiple second cut marks 40 distributed side by side in the wafer 100. Performing step B before performing step C can ensure that multiple subsequent cut marks obtained by subsequent laser stealth processing will not overlap with multiple first cut marks 20 obtained by the first round of laser stealth processing, so that the second cut marks 40 will not overlap with the first cut marks 20, and the multiple second cut marks 40 will fall in multiple first mark inter-regions 30 respectively. The displacement movement stroke in the control step B is half of the single-wheel cutting line spacing, so that the multiple second cutting marks 40 can be evenly divided into multiple first inter-mark areas 30.

[0064] Further, in some embodiments, the rate at which the laser source moves relative to the wafer 100 along the notch direction is between 150 mm / s and 250 mm / s, that is, the moving speed of the laser focus 71 within the wafer 100 is between 150 mm / s and 250 mm / s. With such a setting, compared to the existing laser stealth processing with a cutting speed above 400 mm / s, the cutting speed of the laser stealth processing in this embodiment is significantly reduced. Moreover, in the present invention, the single-round notch row spacing selected during single-round laser stealth processing is larger. Therefore, cutting to obtain notches at a lower cutting speed is not likely to cause warping of the wafer 100. The main reason why the warping of the wafer 100 in the existing laser stealth process intensifies as the cutting speed decreases is that the single-round notch row spacing selected during single-round laser stealth processing is too small. Along with the thermal expansion of the wafer 100 and the dense arrangement of the light spots on the notches, the wafer 100 is severely deformed by heat. In addition, in order to facilitate the expansion of cracks at the notches and increase the number of cutting times to make the laser focus 71 move multiple times along the notch, the warping of the wafer 100 will be further aggravated.

[0065] For example, in order to obtain strip-shaped segmented products with a width of 250 after the wafer 100 is peeled and segmented, the existing laser stealth process selects a single-round notch row spacing of 250 during single-round laser stealth processing, and in order to facilitate the expansion of cracks at the notches, the number of cutting times is at least 5 times;

[0066] And in order to obtain strip-shaped segmented products with the same width of 250 in an embodiment of the present invention, the single-round notch row spacing is 500, and the stroke of the misaligned movement is 250 , that is, when performing step A and step C, the width of each first notch interval region 30 is 500 , the distance between any two adjacent first notches 20 is 500 , the distance between any two adjacent second notches 40 is 500 , and the width of each second notch interval region 51 and the width of each third notch interval region 52 are both 250 .

[0067] With such a setting, during the first-round laser stealth processing and subsequent rounds of stealth processing, the single-round notch row spacing is doubled on the basis of the single-round notch row spacing in the prior art, weakening the influence of the single-round notch row spacing on the warping of the wafer 100; the distance between any one first notch 20 and the adjacent second notch 40 is still 250 , which is consistent with the notch spacing obtained by the existing laser stealth process. It is difficult for the first notch 20 and the second notch 40 to interact to extend cracks, and there is no need to increase the number of cuts. When generating a first notch 20, the laser focus 71 only needs to move along the first notch 20 once, and when generating a second notch 40, the laser focus 71 only needs to move along the second notch 40 once. Thus, the influence of the number of cuts on the warping of the wafer 100 can be avoided.

[0068] Further, in some embodiments, steps A and C are performed within the entire range of the back surface of the wafer 100. The back surface of the wafer 100 is the carbon surface 101 of the wafer 100, and all positions on the carbon surface 101 can be used as the positions where the laser enters the wafer 100. For example, Figures 1 to 3 , both ends of any one of the first notches 20 extend to the circular contour of the carbon surface 101, and both ends of any one of the second notches 40 also extend to the circular contour of the carbon surface 101. Such a setting can ensure that the first notch 20 and the subsequent notches can all extend cracks extending to the outer peripheral wall of the wafer 100, so as to facilitate the peeling and slicing of the wafer 100 to obtain qualified strip-shaped sliced products with smooth edges.

[0069] Further, the wafer processing method based on laser stealth further includes:

[0070] Step D: Perform compensated laser stealth processing within the low light transmission range 102 on the back surface of the wafer 100 to obtain a plurality of compensated notches 60 arranged side by side and spaced apart within the wafer 100. The plurality of compensated notches 60 respectively coincide with a plurality of subsequent notches within the low light transmission range 102 one by one; or, the plurality of compensated notches 60 respectively coincide with a plurality of first notches 20 within the low light transmission range 102 one by one. During the process of obtaining the compensated notches 60, the laser source is also controlled to make a notch movement relative to the wafer 100 along the notch direction perpendicular to the trace movement direction and the axial direction of the wafer 100. The first notch 20, all subsequent notches including the second notch 40, and the compensated notches 60 all extend along the notch direction.

[0071] With such a setting, step D can achieve compensated cutting of the wafer 100 by the laser, making it easier for the first notch 20 or subsequent notches to extend cracks. Especially for wafers 100 with a larger diameter, the effect of compensated cutting is more significant, which can fully modify the first notch 20 or subsequent notches within the low light transmission range 102 of the wafer 100 and reduce the mechanical energy required for the first notch 20 or subsequent notches to extend cracks. When the diameter of the wafer 100 is small, step D can be performed or skipped. Compared with wafers 100 with a larger diameter, the low light transmission range 102 of wafers 100 with a smaller diameter is smaller, and it is more difficult for the first notch 20 and subsequent notches to extend cracks, and the required mechanical energy is lower. Therefore, the demand for generating compensated notches 60 through compensated cutting is lower.

[0072] The low light transmittance range 102 is specifically a cylindrical spatial range. The low light transmittance range 102 is substantially coaxial with the entire wafer 100. If the wafer 100 is viewed from above at the viewing angle facing the carbon surface 101 of the wafer 100, the low light transmittance range 102 is approximately a circular range, and the center of the low light transmittance range 102 is the center of the carbon surface 101. The low light transmittance range 102 has a lower light transmittance compared to the outside of the low light transmittance range 102. Generally, the light transmittance within the wafer 100 is strongly correlated with the resistivity within the wafer 100. Refer to Figure 6 , there is a range with a relatively low resistivity within the wafer 100, and this range coincides with the low light transmittance range 102. Figure 6 In

[0073] Refer to Figure 4 , Figure 4 It schematically shows a plurality of compensation notches 60 generated within the low light transmittance range 102 through step D. Figure 4 In Figure 4 , the circular area including the low light transmittance range 102 is coaxial with the end face of the wafer 100, and the diameter of the circular area including the low light transmittance range 102 is smaller than the diameter of the wafer 100. The distance between any two adjacent compensation notches 60 is equal to the aforementioned single - pass notch pitch, or equal to twice, three times, or more integer multiples of the single - pass notch pitch. The number of compensation notches 60 does not exceed the number of the first notches 20, nor does it exceed the number of subsequent notches. Optionally, as , the distribution span of the compensation notches 60 in the length direction of the cutting surface 104 is X1, the diameter of the wafer 100 is X, and the width of the highest light transmittance range of the wafer 100 is Y, X1 = X - (2Y ± 10)

[0074] Furthermore, in some embodiments, control the laser source to generate laser with a global configuration power P 全 and execute step A and step C, 40W ≤ P 全 ≤ 50W; control the laser source to generate laser with a compensation configuration power P 补 and execute step D, 30W ≤ P 补 ≤ 40W. With such settings, the cutting power of laser stealth machining is reduced, and the finally obtained notches make the wafer 100 relatively easy to peel and slice.

[0075] To obtain a segmented product with a width of 250 by using the existing laser stealth process, the laser source needs to generate laser with a power of 60 - 80 W. For each generated cut mark, the laser focus 71 needs to move along the cut mark multiple times to achieve multi-round repeated cutting. Only in this way can the cut mark expand to form a crack meeting the segmentation requirement. However, since the single-round cut mark row spacing for each round of cutting is 250 ,the wafer 100 has significant thermal expansion and severe warping;

[0076] To obtain a segmented product with a width of 250 by using the wafer processing method based on laser stealth of the present invention, since during the first-round laser stealth processing for generating the first cut mark 20, the single-round cut mark row spacing is controlled to be 500 ,and during the generation of the second cut mark 40, the single-round cut mark row spacing is controlled to be 500 ,the warping of the wafer 100 is not obvious, and the deformation situation of the wafer 100 is alleviated and improved. The distance 250 between the first cut mark 20 and the second cut mark 40 is less than the single-round cut mark row spacing of 500 . The first cut mark 20 and the second cut mark 40 are prone to expand cracks through interaction, reducing the mechanical energy required for crack expansion. Therefore, there is no need to repeatedly cut the wafer 100 with high-power laser. Thus, it is allowed to reduce the power of the laser source and the number of times the laser focus 71 moves along the cut mark.

[0077] In some embodiments, the wafer processing method based on laser stealth further includes:

[0078] Step S: Using the back surface of the wafer 100 as the laser incident surface, making the position of the laser focus 71 fall inside the wafer 100, and controlling the distance between the position of the laser focus 71 and the back surface of the wafer 100 to be between 150 ~250 .

[0079] Referring to Figure 5 , the carbon surface 101 and the silicon surface 103 of the wafer 100 are respectively the two end faces of the wafer 100. The carbon surface 101 is the back surface of the wafer 100 and serves as the laser incident surface. The laser focus 71 acts on the inside of the wafer 100 at the height position shown by the dashed line in Figure 5 , thereby generating a light spot and then a cut mark at the height position shown by the dashed line. The distance from the laser focus 71 to the carbon surface 101 is represented by d, and 150 ≤d≤250 .

[0080] ​In some embodiments, step A is first performed to obtain N first cuts 20 and N - 1 first inter-cut regions 30, and then step C is performed. N is the expected number of first cuts 20 to be obtained. In other words, only after the first round of laser stealth machining is completed and all the required first cuts 20 and first inter-cut regions 30 are obtained, step C is performed to obtain the second cuts 40, rather than performing step C to obtain some second cuts 40 after obtaining some first cuts 20 and then performing step A to obtain the remaining first cuts 20.

[0081] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0082] Those of ordinary skill in the art of this technology should recognize that the above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. As long as appropriate changes and variations are made to the above embodiments within the spirit of the present invention, they fall within the scope of the present invention claimed.

Claims

1. A wafer processing method based on laser stealth, characterized in that, Including: A. Perform the first round of laser stealth machining to obtain a plurality of first cut marks (20) arranged side by side at intervals and a plurality of first inter-mark regions (30) within the wafer (100); C. Perform subsequent laser stealth machining to obtain a plurality of subsequent cut marks arranged side by side at intervals and a plurality of subsequent inter-mark regions within the wafer (100), The subsequent cut marks include a plurality of second cut marks (40) respectively located within a plurality of first inter-mark regions (30), and the subsequent inter-mark regions include a plurality of second inter-mark regions (51) and third inter-mark regions (52). Each second cut mark (40) divides the first inter-mark region (30) into a second inter-mark region (51) and a third inter-mark region (52).

2. The wafer processing method based on laser stealth as claimed in claim 1, wherein Each second cut mark (40) equally divides the first inter-mark region (30), and the second inter-mark region (51) and the third inter-mark region (52) have the same width.

3. The laser stealth-based wafer machining method according to claim 2, wherein Step A includes: A1. Control the laser source to perform a cut mark movement relative to the wafer (100) along the cut mark direction, so that the laser focus (71) translates relative to the wafer (100) along the cut mark direction; A2. Control the laser source to perform a mark movement relative to the wafer (100) along the mark movement direction perpendicular to the cut mark direction and the axial direction of the wafer (100), so that the position of the laser focus (71) translates relative to the wafer (100) along the mark movement direction. The stroke of the mark movement is equal to the single-round cut mark row spacing and equal to the width of the first inter-mark region (30); A3. Repeat steps A1 and A2 several times; The laser stealth-based wafer machining method further includes: B. Control the laser source to perform a misalignment movement relative to the wafer (100) along the misalignment direction perpendicular to the cut mark direction and the axial direction of the wafer (100), so that the position of the laser focus (71) translates relative to the wafer (100) along the mark movement direction. The stroke of the misalignment movement is one-half of the single-round cut mark row spacing; Step C includes: C1. Control the laser source to perform a cut mark movement relative to the wafer (100) along the cut mark direction, so that the laser focus (71) translates relative to the wafer (100) along the cut mark direction; C2. Control the laser source to perform a mark movement relative to the wafer (100) along the mark movement direction perpendicular to the cut mark direction and the axial direction of the wafer (100), so that the position of the laser focus (71) translates relative to the wafer (100) along the mark movement direction. The stroke of the mark movement is equal to the single-round cut mark row spacing and equal to the width of the first inter-mark region (30); C3. Repeat steps C1 and C2 several times.

4. The wafer processing method based on laser stealth as claimed in claim 3, wherein The rate at which the laser source performs a cut mark movement relative to the wafer (100) along the cut mark direction is between 150 mm / s and 250 mm / s.

5. The wafer processing method based on laser stealth as claimed in claim 3, wherein The row spacing of the single-wheel notch is 500 , and the stroke of the offset movement is 250 .

6. The wafer processing method based on laser stealth as claimed in claim 1, wherein, Steps A and C are performed within the entire range of the back surface of the wafer (100); The laser stealth-based wafer machining method further includes: D. Perform compensated laser stealth machining within the low light transmission range (102) on the back surface of the wafer (100) to obtain a plurality of compensated cut marks (60) arranged side by side at intervals within the wafer (100), Among them, multiple compensation notches (60) respectively coincide with multiple subsequent notches within the low light transmission range (102) one by one; alternatively, multiple compensation notches (60) respectively coincide with multiple first notches (20) within the low light transmission range (102) one by one.

7. The wafer processing method based on laser stealth as described in claim 6, wherein The width of the low light transmission range (102) in the length direction of the cutting surface (104) is X1, the diameter of the wafer (100) is X, the width of the highest light transmission range of the wafer (100) is Y, and X1 = X - (2Y ± 10) .

8. The wafer processing method based on laser stealth as described in claim 6, wherein Control the laser source to configure the power P in the whole area 全 Generate laser and perform steps A and C, 40W≤P 全 ≤50W.

9. The wafer processing method based on laser stealth as claimed in claim 8, wherein, Control the laser source to compensate for the configured power P 补 Generate laser light and perform step D, where 30W ≤ P 补 ≤ 40W.

10. The wafer processing method based on laser stealth according to any one of claims 1 to 9, characterized in that, The wafer processing method based on laser stealth further includes: Step S: Use the back surface of the wafer (100) as the laser incident surface, and make the position of the laser focus (71) fall within the wafer (100), and control the distance between the position of the laser focus (71) and the back surface of the wafer (100) to be between 150 ~250 ; and / or first perform step A to obtain N first notches (20) and N - 1 first notch intervals (30), and then perform step C, where N is the expected number of first notches (20) to be obtained.

Images