Electrical grounding resistance detection system for constructional engineering

Abstract

The invention relates to the technical field of resistance measurement, in particular to a constructional engineering electrical grounding resistance detection system which comprises a path monitoring module, a delay judgment module, a path switching module, an interval regulation and control module and a data correction module. According to the method, the voltage stability is judged by collecting the path node voltage change value and the timestamp and calculating the voltage difference, precision screening is completed in cooperation with path state information, the abnormal fluctuation recognition capability is improved, the delay value change trend is combined with a period difference value comparison mode, and path stability evaluation is assisted; the path switching behavior is combined with feedback response and relay state recognition, the accuracy of channel switching is improved, the sampling interval is dynamically regulated and controlled according to delay change, clearer response characteristics are obtained in combination with waveform displacement mapping operation, the accuracy of data alignment is enhanced, and the accuracy of channel switching is improved. The whole process realizes a closed-loop processing structure of path identification, delay judgment, switching confirmation and waveform correction, and effectively improves the response consistency and time precision of ground resistance measurement.

Description

Technical Field

[0001] The present invention relates to the technical field of resistance measurement, and particularly to an electrical grounding resistance detection system for building engineering. Background Art

[0002] The technical field of resistance measurement involves the determination of the voltage generated when current passes through a conductor, and related technologies for calculating its resistance value through Ohm's law. The core content of this technical field lies in high-precision and fast-response resistance detection means and their implementation methods in various application scenarios, especially in practical applications such as power systems, safety detection, and equipment performance evaluation. Resistance measurement not only covers simple single-point measurement methods but also involves multi-point monitoring, on-line testing, environmental interference suppression, and automatic calibration mechanisms, forming a complete set of detection theories and practical systems. The technological development in this field continuously promotes the improvement of measurement accuracy, anti-interference ability, and automation level, and is widely used in aspects such as the safety performance evaluation of electrical equipment, the health status monitoring of power lines, and the quality inspection of electronic components.

[0003] Among them, an electrical grounding resistance detection system for building engineering refers to a complete set of systems used to measure the resistance value between the grounding system of a building's electrical system and the earth. The main theme of this patent focuses on the effective acquisition of the resistance value of the grounding system in building construction sites or existing buildings, covering detection methods centered on the layout of measurement electrodes, current injection methods, and voltage acquisition circuits. This system usually applies an alternating current between the grounding body to be measured and the auxiliary electrode, and records the voltage value through a specific measurement path, and then calculates the grounding resistance value using Ohm's law. The involved content also includes data recording circuits, environmental parameter correction structures, and high-impedance voltage acquisition technologies used in the test, ensuring the completion of resistance measurement operations under complex grounding structures and on-site interference conditions.

[0004] The prior art only relies on static voltage sampling in path voltage state recognition, lacking real-time analysis of voltage fluctuation trends and making it difficult to distinguish short-term interference from continuous anomalies. In path signal delay processing, a periodic delay comparison mechanism is not established, resulting in the inability to timely identify unstable signal transmission problems. During the path switching process, it relies on preset judgments and lacks confirmation of feedback information after switching, increasing the risk of incorrect power supply selection. In the waveform sampling strategy, the sampling interval is not adjusted according to the path characteristics, resulting in inaccurate timing of waveform response data and affecting the effectiveness of resistance calculation and data calibration accuracy. Summary of the Invention

[0005] The purpose of the present invention is to solve the deficiencies existing in the prior art, and to propose an electrical grounding resistance detection system for building engineering.

[0006] To achieve the above purpose, the present invention adopts the following technical solution: An electrical grounding resistance detection system for building engineering includes: The path monitoring module obtains the voltage change value of the power supply path node and the sampling timestamp, calculates the adjacent voltage difference, compares the voltage difference with the stability threshold, determines whether the current path is in an unstable voltage state, records the path identifier and status, and generates a path stability status value; The delay determination module, based on the path stability status value, collects the input and output timestamps, calculates the difference between the two timestamps as the path signal delay value, compares whether the difference between the delay values in two adjacent periods exceeds the set signal delay tolerance value, and generates a path delay anomaly flag value; The path switching module, according to the path stability status value and the path delay anomaly flag value, filters the stable path, generates a power supply switching instruction, collects the switching feedback, records the relay response, and generates a power supply channel switching confirmation value; The interval regulation module calls the power supply channel switching confirmation value, collects the current and pre-switching delay values, calculates the delay difference, compares the difference with the sampling reference value, adjusts the sampling interval, selects the data of the grounding conduction loop detection current monitoring terminal in the distribution switch control device, extracts the node response and the returned waveform, calculates the waveform displacement mapping, and generates a resistance detection waveform offset amount.

[0007] As a further solution of the present invention, the path stability status value includes path identifier information, voltage stability category, and voltage fluctuation amplitude. The path delay anomaly flag value is specifically the delay change amplitude, cycle change identifier, and anomaly determination label. The power supply channel switching confirmation value includes relay response characteristics, switching execution feedback, and channel identification code. The resistance detection waveform offset amount is specifically the waveform response time difference, node mapping characteristics, and waveform shape change.

[0008] As a further solution of the present invention, the path monitoring module includes: The voltage acquisition sub-module obtains the voltage change value of the power supply path node and the corresponding sampling timestamp, records the multi-node numbers and their sampling sequences, establishes the voltage time series data of the sampling nodes, and generates a path voltage sampling sequence value; The path voltage difference generation sub-module, based on the path voltage sampling sequence value, performs a difference operation on the node voltage values at adjacent sampling time points, records the voltage change difference of each group of adjacent time points, and generates a path voltage difference sequence; The stability determination sub-module calls the path voltage difference sequence, compares the absolute values of the multi-voltage differences with the stability threshold, counts the number of differences exceeding the threshold, and calculates the unstable ratio value in combination with the total number of node samplings. Using the formula: ; Performs an operation to obtain the path instability status value, assigns a path stability identifier, and generates a path stability status value; Wherein, Represents the path stability status value, Represents the number of pairs of sampling nodes, Represents the difference in adjacent voltages of the i-th group, Represents the number of times the voltage difference exceeds the stability threshold, Represents the sampling time interval of the i-th group, Represents the initial sampling time point.

[0009] As a further solution of the present invention, the delay determination module includes: The timestamp acquisition sub-module acquires the path stability status value, obtains the input timestamp and output timestamp of the node, distinguishes and records the node positions of the two types of acquired timestamps, and generates a path timestamp data set; The path delay calculation sub-module, based on the path timestamp data set, calls the input timestamp and output timestamp of adjacent nodes, calculates the time difference between the output timestamp and the input timestamp as the signal transmission delay value, and uses the formula: ; Performs operations to obtain the transmission delay value under each path, and establishes a path delay change sequence; Among them, Represents the delay value of path a in period q, Represents the output timestamp of path a in period q, Represents the input timestamp of path a in period q, Represents the path status value under period q, Represents the hop length of path a under period q, Represents the forwarding blocking ratio of the k-th hop in the path sequence, and n is the total number of hops of the path; The abnormal marking generation sub-module calls the path delay change sequence, calculates the difference based on the delay values of the same path in two adjacent periods and compares it with the signal time delay tolerance value. If it exceeds the tolerance value, it is determined as abnormal, obtains the abnormal period and path index, and generates a path delay abnormal marking value.

[0010] As a further solution of the present invention, the path switching module includes: The path stability evaluation sub-module establishes a corresponding relationship based on the time series change data of the path stability status value and the path number, judges the state persistence of the path stability status value within the sliding time window, compares it with the set stability threshold, filters the path numbers whose stability status values meet the threshold, and generates a path stability screening value; The delay anomaly path screening sub-module calls the path stability screening value and the path delay anomaly marking value, reads and classifies the path delay anomaly marking value path by path, identifies the paths with the marking value in the normal state, and performs an intersection process with the path stability screening value. Using the formula: ; Calculate the path optimal adaptability through operation, use the path number with the maximum adaptability as the current selectable path, and generate a stable and available path number value; Among them, represents the stability state value of the c-th path, represents the transmission delay value of the c-th path, represents the average value of the path delay marker distribution, represents the available duration of the path in the current cycle, represents the path data transmission speed, represents the number of times of path anomaly triggering, represents the path optimal adaptability; The power supply channel verification sub-module issues a power supply switching command and collects a switching feedback value based on the stable and available path number value and the power supply switching instruction content, records and compares the relay response state through the feedback value, judges the matching degree of the relay response and the stability degree of the feedback value, and generates a power supply channel switching confirmation value.

[0011] As a further solution of the present invention, the interval regulation module includes: The delay difference extraction sub-module calls the power supply channel switching confirmation value, collects the current delay value and the delay value before switching, calculates the difference between the current delay value and the delay value before switching, compares the relative difference between the difference and the set sampling reference value, and obtains a delay comparison deviation value; The sampling interval adjustment sub-module calls the delay comparison deviation value and compares it with the set sampling interval range threshold, and judges whether the deviation excess amount exceeds the sampling interval adjustment threshold. If the deviation exceeds, the current sampling period is corrected by adjusting the sampling interval control parameter, and the corrected sampling time interval parameter is obtained; The current waveform mapping sub-module selects the data of the grounding conduction loop detection current monitoring terminal in the distribution switch control device according to the corrected sampling time interval parameter, extracts the node response data and the returned current waveform sequence, calculates the displacement mapping difference between the two waveform sequences, using the formula: ; Calculate the waveform mapping residual amount, and compare it with the set determination threshold to obtain the resistance detection waveform offset amount; Among them, represents the returned current waveform data of the n-th sampling point, represents the The node response waveform data of representing the standard deviation of the returned waveform data, representing the standard deviation of the response waveform data, representing the total number of sampling points, representing the waveform mapping residual.

[0012] As a further solution of the present invention, the system further includes: Based on the resistance detection waveform offset, the data correction module performs a difference comparison with the time points in the device standard timing table, calculates the time offset value, and through the time axis rearrangement operation in the buffer area, calls the load change amplitude value and the current cycle waveform offset value in the grounding electrode structure of the distribution switch control device for unified calibration to obtain the grounding resistance detection offset correction value; The grounding resistance detection offset correction value includes a calibrated time axis, a load amplitude matching value, and a correction coefficient distribution.

[0013] As a further solution of the present invention, the data correction module includes: Based on the resistance detection waveform offset, the multi-peak waveform delay extraction sub-module obtains the waveform time point sequence and the reference start time node value within the current detection cycle, judges the time delay amplitude of the multi-peak points in the waveform sequence relative to the reference time point, calculates the offset time interval value of the multi-waveform points, and obtains the waveform delay interval value; The timing comparison sub-module calls the waveform delay interval value, and according to the calibrated time point value set in the device standard timing table, uses the formula: ; Calculates the standard offset under multiple cycles, combines it with the offset trend value of the previous cycle, and generates a unified calibration offset value; Wherein, represents the standard deviation of the calibration offset within the k-th cycle, represents the time delay of the d-th waveform in the k-th cycle, represents the reference time point of the d-th waveform, represents the total number of measurement points within the cycle, is the average time offset within the measurement cycle, represents the frequency modulation coefficient of the k-th cycle, is the frequency modulation reference constant, is the additional adjustment parameter within the k-th cycle; The time axis rearrangement sub-module calls the unified calibration offset value, rearranges the time axis of the current cycle waveform in the buffer, obtains the current load change amplitude value of the distribution switch control device, synchronously analyzes the load change amplitude value with the time series corresponding to the rearranged waveform time axis, integrates the difference value interval, and uniformly updates the time reference sequence to generate a grounding resistance detection offset correction value.

[0014] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In the present invention, by collecting the voltage change value and timestamp of the path node, calculating the voltage difference to judge the voltage stability, and cooperating with the path state information to complete the accuracy screening, the abnormal fluctuation recognition ability is improved. The change trend of the delay value is combined with the cycle difference comparison method to assist the path stability evaluation. The path switching behavior is combined with the feedback response and relay state recognition to improve the accuracy of channel switching. The sampling interval is dynamically adjusted according to the delay change, and the waveform displacement mapping operation is combined to obtain a clearer response feature, enhancing the accuracy of data alignment. The overall process realizes a closed-loop processing structure of path recognition, delay judgment, switching confirmation, and waveform correction, effectively improving the response consistency and time accuracy of grounding resistance measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is the system flow chart of the present invention; Figure 2 is the acquisition step flow chart of the path monitoring module of the present invention; Figure 3 is the acquisition step flow chart of the delay determination module of the present invention; Figure 4 is the acquisition step flow chart of the path switching module of the present invention; Figure 5 is the acquisition step flow chart of the interval regulation module of the present invention; Figure 6 is the acquisition step flow chart of the data correction module of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the system or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, in the description of the present invention, the meaning of "a plurality of" is two or more, unless otherwise specifically defined.

[0018] Embodiment 1. Please refer to Figure 1 , a building engineering electrical grounding resistance detection system includes:

[0019] The path monitoring module obtains the voltage change value of the power supply path node and the sampling timestamp, calculates the adjacent voltage difference, compares the voltage difference with the stability threshold, determines whether the current path is in an unstable voltage state, records the path identifier and status, and generates a path stability status value; The delay determination module, based on the path stability status value, collects the input and output timestamps, calculates the difference between the two timestamps as the path signal delay value, compares whether the difference between the delay values in two adjacent cycles exceeds the set signal time delay tolerance value, and generates a path delay anomaly flag value; The path switching module, according to the path stability status value and the path delay anomaly flag value, filters the stable path, generates a power supply switching instruction, collects the switching feedback, records the relay response, and generates a power supply channel switching confirmation value; The interval regulation module calls the power supply channel switching confirmation value, collects the current and pre-switching delay values, calculates the delay difference, compares the difference with the sampling reference value, adjusts the sampling interval, selects the data of the grounding conduction loop detection current monitoring terminal in the distribution switch control device, extracts the node response and the returned waveform, calculates the waveform displacement mapping, and generates a resistance detection waveform offset value; The data correction module, based on the resistance detection waveform offset value, performs a difference comparison with the time points in the device standard timing table, calculates the time offset value, and then through the time axis rearrangement operation in the buffer area, uniformly calibrates the load change amplitude value and the current cycle waveform offset value in the grounding electrode structure of the distribution switch control device to obtain a grounding resistance detection offset correction value.

[0020] The path stability status value includes path identification information, voltage stability category, and voltage fluctuation amplitude. The path delay anomaly marker value is specifically the delay change amplitude, cycle change identification, and anomaly determination label. The power supply channel switching confirmation value includes relay response characteristics, switching execution feedback, and channel identification code. The resistance detection waveform offset amount is specifically the waveform response time difference, node mapping characteristics, and waveform morphology change. The ground resistance detection offset correction value includes calibration time axis, load amplitude matching value, and correction coefficient distribution.

[0021] Please refer to Figure 2 , the path monitoring module includes: The voltage acquisition sub-module obtains the voltage change value of the power supply path node and the corresponding sampling timestamp, records the multi-node numbers and their sampling sequences, establishes the voltage time series data of the sampling nodes, and generates the path voltage sampling sequence value; First, perform voltage sampling actions on multiple nodes on the path one by one to monitor the voltage status of each node at a certain moment and record the voltage values of the nodes and the corresponding sampling moments, generating node voltage time series data. The specific operation is as follows: taking 3 nodes (node numbers are A1, A2, and A3 in sequence) on a typical path as an example, perform voltage sampling actions on the 3 nodes in sequence and generate sequence data. For example, at the initial time point t? = 0s, the voltages sampled by nodes A1, A2, and A3 are 220V, 218V, and 219V respectively. At the next sampling time point t? = 5s, the sampling voltages of nodes A1, A2, and A3 are 219V, 216V, and 217V respectively. At the subsequent time point t? = 10s, the node voltages are 217V, 214V, and 215V respectively. Record the above node voltage data and timestamps to form the path voltage sampling sequence value.

[0022] The path voltage difference generation sub-module performs difference operations on the node voltage values at adjacent sampling time points based on the path voltage sampling sequence value, records the voltage change differences of each group of adjacent time points, and generates the path voltage difference sequence; By calling the path voltage sampling sequence data, the voltage data of each node at adjacent sampling time points is subjected to a difference operation one by one. The specific steps are as follows: Taking node A1 as an example, the voltage difference is calculated using the voltage sampling values of two adjacent times. For example, the voltage difference between 220V at time t0 and 219V at time t1 of node A1 is calculated, that is, ΔV1 = 219V - 220V = -1V; then the difference between 217V at time t2 and 219V at time t1 is calculated, ΔV2 = 217V - 219V = -2V; and so on. The ΔV2 of node A2 is calculated as 216V - 218V = -2V, ΔV2 = 214V - 216V = -2V, and the ΔV1 of node A3 is 217V - 219V = -2V, ΔV2 = 215V - 217V = -2V. Thus, the voltage change differences of each group of adjacent time point nodes are recorded, and the path voltage difference sequence [-1V, -2V, -2V, -2V, -2V, -2V] is obtained.

[0023] The stability determination sub-module calls the path voltage difference sequence, compares the absolute values of multiple voltage differences with the stability threshold, counts the number of differences exceeding the threshold, and calculates the instability ratio value in combination with the total number of node samplings. The formula is as follows: ; The operation obtains the path instability status value, assigns a path stability identifier, and generates the path stability status value; Among them, represents the path stability status value, represents the number of pairs of sampling nodes, represents the i-th group of adjacent voltage differences, represents the number of times the voltage difference exceeds the stability threshold, represents the i-th group of sampling time intervals, represents the initial sampling time point.

[0024] First, call the path voltage difference sequence, and compare the absolute values of the difference data in the sequence with the stability threshold one by one. The determination method of the stability threshold is specifically combined with the allowable voltage fluctuation reference range of the path (for example, set to ±1.5V). If it exceeds ±1.5V, it is considered that the voltage change is unstable. For example, in the above sequence difference [-1V, -2V, -2V, -2V, -2V, -2V], the number of times EX that the absolute value exceeds the stability threshold (1.5V) is 5 times; then, according to the total number of node samplings, determine the number of pairs of sampling nodes SN. In this example, a total of 3 nodes are sampled, with 2 sampling time intervals, so the number of node pairs is SN = 6 (3 nodes × 2 time intervals); further call the sampling time interval ST. Taking ST1 and ST2 both being 5s in this example as an example, introduce the initial sampling moment = 0s, and by calling the path stability status value formula: ; In the formula, is the path stability status value, is the number of pairs of sampling nodes, is the voltage difference between nodes, is the number of times the difference exceeds the threshold (there are 5 times in total above), is the sampling interval (the value is 5s), is the initial sampling time 0s, and substitute the above data for calculation in turn: Take the difference of node A1 as an example for detailed calculation: ; Calculate the PS values of nodes A2 and A3 in a similar way as: ; Then accumulate the PS values of each node to obtain the total path stability status value: ; Compare the path stability status value 0.2582 with the preset instability reference value range (stable for 0 - 0.2, unstable for above 0.2). Since the obtained result 0.2582 is greater than 0.2, it indicates that the path status belongs to the unstable state, and further mark the stability status of this path as "unstable".

[0025] Table 1 Data table of path node voltages and differences Table 1 Data table of path node voltages and differences , As shown in Table 1, the voltage values of path nodes A1, A2, and A3 at each sampling moment, as well as the specific values of the difference ΔV calculated between adjacent moments, are used for the above calculation of the path stability status.

[0026] Please refer to Figure 3 , the delay determination module includes: The timestamp acquisition sub - module acquires the path stability status value, obtains the input timestamp and output timestamp of the node, differentiates and marks the two types of acquired timestamps and records the node positions, generating a path timestamp data set; First, the acquisition module accesses each node in real - time, records the time when the current data packet is received as the input timestamp TI by calling the built - in system clock of the node a,x , and at the same time records the corresponding time as the output timestamp TO when the data packet leaves the node a,x , where the nodes can be numbered starting from 0 and incremented sequentially until the end of the path. Taking path a as an example, its nodes are numbered Node0, Node1, Node2... Node k, the acquisition module records the TI and TO of each node respectively, and generates timestamp entries with the path number and node serial number to facilitate subsequent differentiation; when recording the timestamp, the module also calls the path stability status value PS x , this status value is provided by the network topology monitoring module, which is generated by weighted aggregation of multiple parameters such as the frequency of rerouting events and the duration of path stability on the path within each period. For standardization, this value can be set as a floating-point value between 0 and 1 through a scoring mechanism. The closer it is to 1, the more stable the path state; combining the timestamp information collected for each path, a path timestamp dataset is finally generated. Each data entry should include the path number a, the period number q, the node number, TI a,x , TO a,x and PS x and other parameters to form a structured dataset for subsequent calculation module calls. Assume that path a passes through 3 nodes in period 1, and its timestamp information is as follows: Table 2 Path Timestamp Dataset (Example) , As shown in Table 2, the input and output timestamps of each node in path a in period 1 have been collected, and the status value PS x is uniformly 0.82, and subsequent delay calculation operations will be performed based on this.

[0027] Based on the path timestamp dataset, the path delay calculation sub-module calls the input timestamp and output timestamp of adjacent nodes, calculates the time difference between the output timestamp and the input timestamp as the signal transmission delay value, using the formula: ; Calculate the transmission delay value for each path through operation and establish a path delay change sequence; Among them, represents the delay value of path i in period j, represents the output timestamp of path a in period q, represents the input timestamp of path a in period q, represents the path status value in period q, represents the hop length of path a in period q, represents the forwarding blocking ratio of the k-th hop in the path sequence, is the total number of hops of the path; It is necessary to aggregate the TI and TO data of all nodes according to the path number and period number, and extract each group of input and output timestamps in adjacent nodes. For example, in path a, the TO a,x of node Node0 and the TI a,xThat is, a set of time data corresponding to a period. To calculate the delay value, a time difference operation needs to be performed based on this period of data, that is, subtracting the input time of the next node from the output time to obtain the basic time delay ΔT of the transmission segment. x = TO a,x - TI a,x , and then combined with the path status value PS x and the square root of the product of the hop count length HC a,x of this path as the adjustment term. The hop count length HC is directly read from the path topology structure, reflecting the number of hops between nodes. Suppose path a has a total of 3 hops in cycle 1, then HC a,x = 3; In addition, the forwarding blocking ratio FBR u needs to record the network congestion situation at each hop node. The setting range is from 0 to 1. Less than 0.3 is regarded as low blockage, 0.3 to 0.7 is medium blockage, and greater than 0.7 is high blockage. The network congestion monitoring module is used to regularly read the ratio of the router cache queue length to the processing rate for conversion. After each hop node independently obtains the FBR value, they are summed up to summarize the blocking effect; Taking path a as an example, assume the following parameter values: TO a,x = 101.02 ms; TI a,x = 100.00 ms; PS x = 0.82; HC a,x = 3; FBR1 = 0.25, FBR2 = 0.60, FBR3 = 0.40; Substitute into the formula: ; First step, calculate the time difference term: ; Second step, take the square root of the product of the status value and the hop count: ; Third step, sum the forwarding blocking ratios: ; Fourth step, substitute into the formula: ; This result shows that the overall signal transmission delay of path a in cycle 1 is 1.15 ms. Subsequently, the DL a,x values of each path in all cycles will be recorded in sequence to form a path delay change sequence for detecting network abnormal fluctuations.

[0028] The abnormal mark generation sub-module calls the path delay change sequence, calculates the difference based on the delay values of the same path in two adjacent cycles, and compares it with the signal time delay tolerance value. If it exceeds the tolerance value, it is determined as abnormal, obtains the abnormal cycle and path index, and generates a path delay abnormal mark value.

[0029] For example, the delay values of path a in cycle 1 and cycle 2 are DL a,1 and DL a,2 , calculate their difference ΔDL = |DL a,2 -DL a,1 |. This difference needs to be compared with the delay tolerance value T_tol. The tolerance value is set according to the maximum time delay fluctuation allowed by the network, usually set as the maximum delay floating ratio under the maximum bandwidth occupancy. For example, if the maximum tolerance allowed by the network is 15%, and the average path delay is 1ms, then = 1 * 0.15 = 0.15ms; taking path a as an example, if the delay in cycle 1 is 1.15ms and the delay in cycle 2 rises to 1.38ms, then: ; Since the difference exceeds the set tolerance threshold, the system determines that path a has an abnormal fluctuation in cycle 2, records the abnormal path index a and cycle number 2, generates an abnormal mark (which can be set as a binary value 1 representing abnormal and 0 representing normal), and adds a delay abnormal event to the recording module, which can be used as a basis for adjusting the network scheduling strategy later. This judgment process marks all abnormal cycle and path combinations by traversing the path delay change sequence and comparing the difference with the tolerance item by item, and finally forms a set of delay abnormal mark values.

[0030] Please refer to Figure 4 , the path switching module includes: The path stability evaluation sub-module establishes a corresponding relationship between the time series change data of the path stability state value and the path number, judges the state persistence of the path stability state value within a sliding time window, and compares it with the set stability threshold, filters the path numbers whose stability state values meet the threshold, and generates a path stability screening value; First, perform number mapping processing on all path numbers in the system, set the number list such as paths P1 to Pn, and record the stability status values of each path according to the time series to form a stability data sequence set. In the example, it is assumed that data for path P1 is collected every 5 seconds, and a total of 10 times are collected. The obtained stability status values are [0.85, 0.87, 0.86, 0.83, 0.88, 0.86, 0.89, 0.84, 0.85, 0.86]. Associate this value sequence with path P1. By traversing the stability time series of each path, calculate its state persistence within the set sliding time window W. Let W be 3 time nodes, that is, perform volatility analysis on each group of adjacent 3 values. During the execution process, call the difference between the maximum and minimum values within the sliding window to determine whether it exceeds the preset stability threshold. If the stability threshold is set to 0.06, then the difference in the sliding window [0.85, 0.87, 0.86] for P1 is 0.02, meeting the stability requirements, and continue to analyze the next window. If it is found that the maximum-minimum difference in a certain window such as [0.89, 0.84, 0.85] is 0.05, it is still considered to meet the requirements. If a certain window exceeds 0.06, it is considered that the path is unstable during this time period. By traversing, count the proportion of windows that meet the stability requirements for each path. If the proportion is greater than 80%, the path is stable. Screen out all path numbers that meet the proportion as the path stability screening result value to form a path stability screening value set; combined with the specific path situation, Table 1 lists the path numbers, sampling data, and stability screening judgment results within the monitoring period of a certain system.

[0031] Table 3 Path Stability Status Judgment Table , As shown in Table 3, by comparing the maximum value of the sliding window difference with the stability threshold, calculate the stability ratio of each path to determine whether the screening standard is met; The delayed abnormal path screening sub-module calls the path stability screening value and the path delay abnormal marking value, reads and classifies the path delay abnormal marking value path by path, identifies the paths with the marking value in the normal state, and performs an intersection process with the path stability screening value. Use the formula: ; Calculate the path optimal adaptability through the operation, and use the path number with the maximum adaptability as the current selectable path to generate a stable and available path number value; Among them, represents the stability status value of the c-th path, represents the transmission delay value of the c-th path, represents the average value of the delay marking distribution of the c-th path, represents the available duration of the path in the current cycle, represents the path data transmission speed, Indicates the number of times of path anomaly trigger, Indicates the path optimization adaptation degree; During the execution process, the delayed anomaly marking value matrix is called first. The delayed anomaly marking values of each path are stored by period. The marking value is set to 0 for normal and 1 for anomaly. For example, the delay marking value of path P1 is [0, 0, 0, 1, 0, 0, 0, 0, 0, 0], where an anomaly occurs in the 4th period. By counting the number of occurrences of anomaly values and combining whether they occur continuously, it is identified whether the path can be considered a normal path in the current period. The anomaly trigger allowable threshold is set to 10% of the period, that is, 10 samples are taken in one period and the number of anomalies shall not exceed 1. Then P1 meets the screening criteria and is judged as a path with normal delay status. After that, the intersection calculation is performed between the path number and the aforementioned stability screening value to screen out the path numbers that meet both types of screening conditions, and finally participate in the adaptation degree calculation. In the adaptation degree calculation, the given formula is used: ; The explanations of each parameter are as follows: is the stability status value of path c, and the numerical source is the aforementioned stability sequence mean value; is the actual average transmission delay value of path c (unit: ms), which is obtained by measuring the actual transmitted data packets. For example, the round-trip time mean value is taken for 10 data packets in each period; is the mean value of the path delay marking distribution, which is obtained by averaging the anomaly marking value array. For example, the mean value in [0, 0, 0, 1, 0, 0, 0, 0, 0, 0] is 0.1; is the available duration of path r in the current period, unit: s, which can be obtained by the difference between the system running time and the anomaly time; is the average transmission rate of path r, unit: Mbps, which is calculated by data volume / time consumption; is the number of times of path r anomaly trigger, which is obtained by counting the periods with delay marking of 1. Now, taking path P1 as an example to calculate its adaptation degree, let: , , , , , ; Then: ; ; ; The result shows that the path preference adaptation degree of path P1 in the current period is 0.0077. By calculating the adaptation degree results of all candidate paths and comparing them, the path number with the largest adaptation degree value is selected as the current optional path number, and a stable and available path number value is generated.

[0032] Based on the stable and available path number value and the power supply switching instruction content, the power supply channel verification sub-module issues a power supply switching instruction and collects the switching feedback value. By comparing and recording the relay response status with the feedback value, it judges the matching degree of the relay response and the stability degree of the feedback value, and generates a power supply channel switching confirmation value.

[0033] During the execution process, first, a switching control command is transmitted to the target power supply control node. The command content is to select the path number and perform a power supply redirection operation. The sending time and response time of the control node are recorded. After collecting the feedback value, the relay response status is recorded. The response status value is set to two levels, high level or low level. The current closed state of the relay is obtained through the electrical signal detection module and compared with the previous state. The continuous stable time period after switching is recorded. By statistically analyzing the volatility of the feedback value, it is judged whether the power supply channel reaches the set stability standard. In the example, it is set that the change of the feedback state shall not exceed ±5% of the time period. If there are only 2 level flips within 100 seconds of operation and the volatility is 2%, which meets the set standard, finally, a power supply channel switching confirmation value is output.

[0034] Please refer to Figure 5 , the interval regulation module includes: The delay difference extraction sub-module calls the power supply channel switching confirmation value, collects the current delay value and the delay value before switching, calculates the difference between the current delay value and the delay value before switching, and compares the relative difference between the difference and the set sampling reference value to obtain a delay comparison deviation value; First, the current delay value and the delay value before switching are extracted from the internal storage unit of the distribution switchgear. For example, the current delay value obtained by real-time collection through the high-precision timer in the device is 150 milliseconds, while the delay value before switching is extracted from the historical data storage unit, and the value is 142 milliseconds. Then, the difference between the two delay values is calculated, that is . Then, based on the set sampling reference value (for example, the sampling reference value is set to 145 milliseconds, and this value is determined by the historical operation average value), the relative difference is further calculated. The relative difference is calculated through the formula . Then, the relative difference is called to compare with the set reference deviation threshold (for example, the threshold is 0.05, which is determined based on the historical operation error statistics), and the numerical comparison between the relative difference and the reference deviation threshold is performed to obtain a delay comparison deviation value of 0.055, indicating that it exceeds the reference threshold of 0.05.

[0035] The sampling interval adjustment sub-module calls the delay comparison deviation value and compares it with the set sampling interval range threshold, and judges whether the deviation excess amount exceeds the sampling interval adjustment threshold. If the deviation exceeds, the current sampling period is corrected by adjusting the sampling interval control parameter to obtain the corrected sampling time interval parameter; Call the obtained delay comparison deviation value of 0.055, and then call the pre-stored sampling interval range threshold (for example, the range threshold setting interval is [0.03, 0.06], determined according to historical fluctuation statistics), and perform an interval comparison on the delay comparison deviation value to judge whether the current deviation value exceeds the threshold range; further calculate the deviation excess amount, that is, the difference between the deviation value of 0.055 and the interval maximum value of 0.06 is 0.005. Compare this value with the pre-stored sampling interval adjustment threshold (for example, the threshold is set to 0.004, determined by operation fluctuation experience), and find that 0.005 is greater than 0.004, so it is determined that the deviation exceeds the threshold range, and call the sampling interval control parameter (such as the initial sampling period is 100ms) to correct the current sampling period. For example, adjust it to a new sampling period through the formula: Finally, the corrected sampling time interval parameter is obtained as 100.5 milliseconds.

[0036] The current waveform mapping sub-module selects the data of the grounding conduction loop detection current monitoring terminal in the distribution switch control device according to the corrected sampling time interval parameter, extracts the node response data and the returned current waveform sequence, and performs a displacement mapping difference calculation on the two waveform sequences, using the formula: ; Calculate the waveform mapping residual amount, and compare it with the set judgment threshold to obtain the resistance detection waveform offset amount; Among them, represents the th returned current waveform data of the sampling point, represents the th node response waveform data of the sampling point, represents the standard deviation of the returned waveform data, represents the standard deviation of the response waveform data, represents the total number of sampling points, represents the waveform mapping residual amount.

[0037] Call the corrected sampling time interval parameter (100.5 milliseconds) obtained in the previous step, and extract the real-time data of the grounding conduction loop detection current monitoring terminal from the distribution switch control device according to this parameter. Taking specific numerical data as an example, in a certain data acquisition, the returned current waveform data and the node response waveform data are respectively collected, and the example is shown in Table 4: Table 4 Current Waveform Data Acquisition Table

[0038] As shown in Table 4, the sampled data is then called one by one for differential displacement mapping, using the following formula: ; The specific parameter descriptions are as follows: : Returns the current waveform data, specifically taking the value of the c-th sampling point in Table 1. For example, the data of the first sampling point is 15.4 mA; : Node response waveform data, specifically taking the value of the c-th sampling point in Table 1. For example, the data of the first sampling point is 14.9 mA; : Total number of sampling points, determined according to Table 1, taking 5; : Returns the standard deviation of the current waveform. The calculation process is to first calculate the mean value of the waveform data as , and then further calculate the standard deviation ; : Standard deviation of the node response waveform, calculating the mean value , and then calculating the standard deviation .

[0039] Further substitute the data for calculation: ; The waveform mapping residual is obtained as 0.067. Then, this value is compared with the set determination threshold (for example, the threshold is set to 0.06, determined by the statistical difference of the device's historical waveforms). It is found that 0.067 exceeds the determination threshold of 0.06, so the resistance detection waveform offset is 0.067, indicating that the waveform has shifted and exceeds the set range.

[0040] The advantage of the formula is that by introducing the cubic term of the waveform difference, the sensitivity to abnormal points is enhanced, the mapping range of small waveform differences is effectively expanded, and the accuracy of abnormal waveform determination is significantly improved.

[0041] This result indicates that the waveform mapping residual of 0.067 exceeds the set determination threshold of 0.06, confirming that the current waveform is in an offset state, and the resistance detection waveform offset is 0.067.

[0042] Please refer to Figure 6 , the data correction module includes: The multi-peak waveform delay extraction sub-module obtains the waveform time point sequence and the reference starting time node value within the current detection period based on the resistance detection waveform offset, determines the time delay amplitude of the multi-peak points in the waveform sequence relative to the reference time point, calculates the offset time interval value of the multi-waveform points, and obtains the waveform delay interval value; First, it is necessary to collect the waveform data sequence within each detection period. The sampling frequency is set to 10 kHz, and the recording time length is 100 ms. Therefore, each detection period contains 1000 sampling points. On this basis, the system extracts the time point sequence corresponding to the sampling signal in the current detection period according to the initial value of the waveform offset feedback by the resistance detection module, sets the reference starting time node value to 0 ms, and then calculates the time difference relative to the reference time point point by point by traversing the waveform time point sequence, and identifies the position of the local maximum point. The identification criterion uses the five-point moving average method in cooperation with the critical difference determination. If a certain point is greater than its two adjacent points before and after, and the amplitude difference from the adjacent points is greater than 2.5 mV, it is determined as a local peak point. After identifying more than one peak in the current period, the system sequentially calls the relative time points of these peak points and the starting time for subtraction operations to obtain the time delay values of each peak point. Taking four peak points identified in a certain period as an example, they are located at sampling point numbers 150, 320, 530, and 710 respectively, corresponding to time points of 15 ms, 32 ms, 53 ms, and 71 ms. Then, the peak time delay sequence of this period can be calculated as [15, 32, 53, 71] ms; subsequently, the system calculates the pairwise differences of this delay sequence, extracts the difference between the maximum and minimum values, and calculates the offset time interval value. In this example, the offset time interval is 71 ms - 15 ms = 56 ms; if it is necessary to determine whether this offset time belongs to "significant delay", the judgment interval can be set as: offset time < 20 ms is normal, 20 ms ≤ offset time ≤ 50 ms is medium offset, and offset time > 50 ms is significant offset. Therefore, this period is identified as a significant offset period, and the waveform delay interval value is 56 ms.

[0043] The timing comparison sub-module calls the waveform delay interval value and calculates the standard offset under multiple cycles according to the calibrated time point value set in the device standard timing table using the formula: ; Combines it with the offset trend value of the previous cycle to generate a unified calibration offset value; Among them, represents the standard deviation of the calibration offset in the k-th cycle, represents the time delay of the d-th waveform in the k-th cycle, represents the reference time point of the d-th waveform, represents the total number of measurement points in the cycle, is the average time offset within the measurement cycle, represents the frequency modulation coefficient in the k-th period, is the frequency modulation reference constant, is the additional adjustment parameter within the k-th period; First, call the calibrated reference time point sequence RT from the device standard timing table, set the RT value to [10, 30, 50, 70] ms, perform a one-to-one difference calculation with the delay sequence [15, 32, 53, 71] ms identified in the detection period, and obtain the difference array as [5, 2, 3, 1] ms. Calculate the average offset μ as: (5 + 2 + 3 + 1) / 4 = 2.75 ms. Then subtract μ from each difference, square it, and sum: (5 - 2.75)² + (2 - 2.75)² + (3 - 2.75)² + (1 - 2.75)² = 5.06 + 0.56 + 0.06 + 3.06 = 8.74 ms²; the number of measurement points MP within the period is 4, and the standard deviation part is √(8.74 / 4) = 1.48 ms. Assume that the frequency modulation coefficient Fk in this period is 12 Hz, the frequency modulation reference constant FC is 50 Hz, and the additional adjustment parameter Ak is 3, and substitute them into the formula ; Then the standard offset SDk in this period is 1.706 ms; combined with the offset trend value of the previous period, if the SD value in the previous period is 1.45 ms, the system calculates the weighted average of the two values, sets the weight of the current period to 0.6, and the previous period to 0.4. The unified calibrated offset value SDu = 0.6 × 1.706 + 0.4 × 1.45 = 1.624 ms; the benefit of the formula is that by combining the instantaneous offset with the historical offset trend in proportion, the offset calibration of the current period is more continuous and stable.

[0044] The time axis rearrangement sub-module calls the unified calibrated offset value, rearranges the time axis of the current period waveform in the buffer area, obtains the current load change amplitude value of the distribution switch control device, synchronously analyzes the load change amplitude value with the time series corresponding to the rearranged time axis of the waveform, integrates the difference value interval, and uniformly updates the time reference sequence to generate the grounding resistance detection offset correction value.

[0045] After obtaining the unified calibration offset value SDu = 1.624 ms, recalculate the entire waveform time axis in the current cycle buffer. The rearrangement method is to subtract SDu from the original time value of each sampling point. For example, if the original time of a certain sampling point is 53 ms, then after adjustment it is 53 - 1.624 = 51.376 ms. Batch execute this operation to form a new time axis sequence; at the same time, the system calls the real-time load measurement module of the control device to obtain the load change amplitude value of the current cycle. The measurement method is to collect current and voltage within every 10 ms cycle, calculate the instantaneous power through P = UI, record the power change rate of the current cycle, and set that if the power change amplitude exceeds 5%, it is recorded as an effective load change. Assume that the power changes from 1.8 kW to 2.0 kW within the cycle, then the change amplitude is 11.1%, which is recorded as an effective load change. Subsequently, synchronize the load change amplitude value with the time series after the time axis rearrangement one by one, and respectively obtain the time difference between the power change mutation point and the key point of the rearranged waveform. If the difference is within the range of ±2 ms, it is determined as a synchronization point. The system further integrates the deviation between the waveform offset value interval and the load change time point, adjusts the original reference sequence RT by uniformly updating the time reference sequence, forms a new calibration reference RT', and generates the final grounding resistance detection offset correction value according to the difference trend. This correction value is the overall translation value between the new RT' and the original RT. If the overall average offset is -1.7 ms, the final correction value is set to -1.7 ms.

[0046] Table 5 Monitoring Cycle Waveform Delay and Offset Calibration Parameter Table , As shown in Table 5, the calibration offset value of each cycle is calculated by combining the difference sequence and the frequency modulation parameters, and the unified offset result of 1.624 ms is obtained by combining the trend of the previous cycle. This result indicates that there is still a systematic delay in the current detection cycle under the premise of a low standard deviation, and unified correction is required in the subsequent detection steps.

[0047] The above is only a preferred embodiment of the present invention, and it does not limit the present invention in other forms. Any person skilled in the relevant art may use the disclosed technical content to make changes or modifications into equivalent embodiments with equivalent changes and apply them to other fields. However, as long as it does not depart from the technical solution content of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. An electrical grounding resistance detection system for construction engineering, characterized in that, The system includes: The path monitoring module obtains the voltage change value and sampling timestamp of the power supply path node, calculates the adjacent voltage difference, compares the voltage difference with the stability threshold, determines whether the current path is in an unstable voltage state, records the path identifier and status, and generates a path stability status value; The delay determination module, based on the path stability status value, collects the input and output timestamps, calculates the difference between the two timestamps as the path signal delay value, compares whether the difference between the delay values in two adjacent periods exceeds the set signal time delay tolerance value, and generates a path delay anomaly flag value; The path switching module, according to the path stability status value and the path delay anomaly flag value, filters the stable path, generates a power supply switching instruction, collects the switching feedback, records the relay response, and generates a power supply channel switching confirmation value; The interval regulation module calls the power supply channel switching confirmation value, collects the current and pre-switching delay values, calculates the delay difference, compares the difference with the sampling reference value, adjusts the sampling interval, selects the data of the grounding conduction loop detection current monitoring terminal in the distribution switch control device, extracts the node response and the returned waveform, calculates the waveform displacement mapping, and generates a resistance detection waveform offset amount.

2. The building engineering electrical grounding resistance detection system according to claim 1, characterized in that The path stability status value includes path identifier information, voltage stability category, and voltage fluctuation amplitude. The path delay anomaly flag value specifically includes delay change amplitude, cycle change identifier, and anomaly determination label. The power supply channel switching confirmation value includes relay response characteristics, switching execution feedback, and channel identification code. The resistance detection waveform offset amount specifically includes waveform response time difference, node mapping characteristics, and waveform shape change.

3. The building engineering electrical grounding resistance detection system according to claim 2, wherein The path monitoring module includes: The voltage acquisition sub-module obtains the voltage change value and corresponding sampling timestamp of the power supply path node, records the multi-node numbers and their sampling sequences, establishes the voltage time series data of the sampling nodes, and generates a path voltage sampling sequence value; The path voltage difference generation sub-module, based on the path voltage sampling sequence value, performs a difference operation on the node voltage values at adjacent sampling time points, records the voltage change difference of each group of adjacent time points, and generates a path voltage difference sequence; The stability determination sub-module calls the path voltage difference sequence, compares the absolute values of the multi-voltage differences with the stability threshold, counts the number of differences exceeding the threshold, and calculates the instability ratio value in combination with the total number of node samplings. Using the formula: ； Performs an operation to obtain the path instability status value, assigns a path stability identifier, and generates a path stability status value; Among them, represents the path stability status value, represents the number of pairs of sampling nodes, represents the difference in adjacent voltages of the i-th group, represents the number of times the voltage difference exceeds the stability threshold, represents the sampling time interval of the i-th group, represents the initial sampling time point.

4. The building engineering electrical grounding resistance detection system according to claim 3, characterized in that, The delay determination module includes: The timestamp acquisition sub-module collects the path stability status value, obtains the input timestamp and output timestamp of the node, distinguishes and records the positions of the two types of collected timestamps, and generates a path timestamp data set; The path delay calculation sub-module, based on the path timestamp data set, calls the input timestamp and output timestamp of adjacent nodes, calculates the time difference between the output timestamp and the input timestamp as the signal transmission delay value. Using the formula: ； Performs an operation to obtain the transmission delay value under each path, and establishes a path delay change sequence; Among them, represents the delay value of path i in period j, represents the output timestamp of path a in period q, represents the input timestamp of path a in period q, represents the path status value in period q, represents the hop length of path a in period q, represents the forwarding blocking ratio of the k-th hop in the path sequence, where n is the total number of hops in the path; The abnormal marking generation sub-module calls the path delay change sequence, calculates the difference based on the delay values of the same path in two adjacent cycles, and compares it with the signal time delay tolerance value. If it exceeds the tolerance value, it is determined as abnormal, obtains the abnormal cycle and path index, and generates a path delay abnormal marking value.

5. The building engineering electrical grounding resistance detection system according to claim 4, characterized in that, The path switching module includes: The path stability evaluation sub-module establishes a correspondence relationship between the time series change data of the path stability state value and the path number, judges the state persistence of the path stability state value within the sliding time window, compares it with the set stability threshold, screens the path numbers whose stability state values meet the threshold, and generates a path stability screening value; The delayed abnormal path screening sub-module calls the path stability screening value and the path delay abnormal marking value, reads and classifies the path delay abnormal marking value path by path, identifies the paths with the marking value in the normal state, and performs an intersection operation with the path stability screening value. Using the formula: ； Calculate the path optimal adaptability, and use the path number with the maximum adaptability as the current selectable path to generate a stable and available path number value; Among them, represents the stability status value of the c-th path, represents the transmission delay value of the c-th path, represents the mean value of the delay marker distribution of the c-th path, represents the available duration of the path in the current period, represents the path data transmission speed, represents the number of times of path anomaly triggering, represents the path optimal adaptation degree; The power supply channel verification sub-module issues a power supply switching command based on the stable and available path number value and the content of the power supply switching instruction, collects the switching feedback value, records and compares the relay response state through the feedback value, judges the matching degree of the relay response and the stability degree of the feedback value, and generates a power supply channel switching confirmation value.

6. The electrical grounding resistance detection system for building engineering according to claim 5, wherein, The interval regulation module includes: The delay difference extraction sub-module calls the power supply channel switching confirmation value, collects the current delay value and the delay value before switching, calculates the difference between the current delay value and the delay value before switching, compares the relative difference between the difference and the set sampling reference value, and obtains a delay comparison deviation value; The sampling interval adjustment sub-module calls the delay comparison deviation value and compares it with the set sampling interval range threshold, and judges whether the deviation excess amount exceeds the sampling interval adjustment threshold. If the deviation exceeds, it corrects the current sampling period by adjusting the sampling interval control parameter to obtain the corrected sampling time interval parameter; The current waveform mapping sub-module selects the data of the grounding conduction loop detection current monitoring terminal in the distribution switch control device according to the corrected sampling time interval parameter, extracts the node response data and the returned current waveform sequence, calculates the displacement mapping difference between the two waveform sequences. Using the formula: ； Calculate the waveform mapping residual amount, and compare it with the set judgment threshold to obtain the resistance detection waveform offset amount; Among them, represents the return current waveform data of the th sampling point, represents the node response waveform data of the th sampling point, represents the standard deviation of the return waveform data, represents the standard deviation of the response waveform data, represents the total number of sampling points, represents the waveform mapping residual amount.

7. The electrical grounding resistance detection system for building engineering according to claim 6, wherein The system further includes: The data correction module compares the resistance detection waveform offset amount with the time points in the device standard time sequence table to calculate the time offset value. After that, through the time axis rearrangement operation in the buffer, it calls the load change amplitude value and the current cycle waveform offset value in the grounding electrode structure of the distribution switch control device for unified calibration to obtain the grounding resistance detection offset correction value; The grounding resistance detection offset correction value includes a calibrated time axis, a load amplitude matching value, and a correction coefficient distribution.

8. The building engineering electrical grounding resistance detection system according to claim 7, wherein The data correction module includes: The multi-peak waveform delay extraction sub-module obtains the waveform time point sequence and the reference start time node value within the current detection period based on the waveform offset detected by the resistor, determines the time delay amplitude of the multi-peak points in the waveform sequence relative to the reference time point, calculates the offset time interval value of the multi-waveform points, and obtains the waveform delay interval value; The timing comparison sub-module calls the waveform delay interval value, and according to the calibrated time point value set in the device standard timing table, uses the formula: ； Calculate the standard offset under multiple cycles, combine it with the offset trend value of the previous cycle, and generate a unified calibration offset value; Among them, represents the standard deviation of the calibration offset within the k-th period, represents the time delay of the d-th waveform in the k-th period, represents the reference time point of the d-th waveform, represents the total number of measurement points within the period, is the average time offset within the measurement period, represents the frequency modulation coefficient of the k-th period, is the frequency modulation reference constant, is the additional adjustment parameter within the k-th period; The time axis rearrangement sub-module calls the unified calibration offset value, rearranges the current cycle waveform time axis in the buffer, obtains the current load change amplitude value of the distribution switch control device, synchronously analyzes the load change amplitude value with the time series corresponding to the rearranged waveform time axis, integrates the difference value interval and uniformly updates the time reference sequence to generate a grounding resistance detection offset correction value.

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