Automatic generation method and storage medium for continuity test interface board and channel correspondence

Abstract

This invention relates to the field of chip testing technology, and discloses a continuity test interface board, a method for automatically generating channel correspondences, and a storage medium. The method includes a test interface board with several square test areas centered on the same point. These square test areas increase proportionally from the inside out along the diagonal of the test interface board. Each square test area has an equal number of pads connected to its outer side, with the pads evenly spaced. The other end of each pad is located outside the test interface board. The pads connected to the inner square test areas pass through the outer square test areas and are positioned between the pads connected to the outer square test areas. By strategically arranging the pads, the test interface board can be compatible with various types and specifications of chips under test. Furthermore, the correspondence between pads and channels improves the overall efficiency of chip testing, ensures the accuracy of complex package testing, and enhances the degree of automated testing.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically to a continuity test interface board, a method for automatically generating channel correspondence, and a storage medium. Background Technology

[0002] With the rapid development of semiconductor technology, chip packaging forms are becoming increasingly diversified, including QFN (Quad Flat Package), DFN (Dual In-line Package), DIP (Dual In-line Package), and SIP (System-in-Package). These packaging forms differ significantly in size, pin layout, and electrical characteristics, posing challenges to semiconductor testing. QFN packaged chips are compact with small pin pitch, effectively saving board space and suitable for portable electronic devices with stringent space requirements. DIP packaged chips are relatively larger with larger pin pitch, facilitating manual soldering and debugging, and are often used in traditional electronic devices that are cost-sensitive and have less space constraints. In terms of pin layout, QFN packaged pins are distributed around the chip and are flat; DFN package is similar to QFN, but with subtle differences in pin shape and arrangement; DIP packaged pins are dual in-line and neatly arranged; SIP package, as a system-in-package, integrates multiple chips or circuits with different functions, with a more complex pin layout that may include various types of pins to achieve electrical connections and signal transmission between different chips. In terms of electrical characteristics, chips with different packaging forms vary in signal transmission speed, power consumption, and anti-interference capabilities. High-speed signal transmission places higher demands on the electrical performance of chip packages. For example, in PCIeGen5 testing, the signal frequency reaches several GHz, requiring strict control over issues such as reflection and crosstalk during signal transmission. This necessitates that the chip package has good impedance matching and equal-length differential pair wiring.

[0003] Traditional loadboards are typically designed for a single package type, making them incompatible with multiple packages. Furthermore, adapting to different packages requires extensive manual configuration, leading to inefficiency. When facing chip testing needs across different package types, traditional loadboards struggle to maintain compatibility, necessitating frequent replacements and increasing testing costs and time. Moreover, adapting to different packages often involves significant manual configuration, such as adjusting test channel connections and setting test parameters. This manual operation is not only inefficient but also prone to errors, failing to meet the demands of large-scale, high-efficiency chip testing.

[0004] Furthermore, with increasing package density and signal frequencies, the electrical performance and signal integrity of test channels become particularly important. For example, high-speed signal testing requires strict impedance matching and differential pair equal-length wiring. At the same time, the need for automation in multi-channel testing is becoming increasingly prominent; for instance, RF switch matrices have been introduced in PCIe Gen5 testing to enable dynamic switching between multiple channels.

[0005] In the field of semiconductor packaging and testing, automated and intelligent testing tools are becoming increasingly prevalent. For example, software tools can automatically generate test channel mappings, significantly reducing manual configuration time. Furthermore, the emergence of new packaging technologies such as 3D packaging and multi-chip packaging has further driven innovation in testing technologies.

[0006] However, existing technologies still have shortcomings in terms of multi-package compatibility, channel mapping efficiency, and automation. Therefore, developing a test interface board that can be compatible with multiple package types, automatically adapt to different package sizes, and automatically generate channel mappings is of significant practical importance. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a continuity test interface board, a method for automatically generating channel correspondence, and a storage medium.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] A continuity test interface board is provided, which has several square test areas with the same center. The square test areas increase proportionally from the inside to the outside along the diagonal of the test interface board. The same number of pads are connected to the outside of each square test area. The pads are evenly distributed at equal intervals. The other end of the pads is located outside the test interface board. The pads connected to the inner square test areas pass through the outer square test areas. The pads connected to the inner square test areas are located between the pads connected to the outer square test areas.

[0010] In this invention, preferably, the test interface board has mounting holes on its diagonal.

[0011] In this invention, preferably, the test interface board is also provided with positioning holes, which are configured as an asymmetrical mechanism to ensure correct chip installation.

[0012] In this invention, preferably, the pad is rectangular and made of metal.

[0013] In this invention, preferably, the pads are circular and are evenly distributed within each square test area of ​​the test interface board.

[0014] In this invention, preferably, each pad is connected to a unique test machine channel, and each pad has a corresponding channel relationship within the test machine.

[0015] The method for automatically generating channel correspondence includes the following steps:

[0016] The chip to be tested is placed on the test interface board, and the pins of the chip to be tested are electrically connected to the pads. The pads are electrically connected to the test machine through channels.

[0017] The tester starts the test and automatically associates the test chip pins with the test channels based on the coordinate matching of the pads.

[0018] After obtaining the packaging parameters of the chip to be tested, a channel relationship mapping table is generated.

[0019] In this invention, preferably, a matrix switch circuit is also connected between the channel and the testing machine.

[0020] In this invention, preferably, when the number of pins of the chip under test is less than the maximum connection size of the test interface board, the pin coordinates of the chip under test are converted to the LoadBoard coordinate system:

[0021] X LoadBoard = X MinPackage +Δ X

[0022] Y LoadBoard = Y MinPackage +Δ Y ,

[0023] Where ΔX and ΔY are the offsets of the chip under test in the X and Y axes of the test interface board, respectively. X MinPackage and Y MinPackage These are the basic quantities of the interface board under test in the X and Y axes.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] The test interface board of this invention is provided with test areas of multiple sizes. By specially arranging the pads, the test interface board is compatible with various types and specifications of chips to be tested. At the same time, by the correspondence between the pads and channels, the overall efficiency of chip testing is improved, the accuracy of complex package testing is guaranteed, and the degree of automated testing is enhanced. Attached Figure Description

[0026] Figure 1This is a schematic diagram of the test interface board described in this invention.

[0027] Figure 2 This is another structural schematic diagram of the test interface board described in this invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] Please see Figure 1In practical chip testing scenarios, the design of test interface boards needs to fully consider the diversity and complexity of different chip package types. A preferred embodiment of this invention provides a continuity test interface board, which has several square test areas with the same center. These square test areas increase proportionally from the inside out along the diagonal of the test interface board. This layout is designed based on in-depth research into the sizes and pin distribution patterns of various chip packages. For example, common package types such as QFN, DFN, DIP, and SIP, although differing significantly in size, pin layout, and electrical characteristics, can be effectively compatible with chips of different pin counts within the same package type through this multi-size test area design. Each square test area has the same number of pads connected to its outer side. These pads are evenly distributed at equal intervals, and the other end of each pad is located outside the test interface board. The pads connected to the inner square test areas pass through the outer square test areas and are located between the pads connected to the outer square test areas. The test interface board is designed according to the maximum size of QFN or QFP devices to accommodate a wider range of chip sizes. The width of the pads is also determined based on the maximum size. The pads are arranged with the inner pads longer than the outer pads, with the pads in the central square test area being longer than those in the outer square test area. This accommodates chips with different pin counts within the same package and improves testing efficiency. Each square test area has the same number of pads on its outer side, and the pads are evenly distributed to ensure that chips with different pin counts can be tested on the same test interface board. The uniform distribution and connection method of the pads ensure the reliability and consistency of the electrical connections, improving the accuracy and efficiency of chip testing.

[0031] Specifically, taking QFN packaged chips as an example, their pins are typically distributed around the perimeter of the chip with a small pin pitch. On this test interface board, the inner square test area can accommodate QFN chips with fewer pins, and its connecting pads extend through the outer square test area and are located between the outer pads. The outer square test area can accommodate QFN chips with more pins. This layout allows for flexible adjustment of the connection position with the chip pins. For DIP packaged chips with larger pin pitch, the spacing between the pads on this test interface board is increased to accommodate DIP packaged chips. Multiple sizes of inner and outer square test areas and their connected pads can be used to adapt to the pins of DIP packaged chips.

[0032] In this embodiment, mounting holes are provided on the diagonal of the test interface board. These mounting holes can be of standardized size and shape, such as common circles or squares, to ensure compatibility with existing mounting devices. They can also be of the largest compatible package size. Positioning the mounting holes diagonally provides a more stable fixation, preventing displacement or loosening of the test interface board during use. The number and position of the mounting holes can be adjusted according to actual needs to accommodate test interface boards of different sizes and shapes. The material and processing technology of the mounting holes can be selected from durable and non-deformable materials to ensure long-term reliability. The diagonal mounting hole design simplifies and simplifies the fixing and installation process of the test interface board with the testing machine, reducing the complexity of manual operation and resulting in higher reliability and ease of use in practical applications.

[0033] Specifically, during chip testing, the test interface board typically needs to be mounted in a specific location on the test equipment and secured using screws or other fasteners through mounting holes. The number of mounting holes is generally 2-4, depending on the size and shape of the test interface board. For smaller test interface boards, 2 mounting holes may be sufficient to ensure stability; while for larger test interface boards, 4 mounting holes may be required. The mounting holes are generally made of high-strength metal materials, such as aluminum alloy or stainless steel. These materials have good wear resistance and corrosion resistance, ensuring that the mounting holes are not easily deformed during long-term use and guaranteeing a consistently stable and reliable fixation of the test interface board.

[0034] In this embodiment, the test interface board is also provided with positioning holes, which are located outside the test area. In actual operation, if the chip is installed in the wrong direction, it will not only lead to inaccurate test results, but may also damage the chip or the test interface board. The positioning holes are designed as an asymmetrical mechanism to ensure that the chip is installed correctly, thereby avoiding test failures or damage caused by incorrect installation.

[0035] Specifically, one common implementation involves designing two positioning holes, one circular and the other elliptical. This is for chips under test (DUTs) with circular and elliptical positioning slots, ensuring that the DUT can only mate with the test interface board in one correct orientation during installation.

[0036] Specifically, another implementation involves creating specific protrusions or grooves around the positioning holes. This is designed for chips with matching grooves or protrusions, and the correct chip mounting is ensured through this physical structural constraint. During production, the dimensional and positional accuracy requirements for the positioning holes are high. Generally, the diameter tolerance of the positioning holes is controlled within ±0.05mm, and the positional accuracy within ±0.1mm, to guarantee accurate chip mounting.

[0037] In this embodiment, the asymmetrical design of the positioning holes can be achieved in various ways. This design ensures that the chip can only mate with the test interface board in one correct orientation during installation, thus avoiding the possibility of incorrect installation. Through a simple physical structure design, correct chip installation is ensured, improving test reliability and efficiency, and reducing the risk of test failures and equipment damage due to incorrect installation.

[0038] In this embodiment, the solder pad is rectangular and made of metal. Using a rectangular solder pad provides a larger contact area, thereby improving the stability and reliability of the electrical connection.

[0039] Specifically, the design of the solder pads has a significant impact on the electrical performance and reliability of the test. When using rectangular strip-shaped solder pads, their length and width need to be optimized based on the size of the chip pins and electrical requirements. Generally, the length can be between 1 and 3 mm, and the width between 0.2 and 0.5 mm. This size provides a larger contact area, thereby improving the stability and reliability of the electrical connection. In terms of manufacturing process, rectangular strip-shaped solder pads can be fabricated using the etching process of printed circuit boards (PCBs), with etching precision controlled within ±0.05 mm to ensure the accuracy of the solder pad dimensions.

[0040] Please see Figure 2 In this embodiment, the pads are circular and evenly distributed across the square test areas of the test interface board. This even distribution helps optimize the pad layout, ensuring each pad is positioned uniformly on the test interface board and avoiding electrical performance issues caused by uneven pad shape or distribution. This approach improves the versatility and testing accuracy of the test interface board, meeting the testing requirements of different specifications and forms of Ball Grid Array (BGA) packages.

[0041] Specifically, circular pads are evenly distributed within each square test area. The diameter of the circular pads is typically between 0.3 and 0.8 mm. Precise wiring techniques and manufacturing processes such as laser cutting ensure that each pad is evenly distributed within its respective square test area. In practical applications, circular pads are suitable for testing Ball Grid Array (BGA) packaged chips. The pins of BGA packaged chips are arranged in a spherical shape on the bottom of the chip, and circular pads allow for better electrical connections to these pins. When designing the distribution of circular pads, the spacing and layout of the chip pins must be considered to ensure accurate connections between the pads and pins.

[0042] Specifically, circular pads can be achieved through precise wiring techniques, ensuring that each pad is evenly distributed within each square test area. Circular pads can be manufactured using techniques such as laser cutting to guarantee precise shape and smooth edges. Furthermore, the circular pads are made of metals with excellent electrical conductivity to ensure good electrical connection performance. The evenly distributed circular pads improve the electrical performance and testing accuracy of the test interface board, offering greater versatility and adaptability to the testing needs of various package types.

[0043] In this embodiment, each pad is connected to a unique test machine channel, and a channel correspondence is established within the test machine for each pad. This channel correspondence allows for the positioning of the pins of the chip under test connected to the pad, ensuring the accuracy and reliability of the test.

[0044] Specifically, each pad corresponds to a unique test channel, and the test machine maintains a channel mapping system. During actual testing, once the chip under test is placed on the test interface board and its pins are electrically connected to the pads, the test machine initiates testing. The test machine's internal software automatically associates the chip pins with the test channels based on the pad coordinates. For example, the test machine reads the X and Y coordinates of the pads on the test interface board and compares them with pre-stored chip pin coordinates to determine the corresponding test channel for each pin. After obtaining the package parameters of the chip under test, the test machine generates a channel mapping table. Package parameters include the number of pins, pin spacing, pin layout, etc., enabling the test machine to generate a more accurate channel mapping table. The channel mapping table is presented in spreadsheet format, containing pin numbers, pad numbers, and test channel numbers for easy viewing and analysis by testers.

[0045] Another preferred embodiment of the present invention is a method for automatically generating channel correspondence, comprising the steps of:

[0046] The chip to be tested is placed on the test interface board, and the pins of the chip to be tested are electrically connected to the pads. The pads are electrically connected to the test machine through channels.

[0047] The tester starts the test and automatically associates the test chip pins with the test channels based on the coordinate matching of the pads.

[0048] After obtaining the packaging parameters of the chip to be tested, a channel relationship mapping table is generated.

[0049] Specifically, the chip under test (DUT) is placed on the test interface board, and its pins are electrically connected to the pads. These pads are then electrically connected to the test machine via channels, establishing the initial connection between the chip and the test machine. Once the test machine starts testing, it automatically associates the chip pins with the test channels based on the pad coordinates, thus automatically generating the test channel relationships. After obtaining the package parameters of the DUT, a channel relationship mapping table is generated. This automatic matching and generation of the channel relationship mapping table solves the technical problem of automatically generating the chip pin-to-test channel relationship, reducing manual configuration time and improving testing efficiency and accuracy. A detailed mapping table is also generated, which can be saved as an electronic file for subsequent testing and analysis.

[0050] In this embodiment, a matrix switch circuit is also connected between the channel and the testing machine to improve testing efficiency and accuracy. The matrix switch circuit connects the channel and the testing machine, enabling dynamic switching between multiple channels and the testing machine. This design allows for flexible selection and switching of test channels as needed during testing, improving efficiency and accuracy, and is particularly suitable for multi-channel testing scenarios. The application of the matrix switch circuit makes the automatic generation of channel mapping relationships more efficient, reducing the need for manual intervention and increasing the automation level of testing. The matrix switch circuit can be designed as an N×M matrix structure, where N and M represent the number of input and output channels, respectively. By controlling the switch states in the matrix, connections between any input and output channels can be achieved.

[0051] Specifically, matrix switch circuits are typically designed as an N×M matrix structure, such as an 8×8 or 16×16 matrix. During testing, the connection between any input and output channels can be achieved by controlling the switch states in the matrix according to testing requirements. When the electrical performance of multiple different pins needs to be tested, the matrix switch circuit can quickly switch test channels, avoiding the cumbersome operation of frequently changing test circuits in traditional testing methods. The control of the matrix switch circuit can be implemented through the software system inside the testing machine. Testers only need to set the corresponding test parameters in the testing software, and the software system will automatically control the switching of the matrix switch circuit.

[0052] Specifically, when the number of pins of the chip under test is less than the maximum connection size of the test interface board, the pin coordinates of the chip under test are converted to the LoadBoard coordinate system:

[0053] X LoadBoard = X MinPackage +Δ X

[0054] Y LoadBoard = Y MinPackage +Δ Y ,

[0055] Where ΔX and ΔY are the offsets of the chip under test in the X and Y axes of the test interface board, respectively. X MinPackage and Y MinPackage These are the base quantities for the interface board under test in the X and Y axes. When the number of pins of the chip under test is less than the maximum connection size of the interface board, the pin coordinates of the chip under test are converted to the LoadBoard coordinate system, and the X coordinates are calculated. LoadBoard and Y LoadBoard This method ensures that the pins of the chip under test (DUT) are correctly mapped to the pad locations on the test interface board, thus achieving precise electrical connections. ΔX and ΔY represent the directional offsets of the DUT on the test interface board along the X and Y axes, respectively. MinPackage and Y MinPackage This represents the baseline coordinates of the test interface board along the X and Y axes. This coordinate transformation allows for flexible adaptation to chips of different sizes and pin layouts, resolving connection issues caused by insufficient pin counts and improving test compatibility and accuracy.

[0056] Specifically, in actual operation, the placement position of the chip under test on the test interface board is first determined. Based on the position of the first pin at the upper left of the chip under test, the test machine calculates its offset ΔX and ΔY in the X and Y axes. MinPackage and Y MinPackage These are the baseline quantities of the interface board under test in the X and Y axes. These baseline quantities can be obtained from the design drawings of the interface board or through actual measurements. For example, for a specific test interface board, X... MinPackage It could be 10mm, Y MinPackage It could be 15mm. This can be determined by calculating X. LoadBoard = X MinPackage + ΔX and Y LoadBoard = Y MinPackage +ΔY converts the pin coordinates of the chip under test to coordinates in the LoadBoard coordinate system, thereby ensuring that the pins of the chip under test can be correctly mapped to the pad positions of the test interface board, achieving precise electrical connection.

[0057] In some other preferred embodiments of the present invention, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, causes the processor to perform the steps of the method as described in the above embodiments.

[0058] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0059] The above description is a detailed description of the preferred embodiments of the present invention. However, the embodiments are not intended to limit the scope of the patent application of the present invention. All equivalent changes or modifications made under the technical spirit of the present invention should fall within the patent scope covered by the present invention.

Claims

1. A method for automatically generating channel correspondence, characterized in that, A continuity test interface board is adopted, which is provided with several square test areas with the same center. The square test areas increase proportionally from the inside to the outside along the diagonal of the test interface board. The same number of pads are connected to the outside of each square test area. The pads are evenly distributed at equal intervals. The other end of the pads is located outside the test interface board. The pads connected to the inner square test areas pass through the outer square test areas. The pads connected to the inner square test areas are located between the pads connected to the outer square test areas. The steps include: The chip to be tested is placed on the test interface board, and the pins of the chip to be tested are electrically connected to the pads. The pads are electrically connected to the test machine through a channel, and a matrix switch circuit is also connected between the channel and the test machine. The tester starts the test and automatically associates the test chip pins with the test channels based on the coordinate matching of the pads. After obtaining the packaging parameters of the chip to be tested, a channel relationship mapping table is generated; When the number of pins of the chip under test is less than the maximum connection size of the test interface board, the pin coordinates of the chip under test are converted to the LoadBoard coordinate system: X LoadBoard = X MinPackage +D X Y LoadBoard = Y MinPackage +D Y , Where ΔX and ΔY are the offsets of the chip under test in the X and Y axes of the test interface board, respectively. X MinPackage and Y MinPackage These are the basic quantities of the interface board under test in the X and Y axes.

2. The method for automatically generating channel correspondence according to claim 1, characterized in that, The test interface board has mounting holes on its diagonal lines.

3. The method for automatically generating channel correspondence according to claim 2, characterized in that, The test interface board is also provided with positioning holes.

4. The method for automatically generating channel correspondence according to claim 1, characterized in that, The pads are rectangular strips and made of metal.

5. The method for automatically generating channel correspondence according to claim 1, characterized in that, Each of the pads is connected to a unique test machine channel, and each pad has a corresponding channel relationship within the test machine.

6. A storage medium, characterized in that, The system contains a computer program that, when executed by a processor, causes the processor to perform the steps of the automatic generation method for channel correspondence as described in any one of claims 1-5.

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