Display panel, display module and display device

Abstract

The embodiment of the invention provides a display panel, a display module and a display device, relates to the technical field of display, and aims to simplify the circuit structure of the display panel. The display panel is provided with a display area and a light-transmitting area. The display panel comprises a first substrate, a second substrate, a liquid crystal layer and a frame sealing part, wherein the first substrate and the second substrate are oppositely arranged; the liquid crystal layer and the frame sealing part are arranged between the first substrate and the second substrate; the frame sealing part is arranged around the liquid crystal layer. The display panel further comprises a first pixel circuit, a first grid line, a first data line and a first transistor which are located in the display area, and a second pixel circuit and a second data line which are located in the light-transmitting area. The first grid line is electrically connected with the first transistor, and the first data line is coupled with the first pixel electrode through the first transistor; the second data line is coupled to the second pixel electrode. The first data line is coupled with the second data line; or, the first data line and the second data line are insulated from each other, and the at least one light-emitting data input end is coupled with the second data line. The display panel is used for displaying images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel, a display module, and a display device. Background Art

[0002] In some liquid crystal display panels, a liquid crystal layer is used to implement image display in a display area, and a light-emitting diode is used as a light-emitting device in an indicator area located outside the boundary of the display area, so as to realize the light emission of the indicator area. Summary of the Invention

[0003] The purpose of the embodiments of the present disclosure is to provide a display panel, a display module, and a display device, which are used to simplify the circuit structure of the display panel.

[0004] To achieve the above purpose, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a display panel is provided. The display panel has a display area and a light-transmitting area located on at least one side of the display area. The light-transmitting area emits light of one color within one light-emitting cycle of the light-transmitting area. The display panel includes: a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer, a first pixel circuit, a second pixel circuit, a sealing frame portion, a first gate line, a first data line, a first transistor, and a second data line disposed between the first substrate and the second substrate.

[0006] The sealing frame portion is disposed around the liquid crystal layer, and the inner sidewall of the sealing frame portion is used to define a liquid crystal sealing area. Both the display area and the light-transmitting area are located within the liquid crystal sealing area. The first pixel circuit is located within the display area, and the first pixel circuit includes a first pixel electrode and a first common electrode. The first pixel electrode and the first common electrode are configured to drive the liquid crystal molecules in the liquid crystal layer to move. The second pixel circuit is located within the light-transmitting area, and the second pixel circuit includes a second pixel electrode and a second common electrode. The second pixel electrode and the second common electrode are configured to drive the liquid crystal molecules in the liquid crystal layer to move.

[0007] The first gate line, the first data line, and the first transistor are located within the display area. The first gate line is electrically connected to the first transistor, and the first data line is coupled to the first pixel electrode through the first transistor. The second data line is located within the light-transmitting area, and the second data line is coupled to the second pixel electrode. The first data line is coupled to the second data line; or, the first data line and the second data line are insulated from each other. The display panel further has a bonding area, and the display panel further includes at least one light-emitting data input terminal located in the bonding area, and the at least one light-emitting data input terminal is coupled to the second data line.

[0008] In the above display panel, both the display area and the light-transmitting area achieve light emission by using a liquid crystal layer, thereby improving the utilization rate of the liquid crystal layer. The first pixel circuit in the display area and the second pixel circuit in the light-transmitting area can both be coupled to the same data line (the first data line is coupled to the second data line). Through the same data line, data signals can be transmitted to the first pixel circuit in the display area and the second pixel circuit in the light-transmitting area in a time-division manner, without the need to separately provide a data line for the second pixel circuit, simplifying the circuit structure. The first pixel circuit in the display area and the second pixel circuit in the light-transmitting area can also transmit data signals through different data lines. In this way, the overall drive control of the display panel is simpler, and the structure of the drive circuit can be simplified.

[0009] In some embodiments, the display panel includes M light-emitting data input terminals, and the display panel further includes: a light-emitting data driving circuit and M control signal terminals. Among them, the M control signal terminals correspond to the M light-emitting data input terminals one by one, M is greater than or equal to 2; the output terminal of the light-emitting data driving circuit is coupled to the second data line.

[0010] The light-emitting data driving circuit is configured to output the signal of the corresponding light-emitting data input terminal from the output terminal of the light-emitting data driving circuit in response to the working levels of the respective M control signal terminals. Among them, when one of the M control signal terminals outputs a working level, the other control signal terminals output non-working levels.

[0011] In some embodiments, the display panel includes a first light-emitting data driving circuit and a second light-emitting data driving circuit, and both the first light-emitting data driving circuit and the second light-emitting data driving circuit are light-emitting data driving circuits. The M control signal terminals include a first control signal terminal and a second control signal terminal. The M light-emitting data input terminals include: a first light-emitting data input terminal and a second light-emitting data input terminal.

[0012] The display panel includes a plurality of second pixel circuits, and the plurality of second pixel circuits include a first-color pixel circuit and a second-color pixel circuit. The colors of the light emitted by the display panel in the regions defined by the first-color pixel circuit and the second-color pixel circuit are different; the second pixel electrode of the first-color pixel circuit is coupled to the output terminal of the first light-emitting data driving circuit, and the second pixel electrode of the second-color pixel circuit is coupled to the output terminal of the second light-emitting data driving circuit.

[0013] In the first light-emitting data driving circuit, the first control signal terminal corresponds to the first light-emitting data input terminal, and the second control signal terminal corresponds to the second light-emitting data input terminal. In the second light-emitting data driving circuit, the first control signal terminal corresponds to the second light-emitting data input terminal, and the second control signal terminal corresponds to the first light-emitting data input terminal.

[0014] In some embodiments, the light-emitting data driving circuit includes M transistors, and the control electrodes of the M transistors are respectively coupled to M control signal terminals.

[0015] In some embodiments, the second data line is electrically connected to the second pixel electrode; alternatively, the display panel further includes: a second transistor, and the second data line is coupled to the second pixel electrode through the second transistor.

[0016] In some embodiments, the first data line is electrically connected to the second data line. One frame of the display panel includes a picture display stage and a blanking stage, and one light-emitting cycle of the light-transmitting region is within one frame of the display panel. The first data line transmits a first data signal to the first pixel electrode during the picture display stage, and transmits a second data signal to the second pixel electrode during the light-emitting cycle.

[0017] In some embodiments, during the light-emitting stage, the light-emitting cycle is shorter than the blanking stage in duration.

[0018] In some embodiments, when the display panel includes a first transistor, the display panel further includes: a first gate driving circuit. The first gate driving circuit includes: an input sub-circuit, a first pull-up node, and a first output sub-circuit. The input sub-circuit is coupled to the input signal terminal and the first pull-up node. The input sub-circuit is configured to transmit the input signal from the input signal terminal to the first pull-up node.

[0019] The first output sub-circuit is coupled to the first pull-up node, the clock signal terminal, the first signal output terminal, and the second signal output terminal. The first signal output terminal is coupled to the control electrode of the first transistor through a first gate line. The first output sub-circuit is configured to transmit the clock signal from the clock signal terminal to the first signal output terminal under the control of the voltage of the first pull-up node. The first output sub-circuit is further configured to transmit the clock signal from the clock signal terminal to the second signal output terminal under the control of the voltage of the first pull-up node.

[0020] When the display panel includes a second transistor, the display panel further includes: a second gate driving circuit; the second gate driving circuit includes: a second pull-up node and a second output sub-circuit.

[0021] The second pull-up node is electrically connected to the enable signal terminal. The second output sub-circuit is coupled to the second pull-up node, the enable signal terminal, and the third signal output terminal. The third signal output terminal is coupled to the control electrode of the second transistor through a second gate line; the second output sub-circuit is configured to transmit the enable signal from the enable signal terminal to the third signal output terminal under the control of the voltage of the second pull-up node, so as to charge the third signal output terminal.

[0022] In some embodiments, the first gate circuit further includes: a first control sub-circuit and a first reset sub-circuit. The first control sub-circuit is coupled to a first pull-down node and a first pull-up node. The first control sub-circuit is configured to pull up the first pull-down node and pull down the first pull-up node in response to a high level of the first pull-down node. The first control sub-circuit is further configured to pull down the first pull-down node in response to a high level of the first pull-up node.

[0023] The first reset sub-circuit is coupled to the first pull-down node, a first signal output terminal, and a second signal output terminal. The first reset sub-circuit is configured to reset the first signal output terminal and the second signal output terminal under the control of the voltage of the first pull-down node.

[0024] The second gate driving circuit further includes: a third control sub-circuit and a fifth reset sub-circuit.

[0025] The third control sub-circuit is coupled to a third pull-down node and a second pull-up node. The third control sub-circuit is configured to pull up the third pull-down node and pull down the second pull-up node in response to a high level of the third pull-down node. The first control sub-circuit is further configured to pull down the third pull-down node in response to a high level of the second pull-up node.

[0026] The fifth reset sub-circuit is coupled to the third pull-down node and a third signal output terminal. The fifth reset sub-circuit is configured to reset the third signal output terminal under the control of the voltage of the third pull-down node.

[0027] In some embodiments, the first output sub-circuit includes: a third transistor M3, a thirteenth transistor M13, and a first capacitor. The control electrode of the third transistor M3 is electrically connected to the first pull-up node. The first electrode of the third transistor M3 is electrically connected to a clock signal terminal. The second electrode of the third transistor M3 is electrically connected to the first signal output terminal. The first plate of the first capacitor is electrically connected to the first pull-up node. The second plate of the first capacitor is electrically connected to the second electrode of the third transistor M3. The control electrode of the thirteenth transistor M13 is electrically connected to the first pull-up node. The first electrode of the thirteenth transistor M13 is electrically connected to the clock signal terminal. The second electrode of the thirteenth transistor M13 is electrically connected to the second signal output terminal.

[0028] The second output sub-circuit includes: a third transistor N3 and a second capacitor. The control electrode of the third transistor N3 is electrically connected to the second pull-up node. The first electrode of the third transistor N3 is electrically connected to an enable signal terminal. The second electrode of the third transistor N3 is electrically connected to the third signal output terminal. The first plate of the second capacitor is electrically connected to the second pull-up node. The second plate of the second capacitor is electrically connected to the second electrode of the third transistor N3.

[0029] In some embodiments, the display panel includes a gate conductive layer, a first insulating layer, a source-drain conductive layer, a second insulating layer, a pixel electrode layer, a third insulating layer, and a common electrode layer, which are sequentially arranged in a direction away from the first substrate.

[0030] The display panel further includes: a first gate line, a data line, a first transistor, and a transfer electrode. The control electrode of the first transistor is electrically connected to the first gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is coupled to the first pixel electrode. The first gate line and the control electrode are located in the gate conductive layer, the data line, the first electrode, and the second electrode are located in the source-drain conductive layer, the first pixel electrode is located in the pixel electrode layer, and the transfer electrode and the first common electrode are located in the common electrode layer.

[0031] In a front projection onto the first substrate, the transfer electrode at least partially overlaps with the first pixel electrode, and the transfer electrode at least partially overlaps with the second electrode.

[0032] The display panel further includes: a first transfer via hole penetrating from the transfer electrode to the second electrode and a second transfer via hole penetrating from the transfer electrode to the first pixel electrode. The transfer electrode is electrically connected to the second electrode through the first transfer via hole, and the transfer electrode is electrically connected to the first pixel electrode through the second transfer via hole.

[0033] On the other hand, a display module is provided. The display module includes: a display panel provided in any of the foregoing embodiments, and a circuit board. The circuit board is electrically connected to the display panel. The circuit board is configured to send a driving signal to the display panel.

[0034] In some embodiments, the display panel further has a sensor area on one side of the display area, and the sensor area is located within the liquid crystal sealing area. The display module further includes: a sensor disposed in the sensor area. The light-transmitting area is configured to change the color of the emitted light according to changes in the operating state of the sensor.

[0035] On yet another aspect, a display device is provided. The display device includes: a backlight module, and a display module disposed on the light-emitting side of the backlight module. The backlight module has a first backlight area and a second backlight area. The front projection of the display area of the display module is within the range of the first backlight area, and the front projection of the light-transmitting area of the display module is within the range of the second backlight area.

[0036] In some embodiments, the turning on and off of the first backlight area and the second backlight area can be independently controlled. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings required for some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, the actual timings of the signals, etc.

[0038] Figure 1 It is a plan view structure diagram of a display device for some embodiments;

[0039] Figure 2 For Figure 1 The cross-sectional structure diagram obtained from the cross-section line G1G1 in;

[0040] Figure 3 It is a structure diagram of a display module for some embodiments;

[0041] Figure 4 It is a plan view structure diagram of a display panel according to some embodiments;

[0042] Figure 5 It is a plan view structure diagram of a display panel according to some other embodiments;

[0043] Figure 6 It is a plan view structure diagram of a display panel according to still some other embodiments;

[0044] Figure 7 It is a plan view structure diagram of a display panel according to yet some other embodiments;

[0045] Figure 8 For Figure 1 The enlarged structure diagram of the region V1 in;

[0046] Figure 9 For Figure 2 The enlarged structure diagram of the region V2 in;

[0047] Figure 10 For Figure 8 The cross-sectional structure diagram obtained from the cross-section line G2G2 in;

[0048] Figure 11 For Figure 8 The cross-sectional structure diagram obtained from the cross-section line G3G3 in;

[0049] Figure 12 For Figure 1 The enlarged structure diagram of the region V1 in;

[0050] Figure 13An enlarged structural diagram of a first common electrode and a second common electrode according to some embodiments;

[0051] Figure 14 Another enlarged structural diagram of a first common electrode and a second common electrode according to some embodiments;

[0052] Figure 15 A preparation flow chart of an array substrate according to some embodiments;

[0053] Figure 16 A planar structural diagram of a display panel according to some embodiments;

[0054] Figure 17 According to Figure 16 An enlarged structural diagram of region V3 in;

[0055] Figure 18 A planar structural diagram of a display panel according to some other embodiments;

[0056] Figure 19 According to Figure 16 Another enlarged structural diagram of region V3 in;

[0057] Figure 20 A timing diagram of a second gate line during a light-emitting period according to some embodiments;

[0058] Figure 21 Another timing diagram of a second gate line during a light-emitting period according to some embodiments;

[0059] Figure 22 According to Figure 16 Another enlarged structural diagram of region V3 in;

[0060] Figure 23 According to Figure 1 An enlarged structural diagram of region V1 in;

[0061] Figure 24 According to Figure 1 Another enlarged structural diagram of region V1 in;

[0062] Figure 25 According to Figure 1 Another enlarged structural diagram of region V1 in;

[0063] Figure 26 According to Figure 1 Another enlarged structural diagram of region V1 in;

[0064] Figure 27 An equivalent circuit diagram of a first pixel circuit in a display panel according to some embodiments;

[0065] Figure 28 Partial enlarged structural diagram of a display panel according to some embodiments;

[0066] Figure 29 Equivalent circuit diagram of a second pixel circuit in a display panel according to some embodiments;

[0067] Figure 30 Timing diagram of the second pixel circuit in the light-emitting stage according to some embodiments;

[0068] Figure 31 Equivalent circuit diagram of a first pixel circuit and a second pixel circuit in a display panel according to some embodiments;

[0069] Figure 32 Equivalent circuit diagram of a first pixel circuit and a second pixel circuit in a display panel according to some other embodiments;

[0070] Figure 33 Timing diagram of the second pixel circuit in the light-emitting stage according to some embodiments;

[0071] Figure 34 Structural diagram of a first gate driving circuit according to some embodiments;

[0072] Figure 35 Structural diagram of a first shift register according to some embodiments;

[0073] Figure 36 Equivalent circuit diagram of a first shift register according to some embodiments;

[0074] Figure 37 Structural diagram of a second shift register according to some embodiments;

[0075] Figure 38 Equivalent circuit diagram of a second shift register according to some embodiments;

[0076] Figure 39 Electrical equivalent circuit diagram of a light-emitting data driving circuit according to some embodiments;

[0077] Figure 40 Equivalent circuit diagram of a light-emitting data driving circuit according to some other embodiments;

[0078] Figure 41 Equivalent circuit diagram of a light-emitting data driving circuit according to some further embodiments;

[0079] Figure 42 Equivalent circuit diagram of a light-emitting data driving circuit according to some still further embodiments;

[0080] Figure 43Timing diagram of a light-emitting data driving circuit in a light-emitting stage according to some embodiments;

[0081] Figure 44 Cross-sectional structure diagram of a display panel according to some embodiments;

[0082] Figure 45 Partially enlarged structure diagram of a display panel according to some embodiments;

[0083] Figure 46 According to Figure 45 Enlarged structure diagram of V4 in

[0084] Figure 47 Cross-sectional structure diagram of a display panel according to some other embodiments. Detailed implementation manners

[0085] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the scope of protection of the present disclosure.

[0086] Unless otherwise required by the context, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples", etc., are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0087] Hereinafter, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0088] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or integrated; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0089] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0090] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0091] As used herein, depending on the context, the term "if" is optionally construed to mean "when", "at the time of", "in response to determining", or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined that..." or "if [the stated condition or event] is detected" is optionally construed to mean "when it is determined that...", "in response to determining...", "at the time of detecting [the stated condition or event]", or "in response to detecting [the stated condition or event]".

[0092] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude devices suitable for or configured to perform additional tasks or steps.

[0093] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond the stated ones.

[0094] As used herein, "about", "substantially" or "approximately" includes the recited value and an average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0095] As used herein, "parallel", "perpendicular", "equal" include the recited situation and situations similar to the recited situation, where the range of the similar situation is within an acceptable deviation range, and the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range of approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range of approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range of approximate equality can be, for example, that the difference between the two equal ones is less than or equal to 5% of either one of them.

[0096] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can also be an intermediate layer between the layer or element and the other layer or substrate.

[0097] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0098] In the embodiments of the present disclosure, Figure 1 is a planar structure diagram of a display device 10000. For the convenience of clearly describing the structure of the display device 10000, only a part of the first sub-pixel region P1 is shown in the figure, and the number of the first sub-pixel regions P1 is not limited to that shown in the figure. As Figure 1 and Figure 2As shown, some embodiments of the present disclosure provide a display device 10000. The display device 10000 can be any device that displays motion (e.g., video), still (e.g., still image), text, or images. More specifically, it is contemplated that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0099] In some embodiments, as Figure 1 and Figure 2 shown, the display device 10000 includes a display module 1000 and a backlight module 2000. The display module 1000 is disposed on the light-emitting side of the backlight module 2000. The backlight module 2000 is configured to provide backlight to the display module 1000.

[0100] The display module 1000 also has a display area AA and a light-transmitting area BB located on at least one side of the display area AA. The backlight module 2000 has a first backlight area BG1 and a second backlight area BG2. The orthographic projection of the display area AA of the display module 1000 is within the range of the first backlight area BG1, and the orthographic projection of the light-transmitting area BB of the display module 1000 is within the range of the second backlight area BG2.

[0101] Exemplarily, the turning on and off of the first backlight area BG1 and the second backlight area BG2 can be independently controlled.

[0102] Based on this, when no picture is displayed in the display area AA, the first backlight area BG1 is turned off, and at this time the second backlight area BG2 can be in an on state, so that when the display module 1000 does not display a picture, the light-transmitting area BB can also emit light.

[0103] Exemplarily, the backlight module 2000 can be a direct-lit backlight module or a side-lit backlight module. Specific adaptive designs can be made according to needs, and the present disclosure does not limit this.

[0104] Exemplarily, the display device 10000 may further include a sensor 300 disposed in the sensor area CC. The sensor includes but is not limited to at least one of a camera module, a fingerprint recognition module, a light sensor, a microphone module, etc.

[0105] Exemplarily, the above display device 10000 may further include a frame and other electronic accessories, etc. Among them, the display module 1000 may be disposed in the frame, for example.

[0106] As Figure 3 shown, the display module 1000 includes: a display panel 100 and a circuit board 200, and the circuit board 200 is electrically connected to the display panel 100. The circuit board 200 is configured to send a driving signal to the display panel 100. The driving signal includes but is not limited to a display driving signal and / or a touch driving signal. The display panel 100 displays an image and / or responds to a touch operation under the drive of the circuit board 200.

[0107] The circuit board 200 includes but is not limited to a PCB (Printed Circuit Board) or an FPC (Flexible Printed Circuit).

[0108] Figures 4 to 7 FIG. is a planar structure diagram of the display panel 100. For the convenience of clearly describing the setting manner of the light-transmitting area BB, only the positional relationship between the display area AA, the light-transmitting area BB, and the sensor area CC of the display panel 100 is shown in the figure. It can be understood that there are other structures provided in the display panel 100.

[0109] In some embodiments, as Figure 1 , Figures 4 to 7 shown, the display panel 100 has a display area AA and a light-transmitting area BB located on at least one side (one side or at least two sides) of the display area AA.

[0110] The sensor area CC may be located within the display area AA or on at least one side of the display area AA, and the present disclosure does not limit this. The light-transmitting area BB can emit light of at least one (one or at least two) color(s), and the light-emitting color of the light-transmitting area BB includes but is not limited to at least one of any colors such as red, green, blue, orange, or white, etc.

[0111] In some examples, the light-transmitting area is configured to change the color of the emitted light according to the change in the working state of the camera module sensor. The light-transmitting area BB is configured to change the color of the emitted light according to the change in the working state of the sensor 300 within the sensor area CC. Wherein, the working state of the sensor 300 includes: an on state and an off state. The light-transmitting area BB is configured to emit a light of one color in response to the on state of the sensor 300; in response to the off state of the sensor 300, it emits a light of another color or does not emit light.

[0112] When the light-transmitting area BB does not emit light when the sensor 300 is in the off state, when the sensor 300 is in the working state, the light-transmitting area BB can emit green light, red light, blue light, orange light, white light, etc.

[0113] When the light-transmitting area BB emits light both when the sensor 300 is in the on state and the off state, it can be that when the sensor 300 is in the on state, the light-transmitting area BB emits green light, and when the sensor 300 is in the off state, the light-transmitting area BB emits red light; it can also be that when the sensor 300 is in the on state, the light-transmitting area BB emits blue light, and when the sensor 300 is in the off state, the light-transmitting area BB emits orange light.

[0114] Specifically, it can be adaptively designed according to actual needs. This is only for illustrative purposes and does not limit the present disclosure.

[0115] Exemplarily, when the sensor 300 is in the on state, the light-emitting color of the light-transmitting area BB can also emit different colors of light according to different working states of the sensor 300. For example, when the sensor 300 is in the first working state, the light-transmitting area BB emits the first color light; when the sensor 300 is in the second working state, the light-transmitting area BB emits the second color light. The first color light and the second color light can be the same color or different colors, and the present disclosure does not limit this.

[0116] Based on this, when the sensor 300 is a camera module, when the camera module is in the state of taking pictures, the light-transmitting area BB emits the first color light; when the camera module is in the video recording state, the light-transmitting area BB emits the second color light.

[0117] Exemplarily, the number of sensors 300 can be one or more.

[0118] When the display module 1000 includes one sensor 300, the sensor 300 is disposed within one sensor area CC.

[0119] When the display module 1000 includes multiple sensors 300, the multiple sensors 300 can be respectively disposed in multiple sensor regions CC, that is, one sensor 300 is disposed in each sensor region CC; or, the multiple sensors 300 are disposed in the same sensor region CC, that is, multiple sensors 300 are disposed in one sensor region CC.

[0120] The number of sensors 300 and the specific implementation manner of the sensors 300 can be adaptively designed according to actual needs. This is only an exemplary illustration here and does not limit the present disclosure.

[0121] In some embodiments, the display module 1000 can include one sensor 300 and one light-transmitting region BB. In this case, the light-transmitting region BB changes the emission color according to the change in the working state of the sensor 300. Alternatively, the display module 1000 includes one sensor 300 and multiple light-transmitting regions BB. In this case, at least one of the multiple light-transmitting regions BB changes the emission color according to the working state of the sensor 300.

[0122] The light-transmitting region BB changing the emission color can be that the emission color of the light-transmitting region BB changes according to the change in the working state of the sensor 300. When the sensor 300 is in the working state, the light-transmitting region BB emits light of one color. When the sensor 300 is in the non-working state, the light-transmitting region BB emits light of another color. The working state of the sensor 300 is distinguished by the different emission colors of the light-transmitting region BB.

[0123] Alternatively, the light-transmitting region BB changing the emission color can also be that the light-transmitting region BB emits light or does not emit light according to the change in the working state of the sensor 300. For example, when the sensor 300 is in the working state, the light-transmitting region BB associated with the sensor 300 emits light. When the sensor 300 is in the non-working state, the light-transmitting region BB does not emit light. The working state of the sensor 300 is distinguished by whether the light-transmitting region BB associated with the sensor 300 emits light.

[0124] The display module 1000 can also include multiple sensors 300 and one light-transmitting region BB. In this case, the light-transmitting region BB changes the emission color according to the change in the working state of at least one of the multiple sensors 300.

[0125] For example, when all of the multiple sensors 300 are in the non-working state, the light-transmitting region BB does not emit light, or emits light of a first color; when at least one of the multiple sensors 300 is in the working state, the light-transmitting region BB emits light of a second color, and the second color is different from the emission color of the first color.

[0126] The display module 1000 may also include a plurality of sensors 300 and a plurality of light-transmitting areas BB, each light-transmitting area BB being arranged corresponding to a sensor 300. In this case, each light-transmitting area BB changes the luminous color according to the change of the working state of the sensor 300 associated therewith.

[0127] Exemplarily, the number of light-transmitting areas BB is greater than or equal to 1. The shape of the light-transmitting area BB includes but is not limited to at least one of a circle, an ellipse, a square, a diamond, a rectangle, an L-shape, a "匚" shape or a "囗" shape.

[0128] In the case where the display panel 100 includes a light-transmitting area BB, the light-transmitting area BB may be located on at least one side of the display area AA. For example, the light-transmitting area BB is located on either side of the display area AA (for example, located on the upper side of the display area AA), and its shape may be a circle (for example, Figure 1 As shown in the figure), oval, square, diamond or rectangle. As another example, the light-transmitting area BB may be located on at least two sides of the display area. Figure 4 As shown, the light-transmitting area BB is located on both sides of the display area to form an L shape; as another example, Figure 5 As shown, the light-transmitting area BB is located on three sides of the display area, forming a "匚" shape; as another example, Figure 6 As shown, the light-transmitting area BB is located on four sides of the display area, forming a "囗" shape.

[0129] like Figure 7 As shown, in the case where the display panel 100 includes a plurality of light-transmitting areas BB, each light-transmitting area BB may be located on at least one side of the display area AA. Exemplarily, each light-transmitting area BB is located on one side of the display area AA; the plurality of light-transmitting areas BB may be all arranged on the same side of the display area AA, or respectively arranged on different sides of the display area AA. For example, the display panel 100 includes M1 (M1 ≥ 2) light-transmitting areas BB1, the M1 light-transmitting areas BB1 are located on the same side of the display area AA, and the M1 light-transmitting areas BB1 are arranged along the extension direction of the edge of the display area. For another example, the display panel 100 includes M2 (M2 ≥ 2) light-transmitting areas BB2, the M2 light-transmitting areas BB2 are located on the same side of the display area AA, and the M1 light-transmitting areas BB2 are arranged in a direction perpendicular to the edge of the display area AA.

[0130] The light-transmitting area BB is located outside the display area AA of the display panel 100. Therefore, the light-transmitting area BB will not affect the normal display of the display. There are no fixed requirements for the number, shape, size, luminous color and setting position of the light-transmitting area BB. It can be adaptively designed according to actual needs, thereby increasing the design flexibility of the display panel 100.

[0131] In some embodiments, Figure 1As shown, the display area AA of the display panel 100 is configured to display an image under the drive of the circuit board 200. One frame of image is displayed within one display frame of the display area AA. The refresh rate of the display panel 100 can be 60HZ or 120HZ, etc. For example, the refresh rate of the display panel 100 is 60HZ; that is, within 1 second, multiple consecutive frames (such as 60 frames) of images can be displayed in the display area AA. The consecutive multiple frames of images can be the same image or not completely the same images. Then, the duration of one display frame is Ts, and Ts is 1 / 60 second.

[0132] As Figure 1 shown, the display area AA of the display panel 100 includes multiple first sub-pixel areas P1. Each first sub-pixel area P1 is configured to emit light of one color, and at least two of the multiple first sub-pixel areas P1 emit light of different colors.

[0133] The multiple first sub-pixel areas P1 include, for example, a red light first sub-pixel area P1(R) with a light-emitting color of red, a green light first sub-pixel area P1(G) with a light-emitting color of green, and a blue light first sub-pixel area P1(B) with a light-emitting color of blue. The multiple first sub-pixel areas P1 may also include a white light first sub-pixel area P1(W) with a light-emitting color of white.

[0134] In some embodiments, as Figure 1 shown, the light-transmitting area BB included in the display panel 100 is configured to emit light of one color within one light-emitting cycle Tf of one light-transmitting area BB. The light-transmitting area BB may emit light of the same color or different colors in two adjacent light-emitting cycles Tf.

[0135] Figure 8 For Figure 1 the enlarged structural diagram of the area V1 in the figure, only some of the first sub-pixel areas P1 and some of the second sub-pixel areas P2 are shown in the figure. The quantities of the first sub-pixel areas P1 and some of the second sub-pixel areas P2 are not limited to those shown in the figure.

[0136] As Figure 8 shown, the light-transmitting area BB of the display panel 100 includes one or more second sub-pixel areas P2. Each second sub-pixel area P2 is configured to emit light of one color. At least two of the multiple second sub-pixel areas P2 emit light of different colors, or all of the multiple second sub-pixel areas P2 emit light of the same color.

[0137] When the light-transmitting region BB includes a second sub-pixel region P2 with multiple (two or more) light-emitting colors, the light-transmitting region BB includes at least one (one or more) light-transmitting unit (which can also be called a repeating minimum unit or a pixel unit), and each light-transmitting unit includes a second sub-pixel region P2 with different light-emitting colors. The fact that the light-transmitting region BB emits light of one color in one emission cycle Tf means that the light-transmitting units in the light-transmitting region BB all emit light of the same color in one emission cycle Tf.

[0138] For example, the light-transmitting region BB includes a plurality of light-transmitting units, and each light-transmitting unit includes a red second sub-pixel region P2(R) and a green second sub-pixel region P2(G). In one emission cycle Tf, the red second sub-pixel region P2(R) emits red light, and the green second sub-pixel region P2(G) does not emit light. At this time, each light-transmitting unit emits red light, and the light-transmitting region BB emits red light. Or, in one emission cycle Tf, when the red second sub-pixel region P2(R) emits red light and the green second sub-pixel region P2(G) emits green light, at this time, both red light and green light are simultaneously emitted in each light-transmitting unit, and the two colors are mixed to form yellow light, and the light-transmitting region BB emits yellow light.

[0139] Another example is that the light-transmitting region BB includes a plurality of light-transmitting units, and each light-transmitting unit includes a red second sub-pixel region P2(R), a green second sub-pixel region P2(G), and a blue second sub-pixel region P2(B). In one emission cycle Tf, the red second sub-pixel region P2(R) emits red light, and the green second sub-pixel region P2(G) and the blue second sub-pixel region P2(B) do not emit light. At this time, each light-transmitting unit emits red light, and the light-transmitting region BB emits red light; or, in one emission cycle Tf, when the red second sub-pixel region P2(R) emits red light, the green second sub-pixel region P2(G) emits green light, and the blue second sub-pixel region P2(B) emits blue light, at this time, red light, green light, and blue light are simultaneously emitted in each light-transmitting unit, and the three colors are mixed to form white light, and the light-transmitting region BB emits white light.

[0140] Yet another example is that the light-transmitting region BB includes a plurality of light-transmitting units, and each light-transmitting unit includes a white second sub-pixel region P2(W). In one emission cycle Tf, the plurality of white second sub-pixel regions P2(W) emit white light. At this time, each light-transmitting unit emits white light, and the light-transmitting region BB emits white light.

[0141] Of course, the light-transmitting region BB may also include only one light-transmitting unit, and the light-transmitting unit includes a second red sub-pixel region P2(R), a second green sub-pixel region P2(G), and a second blue sub-pixel region P2(B). During a light-emitting cycle Tf, the second red sub-pixel region P2(R) emits red light, and the second green sub-pixel region P2(G) and the second blue sub-pixel region P2(B) do not emit light. At this time, each light-transmitting unit emits red light, and the light-transmitting region BB emits red light; or, during a light-emitting cycle Tf, the second red sub-pixel region P2(R) emits red light, the second green sub-pixel region P2(G) emits green light, and the second blue sub-pixel region P2(B) emits blue light. At this time, the light-transmitting unit emits red light, green light, and blue light simultaneously, and the three colors are mixed to form white light, and the light-transmitting region BB emits white light.

[0142] The duration of all the second sub-pixel regions P2 that emit the same color of light each time they are driven can be referred to as a light-emitting cycle Tf.

[0143] When the light-transmitting region BB includes a second sub-pixel region P2, the light-emitting color of the second sub-pixel region P2 can be any color, such as any one of red, green, blue, orange, white, etc. At this time, the duration of driving the second sub-pixel region P2 to emit light each time is used as a light-emitting cycle Tf.

[0144] When the light-transmitting region BB includes multiple second sub-pixel regions P2, the multiple second sub-pixel regions P2 can all be any color, such as any one of red, green, blue, orange, white, etc. For example, the multiple second sub-pixel regions P2 emit the same color of light. At this time, the duration of driving all the second sub-pixel regions P2 to emit light each time can be referred to as a light-emitting cycle Tf. Another example is that at least two of the multiple second sub-pixel regions P2 emit light of different colors. At this time, the duration of driving all the second sub-pixel regions P2 that initially emit the same color of light each time can be used as a light-emitting cycle Tf.

[0145] For example, the multiple second sub-pixel regions P2 may include a second red sub-pixel region P2(R) with a light-emitting color of red and a second green sub-pixel region P2(G) with a light-emitting color of green.

[0146] At this time, the duration of driving all the second red sub-pixel regions P2 to emit light once is a light-emitting cycle Tf, and the duration of driving all the second green sub-pixel regions P2 to emit light once is also a light-emitting cycle Tf.

[0147] Within the same emission period Tf, the light-transmitting region BB of the display panel 100 emits light of the same color. For example, the light-transmitting region BB of the display panel 100 can emit red light within at least one (one or a continuous plurality of) emission periods Tf, and the light-transmitting region BB of the display panel 100 can emit green light within at least one (one or a continuous plurality of) other emission periods Tf.

[0148] For another example, the multiple second sub-pixel regions P2 further include a blue-light second sub-pixel region P2(B) with an emission color of blue.

[0149] At this time, the duration for driving all the red-light second sub-pixel regions P2(R) to emit light once is one emission period Tf, the duration for driving all the green-light second sub-pixel regions P2(G) to emit light once is also one emission period Tf, and the duration for driving all the blue-light second sub-pixel regions P2(B) to emit light once is also one emission period Tf.

[0150] Within one emission period Tf, the light-transmitting region BB of the display panel 100 emits at least two colors of light. For example, within at least one (one or a continuous plurality of) emission periods Tf, the red-light second sub-pixel regions P2(R), the green-light second sub-pixel regions P2(G), and the blue-light second sub-pixel regions P2(B) all emit light; within at least one (one or a continuous plurality of) emission periods Tf, the red-light second sub-pixel regions P2(R), the green-light second sub-pixel regions P2(G), and the blue-light second sub-pixel regions P2(B) all do not emit light.

[0151] In this way, the light emitted by the red-light second sub-pixel regions P2(R), the green-light second sub-pixel regions P2(G), and the blue-light second sub-pixel regions P2(B) is mixed, enabling the light-transmitting region BB of the display panel 100 to emit white light within at least one (one or a continuous plurality of) emission periods Tf. When the red-light second sub-pixel regions P2(R), the green-light second sub-pixel regions P2(G), and the blue-light second sub-pixel regions P2(B) all do not emit light, the light-transmitting region BB of the display panel 100 can not emit light within at least one (one or a continuous plurality of) other emission periods Tf.

[0152] For yet another example, the multiple second sub-pixel regions P2 are all white-light second sub-pixel regions P2(W) with an emission color of white.

[0153] At this time, the duration for driving all the white-light second sub-pixel regions P2 to emit light once is one emission period Tf.

[0154] In this way, the light-transmitting region BB of the display panel 100 can emit white light within at least one (one or a continuous plurality of) emission periods Tf, and the light-transmitting region BB of the display panel 100 can not emit light within at least one (one or a continuous plurality of) other emission periods Tf.

[0155] The colors of the light emitted from the first sub-pixel region P1 and the second sub-pixel region P2 can be adaptively designed according to actual needs. Here is an exemplary illustration and is not intended to limit the present disclosure.

[0156] In some application scenarios, the light-transmitting region BB can serve as an ambient light or a "breathing light" of the display panel 100, and the light-transmitting region BB can emit light of different colors statically / dynamically.

[0157] One light-emitting stage of the light-transmitting region BB includes a plurality of consecutive light-emitting cycles Tf, and the light-transmitting region BB emits light during these plurality of consecutive light-emitting cycles Tf. When two adjacent light-emitting cycles Tf of the light-transmitting region BB are not continuous, these two adjacent light-emitting cycles Tf belong to different light-emitting stages respectively.

[0158] Based on this, the fact that the light-transmitting region BB emits light of different colors statically means that the light-transmitting region BB emits light of the same color within the same light-emitting stage. The fact that the light-transmitting region BB emits light of different colors dynamically means that the light-transmitting region BB emits light of the same or different colors during a plurality of consecutive light-emitting cycles Tf, and the light-transmitting region BB can emit light of different colors within the same light-emitting stage.

[0159] In some embodiments, we will introduce in detail the structure of the display panel 100 described above. The display panel 100 can be a liquid crystal display panel (abbreviated as LCD). The display panel 100 includes: a first substrate 1 and a second substrate 6 which are oppositely arranged, a liquid crystal layer 4 disposed between the first substrate 1 and the second substrate 6, and a sealing frame portion 5 disposed between the first substrate 1 and the second substrate 6. The sealing frame portion 5 surrounds the liquid crystal layer 4, and the inner sidewall of the sealing frame portion 5 is used to define a liquid crystal sealing region SA. The display region AA, the light-transmitting region BB, and the sensor region CC are all located within the liquid crystal sealing region SA.

[0160] When the display panel 100 is an LCD display panel, in some embodiments of the present disclosure, both the display region AA and the light-transmitting region BB utilize the liquid crystal layer 4 to achieve light emission, thereby improving the utilization rate of the liquid crystal layer 4. Some embodiments of the present disclosure can achieve the light-emitting display of the light-transmitting region BB without additionally providing a light-emitting device (such as a light-emitting diode). Compared with the technical solution of realizing light-emitting display by providing a light-emitting device in the light-transmitting region BB, the structure of the display panel 100 can be simplified, and the preparation steps of the display panel 100 can be reduced.

[0161] Moreover, to ensure the normal display of the display area AA, the coverage range of the liquid crystal layer 4 is larger than that of the display area AA. In other words, the display area AA is within the edge (outer contour) of the liquid crystal layer 4. For example, in the orthographic projection onto the first substrate 1, the liquid crystal layer 4 surrounds the display area AA.

[0162] In some embodiments of the present disclosure, the light-transmitting area BB is also conducive to the liquid crystal layer 4 for light emission. For example, the light-transmitting area BB is within the range of the liquid crystal layer 4, that is, the light-transmitting area BB is also within the edge (outer contour) of the liquid crystal layer 4. Compared with the scheme of arranging the light-emitting device within the light-transmitting area BB to achieve light emission, where the light-emitting device needs to be arranged outside the range of the liquid crystal layer 4, this embodiment can reduce the width of the border AN of the display panel 100, thereby improving the screen-to-body ratio of the display panel 100.

[0163] Figure 9 For Figure 2 The enlarged structural diagram of the area V2 in the Figure 10 The sectional structural diagram of the display panel obtained according to Figure 8 the sectional line G2G2 in the

[0164] In some embodiments, as Figure 9 and Figure 10 shown, the display panel 100 further includes: a first pixel circuit 2 and a second pixel circuit 3 disposed between the first substrate 1 and the second substrate 6. The first pixel circuit 2 is located within the display area AA, and the second pixel circuit 3 is located within the light-transmitting area BB. The area defined by a single first pixel circuit 2 is a first sub-pixel area P1, and the area defined by a single second pixel circuit 3 is a second sub-pixel area P2.

[0165] The first pixel circuit 2 includes a first pixel electrode 21 and a first common electrode 22, and the first pixel electrode 21 and the first common electrode 22 are configured to drive the liquid crystal molecules in the area defined by the first pixel circuit 2 in the liquid crystal layer 4 to move.

[0166] The second pixel circuit 3 includes a second pixel electrode 31 and a second common electrode 32, and the second pixel electrode 31 and the second common electrode 32 are configured to drive the liquid crystal molecules in the area defined by the second pixel circuit 3 in the liquid crystal layer 4 to move.

[0167] The display area AA includes a plurality of first sub-pixel areas P1, and the light-transmitting area BB includes one or more second sub-pixel areas P2. Both the first sub-pixel area P1 and the second sub-pixel area P2 are liquid crystal display areas. The display panel 100 further includes a pixel circuit for driving the movement of liquid crystal molecules in the corresponding areas of the display area AA and the light-transmitting area BB. The pixel circuit drives the deflection of the liquid crystal molecules to control the transmittance of the light emitted by the backlight module 2000, so as to realize image display in the display module 1000.

[0168] The backlight module 2000 emits light of one color. To realize color display in the display module 1000, in some embodiments, such as Figure 9 and Figure 10 shown, the display panel 100 further includes: a color filter layer CF. The color filter layer CF includes a plurality of light filtering parts G.

[0169] The plurality of light filtering parts G at least includes a plurality of first light filtering parts G1 located in the display area AA. The plurality of first light filtering parts G1 are correspondingly arranged with the plurality of first sub-pixel areas P1. The plurality of first light filtering parts G1 include light filtering parts G of at least two filtering colors.

[0170] Exemplarily, the light filtering parts G of at least two filtering colors are, for example, at least two of a first color light filtering part G, a second color light filtering part G, and a third color light filtering part G. The first color, the second color, and the third color can be the three primary colors, such as red, green, and blue.

[0171] Based on this, the first light filtering part G1 includes, but is not limited to, a red light filtering part G, a green light filtering part G, and a blue light filtering part G. The light filtering parts G of different colors are configured to allow light within a set wavelength range to pass through and block light of other wavelengths.

[0172] For example, the backlight module 2000 can emit white light, and the wavelength range of the light emitted by the backlight module 2000 is, for example, 390nm - 780nm.

[0173] When the light emitted by the backlight module 2000 passes through the red light filtering part, the light with a wavelength range between 625nm and 740nm can pass through the red light filtering part and be emitted, and the light of the remaining wavelengths will be blocked by the red light filtering part and cannot be emitted, so as to ensure that the light emitted through the red light filtering part is red light.

[0174] When the light emitted by the backlight module 2000 passes through the green light filtering part, the light with a wavelength range between 500nm and 570nm can pass through the green light filtering part and be emitted, and the light of the remaining wavelengths will be blocked by the green light filtering part and cannot be emitted, so as to ensure that the light emitted through the green light filtering part is green light.

[0175] When the light emitted by the backlight module 2000 passes through the blue light filtering portion, the light with a wavelength range between 450 nm and 490 nm can pass through the blue light filtering portion and be emitted, while the light with other wavelengths will be blocked by the blue light filtering portion and cannot be emitted, thereby ensuring that the light emitted through the blue light filtering portion is blue light.

[0176] In some embodiments, at least one second sub-pixel region P2 included in the light-transmitting region BB is configured to emit light of the same color, and the light emitted by the light-transmitting region BB has the same color as the light emitted by the backlight module 2000.

[0177] Based on this, the light emitted by the backlight module 2000 can be directly emitted after passing through the display module 1000 without changing the emission color, that is, the color filter layer CF may not be provided with a filtering portion G in the region corresponding to the second sub-pixel region P2. In this case, the thickness of the region of the color filter layer CF corresponding to the second sub-pixel region P2 is 0.

[0178] In other embodiments, as Figure 10 shown, the light emitted by at least one second sub-pixel region P2 included in the light-transmitting region BB has a different color from the light emitted by the backlight module 2000.

[0179] Based on this, as Figure 10 shown, the color filter layer CF further includes: one or more second filtering portions G2 located in the light-transmitting region BB, and each second filtering portion G2 is correspondingly arranged with a second sub-pixel region P2. The plurality of second filtering portions G2 include filtering portions G of at least one filtering color.

[0180] In the case where the light-transmitting region BB may include one or more second sub-pixel regions P2, the color filter layer CF may include a second filtering portion G2, and the second filtering portion G2 is correspondingly arranged with the light-transmitting region BB. The single second filtering portion G2 may be correspondingly arranged with one or more second sub-pixel regions P2. Alternatively, the color filter layer CF includes a plurality of second filtering portions G2, and each second filtering portion G2 is correspondingly arranged with a second sub-pixel region P2.

[0181] In some embodiments, as Figure 9 and Figure 10 shown, the color filter layer CF includes a first filtering portion G1 and a second filtering portion G2, and the first filtering portion G1 and the second filtering portion G2 are arranged on the same layer.

[0182] It should be noted that the "same layer" mentioned in the present disclosure refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern and then forming it through a single patterning process using the same mask; or, it can also be formed on the same film layer structure by using different film-forming processes. Depending on the different specific patterns, a single patterning process may include multiple exposure, development, or etching processes, and may also include an evaporation process, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0183] The first color filter portion G1 and the second color filter portion G2 may be provided in different film layer structures or in the same film layer structure. When the first color filter portion G1 and the second color filter portion G2 are provided on the same layer, the first color filter portion G1 and the second color filter portion G2 may be formed in the same process step, thereby reducing the manufacturing steps of the display panel 100.

[0184] In some embodiments, color filter portions G having the same filter color are provided on the same layer.

[0185] Color filter portions of the same color can be formed simultaneously in the same process step, thereby reducing the manufacturing steps of the display panel 100.

[0186] When the color film layer CF only includes the first color filter portion G1, the first color filter portion G1 includes, for example, a plurality of first color light filter portions, a plurality of second color light filter portions, and a plurality of third color light filter portions. The plurality of first color light filter portions are provided on the same layer and can be formed in the same process step, the plurality of second color light filter portions are provided on the same layer and can be formed in the same process step, and the plurality of third color light filter portions are provided on the same layer and can be formed in the same process step, thereby reducing the manufacturing steps of the display panel 100.

[0187] Based on this, the plurality of first color light filter portions, the plurality of second color light filter portions, and the plurality of third color light filter portions can be provided on the same layer. In this way, compared with the case where color filter portions G of different filter colors are provided in layers, it is beneficial to realize the thin and light design of the display panel 100.

[0188] When the color film layer CF includes the first color filter portion G1 and the second color filter portion G2, the first color filter portion G1 includes, for example, a plurality of first color light filter portions, a plurality of second color light filter portions, and a plurality of third color light filter portions. The second color filter portion G2 includes at least one first color light filter portion, and the second color filter portion G2 is provided on the same layer as the first color light filter portion included in the first color filter portion G1 and can be formed in the same process step.

[0189] In this way, compared with the case where the first light filtering part G1 and the second light filtering part G2 are arranged in layers, while reducing the manufacturing steps of the display panel 100, it is also beneficial to realize the thinning design of the display panel 100.

[0190] In some embodiments, as Figure 9 shown, the display panel 100 further includes: a black matrix layer BM. The black matrix layer BM is configured to isolate the light emitted between adjacent first sub-pixel regions P1 to prevent color mixing in the display area AA.

[0191] Exemplarily, the boundary line of the black matrix layer BM is located outside the boundary line of the liquid crystal sealing area SA. In this way, light leakage problems of the display panel 100 can be avoided.

[0192] Exemplarily, as Figure 9 shown, the black matrix layer BM has a plurality of first openings K1 located in the display area AA, and the first openings K1 are correspondingly arranged with the first pixel electrodes 21. Along the arrangement direction of the light-transmitting area BB and the display area AA, the distance between two adjacent first openings K1 is q.

[0193] As Figure 1 shown, the light-transmitting area BB is located on one side of the display area AA along the first direction X, and the arrangement direction of the light-transmitting area BB and the display area AA is the first direction X as Figure 1 shown.

[0194] Exemplarily, each first light filtering part G1 can be arranged in one first opening K1. In this way, the first light filtering part G1 and the black matrix layer BM are arranged on the same layer, which is beneficial to realizing the thinning of the display panel 100.

[0195] In some embodiments, as Figure 10 shown, the black matrix layer BM further has a second opening K2 located in the light-transmitting area BB, and the second opening K2 has the same size as the light-transmitting area BB.

[0196] In this case, the light-transmitting area BB may include a second sub-pixel region P2. Any one of a second light filtering part G2, a transparent filling part, and a scattering particle part may be arranged in the second opening K2.

[0197] When the second light filtering part G1 is arranged in the second opening K2, the second light filtering part G2 and the black matrix layer BM are arranged on the same layer, which is beneficial to realizing the thinning of the display panel 100.

[0198] In some embodiments, the display area AA is adjacent to the light-transmitting area BB. As Figure 9As shown, each first sub-pixel region P1 is located within a first opening K1 of the black matrix layer BM, and adjacent first sub-pixel regions P1 are separated by the black matrix layer BM to prevent color mixing of the light emitted from adjacent first sub-pixel regions P1, thereby ensuring that each first sub-pixel region P1 emits only one color of light. Therefore, there is a gap of q (the distance between two adjacent first openings K1) between two adjacent first sub-pixel regions P1. Based on this, when the display area AA is adjacent to the light-transmitting area BB, the boundary of the first sub-pixel region P1 closest to the light-transmitting area BB is also surrounded by the black matrix layer BM, and there is also a gap between the first sub-pixel region P1 and the second sub-pixel region P2 with the closest distance.

[0199] In this case, the gap between adjacent first sub-pixel region P1 and second sub-pixel region P2 is the distance w between two adjacent first openings K1 and second openings K2 along the arrangement direction of the light-transmitting area BB and the display area AA, and w can be less than the distance q between two adjacent first openings K1.

[0200] Exemplarily, as Figure 9 and Figure 10 shown, along the arrangement direction of the light-transmitting area BB and the display area AA, for example Figure 10 the first direction X shown in

[0201] Figure 2 Figure 8 and Figure 9 Figure 10 Figure 10 and

[0202] Figure 10

[0203] ​​​​​​In this case, the light-transmitting region BB may include a plurality of second sub-pixel regions P2. The black matrix layer BM is also configured to block the light emitted between adjacent second sub-pixel regions P2 to avoid color mixing in the light-transmitting region BB. Any one of a second light-filtering portion G2, a transparent filling portion, and a scattering particle portion may be disposed in the third opening K3.

[0204] When the second light-filtering portion G1 is disposed in the third opening K3, the second light-filtering portion G2 is disposed on the same layer as the black matrix layer BM, which is beneficial to realizing the thinning of the display panel 100.

[0205] Exemplarily, along the arrangement direction of the light-transmitting region BB and the display region AA, for example Figure 10 in the first direction X shown in the figure, the distance between the closest first opening K1 and the third opening K3 is r, 0.5q ≤ r ≤ 1.5q, or r > 1.5q. In some examples, the distance r between the closest first opening K1 and the third opening K3 may be 0.5q, 1.2q, or 1.5q, etc. In other examples, the distance r between the closest first opening K1 and the third opening K3 may be 1.65q, 6.5q, 8q, 15q, or 20q, etc.

[0206] For the setting manners of the light-transmitting region BB and the display region AA and the setting manners of the first opening K1 and the second opening K3, refer to the description of the first opening K1 and the second opening K2 above, and details are not described herein again.

[0207] Based on the above, by controlling the distance between the closest first opening K1 and the third opening K3, when the size of the light-transmitting region BB is the same, the smaller the distance between the first opening K1 and the third opening K3 is, as Figure 1 shown, the size d4 of the border AN of the display panel 100 along the arrangement direction of the light-transmitting region BB and the display region AA, for example, along the Figure 1 first direction X shown in the figure, can be correspondingly smaller, which is beneficial to realizing the narrow-border design of the display panel 100.

[0208] In some embodiments, as Figure 11 shown, the thickness of the black matrix layer BM in the region corresponding to the sensor region CC is 0.

[0209] Based on this, in some examples, in the orthographic projection onto the first substrate 1, the sensor region CC is outside the boundary line of the black matrix layer BM. In other examples, as Figure 11 shown, in the orthographic projection onto the first substrate 1, the boundary line of the black matrix layer BM surrounds the sensor region CC, and the black matrix layer BM has a fourth opening K4 corresponding to the sensor region CC.

[0210] By not providing a black matrix layer BM in the area corresponding to the sensor area CC, light blocking by the black matrix layer BM can be prevented, thereby ensuring the light transmission amount of the sensor area CC to ensure the normal operation of the sensor.

[0211] In some embodiments, the display panel 100 has no conductive material in the sensor area CC.

[0212] Not providing a conductive material in the sensor area CC can reduce the loss of light when it enters the sensor area CC and increase the light transmission amount in the sensor area CC.

[0213] Based on this, in some other embodiments, the display panel 100 has no interlayer insulating layer in the sensor area CC. The interlayer insulating layer is, for example, a spacer insulating film layer between adjacent conductive film layers. When there is no conductive material in the sensor area CC, correspondingly, the interlayer insulating layer can also be not provided in the sensor area CC. In this way, the loss of light when it enters the sensor area CC can be reduced, and the light transmission amount in the sensor area CC can be increased.

[0214] In some embodiments, the thickness of the first alignment layer Q1 and / or the second alignment layer Q2 in the area defined by the sensor area CC is 0.

[0215] The first alignment layer Q1 and / or the second alignment layer Q2 are made of a light-transmissive material. When the first alignment layer Q1 and / or the second alignment layer Q2 in the area defined by the sensor area CC are not removed, the light transmission amount of the sensor area CC can meet the design requirements. When at least one of the first alignment layer Q1 and the second alignment layer Q2 in the area defined by the sensor area CC is removed, the light transmission amount of the sensor area CC is better than the case where they are not removed.

[0216] In some embodiments, as Figure 10 and Figure 11 shown, the first pixel electrode 21 is disposed on the first substrate 1, and the display panel 100 further includes: a first polarizer POL1 disposed on a side of the first substrate 1 away from the second substrate 6, and a second polarizer POL2 disposed on a side of the second substrate 6 away from the first substrate 1.

[0217] In the orthographic projection onto the first substrate 1, the light-transmissive area BB overlaps both the first polarizer POL1 and the second polarizer POL2, and at least a part of the sealing frame portion 5 is located outside the boundary of the first polarizer POL1.

[0218] Exemplarily, the sealing frame portion 5 is, for example, made of a sealant. When forming the sealing frame portion 5, the sealant is filled in the preset position, and then, methods such as light irradiation are used to cure the sealant to form the sealing frame portion 5.

[0219] The polarizer blocks some light and converts the light into linearly polarized light. Therefore, there will be a certain loss of light passing through the polarizer. By making at least a part of the sealing frame portion 5 located outside the boundary of the first polarizer POL1, in this way, when curing the sealant, the light can directly irradiate on the sealant, which is beneficial to quickly curing the sealant and improving the manufacturing efficiency of the display panel 100.

[0220] As Figure 10 shown, within the area corresponding to the sealing frame portion 5, a black matrix layer BM is further provided between the second substrate 6 and the liquid crystal layer 4. In some other embodiments, during the manufacturing process of the display panel 100, the light irradiates from the side of the second substrate 6 towards the sealant for light curing. To avoid the black matrix layer BM blocking the light, at least a part of the sealing frame portion 5 is located outside the boundary of the black matrix layer BM, so as to ensure that the light can irradiate towards the sealant.

[0221] Based on this, at least a part of the sealing frame portion 5 is also located outside the boundary of the second polarizer POL2. In this way, when curing the sealant, the light can directly irradiate on the sealant, which is beneficial to quickly curing the sealant and improving the manufacturing efficiency of the display panel 100.

[0222] Figure 12 For the display panel according to Figure 1 is an enlarged structural diagram of region V1 in. To clearly describe the positional relationship between the polarizer POL, the support structure 10, the light-transmitting region BB, and the sensor region CC, only the polarizer POL, the support structure 10, the light-transmitting region BB, and the sensor region CC are shown in the figure, while the remaining structures in the display panel are not shown.

[0223] In some embodiments, as Figure 12 shown, the sensor region CC is located outside the boundary of the first polarizer POL1, and the second polarizer POL2 has a fifth opening K5 corresponding to the sensor region CC.

[0224] With such a design, no polarizer POL is provided within the area corresponding to the sensor region CC, thus ensuring the light transmission amount of the sensor region CC.

[0225] In some embodiments, as Figure 12 shown, in the orthographic projection onto the first substrate 1, the fifth opening K5 surrounds the sensor region CC.

[0226] With such a design, it can be ensured that the light can pass through the fifth opening K5 and enter the sensor region CC without being blocked by the second polarizer POL2, thereby ensuring the light transmission amount of the sensor region CC.

[0227] In some embodiments, as Figure 12As shown, in the orthographic projection onto the first substrate 1, the display area AA and the light-transmitting area BB fall within the range of the first polarizer POL1, and the minimum distance between the boundary of the first polarizer POL1 and the boundary of the display area AA and the light-transmitting area BB is d1, 0<d1≤3mm.

[0228] Any border of the first polarizer POL1 is located outside the border of the display area AA and the light transmission area BB, and the distance between the border of the first polarizer POL1 and the border of the display area AA and the light transmission area BB can be 0.2mm, 1mm, 1.7mm or 3mm.

[0229] There may be some areas at the edge of the polarizer POL that cannot play an effective polarization role (invalid area of ​​the polarizer POL), and there may be some deviation between the actual coverage area of ​​the polarizer POL and the target coverage area during the assembly process of the display panel 100. Therefore, the actual size of the polarizer POL should be larger than the size of the area that the polarizer POL needs to cover, so as to ensure that the effective area of ​​the polarizer POL can completely cover the display area AA and the light-transmitting area BB.

[0230] In some embodiments, Figure 12 As shown, the display panel 100 further includes: a support structure 10. In the orthographic projection onto the first substrate 1, the support structure 10 is located outside the boundary of the first polarizer POL1 and extends along the boundary of the first polarizer POL1; the support structure 10 avoids the sensor area CC.

[0231] Exemplarily, the support structure 10 and the first polarizer POL1 are arranged side by side along a plane parallel to the first substrate 1 , and the distances between the support structure 10 and the first polarizer POL1 and the first substrate 1 are the same or substantially the same.

[0232] The support structure 10 is, for example, disposed around a boundary line of the first polarizer POL1 .

[0233] By providing the support structure 10 to surround the first polarizer POL1, on the one hand, the edge portion of the first polarizer POL1 can be prevented from being damaged by bumps; on the other hand, by providing the support structure 10, the thickness of the portion outside the boundary line of the first polarizer POL1 is increased, and the thickness uniformity of the display panel 100 can be ensured.

[0234] For example, the support structure 10 may be made of foam tape, which is designed to avoid the sensor area CC and the light transmission area BB, thereby ensuring that the support structure 10 does not block the sensor area CC and the light transmission area BB, and ensuring the light transmission of the sensor area CC and the luminous effect of the light transmission area BB.

[0235] In some embodiments, Figure 12As shown, the minimum distance between the support structure 10 and the first polarizer POL1 is d2, and d2≥6μm. The distance d2 between the support structure 10 and the first polarizer POL1 can be 6μm, 6.3μm, 8.5μm, etc.

[0236] During the preparation process of the display panel 100, the assembly sequence of the support structure 10 and the first polarizer POL1 is not limited. By controlling the minimum distance between the support structure 10 and the first polarizer POL1, it is possible to effectively avoid the situation where the support structure 10 and the first polarizer POL1 affect each other during the preparation process of the display panel 100, causing the other to deviate from the set position, and ensuring that the support structure 10 and the first polarizer POL1 can be set in the target area more accurately.

[0237] In some embodiments of the present disclosure, the first pixel electrode 21 and the first common electrode 22 can be both disposed on the same side of the liquid crystal layer 4, or can be respectively disposed on both sides of the liquid crystal layer 4.

[0238] In the case where the first pixel electrode 21 and the first common electrode 22 are both disposed on the same side of the liquid crystal layer 4, the first pixel electrode 21 and the first common electrode 22 can be both disposed between the liquid crystal layer 4 and the first substrate 1. Based on this, the first pixel electrode 21 and the first common electrode 22 can be disposed on the same layer, or the two can be disposed on different layers.

[0239] For example, for example Figure 10 As shown, the first common electrode 22 is disposed on the side of the first pixel electrode 21 away from the first substrate 1. In this case, the display panel 100 further includes a first spacer layer 31 (for example, an insulating layer) disposed between the first pixel electrode 21 and the first common electrode 22. Of course, the first common electrode 22 can also be disposed on the side of the first pixel electrode 21 close to the first substrate 1.

[0240] See Figure 10 , the following takes the case where the first pixel electrode 21 and the first common electrode 22 are both disposed between the liquid crystal layer 4 and the first substrate 1 as an example to illustrate some embodiments of the present disclosure.

[0241] In some embodiments of the present disclosure, the second pixel electrode 31 and the second common electrode 32 can be both disposed on the same side of the liquid crystal layer 4, or can be respectively disposed on both sides of the liquid crystal layer 4.

[0242] In the case where the display panel 100 includes a plurality of second pixel circuits 3, for example, the second common electrodes 32 of the plurality of second pixel circuits 3 can be an integral structure, and the part of the second common electrode layer corresponding to the region defined by each second pixel circuit 3 is a second common electrode 32.

[0243] For another example, multiple second common electrodes 32 are spaced apart from each other. In this way, compared with multiple second pixel circuits 3 sharing one second common electrode 32, the area of the second common electrode 32 separately provided for each second pixel circuit 3 is smaller, and the resistance is also smaller. Accordingly, the power consumption of the second pixel circuit 3 is smaller. In this case, the multiple second common electrodes 32 can also be connected to each other through connection leads, and the connection leads can be provided on the same layer as the multiple second common electrodes 32, or on one side of the film layer where the multiple second common electrodes 32 are located, closer to / away from the first substrate 1.

[0244] The above is only an exemplary illustration of some possible implementation manners of the present disclosure, and does not limit the present disclosure.

[0245] When both the second pixel electrode 31 and the second common electrode 32 are provided on the same side of the liquid crystal layer 4, the second pixel electrode 31 and the second common electrode 32 can both be provided between the liquid crystal layer 4 and the first substrate 1. Based on this, the second pixel electrode 31 and the second common electrode 32 can be provided on the same layer, or they can be provided on different layers.

[0246] For example, as Figure 10 shown, the second common electrode 32 is provided on the side of the second pixel electrode 31 away from the first substrate 1. In this case, the display panel 100 further includes a second spacer layer 32 (for example, an insulating layer) provided between the second pixel electrode 31 and the second common electrode 32. Of course, the second common electrode 32 can also be provided on the side of the second pixel electrode 31 closer to the first substrate 1.

[0247] See Figure 10 , the following takes the case where both the second pixel electrode 31 and the second common electrode 32 are provided between the liquid crystal layer 4 and the first substrate 1 as an example to illustrate some embodiments of the present disclosure.

[0248] In some embodiments, as Figure 10 shown, the first pixel electrode 21 is provided on the same layer as the second pixel electrode 31.

[0249] In some examples, the first pixel electrode 21 and the second pixel electrode 31 are made of the same material. For example, both are made of a transparent conductive material, where the transparent conductive material can be ITO, IZO, etc.

[0250] When the first pixel electrode 21 and the second pixel electrode 31 are made of the same material, the first pixel electrode 21 and the second pixel electrode 31 can be formed simultaneously through a single preparation process, thereby reducing the preparation steps of the display panel 100.

[0251] In some other examples, the materials of the first pixel electrode 21 and the second pixel electrode 31 are different. When the materials of the first pixel electrode 21 and the second pixel electrode 31 are different, the first pixel electrode 21 and the second pixel electrode 31 can be formed separately and are both disposed on the same insulating material layer.

[0252] In some embodiments, as Figure 10 shown, the first common electrode 22 and the second common electrode 32 are disposed on the same layer.

[0253] The first common electrode 22 and the second common electrode can be formed of the same material. For example, both are made of a transparent conductive material, where the transparent conductive material can be ITO (indium tin oxide) or IZO (indium zinc oxide), etc.

[0254] When the materials of the first common electrode 22 and the second common electrode 32 are the same, the first common electrode 22 and the second common electrode 32 can be formed simultaneously through a single preparation process, thereby reducing the preparation steps of the display panel 100. Moreover, the first common electrode 22 and the second common electrode 32 can be a whole film layer structure or can be independently and separately disposed.

[0255] In some embodiments, as Figure 9 and Figure 10 shown, the first spacer layer 23 and the second spacer layer 33 are disposed on the same layer.

[0256] The first spacer layer 23 and the second spacer layer 33 disposed on the same layer can be formed simultaneously through a single preparation process, thereby reducing the preparation steps of the display panel 100.

[0257] Exemplarily, the first spacer layer 23 and the second spacer layer 33 are made of an insulating material.

[0258] The materials of the first spacer layer 23 and the second spacer layer 33 include but are not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc.

[0259] In some embodiments, as Figure 10 shown, the display panel 100 further includes: a first alignment layer Q1 disposed on one side of the liquid crystal layer 4 close to the first substrate 1, and a second alignment layer Q2 disposed on one side of the liquid crystal layer 4 close to the second substrate 6.

[0260] By providing the first alignment layer Q1 and the second alignment layer Q2, the liquid crystal molecules in the liquid crystal layer 4 are initially aligned, that is, the arrangement direction of the liquid crystal molecules when no electric field is applied is determined. Based on this, the first alignment layer Q1 and the second alignment layer Q2 are respectively disposed on opposite sides of the liquid crystal layer 4 and are in contact with the liquid crystal layer 4.

[0261] Figure 13 andFigure 14 It is an enlarged structural diagram of the first common electrode and the second common electrode. To facilitate a clear description of the structures of the first common electrode and the second common electrode, only part of the first common electrode and the second common electrode are shown in the figure, and the number of the first common electrode and the second common electrode in the display panel is not limited to that shown in the figure.

[0262] In some embodiments, as Figure 13 shown, the first common electrode 22 has a first slit 221, and the second common electrode 32 has a second slit 321.

[0263] By providing the first slit 221, the surface resistance of the first common electrode 22 can be reduced, thereby reducing the power consumption of the display panel 100. By providing the second slit 321, the surface resistance of the second common electrode 32 can be reduced, thereby reducing the power consumption of the display panel 100.

[0264] A plurality of first slits 221 can form at least one slit group XF1', and each slit group XF1' can be correspondingly arranged with a first sub-pixel region P1. A plurality of second slits 321 can form at least one slit group XF1, and each slit group XF1 can be correspondingly arranged with a second sub-pixel region P2.

[0265] The number, shape, etc. of the first slit 221 and the second slit 321 are not limited and can be arbitrarily set according to needs.

[0266] Hereinafter, the shapes of the first slit 221 and the second slit 321 being "<" or ">" are taken as examples for illustration.

[0267] In some embodiments, the first alignment layer Q1 and the second alignment layer Q2 are both rubbing alignment layers, as Figure 13 shown, the shapes of the first slit 221 and the second slit 321 are the same.

[0268] In some other embodiments, the first alignment layer Q1 and the second alignment layer Q2 are both photo-alignment layers, as Figure 13 or Figure 14 shown, the shapes of the first slit 221 and the second slit 321 are the same or different.

[0269] The fact that the shapes of the first slit 221 and the second slit 321 are the same or different as mentioned above means that the bending directions of the first slit 221 and the second slit 321 are the same or different. Hereinafter, the preparation methods of the first alignment layer Q1 and the second alignment layer Q2 will be described.

[0270] In some embodiments, as Figure 15 shown, a preparation method of an array substrate, the preparation method includes the following steps.

[0271] S1. Form a first alignment layer Q1 on a first substrate 1; the first substrate 1 has a display area AA and a light-transmissive area BB located on at least one side of the display area AA.

[0272] S2. Form a first common electrode 22 and a second common electrode 32 on the first alignment layer Q1; the first common electrode 22 is located within the display area AA, and the second common electrode 32 is located within the light-transmissive area BB; the first common electrode 22 has a plurality of first slits 221, and the second common electrode 32 has a plurality of second slits 321.

[0273] Among them, the first alignment layer Q1 and the second alignment layer Q2 are formed by a rubbing alignment process, and the shapes of the first slits 221 and the second slits 321 are the same; alternatively, the first alignment layer Q1 and the second alignment layer Q2 are formed by a photo-alignment process, and the shapes of the first slits 221 and the second slits 321 are the same or different.

[0274] In the case where the first alignment layer Q1 and the second alignment layer Q2 are formed by a rubbing alignment process, the alignment directions of the alignment grooves formed by the first alignment layer Q1 in the regions corresponding to the display area AA and the light-transmissive area BB are the same. Correspondingly, the directions of the first slits 221 on the first common electrode 22 and the second slits 321 on the second common electrode 32 need to be kept consistent to ensure the display effect of the display panel 100.

[0275] In the case where the first alignment layer Q1 and the second alignment layer Q2 are formed by a photo-alignment process, the alignment directions of the alignment grooves formed by the first alignment layer Q1 in the regions corresponding to the display area AA and the light-transmissive area BB can be the same or different. Correspondingly, the first slits 221 on the first common electrode 22 and the second slits 321 on the second common electrode 32 can be the same or different.

[0276] Figure 16 and Figure 18 is a plan view structure diagram of the display panel 100. To facilitate a clear description of the positional relationship between the circuit structure 7 and the light-transmissive area BB, Figure 16 only the sealing frame portion 5, the circuit structure 7, and part of the first common electrode 22, etc. are shown. Figure 18 only the sealing frame portion 5, the circuit structure 7, the first common electrode line COM1, the common electrode sub-line Vcom, and part of the first common electrode 22, etc. are shown. It can be understood that the display panel 100 also includes the remaining structures other than Figure 16 and Figure 18 the structures shown therein.

[0277] In some embodiments, as Figure 16 shown, the display panel 100 further includes: a circuit structure 7 located outside the display area AA, and the circuit structure 7 and the light-transmissive area BB are arranged side by side along the extension direction of at least one side boundary of the display area AA.

[0278] As Figure 7 and Figure 16 shown, when the display panel 100 includes one or more (two or more) light-transmitting regions BB on one side of the display region AA, the circuit structure 7 may be arranged side by side along the extension direction of the one-side boundary of the light-transmitting region BB along the display region AA.

[0279] As Figure 4 shown, when the display panel 100 includes at least one light-transmitting region BB on both sides of the display region AA, the circuit structure 7 may also be arranged side by side along the extension direction of the multi-side (two sides or more) boundaries of the display region AA.

[0280] Among them, the circuit structure 7 only needs to include a conductive pattern. In the display panel 100, the circuit structure 7 can be powered on and cannot be unpowered. The circuit structure 7 includes, for example, at least one of a common electrode line COM, a ground line GND, and a third pixel circuit 8.

[0281] As Figure 16 and Figure 17 shown, in this embodiment, the design of arranging the circuit structure 7 side by side with the light-transmitting region BB along the boundary extension direction of the display region AA is adopted. Compared with the design where the light-transmitting region BB is located on the side of the circuit structure 7 away from the display region AA, or the light-transmitting region BB is located between the circuit structure 7 and the light-transmitting region BB, since in this embodiment, the light-transmitting region BB occupies a part of the original position of the circuit structure 7, there is no need to additionally provide a layout space for the light-transmitting region BB in the width direction of the border AN of the display panel 100. Therefore, the size d4 in the width direction of the border AN of the display panel 100 can correspondingly be smaller, which is beneficial to realizing the narrow-border design of the display panel 100.

[0282] As Figure 17 shown, there may be a gap d5 between the circuit structure 7 and the light-transmitting region BB, and the gap d5 is less than or equal to the external dimension of the light-transmitting region BB, such as the dimension of the light-transmitting region BB along the second direction Y.

[0283] Exemplarily, d5≥6μm. The gap d5 between the circuit structure 7 and the light-transmitting region BB may be 6μm, 6.3μm, 8.5μm, etc.

[0284] Specifically, the circuit structure 7 includes a conductive pattern arranged on the same layer as the second common electrode 32, and there is a gap d5 between the conductive pattern and the second common electrode 32.

[0285] In some embodiments, as Figure 18As shown, the display panel 100 further includes a bonding area BA (Bonding Area) located on one side of the display area AA, and the circuit board 200 is electrically connected to the circuit board 200 within the bonding area BA.

[0286] Exemplarily, at least one second pixel circuit 3 is disposed within the light-transmitting area BB. As Figure 19 and Figure 22 shown, a plurality of second pixel circuits 3 are disposed within the light-transmitting area BB, and the plurality of second pixel circuits 3 are arranged in multiple rows and multiple columns.

[0287] Each row of second pixel circuits 3 is coupled to, for example, a second gate line GL2. As Figure 19 and Figure 22 shown, the second gate line GL2 is led out, for example, from the gap between the second common electrode 32 and the circuit structure 7, and is led out from the side of the second common electrode 22 and the circuit structure 7 close to the display area AA to the bonding area BA.

[0288] In this case, as Figure 19 shown, multiple rows of second pixel circuits 3 are respectively coupled to multiple second gate lines GL2. Of course, as Figure 22 shown, multiple rows of second pixel circuits 3 may also be coupled to the same second gate line GL2. At this time, as Figure 20 and Figure 21 shown, a light-emitting period Tf of the light-transmitting area BB refers to the duration when all the second gate lines GL2 provide a working level to the second pixel circuits 3 coupled thereto once.

[0289] For example, as Figure 19 shown, each row of second pixel circuits 3 is coupled to a second gate line GL2, and multiple rows of second pixel circuits 3 are respectively coupled to multiple second gate lines GL2. The multiple second gate lines GL2 may provide a working level to the multiple rows of second pixel circuits 3 simultaneously, or provide a working level to each row of second pixel circuits 3 in sequence. At this time, a light-emitting period Tf of the light-transmitting area BB refers to the duration when the multiple second gate lines GL2 provide a working level to the multiple rows of second pixel circuits 3 once.

[0290] Again, for example, as Figure 22 shown, multiple rows of second pixel circuits 3 are coupled to the same second gate line GL2, and the duration when the second gate line GL2 provides a working level to the multiple rows of second pixel circuits 3 once is a light-emitting period Tf.

[0291] Each column of second pixel circuits 3 is coupled to, for example, a second data line DL2. The second data line DL2 is led out, for example, from the side of the second common electrode 22 and the circuit structure 7 close to the display area AA to the bonding area BA.

[0292] In some embodiments, the circuit structure 7 includes a part of the first common electrode line COM1. Exemplarily, asFigure 16 and Figure 18 As shown, the first common electrode line COM1 can have one end close to the light-transmitting region BB and the other end extending along the boundary of the display region AA to the bonding region BA. In this way, a part of the first common electrode line COM1 is arranged side by side with the light-transmitting region BB, and the other part extends into the bonding region BA and is not arranged side by side with the light-transmitting region BB. The circuit structure 7 includes the part of the first common electrode line COM1 arranged side by side with the light-transmitting region BB.

[0293] As Figure 18 shown, the first common electrode line COM1 is electrically connected to the first common electrode 22.

[0294] The first common electrode line COM1 and the first common electrode can be formed in the same process step. With such a design, it is beneficial to simplify the preparation steps of the display panel 100.

[0295] Exemplarily, as Figure 18 shown, the display panel 100 further includes a plurality of common electrode sub-lines Vcom. At least part of the common electrode sub-lines Vcom is located in the display region AA and is electrically connected to the second common electrode 22 within the display region AA. At least one end of the common electrode sub-lines Vcom extends outside the display region AA and is electrically connected to the first common electrode line COM1.

[0296] Based on this, the first common electrode line COM1 and the first common electrode 22 can be electrically connected through the common electrode sub-lines Vcom.

[0297] The first common electrode line COM1 and the first common electrode 22 can be arranged on the same layer, or they can be arranged on different layers.

[0298] When the first common electrode line COM1 and the first common electrode 22 are arranged on the same layer, the common electrode sub-lines Vcom can be arranged on the same layer as the first common electrode 22, or the two can be arranged on different layers.

[0299] When the common electrode sub-lines Vcom and the first common electrode 22 are arranged on different layers, the common electrode sub-lines Vcom can be arranged on the side of the first common electrode 22 close to / away from the first substrate 1.

[0300] In some embodiments, as Figure 20 and Figure 22 shown, the first common electrode line COM1 is electrically connected to the second common electrode 32.

[0301] In this embodiment, the second common electrode 32 occupies a part of the original position of the first common electrode line COM1. Therefore, there is no need to additionally provide a layout space for the second common electrode 32 in the width direction of the border AN of the display panel 100. Accordingly, the size d4 in the width direction of the border AN of the display panel 100 can also be smaller, which is conducive to realizing the narrow border design of the display panel 100.

[0302] In some embodiments, as Figure 20 and Figure 22 shown, the first common electrode line COM1 and the second common electrode 32 are provided on the same layer and there is a gap g between them. The display panel 100 further includes: a connection line 9, the connection line 9 is located on one side of the second common electrode 32 close to or away from the first substrate, and straddles the gap g; the first common electrode line COM1 is electrically connected to the second common electrode 32 through the connection line 9.

[0303] The first common electrode line COM1 and the second common electrode 32 transmit the same electrical signal, which is a common voltage signal. Therefore, the first common electrode line COM1 and the second common electrode 32 can be an integral film layer structure. In this embodiment, by setting the first common electrode line COM1 and the second common electrode 32 to be spaced apart from each other, in this way, the area of the second common electrode 32 is smaller than that when they are a film layer structure. In this way, the resistance of the second common electrode 32 is smaller, the power consumption of the second pixel circuit 3 is reduced, and thus the power consumption of the display panel 100 is reduced.

[0304] Exemplarily, the connection line 9 can be made of conductive materials such as metal materials and alloy materials. For example, the material of the connection line 9 includes but is not limited to at least one of gold, silver, copper, aluminum, nickel, or nickel gold, etc.

[0305] Exemplarily, the connection line 9 can be provided on one side of the second common electrode 32 close to or away from the first substrate 1.

[0306] In some embodiments, the first common electrode 22, the second common electrode 32 and the common electrode line COM are provided on the same layer. Therefore, in the process of manufacturing the display panel 100, the first common electrode 22, the second common electrode 32 and the common electrode line COM can be formed in the same process step, thereby reducing the manufacturing steps of the display panel 100.

[0307] By designing the first common electrode 22, the second common electrode 32 and the common electrode line COM to be spaced apart from each other, in this way, the first common electrode 22, the second common electrode 32 and the common electrode line COM are independently arranged. Compared with the design where the first common electrode 22, the second common electrode 32 and the common electrode line COM are integrally connected in a whole layer, the surface resistance of the first common electrode 22, the second common electrode 32 and the common electrode line COM can be reduced, thereby reducing the power consumption of the display panel 100.

[0308] Moreover, the first common electrode 22, the second common electrode 32 and the common electrode line COM can be connected to the same electrical signal. Therefore, by setting the connection line 9, the independently separated first common electrode 22, the second common electrode 32 and the common electrode line COM can be connected to each other, thereby realizing the electrical connection between the first common electrode 22, the second common electrode 32 and the common electrode line COM.

[0309] In some embodiments, as Figure 19 shown, the first common electrode line COM1 has a plurality of first hollow portions 71. For example, the plurality of first hollow portions 71 can form at least one hollow group XF2, and the shapes of the first hollow portions 71 in each hollow group XF2 are the same as or similar to a group of slits XF1 in a sub-pixel region (such as the second sub-pixel region P2) of the second common electrode 32.

[0310] During the preparation process of the display panel 100, when there are a plurality of second slits 321 on the second common electrode, it can be a conductive film layer formed in a whole layer by the same film-forming process, and the first patterning process is performed on the conductive film layer to form the second slits 321 in the light-transmitting region BB; then, the second patterning process is performed on the conductive film layer to form the spaced-apart first common electrode line COM1 and the second common electrode 32. In this way, during the second patterning process, due to reasons such as process accuracy, one or more second pixel electrodes 32 in the finally formed light-transmitting region BB may not have the second slits 321, or the number of the second slits 321 is less than the designed number.

[0311] In this embodiment, by providing a plurality of first hollow portions 71 on the first common electrode line COM1, in this way, a plurality of second slits 321 and a plurality of first hollow portions 71 can be formed simultaneously in the first patterning process. Therefore, during the second patterning process, it can be ensured that the finally formed second common electrode 32 has a plurality of second slits 321.

[0312] In some embodiments, as Figure 23 shown, the connection line 9 extends to the region where the first common electrode line COM1 is located, and is electrically connected to the first common electrode line COM1 through a plurality of connection points in the region where the first common electrode line COM1 is located.

[0313] Exemplarily, in the direction perpendicular to the first substrate 1, when the connection line 9 and the first common electrode line COM1 are in different conductive film layers, an insulating film layer is further provided between the conductive film layer where the connection line 9 is located and the conductive film layer where the first common electrode line COM1 is located. The connection point can be a connection hole penetrating the insulating film layer, and the conductive film layer where the connection line 9 is located is connected to the conductive film layer where the first common electrode line COM1 is located through the connection hole penetrating the insulating film layer. At this time, each connection hole serves as a connection point, and each first common electrode line COM1 is electrically connected to the first common electrode line COM1 through a plurality of connection holes.

[0314] Of course, in some other embodiments, each first common electrode line COM1 can also be electrically connected to the first common electrode line COM1 through a connection hole. In this case, the connection line 9 extends to the area where the first common electrode line COM1 is located, and is electrically connected to the first common electrode line COM1 through a connection point in the area where the first common electrode line COM1 is located.

[0315] In some other embodiments, as Figure 23 shown, the display panel 100 includes a plurality of second common electrodes 32, and the plurality of second common electrodes 32 are connected into an integral structure. The connection line 9 extends to the light-transmitting area BB, and is electrically connected to the integral structure through a plurality of connection points in the light-transmitting area BB.

[0316] By electrically connecting the connection line 9 to the second common electrode 32, the resistance of the second common electrode 32 can be reduced, thereby reducing the power consumption of the second pixel circuit 3, and further reducing the power consumption of the display panel 100.

[0317] When the display panel 100 includes a plurality of (two or more) second common electrodes 32, the plurality of second common electrodes 32 can be an integral structure formed integrally, or can be formed into an integral structure by being connected to each other through connection leads. The plurality of second common electrodes 32 are connected to each other. Therefore, the connection points of the connection line 9 with the integral structure can be that at least one (one or more) connection points are respectively provided corresponding to each second common electrode 32, or a plurality of connection points are provided corresponding to one of the second common electrodes 32.

[0318] In still some other embodiments, as Figure 23 shown, one end of the connection line 9 extends to the area where the first common electrode line COM1 is located, and is electrically connected to the first common electrode line COM1 through a plurality of connection points in the area where the first common electrode line COM1 is located; the other end of the connection line 9 extends to the light-transmitting area BB, and is electrically connected to the integral structure through a plurality of connection points in the light-transmitting area BB.

[0319] This embodiment can be a combination of the above two embodiments, having the same structure and technical effects, which will not be elaborated here.

[0320] In this embodiment, by arranging the connection line 9 to extend to the light-transmitting area BB and electrically connect to a plurality of second common electrodes 32, the effect of better reducing the resistance of the second common electrode 32 can be achieved, which is beneficial to realizing the low-power design of the display panel 100.

[0321] Moreover, in this embodiment, by arranging the connection line 9 to extend to the area where the first common electrode line COM1 is located and electrically connect to the first common electrode line COM1 through a plurality of connection points, in this way, compared with the case where the connection line 9 is not arranged, or the connection line 9 is electrically connected to the first common electrode line COM1 through one connection point, the resistance value of the first common electrode line COM1 is lower, and thus the power consumption of the first common electrode line COM1 is lower, which is beneficial to realizing the low-power design of the display panel 100.

[0322] In some embodiments, such as Figure 23 and Figure 24 shown, the display panel 100 further includes: a second common electrode line COM2, electrically connected to the first common electrode 22; the width of the first common electrode line COM1 is greater than the width of the second common electrode line COM2.

[0323] In the display panel 100 including multiple common electrode lines, the second common electrode 22 occupies a part of the position of the wider one of the original multiple common electrode lines COM. Therefore, there is no need to additionally provide a layout space for the second common electrode 32 in the width direction of the border AN of the display panel 100. Therefore, the size d4 in the width direction of the border AN of the display panel 100 can correspondingly be smaller, which is beneficial to realizing the narrow-border design of the display panel 100.

[0324] For example, as Figure 23 and Figure 24 shown, the display panel 100 includes a first common electrode line COM1 and a second common electrode line COM2, and the width of the first common electrode line COM1 is greater than the width of the second common electrode line COM2. The wider one of the first common electrode line COM1 and the second common electrode line COM2 is arranged side by side with the light-transmitting area BB along the boundary extension direction of the display area AA, and the second common electrode 32 occupies a part of the original position of the first common electrode line COM1.

[0325] Such as Figure 23 and Figure 24 shown, the first common electrode line COM1 can be arranged on one side of the second common electrode line COM2 close to or far from the display area AA. Specifically, it can be selected according to design requirements, and the present disclosure does not limit this.

[0326] In some embodiments, as Figure 23 and Figure 24 shown, the display panel 100 further includes: at least one common electrode line COM, and at least one common electrode line COM is electrically connected to the first common electrode 22.

[0327] The fact that at least one common electrode line COM is electrically connected to the first common electrode 22 means that in the case where the display panel 100 includes one common electrode line COM, the common electrode line COM is electrically connected to the first common electrode 22; or, in the case where the display panel 100 includes a first common electrode line COM1 and a second common electrode line COM2, at least one of the first common electrode line COM1 and the second common electrode line COM2 is electrically connected to the first common electrode 22.

[0328] In the case where the display panel 100 includes multiple common electrode lines COM, the relative positional relationship of the multiple common electrode lines COM in the direction perpendicular to the boundary of the display area AA is not limited. For example, the display panel 100 includes a first common electrode line COM1 and a second common electrode line COM2, as Figure 23 shown, the first common electrode line COM1 may be disposed on a side of the second common electrode line COM2 close to the display area AA; or, as Figure 24 shown, the first common electrode line COM1 may also be disposed on a side of the second common electrode line COM2 away from the display area AA.

[0329] In some embodiments, as Figure 25 shown, the display panel 100 further includes an electrostatic protection circuit ESD (ElectroStatic discharge) and a ground wire GND, and the ground wire GND is electrically connected to the electrostatic protection circuit ESD.

[0330] The electrostatic protection circuit ESD includes, for example, multiple protection transistors, and the drains of the protection transistors are electrically connected to the ground wire GND, so as to conduct the static electricity existing in the display panel 100 through the ground wire GND to form an electrostatic discharge channel, thereby avoiding the influence of static electricity on the first pixel circuit 2 and the second pixel circuit 3.

[0331] Based on this, in some embodiments, as Figure 25 shown, the circuit structure 7 includes a part of the ground wire GND, and the ground wire GND is electrically insulated from the first common electrode 22 and is electrically insulated from the second common electrode 32.

[0332] The second common electrode 32 occupies a portion of the original ground line GND, so there is no need to provide additional layout space for the second common electrode 32 in the width direction of the frame AN ​​of the display panel 100. Therefore, the dimension d4 in the width direction of the frame AN ​​of the display panel 100 can be correspondingly smaller, which is conducive to realizing the narrow frame design of the display panel 100.

[0333] In some embodiments, the ground line GND and the second common electrode 32 are disposed in the same layer with a gap therebetween; and / or the second common electrode 32 is electrically connected to one of the at least one common electrode line COM.

[0334] Exemplarily, the common electrode line COM is arranged outside the display area AA, and in the orthographic projection to the first substrate 1, the common electrode line COM does not overlap with the light-transmitting area BB. In this case, the common electrode line COM may be made of a metal material. When the second common electrode 32 is made of a transparent conductive material, such as ITO, the resistance of the second common electrode 32 is relatively large. By electrically connecting the second common electrode 32 to the common electrode line COM made of a metal material, the resistance of the second common electrode 32 can be reduced, thereby reducing the power consumption of the display panel 100.

[0335] The second common electrode 32 may occupy a portion of at least one of the original common electrode lines COM (for example, the first common electrode line COM1 and the second common electrode line COM2) and the ground line GND. There is no need to provide additional layout space for the second common electrode 32 in the width direction of the frame AN ​​of the display panel 100, which is conducive to realizing a narrow frame design of the display panel 100.

[0336] It should be noted that, in the direction perpendicular to the extending direction of the boundary line of the display area AA, the relative position relationship between the first common electrode line COM1, the second common electrode line COM2, the ground line GND and the electrostatic protection circuit ESD can be adaptively designed as needed, such as Figure 23 , Figure 24 , Figure 25 and Figure 26 Only some possible relative position relationships among the first common electrode line COM1 , the second common electrode line COM2 , the ground line GND and the electrostatic protection circuit ESD are shown, which is not intended to limit the present disclosure.

[0337] To ensure the display quality of the display panel 100, the thickness of each film layer structure in the display area AA needs to be kept consistent, that is, in the multi-layer film layer structure arranged on the first substrate 1, the distance between each position on the same film layer structure and the first substrate 1 should be the same or approximately the same.

[0338] During the manufacturing process of the display panel 100, when forming the multiple first pixel circuits 2 within the display area AA, taking the formation of the first pixel electrodes 21 as an example, it may be that a conductive film layer is first formed using a film-forming process, and then the conductive film layer is patterned to form multiple first pixel electrodes 21.

[0339] When forming the conductive film layer, the thickness of the edge portion of the conductive film layer is thinner than that of the middle portion. Thus, the actual thickness of the first pixel electrodes 21 located on the periphery among the multiple first pixel electrodes 21 is thinner than the required thickness. As a result, it may cause a problem of abnormal light emission in the first sub-pixel region P1 corresponding to the first pixel electrodes 21 on the periphery.

[0340] Based on this, during the manufacturing process of the display panel 100, multiple third pixel circuits 8 can be formed simultaneously while manufacturing the first pixel circuits 2. The third pixel circuits 8 are located outside the display area AA, and the region defined by the third pixel circuits 8 does not emit light.

[0341] The multiple third pixel circuits 8 can be arranged side by side along the extending direction of the boundary line of the display area AA. The third pixel circuit 8 includes a third pixel electrode 81 and a third common electrode 82. The third pixel electrode 81 is provided on the same layer as the first pixel electrode 21, and the third common electrode 82 and the first common electrode 22 are of an integral structure.

[0342] In this way, the third pixel circuits 8 are formed while forming the first pixel circuits 2. During the process of forming the first pixel electrodes 21 and the first common electrodes 22, the first pixel electrodes 21 and the first common electrodes 22 obtained by patterning the conductive film layer have good thickness uniformity. The edge portion of the conductive film layer corresponds to the third pixel circuits 8. Since the third pixel circuits 8 are located outside the display area AA, they will not affect the picture display quality within the display area AA of the display panel 100.

[0343] Based on this, in some embodiments of the present disclosure, as Figure 26 shown, the display panel 100 further includes third pixel circuits 8 located outside the display area AA. The third pixel circuits 8 may have the same structure as the first pixel circuits 2. For example, the third pixel circuit 8 includes a third pixel electrode 81 and a third common electrode 82.

[0344] Exemplarily, the third pixel circuits 8 are also located outside the light-transmitting area BB.

[0345] In some embodiments, the third pixel circuit 8 may be a dummy pixel circuit. Although it has the same structure as a normal display pixel circuit (e.g., the first pixel circuit 2), the circuit board 200 may not apply an electrical signal to the third pixel circuit 8. In this case, in the direction perpendicular to the first substrate 1, the third pixel circuit 8 is located within the range of the black matrix layer BM, and the light emitted from the region defined by the third pixel circuit 8 is blocked by the black matrix layer BM. By providing the third pixel circuit 8, the manufacturing steps of the display panel 100 are not additionally increased, and moreover, the thickness differences caused by the manufacturing process between the plurality of first pixel electrodes 21 and the first common electrode 22 in the display area AA can be avoided.

[0346] In some other embodiments, the circuit board 200 is further configured to apply an electrical signal to the third pixel circuit 8. The above light-transmitting region BB is referred to as the first light-transmitting region BB1, at least a part of the third pixel circuit 8 is located in the second light-transmitting region BB2, the second light-transmitting region BB2 is located outside the display area AA and has no overlap with the first light-transmitting region BB1. In this case, in the direction along the perpendicular to the first substrate 1, the black matrix layer BM is further provided with an opening region corresponding to the third pixel circuit 8 within the second light-transmitting region BB2, and the light emitted from the region defined by the third pixel circuit 8 is not blocked by the black matrix layer BM.

[0347] Based on this, in some embodiments, the first common electrode line COM1 and the first common electrode 21 are provided on the same layer. Based on this, the third common electrode 82 and the first common electrode line COM1 are provided on the same layer. The third common electrode 82 and the first common electrode line COM1 may be an integral structure, or there may be a gap between the two.

[0348] Exemplarily, as Figure 26 shown, the third common electrode 82 and the first common electrode line COM1 are an integral structure.

[0349] In some embodiments, as Figure 26 shown, the circuit structure 7 includes: a third pixel circuit 8. The third pixel circuit 8 is located outside the display area AA. Therefore, the second common electrode 22 occupying at least a part of the original third pixel circuit 8 does not affect the normal picture display of the display area AA of the display panel 100, and is conducive to implementing the narrow border design of the display panel 100.

[0350] Exemplarily, the third common electrode 82 and the second common electrode 32 are disposed on the same layer. In this way, the second common electrode 32 and the third common electrode 82 are formed simultaneously through a single film-forming process. The second common electrode 32 occupies a part of the original position of the third common electrode 82. Therefore, there is no need to additionally provide a layout space for the second common electrode 32 in the width direction of the border AN of the display panel 100. Accordingly, the dimension d4 in the width direction of the border AN of the display panel 100 can also be smaller, which is conducive to implementing the narrow-border design of the display panel 100.

[0351] Exemplarily, as Figure 26 shown, the third common electrode 82, the second common electrode 32, and the first common electrode line COM1 are disposed on the same layer. In this way, the second common electrode 32 occupies a part of the original positions of the third common electrode 82 and the first common electrode line COM1. Therefore, there is no need to additionally provide a layout space for the second common electrode 32 in the width direction of the border AN of the display panel 100. Accordingly, the dimension d4 in the width direction of the border AN of the display panel 100 can also be smaller, which is conducive to implementing the narrow-border design of the display panel 100.

[0352] The specific structures of the first pixel circuit 2 and the second pixel circuit 3 will be introduced below.

[0353] In some embodiments, as Figure 27 and Figure 28 shown, the display panel 100 further includes: a first gate line GL1, a first data line DL1, and a first transistor T1 located in the display area AA. The first gate line GL1 is electrically connected to the first transistor T1, and the first data line DL1 is coupled to the first pixel electrode 21 through the first transistor T1.

[0354] Exemplarily, as Figure 27 shown, the control electrode of the first transistor T1 is electrically connected to the first gate line GL1, the first electrode of the first transistor T1 is electrically connected to the first data line DL1, and the second electrode of the first transistor T1 is electrically connected to the first pixel electrode 21.

[0355] The first transistor T1 is configured to transmit the first data signal provided by the first data line DL1 to the first pixel electrode 21 under the control of the voltage of the first gate line GL1.

[0356] The multiple first sub-pixel areas P1 included in the display area AA are arranged in an array, for example. The first sub-pixel areas P1 with the same emission color can be arranged in a row or a column. Of course, the arrangement manner of the multiple first sub-pixel areas P1 in the display area AA is not limited thereto. For the convenience of describing some embodiments of the present disclosure, some embodiments of the present disclosure will be described below by taking the example that the first sub-pixel areas P1 with the same emission color can be arranged in a column.

[0357] Accordingly, as Figure 28 shown, a plurality of first pixel circuits 2 in the display area AA are arranged in an array, for example.

[0358] As Figure 28 shown, each first gate line GL1 is coupled to a row of first pixel circuits 2. As Figure 27 and Figure 28 shown, each first gate line GL1 is electrically connected to the control electrodes of a plurality of first transistors T1 arranged in a row.

[0359] In some embodiments, as Figure 28 shown, the display panel 100 further includes a first gate lines GL1(m) and b first data lines DL1(n). Wherein, a, b, m, and n are positive integers, a≥m≥1, b≥n≥1.

[0360] Exemplarily, as Figure 28 shown, the first pixel circuits 2 located in the same column are coupled to the same first data line DL1(n), for example, and the first pixel circuits 2 located in the same row are coupled to the same first gate line GL1(m), for example.

[0361] At this time, a plurality of first pixel circuits 2 arranged in an array (a rows × b columns, a≥2, b≥2) are provided in the display area AA, for example, and the display area AA includes a plurality of first sub-pixel areas P1. Each first gate line GL1(m) provides a gate driving signal to the first pixel circuit 2 coupled thereto, for example.

[0362] In some embodiments, as Figure 28 and Figure 29 shown, the display panel 100 further includes: a second data line DL2 located in the light-transmitting area BB. The second data line DL2 is coupled to the second pixel electrode 31.

[0363] In some examples, as Figure 29 shown, the second data line DL2 is electrically connected to the second pixel electrode 31.

[0364] As Figure 29 and Figure 30 shown, in this case, the second sub-pixel area P2 emits light in response to the second data signal from the second data line DL2. When the second data signal is at the operating level, the second sub-pixel area P2 lights up and the light-transmitting area BB lights up; when the second data signal is at the non-operating level, the second sub-pixel area P2 does not emit light.

[0365] As Figure 29 and Figure 30As shown, during the light-emitting stage of the light-transmitting region BB, the second data line DL2 transmits a second data signal to the second pixel electrode 31 to drive the light-transmitting region BB to emit light. The light-emitting stage of the light-transmitting region BB includes at least one light-emitting cycle Ts. During the non-light-emitting stage Toff of the light-transmitting region BB, the light-transmitting region BB does not emit light.

[0366] As Figure 30 shown, to avoid the liquid crystal molecules in the liquid crystal layer 4 from solidifying, during the light-emitting stage of the light-transmitting region BB, the second data signal provided by the second data line DL2 is an electrical signal that alternates between positive and negative (for example, the voltage value corresponding to the second data signal alternates between +5V and -5V); during the non-light-emitting stage of the light-transmitting region BB, the second data line DL2 also transmits an electrical signal that alternates between positive and negative to the second pixel electrode 31, but the light-transmitting region BB does not emit light.

[0367] It should be noted that when the second pixel electrode 31 is electrically connected to the second data line DL2, the light-emitting state of the light-transmitting region BB and the working state of the sensor 300 in the sensor region CC may or may not be related. Specific adaptive designs can be made according to needs.

[0368] When the light-emitting state of the light-transmitting region BB is related to the working state of the sensor 300 in the sensor region CC, the second data signal provided by the second data line DL2 can be a synchronous data signal of the working state of the sensor. For example, when the sensor is in the working state, the second data signal provided by the second data line DL2 is a working level, and the light-transmitting region BB is lit; when the sensor is in the non-working state, the second data signal is a non-working level, and the light-transmitting region BB does not emit light.

[0369] In this way, whether the sensor 300 is in the working state can be intuitively shown by whether the light-transmitting region BB emits light. Of course, it can also be that different working states of the sensor 300 correspond to different colors of light emitted by the light-transmitting region BB.

[0370] The above is only an exemplary description of some specific embodiments of the present disclosure. The data signal input terminal connected to the second pixel electrode 31 can be selected according to needs. This is only an exemplary description of some possible embodiments and does not limit the present disclosure.

[0371] In other examples, as Figure 31 shown, the display panel 100 further includes: a second transistor T2. The second gate line GL2 is electrically connected to the second transistor T2, and the second data line DL2 is coupled to the second pixel electrode 31 through the second transistor T2.

[0372] Exemplarily, as Figure 31As shown, the control electrode of the second transistor T2 is electrically connected to the second gate line GL2, the first electrode of the second transistor T2 is electrically connected to the second data line DL2, and the second electrode of the second transistor T2 is electrically connected to the second pixel electrode 31.

[0373] The second transistor T2 is configured to transmit the second data signal provided by the second data line DL2 to the second pixel electrode 31 under the control of the voltage of the second gate line GL2.

[0374] As Figure 31 and Figure 32 shown, when the voltage transmitted from the second gate line GL2 to the control electrode of the second transistor T2 is at the operating level, the second transistor T2 is turned on, and the second data signal provided by the second data line DL2 can be transmitted to the second pixel electrode 32 through the second transistor T2.

[0375] As Figure 31 、 Figure 32 and Figure 33 shown, when the second gate line GL2 transmits an operating level to the control electrode of the second transistor T2 and the second data signal provided by the second data line DL2 is at the operating level, the light-transmitting area BB is lit.

[0376] In some embodiments, in the display panel 100, some of the plurality of first sub-pixel regions P1 and the plurality of second sub-pixel regions P2 are arranged in a column.

[0377] As Figure 31 and Figure 32 shown, when both the first pixel electrode 2 and the second pixel circuit 3 adopt an active driving method (the display panel 100 includes the first transistor T1 and the second transistor T2), the first pixel electrodes 21 and the second pixel electrodes 31 arranged in a column can be coupled to the same data line DL, or can be coupled to different data lines DL. When at least one of the first pixel circuit 2 and the second pixel circuit 3 adopts a passive driving method, the first pixel electrodes 21 and the second pixel electrodes 31 need to be respectively coupled to different data lines DL.

[0378] In some embodiments, as Figure 31 shown, the display panel 100 includes the first transistor T1 and the second transistor T2, and the second data line DL2 is electrically connected to the first data line DL1. The first pixel electrodes 21 and the second pixel electrodes 31 in the same column can be regarded as being coupled to the same data line DL. The part of the data line DL connected to the first transistor T1 is the first data line DL1, and the part connected to the second transistor T2 is the second data line DL2.

[0379] One frame of the display panel 100 includes a picture display phase and a blanking phase, and one light-emitting period Tf of the light-transmitting area BB is within one frame of the display panel 100. The first data line DL1 transmits a first data signal to the first pixel electrode 21 in the picture display phase, and transmits a second data signal to the second pixel electrode 31 in the light-emitting period Tf.

[0380] One frame of the display panel 100 refers to one frame of the display area AA, and one frame of the display area AA is, for example, one of the display frames mentioned above. In the display frame, the first pixel circuit 2 drives the liquid crystal molecules of the liquid crystal layer 4 in the area defined by the first pixel circuit 2 to move. The area defined by the first pixel circuit 2 is, for example, the first sub-pixel area P1 mentioned above.

[0381] Each display frame at least includes: a data writing phase, a picture display phase and a blanking phase.

[0382] In the data writing phase, the first data line DL1 transmits a display data signal to the first pixel electrode 21 coupled thereto, so as to drive the first sub-pixel region P1 to emit light for display.

[0383] In the blanking phase, the first data line DL1 transmits the second data signal to the second pixel electrode 31 coupled thereto, so as to drive the second sub-pixel region P2 to emit light.

[0384] With this design, time-division multiplexing of the first data line DL1 is achieved, and the same data line DL transmits electrical signals to the first pixel electrode 21 and the second pixel electrode 31 respectively in time-division, thereby reducing the number of data lines DL in the display panel 100 and simplifying the structure of the display panel 100.

[0385] Exemplarily, the light-emitting phase of the light-transmitting area BB includes at least one light-emitting period Tf. When the first pixel electrode 21 and the second pixel electrode 31 are coupled to the same data line DL, in the light-emitting phase of the light-transmitting area BB, the light-emitting period Tf of the light-transmitting area BB is shorter than the duration of the blanking phase of the display area AA.

[0386] The first data line DL1 transmits the second data signal to the second pixel electrode 31 in the blanking phase of the display area AA, and the light-emitting phase of the light-transmitting area BB includes at least one light-emitting period Tf. Therefore, the blanking phase of the display area AA is longer than the light-emitting period Tf.

[0387] Exemplarily, the first data line DL1 may transmit the second data signal to the second pixel electrode 31 during the blanking phase of each frame of the display area AA, or may transmit the second data signal to the second pixel electrode 31 during the blanking phase every k frames (k≥2).

[0388] like Figure 31 , Figure 32 andFigure 33 As shown, within the emission period Tf, the duration during which the voltage of the second gate line GL2 is at an effective level is less than the duration of the emission period Tf. Based on this, the first data line DL1 can continuously transmit a second data signal to the second pixel electrode 31 in the blanking stage in the display area AA, and the voltage of the second gate line GL2 can continuously be at an effective level or periodically be at an effective level within the blanking stage.

[0389] When multiple rows of second pixel circuits 3 included in the display panel 100 are all coupled to the same second gate line GL2, the duration for the second gate line GL2 to provide a working level to the multiple rows of second pixel circuits 3 once is one emission period Tf.

[0390] When each second gate line GL2 is coupled to one row of second pixel circuits 3, multiple rows of second pixel circuits 3 are respectively coupled to multiple second gate lines GL2. The multiple second gate lines GL2 can simultaneously provide a working level to the multiple rows of second pixel circuits 3, or the multiple second gate lines GL2 can sequentially provide a working level to the multiple rows of second pixel circuits 3. At this time, one emission period Tf of the light-transmitting area BB refers to the total duration for all the second gate lines GL2 to provide a working level to the multiple rows of second pixel circuits 3 once.

[0391] In some other embodiments, as Figure 32 shown, the display panel 100 includes a first transistor T1 and a second transistor T2. The second data line DL2 is insulated from the first data line DL1, and the first pixel electrode 21 and the second pixel electrode 31 in the same column are insulated from each other.

[0392] In some embodiments, as Figure 28 、 Figure 31 and Figure 32 shown, when the display panel 100 includes a first transistor T1, the display panel 100 further includes: a first gate driving circuit 12.

[0393] In some examples, as Figure 28 and Figure 34 shown, the first gate driving circuit 12 includes a first shift register unit SR1(j). The first shift register unit SR1(j) is disposed outside the display area AA. A single first shift register unit SR1(j) is, for example, coupled to one row of first pixel circuits 2. A single shift register SR1(j) is, for example, coupled to at least one first gate line GL1(m).

[0394] The first shift register unit SR1(j) can be within the liquid crystal sealing area SA.

[0395] In some other examples, as Figure 28 and Figure 34As shown, the gate driving circuit 12 includes k cascaded first shift registers SR1(j), and a single shift register SR1(j) is coupled to at least one first gate line GL1(m). Wherein, k and j are positive integers, k≥j≥1, and m≥k≥2.

[0396] Hereinafter, taking the case where each of the k cascaded shift registers SR1(j) is correspondingly coupled to a first gate line GL1(m), and each first gate line GL1(m) is coupled to a row of first pixel circuits 2 as an example for illustration.

[0397] In some embodiments, as Figure 34 shown, the first shift register SR1(j) includes a signal input terminal IPT, a first signal output terminal GOUT1, a second signal output terminal OUTC, and a reset signal terminal RST. The first signal output terminal GOUT1 of each stage of the shift register SR1(j) is coupled to the gate line G(m). The second signal output terminal OUTC of the j-th stage shift register SR1(j) is coupled to the signal input terminal IPT of the (j + 1)-th stage shift register SR1(j + 1), and the second signal output terminal OUTC of the j-th stage shift register SR1(j) is coupled to the reset signal terminal RST of the (j - 1)-th stage shift register SR1(j - 1).

[0398] Exemplarily, as Figure 34 shown, except for the first stage first shift register SR1(1), the signal input terminal IPT of each stage of the first shift register SR1(j) is coupled to the second signal output terminal OUTC of its previous stage shift register SR1(j - 1).

[0399] Except for the last stage first shift register SR1(k), the reset signal terminal RST of each stage of the first shift register SR1(j) is coupled to the second signal output terminal OUTC of its next stage shift register SR1(j + 1).

[0400] It should be noted that the above-mentioned first stage first shift register SR1(1) and the last stage first shift register SR1(k) are relative, and are determined according to the forward scan and reverse scan of the gate driving circuit 12.

[0401] When the gate driving circuit 12 is used to perform a forward scan on the first gate line GL1(m), according to the scan order of the first gate line GL1(m), the first first gate line GL1(1) is first input with a scan signal. Therefore, the first shift register SR1(j) that provides the scan signal to the first first gate line GL1(1) is the first stage first shift register SR1(1); the first shift register SR1(j) that provides the scan signal to the last first gate line GL1(a) is the last stage first shift register SR1(k).

[0402] The signal output from the second signal output terminal OUTC serves as the cascading signal for the gate driving circuit 12. The second signal output terminal OUTC of the j-th first shift register SR1(j) is coupled to the signal input terminal IPT of the (j + 1)-th first shift register SR1(j + 1), thereby triggering the (j + 1)-th first shift register SR1(j + 1). The second signal output terminal OUTC of the j-th first shift register SR1(j) is coupled to the reset signal terminal RST of the (j - 1)-th first shift register SR1(j - 1), causing the (j - 1)-th first shift register SR1(j - 1) to be reset.

[0403] When the gate driving circuit 12 is used to perform reverse scanning on the first gate line GL1(m), according to the scanning order of the first gate line GL1(m), the last first gate line GL1(a) is first input with the scanning signal. Therefore, the first shift register SR1(j) that provides the scanning signal to the first gate line GL1(a) is the first-stage first shift register SR1(1); the shift register that provides the scanning signal to the first first gate line GL1(1) is the last-stage first shift register SR1(k).

[0404] On the above basis, as Figure 34 shown, the signal input terminal IPT of the first-stage first shift register SR1(1) is coupled to the start signal terminal STV, for example, and the reset signal terminal RST of the last-stage first shift register SR1(k) is coupled to the above start signal terminal STV, for example.

[0405] Among them, the start signal terminal STV is used to output the start signal. The first-stage first shift register SR1(1) of the gate driving circuit 12 starts to perform line-by-line scanning on the first gate line GL1(m) after receiving the above start signal.

[0406] In this case, when the start signal of the start signal terminal STV is input to the signal input terminal IPT of the first-stage first shift register SR1(1), the reset signal terminal RST of the last-stage first shift register SR1(k) can use the start signal of the start signal terminal STV as the reset signal to reset the last-stage first shift register SR1(k).

[0407] Here, the reset signal terminal RST of the last-stage first shift register SR1(k) can also be separately set as an initialization signal terminal, and this initialization signal terminal can transmit a reset signal to the reset signal terminal RST of the last-stage first shift register SR1(k).

[0408] In some embodiments, the gate driving circuit 12 further includes, for example, peripheral signal traces, and the peripheral signal traces provide working signals for the first shift register SR1(j).

[0409] The first shift register SR1(j) is mainly composed of devices such as transistors and capacitors. During the operation of the first shift register SR1(j), the voltages of each node of the shift register (such as the first node PU1, the first pull-down point PD1, and the second pull-down node PD2) and the signal output terminals (such as the first signal output terminal GOUT1 and the second signal output terminal OUTC) are controlled by transistors, capacitors, etc., so as to realize the output of signals.

[0410] For example, a single first shift register SR1(j) transmits a signal to the first gate line GL1(m) coupled thereto, and each first gate line GL1(m) transmits the aforementioned electrical signal to a row of first pixel circuits 2 coupled thereto.

[0411] The signal output by a single first shift register SR1(j) is transmitted to a row of first pixel circuits 2 through a first gate line GL1(m), so as to control the brightness of the first sub-pixel region P1 of this row and realize color display.

[0412] Exemplarily, the transistors included in the first shift register SR1(j) include but are not limited to thin film transistors, field effect transistors, or other devices with the same characteristics.

[0413] The source electrode (source) of the transistor is called the first pole, and the drain electrode (drain) is called the second pole. Alternatively, the drain can be called the first pole and the source can be called the second pole. According to the form in the drawings, the middle end of the transistor is defined as the gate (which can also be called the gate electrode), the signal input terminal is the source, and the signal output terminal is the drain.

[0414] Exemplarily, the thin film transistors in the first shift register SR1(j) are all oxide transistors. For example, the material of the active layer of the thin film transistor is oxide.

[0415] The transistors adopted in the embodiments of the present disclosure can be P-type switching transistors or N-type switching transistors. The P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level; the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.

[0416] It should be noted that in the first shift register SR1(j) in the embodiments of the present disclosure, in actual use, the types of the transistors are not limited. Each transistor can be set as an N-type switching transistor or a P-type switching transistor according to needs. When the transistors in the shift register are N-type transistors, the effective level of each transistor is a high-level signal.

[0417] Correspondingly set the active levels (which can also be referred to as operating levels, or operating voltages, etc.) of the signal input terminal IPT, the first voltage signal terminal VDD1, the second voltage signal terminal VDD2, the third voltage signal terminal VGL, the fourth voltage signal terminal LVGL, the start signal terminal STV, and the reset signal terminal RST to high-level signals.

[0418] It should be noted that Figure 34 shows an exemplary structure of the first shift register SR1(j) and its included sub-circuits. Those skilled in the art can understand that the first shift register SR1(j) and its included sub-circuits are not limited to Figure 34 the structure shown, as long as its functions can be achieved.

[0419] In addition, for multiple signals and voltages of nodes in various embodiments of the present disclosure, there are corresponding operating levels and non-operating levels (which can also be referred to as the first voltage and the second voltage, or the first target voltage and the second target voltage, etc.). The operating level and the non-operating level only represent two different voltage state quantities of the signal, and do not represent that the operating level or the non-operating level has a specific value throughout the text. In the embodiments of the present disclosure, the operating level (or high level, first voltage, first target voltage, etc.) is taken as an example of the effective voltage for illustration.

[0420] The first signal output terminal GOUT1 of each first shift register SR1(j) is coupled to, for example, the first gate line GL1(m) corresponding to a row of first pixel circuits 2, to provide a gate driving signal to the first gate line GL1(m), thereby driving the display panel 100 to display.

[0421] Exemplarily, during the display stage of the display panel 100, when displaying each frame of the picture, the gate scanning signal is output to the first gate line GL1(m) corresponding to the first shift register SR1(j) through the first shift register SR1(j) step by step, to complete the progressive scanning of multiple rows of first pixel circuits 2. While each row of first pixel circuits 2 is being scanned, each data line DL(n) writes the data voltage signal into each first pixel circuit 2 in that row, to light up each first sub-pixel region P1 in that row.

[0422] In some embodiments, as Figure 35 shown, the first shift register SR1(j) includes: an input sub-circuit 121, a first pull-up node PU1, and a first output sub-circuit 122. The input sub-circuit 121 is coupled to the input signal terminal IPT and the first pull-up node PU1.

[0423] The input sub-circuit 121 is configured to transmit the input signal from the input signal terminal IPT to the first pull-up node PU1.

[0424] The first output sub - circuit 122 is coupled to the first pull - up node PU1, the clock signal terminal CLK, the first signal output terminal GOUT1, and the second signal output terminal OUTC. The first signal output terminal GOUT1 is coupled to the control electrode of the first transistor T1 through the first gate line GL1.

[0425] The first output sub - circuit 122 is configured to transmit the clock signal from the clock signal terminal CLK to the first signal output terminal GOUT1 under the control of the voltage of the first pull - up node PU1.

[0426] The first output sub - circuit 122 is further configured to transmit the clock signal from the clock signal terminal CLK to the second signal output terminal OUTC under the control of the voltage of the first pull - up node PU1.

[0427] Exemplarily, each first gate line GL1(n) is electrically connected to the control electrodes of a plurality of first transistors T1 arranged in a row, and the first transistors T1 in this row are turned on under the control of the voltage of the first gate line GL1(n) electrically connected to them.

[0428] It should be noted that the above is only an example of a possible working mode of the input sub - circuit 121 and the first output sub - circuit 122 when the first shift register SR1(j) is working, and does not limit the specific working modes of the input sub - circuit 121 and the first output sub - circuit 122 in the first shift register SR1(j). The above can be the working modes of the input sub - circuit 121 and the first output sub - circuit 122 in any working stage of the display device, such as the display stage.

[0429] In some embodiments, as Figure 36 shown, the first output sub - circuit 122 includes: a third transistor M3, a thirteenth transistor M13, and a first capacitor C1.

[0430] The control electrode of the third transistor M3 is electrically connected to the first pull - up node PU1, the first pole of the third transistor M3 is electrically connected to the clock signal terminal CLK, and the second pole of the third transistor M3 is electrically connected to the first signal output terminal GOUT1.

[0431] The third transistor M3 is configured to transmit the clock signal provided by the clock signal terminal CLK to the first signal output terminal GOUT1 under the control of the clock signal terminal CLK.

[0432] The first plate of the first capacitor C1 is electrically connected to the first pull - up node PU1, and the second plate of the first capacitor C1 is electrically connected to the second pole of the third transistor.

[0433] The control terminal of the thirteenth transistor M13 is electrically connected to the first pull-up node PU1, the first terminal of the thirteenth transistor M13 is electrically connected to the clock signal terminal CLK, and the second terminal of the thirteenth transistor M13 is electrically connected to the second signal output terminal OUTC.

[0434] The thirteenth transistor M13 is configured to transmit the clock signal provided by the clock signal terminal CLK to the second signal output terminal OUTC under the control of the voltage of the first pull-up node PU1.

[0435] In some embodiments, as Figure 35 shown, the first shift register SR1(j) further includes: a first control sub-circuit 123. The first control sub-circuit 123 is coupled to the first voltage signal terminal VDD1, the first pull-down node PD1, and the first pull-up node PU1.

[0436] The first control sub-circuit 123 is configured to pull up the first pull-down node PD1 under the control of the voltage of the first voltage signal terminal VDD1, and pull down the first pull-up node PU1 in response to the high level of the first pull-down node PD1.

[0437] The first control sub-circuit 123 is further configured to pull down the first pull-down node PD1 in response to the high level of the first pull-up node PU1.

[0438] Exemplarily, as Figure 36 shown, the first shift register SR1(j) further includes: a first pull-down control node PD-CN1, and the first control sub-circuit 123 is further coupled to the first pull-down control node PD-CN1.

[0439] The first control sub-circuit 123 is configured to transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the first pull-down control node PD-CN1 under the control of the voltage of the first voltage signal terminal VDD1, and pull up the first pull-down control node PD-CN1.

[0440] The first control sub-circuit 123 is further configured to transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the first pull-down node PD1 under the control of the voltage of the first pull-down control node PD-CN1.

[0441] It should be noted that the above is only an example of a possible working mode of the first control sub-circuit 123 when the first shift register SR1(j) is working, and does not limit the specific working mode of the first control sub-circuit 123 in the first shift register SR1(j). The above can be the working mode of the first control sub-circuit 123 in any working stage of the display device, such as the display stage.

[0442] In some embodiments, asFigure 36 As shown, the first control sub-circuit 123 includes: a fifth transistor M5, a sixth transistor M6, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.

[0443] The control electrode of the ninth transistor M9 is electrically connected to the first voltage signal terminal VDD1, the first electrode of the ninth transistor M9 is electrically connected to the first voltage signal terminal VDD1, and the second electrode of the ninth transistor M9 is electrically connected to the first pull-down control node PD-CN1.

[0444] The ninth transistor M9 is configured to pull up the first pull-down control node PD-CN1 under the control of the first voltage signal terminal VDD1.

[0445] The control electrode of the eighth transistor M8 is electrically connected to the first pull-up node PU1, the first electrode of the eighth transistor M8 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the eighth transistor M8 is electrically connected to the first pull-down control node PD-CN1.

[0446] The eighth transistor M8 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-down control node PD-CN1 under the control of the voltage of the first pull-up node PU1.

[0447] The control electrode of the fifth transistor M5 is electrically connected to the first pull-down control node PD-CN1, the first electrode of the fifth transistor M5 is electrically connected to the first voltage signal terminal VDD1, and the second electrode of the fifth transistor M5 is electrically connected to the first pull-down node PD1.

[0448] The fifth transistor M5 is configured to pull up the first pull-down node PD1 under the control of the voltage of the first pull-down control node PD-CN1.

[0449] The control electrode of the sixth transistor M6 is electrically connected to the first pull-up node PU1, the first electrode of the sixth transistor M6 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the sixth transistor M6 is electrically connected to the first pull-down node PD1.

[0450] The sixth transistor M6 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-down node PD1 under the control of the voltage of the first pull-up node PU1.

[0451] The control electrode of the tenth transistor M10 is electrically connected to the first pull-down node PD1, the first electrode of the tenth transistor M10 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the tenth transistor M10 is electrically connected to the first pull-up node PU1.

[0452] The tenth transistor M10 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the voltage of the first pull-down node PD1.

[0453] In some other embodiments, as Figure 35 shown, the first shift register SR1(j) further includes: a second control sub-circuit 123'. The second control sub-circuit 123' is coupled to the second voltage signal terminal VDD2, the second pull-down node PD2, and the first pull-up node PU1.

[0454] The second control sub-circuit 123' is configured to pull up the second pull-down node PD2 under the control of the voltage of the second voltage signal terminal VDD2, and pull down the first pull-up node PU1 in response to the high level of the second pull-down node PD2.

[0455] The second control sub-circuit 123' is further configured to pull down the second pull-down node PD2 in response to the high level of the first pull-up node PU1.

[0456] Exemplarily, as Figure 36 shown, the first shift register SR1(j) further includes: a second pull-down control node PD-CN2, and the second control sub-circuit 123' is further coupled to the second pull-down control node PD-CN2.

[0457] The second control sub-circuit 123' is configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the second pull-down control node PD-CN2 under the control of the voltage of the second voltage signal terminal VDD2, and pull up the second pull-down control node PD-CN2.

[0458] The second control sub-circuit 123' is further configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the second pull-down node PD2 under the control of the voltage of the second pull-down control node PD-CN2.

[0459] It should be noted that the above is only an example of a possible working mode of the second control sub-circuit 123' when the first shift register SR1(j) is working, and does not limit the specific working mode of the second control sub-circuit 123' in the first shift register SR1(j). The above can be the working mode of the second control sub-circuit 123' in any working stage of the display device, such as the display stage.

[0460] As a possible implementation manner, in the display stage of the display device 10000, the first control sub-circuit 123 and the second control sub-circuit 123' work alternately. For example, when the first control sub-circuit 123 is in the working state, the second control sub-circuit 123' is in the non-working state.

[0461] In some embodiments, as Figure 36 shown, the second control sub-circuit 123’ includes: a fifth transistor M5’, a sixth transistor M6’, an eighth transistor M8’, a ninth transistor M9’ and a tenth transistor M10’.

[0462] The control electrode of the ninth transistor M9’ is electrically connected to the second voltage signal terminal VDD2, the first electrode of the ninth transistor M9’ is electrically connected to the second voltage signal terminal VDD2, and the second electrode of the ninth transistor M9’ is electrically connected to the second pull-down control node PD-CN2.

[0463] The ninth transistor M9’ is configured to pull up the second pull-down control node PD-CN2 under the control of the second voltage signal terminal VDD2.

[0464] The control electrode of the eighth transistor M8’ is electrically connected to the first pull-up node PU1, the first electrode of the eighth transistor M8’ is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the eighth transistor M8’ is electrically connected to the second pull-down control node PD-CN2.

[0465] The eighth transistor M8’ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull-down control node PD-CN2 under the control of the voltage of the first pull-up node PU1.

[0466] The control electrode of the fifth transistor M5’ is electrically connected to the second pull-down control node PD-CN2, the first electrode of the fifth transistor M5’ is electrically connected to the second voltage signal terminal VDD2, and the second electrode of the fifth transistor M5’ is electrically connected to the second pull-down node PD2.

[0467] The fifth transistor M5’ is configured to pull up the second pull-down node PD2 under the control of the voltage of the second pull-down control node PD-CN2.

[0468] The control electrode of the sixth transistor M6’ is electrically connected to the first pull-up node PU1, the first electrode of the sixth transistor M6’ is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the sixth transistor M6’ is electrically connected to the second pull-down node PD2.

[0469] The sixth transistor M6’ is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull-down node PD2 under the control of the voltage of the first pull-up node PU1.

[0470] The control electrode of the tenth transistor M10’ is electrically connected to the second pull-down node PD2, the first electrode of the tenth transistor M10’ is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the tenth transistor M10’ is electrically connected to the first pull-up node PU1.

[0471] The tenth transistor M10' is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the voltage of the second pull-down node PD2.

[0472] In some embodiments, as Figure 35 shown, the first shift register SR1(j) further includes: a first noise-removing circuit 127. The first noise-removing circuit 127 is coupled to the input signal terminal IPT, the fourth voltage signal terminal LVGL, and the first pull-down node PD1. The first noise-removing circuit 127 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-down node PD1 under the control of the input signal terminal IPT.

[0473] It should be noted that the above is only an example of a possible working mode of the first noise-removing circuit 127 when the first shift register SR1(j) is working, and does not limit the specific working mode of the first noise-removing circuit 127 in the first shift register SR1(j). The above can be the working mode of the first noise-removing circuit 127 in any working stage of the display device, such as the display stage.

[0474] Exemplarily, as Figure 36 shown, the first noise-removing circuit 127 includes a thirteenth transistor M13. The control electrode of the thirteenth transistor M13 is electrically connected to the input signal terminal IPT, the first electrode of the thirteenth transistor M13 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the thirteenth transistor M13 is electrically connected to the first pull-down node PD1.

[0475] The thirteenth transistor M13 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-down node PD1 under the control of the input signal terminal IPT.

[0476] In some embodiments, the first shift register SR1(j) further includes: as Figure 35 shown, a second noise-removing circuit 127'. The second noise-removing circuit 127' is coupled to the input signal terminal IPT, the fourth voltage signal terminal LVGL, and the second pull-down node PD2. The second noise-removing circuit 127' is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second pull-down node PD2 under the control of the input signal terminal IPT.

[0477] It should be noted that the above is only an example of a possible working mode of the second noise reduction circuit 127' when the first shift register SR1(j) is working, and does not limit the specific working mode of the second noise reduction circuit 127' in the first shift register SR1(j). The above can be the working mode of the second noise reduction circuit 127' at any working stage of the display device, such as the display stage.

[0478] Exemplarily, as Figure 36 shown, the second noise reduction circuit 127' includes a thirteenth transistor M13'. The control electrode of the thirteenth transistor M13' is electrically connected to the input signal terminal IPT, the first electrode of the thirteenth transistor M13' is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the thirteenth transistor M13' is electrically connected to the second pull-down node PD2.

[0479] The thirteenth transistor M13' is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second pull-down node PD2 under the control of the input signal terminal IPT.

[0480] As a possible implementation manner, in the display stage of the display device 10000, the first noise reduction circuit 127 and the second noise reduction circuit 127' work alternately. For example, when the first noise reduction circuit 127 is in the working state, the second noise reduction circuit 127' is in the non-working state.

[0481] In some embodiments, as Figure 35 shown, the first shift register SR1(j) further includes: a first reset sub-circuit 124.

[0482] The first reset sub-circuit 124 is coupled to the first pull-down node PD1, the first signal output terminal GOUT1, and the second signal output terminal OUTC.

[0483] The first reset sub-circuit 124 is configured to reset the first signal output terminal GOUT1 and the second signal output terminal OUTC under the control of the voltage of the first pull-down node PD1.

[0484] It should be noted that the above is only an example of a possible working mode of the first reset sub-circuit 124 when the first shift register SR1(j) is working, and does not limit the specific working mode of the first reset sub-circuit 124 in the first shift register SR1(j). The above can be the working mode of the first reset sub-circuit 124 at any working stage of the display device, such as the display stage.

[0485] In some embodiments, as Figure 36 shown, the first reset sub-circuit 124 includes an eleventh transistor M11 and a twelfth transistor M12.

[0486] The control electrode of the eleventh transistor M11 is electrically connected to the first pull-down node PD1. The first pole of the eleventh transistor M11 is electrically connected to the third voltage signal terminal VGL. The second pole of the eleventh transistor M11 is electrically connected to the first signal output terminal GOUT1.

[0487] The eleventh transistor M11 is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the first signal output terminal GOUT1 under the control of the voltage of the first pull-down node PD1.

[0488] The control electrode of the twelfth transistor M12 is electrically connected to the second pull-down node PD2. The first pole of the twelfth transistor M12 is electrically connected to the fourth voltage signal terminal LVGL. The second pole of the twelfth transistor M12 is electrically connected to the second signal output terminal OUTC.

[0489] The twelfth transistor M12 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second signal output terminal OUTC under the control of the voltage of the second pull-down node PD2.

[0490] In some other embodiments, as Figure 35 shown, the first shift register SR1(j) further includes: a second reset sub-circuit 124'. The second reset sub-circuit 124' is coupled to the second pull-down node PD2, the first signal output terminal GOUT1, and the second signal output terminal OUTC.

[0491] The second reset sub-circuit 124' is configured to reset the first signal output terminal GOUT1 and the second signal output terminal OUTC under the control of the voltage of the second pull-down node PD2.

[0492] It should be noted that the above is only an example of a possible working mode of the second reset sub-circuit 124' when the first shift register SR1(j) is working, and does not limit the specific working mode of the second reset sub-circuit 124' in the first shift register SR1(j). The above can be the working mode of the second reset sub-circuit 124' at any working stage of the display device, such as the display stage.

[0493] As a possible implementation manner, in the display stage of the display device 10000, the first reset sub-circuit 124 and the second reset sub-circuit 124' work alternately. For example, when the first reset sub-circuit 124 is in the working state, the second reset sub-circuit 124' is in the non-working state.

[0494] In some embodiments, as Figure 36 shown, the second reset sub-circuit 124' includes an eleventh transistor M11' and a twelfth transistor M12'.

[0495] The control electrode of the eleventh transistor M11’ is electrically connected to the second pull - down node PD2. The first pole of the eleventh transistor M11’ is electrically connected to the third voltage signal terminal VGL. The second pole of the eleventh transistor M11’ is electrically connected to the first signal output terminal GOUT1.

[0496] The eleventh transistor M11’ is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the first signal output terminal GOUT1 under the control of the voltage of the second pull - down node PD2.

[0497] The control electrode of the twelfth transistor M12’ is electrically connected to the second pull - down node PD2. The first pole of the twelfth transistor M12’ is electrically connected to the fourth voltage signal terminal LVGL. The second pole of the twelfth transistor M12’ is electrically connected to the second signal output terminal OUTC.

[0498] The twelfth transistor M12’ is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the second signal output terminal OUTC under the control of the voltage of the second pull - down node PD2.

[0499] In some embodiments, as Figure 35 shown, the first shift register SR1(j) further includes: a third reset sub - circuit 125. The third reset sub - circuit 125 is coupled to the start signal terminal STV, the fourth voltage signal terminal LVGL, and the first pull - up node PU1. The third reset sub - circuit 125 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull - up node PU1 under the control of the start signal terminal STV.

[0500] It should be noted that the above is only an example of a possible working mode of the third reset sub - circuit 125 when the first shift register SR1(j) is working, and does not limit the specific working mode of the third reset sub - circuit 125 in the first shift register SR1(j). The above can be the working mode of the third reset sub - circuit 125 in any working stage of the display device, such as the display stage.

[0501] Exemplarily, as Figure 36 shown, the third reset sub - circuit 125 includes a seventh transistor M7. The control electrode of the seventh transistor M7 is electrically connected to the start signal terminal STV. The first pole of the seventh transistor M7 is electrically connected to the fourth voltage signal terminal LVGL. The second pole of the seventh transistor M7 is electrically connected to the first pull - up node PU1.

[0502] The seventh transistor M7 is configured to transmit the fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull - up node PU1 under the control of the start signal terminal STV.

[0503] In some embodiments, such as Figure 35 shown, the first shift register SR1(j) further includes: a fourth reset sub-circuit 126. The fourth reset sub-circuit 126 is coupled to a reset signal terminal RST, a fourth voltage signal terminal LVGL, and a first pull-up node PU1. The fourth reset sub-circuit 126 is configured to transmit a fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the reset signal terminal RST.

[0504] It should be noted that the above is only an example of a possible working mode of the fourth reset sub-circuit 126 when the first shift register SR1(j) is operating, and does not limit the specific working mode of the fourth reset sub-circuit 126 in the first shift register SR1(j). The above can be the working mode of the fourth reset sub-circuit 126 at any working stage of the display device, such as the display stage.

[0505] Exemplarily, such as Figure 36 shown, the fourth reset sub-circuit 126 includes a fourteenth transistor M14. The control electrode of the fourteenth transistor M14 is electrically connected to the reset signal terminal RST, the first electrode of the fourteenth transistor M14 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the fourteenth transistor M14 is electrically connected to the first pull-up node PU1.

[0506] The fourteenth transistor M14 is configured to transmit a fourth voltage signal provided by the fourth voltage signal terminal LVGL to the first pull-up node PU1 under the control of the reset signal terminal RST.

[0507] In some embodiments, such as Figure 28 and Figure 37 shown, when the display panel 100 includes a second transistor T2, the display panel 100 further includes: a second gate driving circuit 13. The second gate driving circuit 13 includes a second shift register unit SR2. The second shift register unit SR2 is disposed in the liquid crystal sealing region SA, and a single second shift register unit SR2 is, for example, coupled to a row of second pixel circuits 3.

[0508] Exemplarily, the first shift register unit SR1(j) is configured to transmit an electrical signal to the first gate line GL1 to control the first transistor T1 coupled to the first gate line GL1 to turn on. The second shift register SR2 is configured to transmit an electrical signal to the second gate line GL2 to control the second transistor T2 coupled to the second gate line GL2 to turn on.

[0509] The display area AA and the light-transmitting area BB operate independently, and there is no cascading relationship between the second shift register unit SR2 and the first shift register unit SR1(j). A single shift register SR2 is coupled to at least one second gate line GL2.

[0510] Based on this, the second gate line GL2 is coupled to a second pixel circuit 3 through a second transistor T2, and each second gate line GL2 is coupled to at least one row of second pixel circuits 3.

[0511] In some examples, such as Figure 28 and Figure 37 as shown, each second gate line GL2 is coupled to one row of second pixel circuits 3, and each second gate line GL2 can be electrically connected to the control electrodes of a plurality of second transistors T2 arranged in a row. In this way, one second gate line GL2 can control the conduction of a row of second transistors T2 electrically connected thereto.

[0512] In other examples, a plurality of second pixel circuits 3 are all coupled to the same second gate line GL2, and the control electrodes of the plurality of second transistors T2 included in the display panel 100 are all electrically connected to the same second gate line GL2. In this way, one second gate line GL2 can control the conduction of each second transistor T2.

[0513] It should be noted that the connection manner of the second gate line GL2 to the second pixel circuit 3 and the second transistor T2 can be selected as needed. The above is only an exemplary illustration of possible implementation manners of the present disclosure and does not limit the present disclosure.

[0514] Exemplarily, the data line DL (the first data line DL1 or the second data line DL2) is coupled to the second pixel electrode 31, and each data line DL is coupled to at least one column of second pixel circuits 3. The data line DL can be the first data line DL1 and / or the second data line DL2.

[0515] In some examples, such as Figure 28 and Figure 37 as shown, each data line DL is coupled to one column of second pixel circuits 3, and each data line DL can be electrically connected to the first electrodes of a plurality of second transistors T2 arranged in a column. In this way, a single data line DL can transmit a second data signal to a column of second pixel electrodes 31 through a plurality of second transistors T2 electrically connected thereto.

[0516] In other examples, the second pixel circuits 3 included in the display panel 100 are all coupled to the same data line DL, and the control electrodes of the second transistors T2 included in the display panel 100 are all electrically connected to the same data line DL. In this way, one second gate line GL2 can transmit a second data signal to each second pixel electrode 31.

[0517] It should be noted that the connection manner of the data line DL to the second pixel circuit 3 and the second transistor T2 can be selected as needed. The above is only an exemplary illustration of possible implementation manners of the present disclosure and does not limit the present disclosure.

[0518] In some embodiments, as Figure 37 shown, the second shift register SR2 includes: a second pull-up node PU2 and a second output sub-circuit 131. The second pull-up node PU2 is electrically connected to the enable signal terminal OE. The second output sub-circuit 131 is coupled to the second pull-up node PU2, the enable signal terminal OE, and the third signal output terminal GOUT2. The third signal output terminal GOUT2 is coupled to the control electrode of the second transistor T2 through the second gate line GL2.

[0519] The second output sub-circuit 131 is configured to transmit the enable signal from the enable signal terminal OE to the third signal output terminal GOUT2 under the control of the voltage of the second pull-up node PU2, so as to charge the third signal output terminal GOUT2.

[0520] Referring to Figure 35 and Figure 37 , compared with the first gate driving circuit 12, the second gate driving circuit 13 does not need to be provided with an input sub-circuit (the first pixel circuit 2 needs to be provided with an input sub-circuit 121), and the circuit architecture is simpler.

[0521] It should be noted that the above is only an example of a possible working mode of the second output sub-circuit 131 when the second shift register SR2 is working, and does not limit the specific working mode of the second output sub-circuit 131 in the second shift register SR2. The above can be any working stage of the second output sub-circuit 131 in the light-transmitting area BB, such as the working mode in the light-emitting stage.

[0522] Exemplarily, the display panel 100 further includes a reset signal terminal ADD disposed in the liquid crystal sealing area SA, and the reset signal terminal ADD is electrically connected to the second pull-up node PU2. The reset signal terminal ADD is configured to pull down the potential of the second pull-up node PU2 in response to a reset signal.

[0523] By providing the reset signal terminal ADD, when it is necessary to reset the potential of the second pull-up node PU2 to a non-operating level, a reset signal can be sent from the circuit board 200 to the reset signal terminal ADD. Under the control of the reset signal, the reset signal terminal ADD pulls down the potential of the second pull-up node PU2 to reset / reset the second pull-up node PU2.

[0524] In some embodiments, as Figure 38 shown, the second output sub-circuit 131 includes: a third transistor N3 and a second capacitor C2.

[0525] The control electrode of the third transistor N3 is electrically connected to the second pull-up node PU2. The first electrode of the third transistor N3 is electrically connected to the enable signal terminal OE. The second electrode of the third transistor N3 is electrically connected to the third signal output terminal GOUT2.

[0526] The second capacitor C2 is configured to transmit the enable signal transmitted by the enable signal terminal OE to the third signal output terminal GOUT2 under the control of the voltage of the second pull-up node PU2.

[0527] The first electrode plate of the second capacitor C2 is electrically connected to the second pull-up node PU2. The second electrode plate of the second capacitor C2 is electrically connected to the second electrode of the third transistor N3.

[0528] In some embodiments, as Figure 37 shown, the second shift register SR2 further includes: a third control sub-circuit 132. The third control sub-circuit 132 is coupled to the first voltage signal terminal VDD1, the third pull-down node PD3, and the second pull-up node PU2.

[0529] The third control sub-circuit 132 is configured to pull up the third pull-down node PD3 under the control of the voltage of the first voltage signal terminal VDD1, and pull down the second pull-up node PU2 in response to the high level of the third pull-down node PD3.

[0530] The third control sub-circuit 132 is further configured to pull down the third pull-down node PD3 in response to the high level of the second pull-up node PU2.

[0531] Exemplarily, as Figure 38 shown, the second shift register SR2 further includes: a third pull-down control node PD-CN3. The third control sub-circuit 132 is further coupled to the third pull-down control node PD-CN3.

[0532] The third control sub-circuit 132 is configured to transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the third pull-down control node PD-CN3 under the control of the voltage of the first voltage signal terminal VDD1, and pull up the third pull-down control node PD-CN3.

[0533] The third control sub-circuit 132 is further configured to transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the third pull-down node PD3 under the control of the voltage of the third pull-down control node PD-CN3.

[0534] Referring to Figure 35 and Figure 37 , compared with the first gate driving circuit 12, the circuit architecture of the second gate driving circuit 13 is simpler.

[0535] It should be noted that the above is only an example of a possible working mode of the third control sub-circuit 132 when the second shift register SR2 is working, and does not limit the specific working mode of the third control sub-circuit 132 in the second shift register SR2. The above can be the working mode of the third control sub-circuit 132 at any working stage in the light-transmitting area BB, such as the light-emitting stage.

[0536] In some embodiments, as Figure 38 shown, the third control sub-circuit 132 includes: a fourth transistor N4, a fifth transistor N5, a seventh transistor N7, a sixth transistor N6, and an eighth transistor N8.

[0537] The control electrode of the sixth transistor N6 is electrically connected to the first voltage signal terminal VDD1, the first electrode of the sixth transistor N6 is electrically connected to the first voltage signal terminal VDD1, and the second electrode of the sixth transistor N6 is electrically connected to the third pull-down control node PD-CN3.

[0538] The sixth transistor N6 is configured to pull up the third pull-down control node PD-CN3 under the control of the first voltage signal terminal VDD1.

[0539] The control electrode of the seventh transistor N7 is electrically connected to the second pull-up node PU2, the first electrode of the seventh transistor N7 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the seventh transistor N7 is electrically connected to the third pull-down control node PD-CN3.

[0540] The seventh transistor N7 is configured to transmit the fourth power supply signal provided by the fourth voltage signal terminal LVGL to the third pull-down control node PD-CN3 under the control of the voltage of the second pull-up node PU2.

[0541] The control electrode of the fourth transistor N4 is electrically connected to the third pull-down control node PD-CN3, the first electrode of the fourth transistor N4 is electrically connected to the first voltage signal terminal VDD1, and the second electrode of the fourth transistor N4 is electrically connected to the third pull-down node PD3.

[0542] The fourth transistor N4 is configured to transmit the first voltage signal provided by the first voltage signal terminal VDD1 to the third pull-down node PD3 and pull up the third pull-down node PD3 under the control of the voltage of the third pull-down control node PD-CN3.

[0543] The control electrode of the fifth transistor N5 is electrically connected to the second pull-up node PU2, the first electrode of the fifth transistor N5 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the fifth transistor N5 is electrically connected to the third pull-down node PD3.

[0544] The fifth transistor N5 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the third pull - down node PD3 under the control of the voltage of the second pull - up node PU2.

[0545] The control electrode of the eighth transistor N8 is electrically connected to the third pull - down node PD3, the first electrode of the eighth transistor N8 is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the eighth transistor N8 is electrically connected to the second pull - up node PU2.

[0546] The eighth transistor N8 is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull - up node PU2 under the control of the voltage of the third pull - down node PD3.

[0547] In some embodiments, as Figure 37 shown, the second shift register SR2 further includes: a fourth control sub - circuit 133. The fourth control sub - circuit 133 is coupled to the second voltage signal terminal VDD2, the fourth pull - down node PD4, and the second pull - up node PU2.

[0548] The fourth control sub - circuit 133 is configured to pull up the fourth pull - down node PD4 under the control of the voltage of the second voltage signal terminal VDD2, and pull down the second pull - up node PU2 in response to the high level of the fourth pull - down node PD4.

[0549] The fourth control sub - circuit 133 is further configured to pull down the fourth pull - down node PD4 in response to the high level of the second pull - up node PU2.

[0550] Exemplarily, as Figure 38 shown, the second shift register SR2 further includes: a fourth pull - down control node PD - CN4, and the fourth control sub - circuit 133 is further coupled to the fourth pull - down control node PD - CN4.

[0551] The fourth control sub - circuit 133 is configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the fourth pull - down control node PD - CN4 under the control of the voltage of the second voltage signal terminal VDD2, and pull up the fourth pull - down control node PD - CN4.

[0552] The fourth control sub - circuit 133 is further configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the fourth pull - down node PD4 under the control of the voltage of the fourth pull - down control node PD - CN4.

[0553] Referring to Figure 35 and Figure 37 , compared with the first gate driving circuit 12, the circuit architecture of the second gate driving circuit 13 is simpler.

[0554] It should be noted that the above is only an example of a possible working mode of the fourth control sub-circuit 133 when the second shift register SR2 is working, and it does not limit the specific working mode of the fourth control sub-circuit 133 in the second shift register SR2. The above can be the working mode of the fourth control sub-circuit 133 in any working stage of the light-transmitting area BB, such as the light-emitting stage.

[0555] As a possible implementation manner, in the light-emitting stage of the light-transmitting area BB, the third control sub-circuit 132 and the fourth control sub-circuit 133 work alternately. For example, when the third control sub-circuit 132 is in the working state, the fourth control sub-circuit 133 is in the non-working state.

[0556] In some embodiments, as Figure 38 shown, the fourth control sub-circuit 133 includes: a fourth transistor N4', a fifth transistor N5', a sixth transistor N6', a seventh transistor N7' and an eighth transistor N8'.

[0557] The control electrode of the sixth transistor N6' is electrically connected to the second voltage signal terminal VDD2, the first electrode of the sixth transistor N6' is electrically connected to the second voltage signal terminal VDD2, and the second electrode of the sixth transistor N6' is electrically connected to the fourth pull-down control node PD-CN4.

[0558] The sixth transistor N6' is configured to pull up the fourth pull-down control node PD-CN4 under the control of the second voltage signal terminal VDD2.

[0559] The control electrode of the seventh transistor N7' is electrically connected to the second pull-up node PU2, the first electrode of the seventh transistor N7' is electrically connected to the fourth voltage signal terminal LVGL, and the second electrode of the seventh transistor N7' is electrically connected to the fourth pull-down control node PD-CN4.

[0560] The seventh transistor N7' is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the fourth pull-down control node PD-CN4 under the control of the voltage of the second pull-up node PU2.

[0561] The control electrode of the fourth transistor N4' is electrically connected to the fourth pull-down control node PD-CN4, the first electrode of the fourth transistor N4' is electrically connected to the second voltage signal terminal VDD2, and the second electrode of the fourth transistor N4' is electrically connected to the fourth pull-down node PD4.

[0562] The fourth transistor N4' is configured to transmit the second voltage signal provided by the second voltage signal terminal VDD2 to the fourth pull-down node PD4 and pull up the fourth pull-down node PD4 under the control of the voltage of the fourth pull-down control node PD-CN4.

[0563] The control electrode of the fifth transistor N5' is electrically connected to the second pull-up node PU2. The first electrode of the fifth transistor N5' is electrically connected to the fourth voltage signal terminal LVGL. The second electrode of the fifth transistor N5' is electrically connected to the fourth pull-down node PD4.

[0564] The fifth transistor N5' is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the fourth pull-down node PD4 under the control of the voltage of the second pull-up node PU2.

[0565] The control electrode of the eighth transistor N8' is electrically connected to the fourth pull-down node PD4. The first electrode of the eighth transistor N8' is electrically connected to the fourth voltage signal terminal LVGL. The second electrode of the eighth transistor N8' is electrically connected to the second pull-up node PU2.

[0566] The eighth transistor N8' is configured to transmit the fourth power signal provided by the fourth voltage signal terminal LVGL to the second pull-up node PU2 under the control of the voltage of the fourth pull-down node PD4.

[0567] In some embodiments, as Figure 37 shown, the second shift register SR2 further includes: a fifth reset sub-circuit 134. The fifth reset sub-circuit 134 is coupled to the third pull-down node PD3 and the third signal output terminal GOUT2.

[0568] The fifth reset sub-circuit 134 is configured to reset the third signal output terminal GOUT2 under the control of the voltage of the third pull-down node PD3.

[0569] See Figure 35 and Figure 37 , compared with the first gate driving circuit 12, the circuit architecture of the second gate driving circuit 13 is simpler.

[0570] It should be noted that the above is only an example of a possible working mode of the fifth reset sub-circuit 134 when the second shift register SR2 is working, and does not limit the specific working mode of the fifth reset sub-circuit 134 in the second shift register SR2. The above can be any working stage of the fifth reset sub-circuit 134 in the light-transmitting area BB, such as the working mode in the light-emitting stage.

[0571] In some embodiments, as Figure 38As shown, the fifth reset sub-circuit 134 includes a ninth transistor N9. The control electrode of the ninth transistor N9 is electrically connected to the third pull-down node PD3. The first electrode of the ninth transistor N9 is electrically connected to the third voltage signal terminal VGL. The second electrode of the ninth transistor N9 is electrically connected to the third signal output terminal GOUT2. The ninth transistor N9 is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the third signal output terminal GOUT2 under the control of the voltage of the third pull-down node PD3.

[0572] In some embodiments, as Figure 37 shown, the second shift register SR2 further includes: a sixth reset sub-circuit 135. The sixth reset sub-circuit 135 is coupled to the fourth pull-down node PD4 and the third signal output terminal GOUT2.

[0573] The sixth reset sub-circuit 135 is configured to reset the third signal output terminal GOUT2 under the control of the voltage of the fourth pull-down node PD4.

[0574] Refer to Figure 35[[END and ​ , compared with the first gate driving circuit 12, the circuit architecture of the second gate driving circuit 13 is simpler.

[0575] It should be noted that the above is only an example of a possible working mode of the sixth reset sub-circuit 135 when the second shift register SR2 is working, and is not a limitation on the specific working mode of the sixth reset sub-circuit 135 in the second shift register SR2. The above can be any working stage of the sixth reset sub-circuit 135 in the light-transmitting region BB, such as the working mode in the light-emitting stage.

[0576] As a possible implementation manner, in the light-emitting stage of the light-transmitting region BB, the fifth reset sub-circuit 134 and the sixth reset sub-circuit 135 work alternately. For example, when the fifth reset sub-circuit 134 is in the working state, the sixth reset sub-circuit 135 is in the non-working state.

[0577] In some embodiments, as ​ shown, the sixth reset sub-circuit 135 includes a ninth transistor N9'. The control electrode of the ninth transistor N9' is electrically connected to the fourth pull-down node PD4. The first electrode of the ninth transistor N9' is electrically connected to the third voltage signal terminal VGL. The second electrode of the ninth transistor N9' is electrically connected to the third signal output terminal GOUT2. The ninth transistor N9' is configured to transmit the third voltage signal provided by the third voltage signal terminal VGL to the third signal output terminal GOUT2 under the control of the voltage of the fourth pull-down node PD4.

[0578] In some embodiments, as ​ and ​As shown, the display panel 100 further includes at least one light-emitting data input terminal VL outside the display area AA, and the light-emitting data input terminal VL is insulated from the data line DL.

[0579] Exemplarily, the light-emitting data input terminal VL may be located within the bonding area BA.

[0580] Exemplarily, a single light-emitting data input terminal VL is coupled to at least one second pixel electrode 31. The single light-emitting data input terminal VL may be coupled to one second pixel electrode 31; or, the single light-emitting data input terminal VL is coupled to multiple second pixel electrodes 31.

[0581] The following takes the display panel 100 including multiple second pixel circuits 3 as an example for illustration.

[0582] In some examples, the display panel 100 has the same light-emitting color in the regions defined by different second pixel circuits 3. The region defined by the second pixel circuit 3 is, for example, the aforementioned second sub-pixel region P2.

[0583] The second pixel electrodes 31 of different second pixel circuits 3 may all be coupled to the same light-emitting data input terminal VL; or, the light-emitting data input terminals VL and the second pixel electrodes 31 are arranged in one-to-one correspondence, and different second pixel electrodes 31 are respectively coupled to different light-emitting data input terminals VL; or, a part of the multiple second pixel electrodes 31 is coupled to one light-emitting data input terminal VL, and the other part is coupled to another light-emitting data input terminal VL.

[0584] According to the different connection manners of the light-emitting data input terminal VL and the second pixel circuit 3, the multiple second pixel circuits 3 included in the display panel 100 may work simultaneously or in a time-sharing manner, and specific selection and setting can be made according to needs, and the present disclosure does not limit this.

[0585] In some other examples, the multiple second pixel circuits 3 at least include a first-color pixel circuit 3a and a second-color pixel circuit 3b, and the colors of the emitted light in the regions defined by the first-color pixel circuit 3a and the second-color pixel circuit 3b of the display panel 100 are different. The region defined by the first-color pixel circuit 3a is, for example, the second sub-pixel region P2(1) of the first light-emitting color, and the region defined by the second-color pixel circuit 3b is, for example, the second sub-pixel region P2(2) of the second light-emitting color.

[0586] The second pixel electrodes 31 of different first-color pixel circuits 3a may all be coupled to the same light-emitting data input terminal VL; alternatively, the light-emitting data input terminal VL is provided in one-to-one correspondence with the second pixel electrodes 31, the second pixel electrodes 31 of the first-color pixel circuits 3a are all coupled to one light-emitting data input terminal VL, and the second pixel electrodes 31 of the second-color pixel circuits 3b are all coupled to another light-emitting data input terminal VL; or, the light-emitting data input terminal VL is provided in one-to-one correspondence with the second pixel electrodes 31, the second pixel electrodes 31 of different first-color pixel circuits 3a are respectively coupled to different light-emitting data input terminals VL, and the second pixel electrodes 31 of different second-color pixel circuits 3b are respectively coupled to different light-emitting data input terminals VL.

[0587] The first light-emitting color and the second light-emitting color may be any two of the three primary colors. For example, the second sub-pixel region P2(1) of the first light-emitting color is the second sub-pixel region P2(R) of red light, and the second sub-pixel region P2(2) of the second light-emitting color is the second sub-pixel region P2(G) of green light.

[0588] The second sub-pixel region P2(R) of red light and the second sub-pixel region P2(G) of green light may be lit simultaneously or in a time-division manner.

[0589] When the second sub-pixel region P2(R) of red light and the second sub-pixel region P2(G) of green light are lit simultaneously, the display panel 100 may emit light / not emit light through the light-transmitting region BB (the second sub-pixel region P2(R) of red light and the second sub-pixel region P2(G) of green light), corresponding to the working state / non-working state of the sensor 300.

[0590] When the second sub-pixel region P2(R) of red light and the second sub-pixel region P2(G) of green light may be lit in a time-division manner, the display panel 100 may also be lit by the second sub-pixel region P2(R) of red light or the second sub-pixel region P2(G) of green light to distinguish the working state and the non-working state of the sensor 300.

[0591] Exemplarily, the light-emitting data input terminal VL may be located in the bonding area BA.

[0592] Exemplarily, the fact that at least one light-emitting data input terminal VL is insulated from the data line DL means that the light-emitting data input terminal VL is electrically insulated from the first data line DL1 and / or the second data line DL2.

[0593] The light-emitting data input terminal VL is configured to provide a second data signal to the second pixel electrode 31.

[0594] The second data signal may be a grayscale signal, and the second sub-pixel region P2 achieves different emission brightness according to different grayscale signals received by the second pixel electrode 31. For example, the emission brightness of the light-transmitting region BB adopts 256 grayscale levels. Correspondingly, the emission brightness of the second sub-pixel region P2 adopts 256 grayscale levels. When the second sub-pixel region P2 emits light and does not emit light, the grayscale signals received by the second pixel electrode 31 are different.

[0595] Based on this, when the second sub-pixel region P2 does not emit light, the grayscale signal received by the second pixel electrode 31 may be L0. Correspondingly, when the second sub-pixel region P2 emits light, the grayscale signal received by the second pixel electrode 31 may be any value from L1 to L255.

[0596] Furthermore, when the light-transmitting region BB changes the emission brightness according to the working state of the sensor 300, it may be that when the sensor 300 is in the working state, the second sub-pixel region P2 emits light of the first brightness, and when the sensor 300 is in the non-working state, the second sub-pixel region P2 does not emit light or emits light of the second brightness.

[0597] Based on this, when the second sub-pixel region P2 emits light of the first brightness and the second brightness, the grayscale signals received by the second pixel electrode 31 may be any two different values from L1 to L255. The specific values can be selected according to needs, as long as the brightness difference between the light of the first brightness and the light of the second brightness can be clearly distinguished.

[0598] The above is only an exemplary illustration of some possible implementation manners of the present disclosure, and does not limit the present disclosure.

[0599] In some embodiments, as ​ and ​ shown, the display panel 100 includes: M light-emitting data input terminals VL(f) (1 ≤ f ≤ M), where M is greater than or equal to 2. Each light-emitting data input terminal VL(f) is coupled to at least one second pixel electrode 31.

[0600] The display panel 100 further includes: a light-emitting data driving circuit 14 and M control signal terminals IN(f). Among them, the M control signal terminals IN(f) correspond to the M light-emitting data input terminals VL(f) one by one.

[0601] The light-emitting data driving circuit 14 is configured to output the signal of the corresponding light-emitting data input terminal VL from the output terminal of the light-emitting data driving circuit 14 in response to the respective working levels of the M control signal terminals IN(f). Among them, when one of the M control signal terminals IN(h) outputs a working level, the other control signal terminals IN(f) output non-working levels.

[0602] The second pixel electrode 31 of the second sub-pixel region P2 with the same emission color can be coupled to the same light-emitting data input terminal VL(f). With such a design, when the display panel 100 includes multiple second sub-pixel regions P2 with different emission colors, when the second sub-pixel region P2 of one emission color receives the second data signal provided by the corresponding light-emitting data input terminal VL(f) and emits light, the second sub-pixel regions P2 of the remaining emission colors will not receive the second data signal provided by their corresponding light-emitting data input terminals VL(f), so that the second sub-pixel regions P2 with the same emission color can be lit simultaneously, and the second sub-pixel regions P2 with different emission colors will not be lit simultaneously.

[0603] In some embodiments, as ​ shown, the output terminal of the light-emitting data driving circuit 14 is electrically connected to the second pixel electrode 31.

[0604] When the second data signal is provided to the second pixel electrode 31 through the light-emitting data driving circuit 14, the second pixel circuit 3 can be driven in an active driving mode or a passive driving mode.

[0605] When the second pixel circuit 3 is driven in a passive driving mode, in some examples, as ​ shown, the light-emitting data input terminal VL is coupled to the second pixel electrode 31 through the light-emitting data driving circuit 14.

[0606] In some examples, as ​ shown, the second pixel circuit 3 is driven in an active driving mode, and the display panel 100 further includes a second transistor T2. The light-emitting data input terminal VL and the second pixel electrode 31 are coupled to the first pole of the second transistor T2 through the light-emitting data driving circuit 14, and the second pole of the second transistor T2 is electrically connected to the second pixel electrode 31.

[0607] In this case, as ​ shown, the display panel 100 further includes: a second transistor T2, and the output terminal of the light-emitting data driving circuit 14 is coupled to the second pixel electrode 31 through the second transistor T2.

[0608] The driving mode of the second pixel circuit 3 in the passive driving mode can be selected as needed. This is only an exemplary illustration of some possible implementation manners of the present disclosure and does not limit the present disclosure.

[0609] In some embodiments, as ​ and ​As shown, the display panel 100 includes: a first light-emitting data driving circuit 141 and a second light-emitting data driving circuit 142. Both the first light-emitting data driving circuit 141 and the second light-emitting data driving circuit 142 are light-emitting data driving circuits 14. The M control signal terminals IN(f) include a first control signal terminal IN(1) and a second control signal terminal IN(2). The M light-emitting data input terminals VL(f) include: a first light-emitting data input terminal VL(1) and a second light-emitting data input terminal VL(2).

[0610] The display panel 100 includes a plurality of second pixel circuits 3. The plurality of second pixel circuits 3 include a first color pixel circuit 3a and a second color pixel circuit 3b. The colors of the light emitted by the display panel 100 in the region defined by the first color pixel circuit 3a and the region defined by the second color pixel circuit 3b are different. The second pixel electrode 31a of the first color pixel circuit 3a is coupled to the output terminal of the first light-emitting data driving circuit 141, and the second pixel electrode 31b of the second color pixel circuit 3b is coupled to the output terminal of the second light-emitting data driving circuit 142.

[0611] In the first light-emitting data driving circuit 141, the first control signal terminal IN(1) corresponds to the first light-emitting data input terminal VL(1), and the second control signal terminal IN(2) corresponds to the second light-emitting data input terminal VL(2).

[0612] The first light-emitting data driving circuit 141 is configured to transmit the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) to the second pixel electrode 31a under the control of the first control signal terminal IN(1).

[0613] In the second light-emitting data driving circuit 142, the first control signal terminal IN(1) corresponds to the second light-emitting data input terminal VL(2), and the second control signal terminal IN(2) corresponds to the first light-emitting data input terminal VL(1).

[0614] The second light-emitting data driving circuit 142 is configured to transmit the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) to the second pixel electrode 31b under the control of the second control signal terminal IN(2).

[0615] Exemplarily, in the light-emitting stage of the light-transmitting area BB, the red second sub-pixel area P2(R) and the green second sub-pixel area P2(G) emit light in a time-division manner, for example. When the red second sub-pixel area P2(R) emits light, the green second sub-pixel area P2(G) does not emit light; when the green second sub-pixel area P2(G) emits light, the red second sub-pixel area P2(R) does not emit light.

[0616] As ​ 、 ​ and ​As shown, the light-emitting stage of the light-transmitting region BB includes a first light-emitting stage Tf1 and a second light-emitting stage Tf2. During the first light-emitting stage Tf1, the red second sub-pixel region P2(R) emits light, and the green second sub-pixel region P2(G) does not emit light; during the second light-emitting stage Tf2, the green second sub-pixel region P2(G) emits light, and the red second sub-pixel region P2(R) does not emit light.

[0617] When the voltage of the light-emitting data signal received by the second pixel electrode 31 is higher than or equal to the set operating voltage, the second sub-pixel region P2 emits light; when the voltage of the light-emitting data signal received by the second pixel electrode 31 is lower than the set operating voltage, the second sub-pixel region P2 does not emit light.

[0618] As ​ shown, the voltage of the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) is higher than or equal to the set operating voltage, and the voltage of the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) is lower than the set operating voltage.

[0619] During the first light-emitting stage Tf1, as ​ shown, the second control signal provided by the second control signal terminal IN(2) is at a non-operating level, and the first control signal provided by the first control signal terminal IN(1) is at an operating level at least for part of the time.

[0620] As ​ and ​ shown, when the first control signal is at an operating level, the first light-emitting data driving circuit 141 transmits the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) to the second pixel electrode 31a, and the red second sub-pixel region P2(R) emits light.

[0621] As ​ and ​ shown, when the first control signal is at an operating level, the second light-emitting data driving circuit 142 transmits the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) to the second pixel electrode 31b, and the green second sub-pixel region P2(G) does not emit light.

[0622] During the second light-emitting stage Tf2, as ​ shown, the first control signal provided by the first control signal terminal IN(1) is at a non-operating level, and the second control signal provided by the second control signal terminal IN(2) is at an operating level at least for part of the time.

[0623] As ​ and ​As shown, when the second control signal is at the working level, the first light-emitting data driving circuit 141 transmits the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) to the second pixel electrode 31a, and the red second sub-pixel area P2(R) does not emit light.

[0624] like ​ and ​ As shown, when the first control signal is at the working level, the second light-emitting data driving circuit 142 transmits the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) to the second pixel electrode 31b, and the green second sub-pixel area P2(G) emits light.

[0625] In the case where the light-emitting data driving circuit 14 is not provided, when the second sub-pixel area P2 corresponding to the second data line DL2 emits light, the voltage of the second data signal transmitted by the second data line DL2 is higher than or equal to the set working voltage; when the second sub-pixel area P2 corresponding to the second data line DL2 does not emit light, the voltage of the second data signal transmitted by the second data line DL2 is lower than the set working voltage. In this case, the same second data line DL2 needs to transmit at least two different second data signals.

[0626] In this embodiment, by providing the data driving circuit 14, the control signal terminal IN(f) and the light emitting data input terminal VL(f), the same second data line DL2 only needs to transmit one light emitting data signal. The light emitting data signal transmitted by the signal line connecting the light emitting data input terminal VL(f) and the data driving circuit 14 remains unchanged, and compared with using the data line DL to transmit the light emitting data signal, the driving circuit of the display panel 100 can be simplified.

[0627] Moreover, in the light-emitting stage of the light-transmitting area BB, the second pixel electrodes 31 corresponding to the second sub-pixel areas P2 of different light-emitting colors are all coupled to the same light-emitting data input terminal VL(f), and the time-sharing lighting of the second sub-pixel areas P2 of different light-emitting colors is realized through different connection methods of the data driving circuit 14, the control signal terminal IN(f) and the light-emitting data input terminal VL(f).

[0628] Compared with setting different luminous data input terminals VL(f) for the second sub-pixel areas P2 with different luminous colors, some embodiments of the present disclosure can reduce the number of luminous data input terminals VL(f), thereby facilitating reducing the width of the border AN of the display panel 100.

[0629] In some embodiments, ​ and ​ As shown, the light-emitting data driving circuit 14 includes M transistors, and control electrodes of the M transistors V are respectively coupled to M control signal terminals IN.

[0630] Exemplarily, as ​ shown, the first light-emitting data driving circuit 141 includes: a first data driving transistor V1 and a first data driving transistor V1'.

[0631] The control electrode of the first data driving transistor V1 is electrically connected to the first control signal terminal IN(1), the first electrode of the first data driving transistor V1 is electrically connected to the first light-emitting data input terminal VL(1), and the second electrode of the first data driving transistor V1 is coupled to the second pixel electrode 31a of the first color pixel circuit 3a.

[0632] The first data driving transistor V1 is configured to be turned on under the control of the first control signal terminal IN(1) and transmit the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) to the second pixel electrode 31a.

[0633] The control electrode of the first data driving transistor V1' is electrically connected to the second control signal terminal IN(2), the first electrode of the first data driving transistor V1' is electrically connected to the second light-emitting data input terminal VL(2), and the second electrode of the first data driving transistor V1' is coupled to the second pixel electrode 31a of the first color pixel circuit 3a.

[0634] The first data driving transistor V1' is configured to be turned on under the control of the second control signal terminal IN(2) and transmit the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) to the second pixel electrode 31a.

[0635] As ​ shown, the second light-emitting data driving circuit 142 includes: a second data driving transistor V2 and a second data driving transistor V2'.

[0636] The control electrode of the second data driving transistor V2 is electrically connected to the first control signal terminal IN2(1), the first electrode of the second data driving transistor V2 is electrically connected to the second light-emitting data input terminal VL(2), and the second electrode of the second data driving transistor V2 is coupled to the second pixel electrode 31b of the second color pixel circuit 3b.

[0637] The second data driving transistor V2 is configured to be turned on under the control of the first control signal terminal IN(1) and transmit the second light-emitting data signal provided by the second light-emitting data input terminal VL(2) to the second pixel electrode 31b.

[0638] The control electrode of the second data driving transistor V2' is electrically connected to the first control signal terminal IN(1), the first electrode of the second data driving transistor V2' is electrically connected to the first light-emitting data input terminal VL(1), and the second electrode of the second data driving transistor V2' is coupled to the second pixel electrode 31b of the second color pixel circuit 3b.

[0639] The second data-driven transistor V2' is configured to turn on under the control of the second control signal terminal IN(2) and transmit the first light-emitting data signal provided by the first light-emitting data input terminal VL(1) to the second pixel electrode 31b.

[0640] The second sub-pixel regions P2 of different light-emitting colors respectively transmit light-emitting data signals to the corresponding second pixel electrodes 31 through different light-emitting data driving circuits 14 (such as the first light-emitting data driving circuit 141 and the second light-emitting data driving circuit 142). The second pixel electrodes 31 corresponding to the second sub-pixel regions P2 of different light-emitting colors are coupled to the same light-emitting data input terminal VL(f). Through different connection manners of the data driving circuit 14, the control signal terminal IN(f), and the light-emitting data input terminal VL(f), the second sub-pixel regions P2 of different light-emitting colors are lit up in a time-sharing manner. The number of settings of the light-emitting data input terminal VL(f) can be reduced, which is beneficial to reducing the width of the border AN of the display panel 100.

[0641] Moreover, the structure of the light-emitting data driving circuit 14 is simple, so that the structure of the display panel 100 can be simplified.

[0642] The film layer structure of the display panel 100 will be introduced below.

[0643] ​ It is a partial cross-sectional view within the display area AA of the display panel 100 of some embodiments. Only the first transistor T1, the first pixel electrode 21, and the first common electrode 22 are shown in the figure.

[0644] In some embodiments, as ​ shown, the display panel 100 includes: a gate conductive layer G, a first insulating layer J1, a source-drain conductive layer SD, a second insulating layer J2, a pixel electrode layer D1, a third insulating layer J3, and a common electrode layer D2, which are sequentially arranged in a direction away from the first substrate 1.

[0645] The display panel 100 further includes: a first transistor T1. The control electrode T1 of the first transistor T1 G is located within the gate conductive layer G, the first pole T1 of the first transistor T1 S and the second pole T1 of the first transistor T1 D are located within the source-drain conductive layer SD, the first pixel electrode 21 is located within the pixel electrode layer D1, and the first common electrode 22 is located within the common electrode layer D2.

[0646] The display panel 100 further includes: a connection hole L that penetrates from the first pixel electrode 21 to the second pole T1 of the first transistor T1 D The first pixel electrode 21 is electrically connected to the second pole T1 of the first transistor T1 through the connection hole L. D electrically connected.

[0647] ​ It is a partial enlarged structural diagram of the display area AA of the display panel 100. ​ It is ​ an enlarged structural diagram of the area V4 in ​ It is a cross-sectional structural diagram obtained according to the section line G4-G4 in ​ In some other embodiments, as shown in

[0648] In some other embodiments, such as ​ , ​ and ​ shown, the display panel 100 further includes: a first gate line GL1, a data line DL, a first transistor T1, and a transfer electrode 14. The control electrode T1 of the first transistor T1 G is electrically connected to the first gate line GL1, the first electrode T1 of the first transistor T1 S is electrically connected to the data line DL, and the second electrode T1 of the first transistor T1 D is coupled to the first pixel electrode 21.

[0649] As shown in ​ the display panel 100 includes a gate conductive layer G, a first insulating layer J1, a source-drain conductive layer SD, a second insulating layer J2, a pixel electrode layer D1, a third insulating layer J3, and a common electrode layer D2, which are sequentially arranged in a direction away from the first substrate 1.

[0650] The first gate line GL1 and the control electrode T1 of the first transistor T1 G are located in the gate conductive layer G, the data line DL, the first electrode T1 of the first transistor T1 S and the second electrode T1 of the first transistor T1 D are located in the source-drain conductive layer SD, the first pixel electrode 21 is located in the pixel electrode layer D1, and the transfer electrode 14 and the first common electrode 22 are located in the common electrode layer D2.

[0651] In the orthographic projection onto the first substrate 1, the transfer electrode 14 and the first pixel electrode 21 at least partially overlap, and the transfer electrode 14 and the second electrode T1 of the first transistor T1 D at least partially overlap.

[0652] The display panel 100 further includes: a first transfer via hole R1 that penetrates from the transfer electrode 14 to the second electrode T1 of the first transistor T1 D and a second transfer via hole R2 that penetrates from the transfer electrode 14 to the first pixel electrode 21.

[0653] The transfer electrode 14 is electrically connected to the second electrode T1 of the first transistor T1 through the first transfer via hole R1 D and the transfer electrode 14 is electrically connected to the first pixel electrode 21 through the second transfer via hole R2.

[0654] In some embodiments of the present disclosure, as ​ shown, by providing a transfer electrode 14, the first pixel electrode 21 is electrically connected to the transfer electrode 14, thereby reducing the resistance of the first pixel electrode 21 and further reducing the power consumption of the display panel 100.

[0655] In some embodiments of the present disclosure, by providing a transfer electrode 14, the transfer electrode 14 may be provided on the same layer as the first common electrode 22. In this way, the transfer electrode 14 and the first common electrode 22 can be formed simultaneously in the same manufacturing step without adding additional manufacturing steps.

[0656] Moreover, as ​ shown, the first pixel electrode 21 is connected to the second pole T1 of the first transistor T1 through a connection hole L penetrating through to the second pole T1 of the first transistor T1 D of the first transistor T1. In this way, during the manufacturing process of the display panel 100, before forming the first pixel electrode 21, it is necessary to first form a connection hole L penetrating through to the second pole T1 of the first transistor T1 D of the first transistor T1. D of the first transistor T1.

[0657] Based on this, in the display panel 100 provided by some embodiments of the present disclosure, as ​ shown, the first pixel electrode 21 is connected to the second pole T1 of the first transistor T1 through the transfer electrode 14 D of the first transistor T1.

[0658] In this way, before forming the first pixel electrode 21, there is no need to provide a connection hole L. After forming the first pixel electrode 21 and before forming the first common electrode 22, the first transfer via hole R1 and the second transfer via hole R2 are formed simultaneously through a single drilling step, so that the transfer electrode 14 formed in subsequent process steps can connect the first pixel electrode 21 to the second pole T1 of the first transistor T1 through the first transfer via hole R1 and the second transfer via hole R2 D of the first transistor T1. While reducing the power consumption of the display panel 100, it does not add additional process steps.

[0659] As ​ shown, the first pixel electrode 21 is connected to the second pole T1 of the first transistor T1 through a connection hole penetrating through to the second pole T1D of the first transistor T1 D of the first transistor T1. In this way, during the manufacturing process of the display panel 100, before forming the first common electrode 22, it is necessary to first form a connection hole penetrating through to the second pole T1 of the first transistor T1 D of the first transistor T1.

[0660] Exemplarily, the data line DL may be the aforementioned first data line DL1.

[0661] Exemplarily, the third insulating layer J3 and the second spacer layer 33 described above may be the same film structure.

[0662] Exemplarily, as ​ shown, the display panel 100 further includes an active layer B, and the active layer B is located between the first substrate 1 and the gate conductive layer G. The active layer B includes an active pattern, the gate conductive layer G includes a gate conductive pattern, and the overlapping portion of the active pattern and the gate conductive pattern serves as the control electrode of a transistor (such as the first transistor T1 and the second transistor T2).

[0663] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that, It has a display area and a light-transmissive area located on at least one side of the display area; The light-transmissive area emits light of one color within one light-emitting cycle of the light-transmissive area; The display panel includes: A first substrate and a second substrate disposed opposite each other; A liquid crystal layer disposed between the first substrate and the second substrate; A first pixel circuit disposed between the first substrate and the second substrate and located within the display area; The first pixel circuit includes a first pixel electrode and a first common electrode; The first pixel electrode and the first common electrode are configured to drive the movement of liquid crystal molecules in the liquid crystal layer; A second pixel circuit disposed between the first substrate and the second substrate and located within the light-transmissive area; The second pixel circuit includes a second pixel electrode and a second common electrode; The second pixel electrode and the second common electrode are configured to drive the movement of liquid crystal molecules in the liquid crystal layer; A sealing frame portion disposed between the first substrate and the second substrate and surrounding the liquid crystal layer; The inner sidewall of the sealing frame portion is used to define a liquid crystal sealing area, and both the display area and the light-transmissive area are located within the liquid crystal sealing area; A first gate line, a first data line, and a first transistor located within the display area, the first gate line is electrically connected to the first transistor, and the first data line is coupled to the first pixel electrode through the first transistor; A second data line located within the light-transmissive area, the second data line is coupled to the second pixel electrode; The first data line is coupled to the second data line; or, the first data line and the second data line are insulated from each other, the display panel further has a bonding area, and the display panel further includes at least one light-emitting data input terminal located within the bonding area, and the at least one light-emitting data input terminal is coupled to the second data line.

2. The display panel according to claim 1, wherein The display panel includes M light-emitting data input terminals, and the display panel further includes: a light-emitting data driving circuit and M control signal terminals; wherein, the M control signal terminals correspond to the M light-emitting data input terminals one by one, M is greater than or equal to 2; the output terminal of the light-emitting data driving circuit is coupled to the second data line; The light-emitting data driving circuit is configured to output the signal of the corresponding light-emitting data input terminal from the output terminal of the light-emitting data driving circuit in response to the respective operating levels of the M control signal terminals; wherein, when one of the M control signal terminals outputs an operating level, the other control signal terminals output non-operating levels.

3. The display panel according to claim 2, wherein, The display panel includes a first light-emitting data driving circuit and a second light-emitting data driving circuit, and both the first light-emitting data driving circuit and the second light-emitting data driving circuit are the light-emitting data driving circuit; The M control signal terminals include a first control signal terminal and a second control signal terminal; The M light-emitting data input terminals include: a first light-emitting data input terminal and a second light-emitting data input terminal; The display panel includes a plurality of second pixel circuits, the plurality of second pixel circuits including a first-color pixel circuit and a second-color pixel circuit, and the colors of the light emitted from the regions defined by the first-color pixel circuit and the second-color pixel circuit of the display panel are different; the second pixel electrode of the first-color pixel circuit is coupled to the output terminal of the first light-emitting data driving circuit, and the second pixel electrode of the second-color pixel circuit is coupled to the output terminal of the second light-emitting data driving circuit; In the first light-emitting data driving circuit, the first control signal terminal corresponds to the first light-emitting data input terminal, and the second control signal terminal corresponds to the second light-emitting data input terminal; In the second light-emitting data driving circuit, the first control signal terminal corresponds to the second light-emitting data input terminal, and the second control signal terminal corresponds to the first light-emitting data input terminal.

4. The display panel according to claim 2, wherein, The light-emitting data driving circuit includes M transistors, and the control electrodes of the M transistors are respectively coupled to M control signal terminals.

5. The display panel according to claim 4, wherein The second data line is electrically connected to the second pixel electrode; Or, The display panel further includes: a second transistor, and the second data line is coupled to the second pixel electrode through the second transistor.

6. The display panel according to claim 1, wherein The first data line is electrically connected to the second data line; One frame of the display panel includes a picture display stage and a blanking stage, and one light-emitting cycle of the light-transmitting region is within one frame of the display panel; The first data line transmits a first data signal to the first pixel electrode in the picture display stage and transmits a second data signal to the second pixel electrode in the light-emitting cycle.

7. The display panel according to claim 6, wherein, In the light-emitting stage, the light-emitting cycle is shorter than the blanking stage in terms of time length.

8. The display panel according to any one of claims 1 to 7, characterized in that, When the display panel includes the first transistor, the display panel further includes: a first gate driving circuit; the first gate driving circuit includes: an input sub-circuit, a first pull-up node, and a first output sub-circuit; The input sub-circuit is coupled to the input signal terminal and the first pull-up node; the input sub-circuit is configured to transmit the input signal from the input signal terminal to the first pull-up node; The first output sub-circuit is coupled to the first pull-up node, the clock signal terminal, the first signal output terminal, and the second signal output terminal; the first signal output terminal is coupled to the control electrode of the first transistor through the first gate line; the first output sub-circuit is configured to transmit the clock signal from the clock signal terminal to the first signal output terminal under the control of the voltage of the first pull-up node; the first output sub-circuit is further configured to transmit the clock signal from the clock signal terminal to the second signal output terminal under the control of the voltage of the first pull-up node; When the display panel includes the second transistor, the display panel further includes: a second gate driving circuit; the second gate driving circuit includes: a second pull-up node and a second output sub-circuit; The second pull-up node is electrically connected to the enable signal terminal; The second output sub-circuit is coupled to the second pull-up node, the enable signal terminal, and the third signal output terminal; the third signal output terminal is coupled to the control electrode of the second transistor through a second gate line; the second output sub-circuit is configured to transmit the enable signal from the enable signal terminal to the third signal output terminal under the control of the voltage of the second pull-up node, so as to charge the third signal output terminal.

9. The display panel according to claim 8, wherein The first gate circuit further includes: a first control sub-circuit and a first reset sub-circuit; The first control sub-circuit is coupled to the first pull-down node and the first pull-up node; the first control sub-circuit is configured to pull up the first pull-down node and pull down the first pull-up node in response to the high level of the first pull-down node; the first control sub-circuit is further configured to pull down the first pull-down node in response to the high level of the first pull-up node; The first reset sub-circuit is coupled to the first pull-down node, the first signal output terminal, and the second signal output terminal; the first reset sub-circuit is configured to reset the first signal output terminal and the second signal output terminal under the control of the voltage of the first pull-down node; The second gate driving circuit further includes: a third control sub-circuit and a fifth reset sub-circuit; The third control sub-circuit is coupled to the third pull-down node and the second pull-up node; the third control sub-circuit is configured to pull up the third pull-down node and pull down the second pull-up node in response to the high level of the third pull-down node; the third control sub-circuit is further configured to pull down the third pull-down node in response to the high level of the second pull-up node; The fifth reset sub-circuit is coupled to the third pull-down node and the third signal output terminal; the fifth reset sub-circuit is configured to reset the third signal output terminal under the control of the voltage of the third pull-down node.

10. The display panel according to claim 8, wherein, The first output sub-circuit includes: a third transistor M3, a thirteenth transistor M13, and a first capacitor; The control electrode of the third transistor M3 is electrically connected to the first pull-up node, the first electrode of the third transistor M3 is electrically connected to the clock signal terminal, and the second electrode of the third transistor M3 is electrically connected to the first signal output terminal; The first electrode plate of the first capacitor is electrically connected to the first pull-up node, and the second electrode plate of the first capacitor is electrically connected to the second electrode of the third transistor M3; The control electrode of the thirteenth transistor M13 is electrically connected to the first pull-up node, the first electrode of the thirteenth transistor M13 is electrically connected to the clock signal terminal, and the second electrode of the thirteenth transistor M13 is electrically connected to the second signal output terminal; The second output sub-circuit includes: a third transistor N3 and a second capacitor; The control electrode of the third transistor N3 is electrically connected to the second pull-up node, the first electrode of the third transistor N3 is electrically connected to the enable signal terminal, and the second electrode of the third transistor N3 is electrically connected to the third signal output terminal; The first electrode plate of the second capacitor is electrically connected to the second pull-up node, and the second electrode plate of the second capacitor is electrically connected to the second pole of the third transistor N3.

11. The display panel according to claim 1, wherein The display panel includes a gate conductive layer, a first insulating layer, a source-drain conductive layer, a second insulating layer, a pixel electrode layer, a third insulating layer, and a common electrode layer that are sequentially arranged in a direction away from the first substrate. The display panel further includes: a first gate line, a data line, a first transistor, and a transfer electrode; the control electrode of the first transistor is electrically connected to the first gate line, the first pole of the first transistor is electrically connected to the data line, and the second pole of the first transistor is coupled to the first pixel electrode. The first gate line and the control electrode are located in the gate conductive layer, the data line, the first pole, and the second pole are located in the source-drain conductive layer, the first pixel electrode is located in the pixel electrode layer, and the transfer electrode and the first common electrode are located in the common electrode layer. In the orthographic projection onto the first substrate, the transfer electrode at least partially overlaps with the first pixel electrode, and the transfer electrode at least partially overlaps with the second pole. The display panel further includes: A first transfer via hole that penetrates from the transfer electrode to the second pole; the transfer electrode is electrically connected to the second pole through the first transfer via hole. A second transfer via hole that penetrates from the transfer electrode to the first pixel electrode; the transfer electrode is electrically connected to the first pixel electrode through the second transfer via hole.

12. A display module, characterized in that, Comprising: The display panel according to any one of claims 1 to 11; A circuit board, electrically connected to the display panel; the circuit board is configured to send a driving signal to the display panel.

13. The display module according to claim 12, wherein The display panel further has a sensor area on one side of the display area, and the sensor area is located in the liquid crystal sealing area; the display module further includes: A sensor, disposed in the sensor area, and the light-transmitting area is configured to change the color of the emitted light according to the change in the working state of the sensor.

14. A display device, characterized in that, Comprising: A backlight module; The display module according to claim 12 or 13, and the display module is disposed on the light-emitting side of the backlight module; The backlight module has a first backlight area and a second backlight area; The orthographic projection of the display area of the display module onto the backlight module is within the range of the first backlight area; the orthographic projection of the light-transmitting area of the display module onto the backlight module is within the range of the second backlight area.

15. The display device according to claim 14, characterized in that, The turning on and off of the first backlight area and the second backlight area can be independently controlled.

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