Array substrate, display panel and display device

Abstract

According to the array substrate, the display panel and the display device, the array substrate is included in the display device, the display device comprises a backlight module located on the light incidence side of the array substrate, and the array substrate comprises a substrate body which comprises a display area; the multiple insulating film layers are at least arranged in the display area in a stacked mode, the wave crest of the transmission spectrum of the multiple insulating film layers and the wave crest of the emission spectrum of the backlight module are at most partially overlapped, and / or the wave trough of the transmission spectrum of the multiple insulating film layers and the wave trough of the emission spectrum of the backlight module are at most partially overlapped.

Description

[0001] This application claims the priority of a Chinese patent application with the application number 202410005751.6 and the invention title "Array Substrate, Display Panel and Display Device" filed with the National Intellectual Property Administration of the People's Republic of China on January 2, 2024. The entire content thereof is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel and a display device. Background Art

[0003] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high image quality, no radiation and convenient carrying. In recent years, it has developed rapidly and has gradually replaced the traditional Cathode Ray Tube display (CRT), occupying a dominant position in the current flat panel display market. Currently, TFT-LCD has been widely used in various products of different sizes, covering almost all the main electronic products in today's information society, such as liquid crystal TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablet computers, navigators, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays and virtual displays, etc. Summary of the Invention

[0004] Embodiments of the present disclosure provide an array substrate, a display panel and a display device to improve the color shift defect.

[0005] Embodiments of the present disclosure provide an array substrate, a display panel and a display device, and the specific solutions are as follows:

[0006] An array substrate provided by an embodiment of the present disclosure is included in a display device. The display device includes a backlight module on the light incident side of the array substrate. The array substrate includes:

[0007] A substrate, and the substrate includes a display area;

[0008] A plurality of insulating film layers are stacked at least in the display area. The peak of the transmission spectrum of the plurality of insulating film layers and the peak of the emission spectrum of the backlight module overlap at most partially, and / or the trough of the transmission spectrum of the plurality of insulating film layers and the trough of the emission spectrum of the backlight module overlap at most partially.

[0009] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the plurality of insulating film layers include a gate insulating layer and a passivation layer arranged in a stacked manner, wherein the gate insulating layer includes a first silicon nitride layer and a first silicon oxide layer arranged in a stacked manner, the passivation layer includes a second silicon nitride layer, the thickness of the first silicon nitride layer is 3200μm - 4000μm, the thickness of the first silicon oxide layer is 470μm - 610μm, and the thickness of the second silicon nitride layer is 1200μm - 1800μm.

[0010] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the plurality of insulating film layers include a gate insulating layer, and the gate insulating layer includes a first silicon nitride layer, a first silicon oxynitride layer, and a first silicon oxide layer arranged in a stacked manner, and the refractive index of the first silicon oxynitride layer is greater than the refractive index of the first silicon oxide layer and less than the refractive index of the first silicon nitride layer.

[0011] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the thickness of the first silicon oxynitride layer is 850μm - 2300μm.

[0012] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the plurality of insulating film layers include a passivation layer, and the passivation layer includes a second silicon oxide layer, a second silicon oxynitride layer, and a second silicon nitride layer arranged in a stacked manner, and the refractive index of the second silicon oxynitride layer is greater than the refractive index of the second silicon oxide layer and less than the refractive index of the second silicon nitride layer.

[0013] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the thickness of the second silicon nitride layer is 400μm - 600μm.

[0014] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the plurality of insulating film layers include a gate insulating layer, and the gate insulating layer includes at least one hollow structure located in the opening area of the display area.

[0015] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, there are also provided a plurality of first conductive patterns located on the side of the gate insulating layer away from the substrate and / or between the gate insulating layer and the substrate;

[0016] The first conductive pattern is located in the non-opening area of the display area, and the minimum distance between the orthographic projection of the first conductive pattern on the substrate and the orthographic projection of the hollow structure on the substrate is 2.5μm - 5.5μm.

[0017] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, a pixel electrode covering the opening area of the display area is further included. The plurality of first conductive patterns include the first pole of a transistor. The plurality of insulating layers include a passivation layer and a planarization layer on the side of the layer where the first pole of the transistor is located and away from the substrate. The pixel electrode is connected to the first pole of the transistor through a via hole penetrating the passivation layer and the planarization layer.

[0018] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, a plurality of second conductive patterns located on the side of the gate insulating layer away from the substrate are further included. The orthographic projection of the second conductive pattern on the substrate at least partially overlaps with the orthographic projection of the hollow structure on the substrate. The line width of the second conductive pattern is 4 μm to 8 μm.

[0019] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the peak of the transmission spectrum of the plurality of insulating film layers and the peak of the emission spectrum of the backlight module, and the valley of the transmission spectrum of the plurality of insulating film layers and the valley of the emission spectrum of the backlight module are staggered in the wavelength bands of 525 nm to 550 nm and 610 nm to 650 nm.

[0020] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, including the above-mentioned array substrate provided by the embodiments of the present disclosure, and an opposing substrate disposed opposite to the array substrate.

[0021] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure, and a backlight module located on the light-incident side of the display panel.

[0022] In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, the backlight module includes a quantum dot light-emitting device.

[0023] The beneficial effects of the present disclosure are as follows:

[0024] In the array substrate, display panel, and display device provided by the present disclosure, the array substrate is included in the display device. The display device includes a backlight module located on the light-incident side of the array substrate. The array substrate includes: a substrate, the substrate includes a display area; a plurality of insulating film layers stacked at least in the display area. The peak of the transmission spectrum of the plurality of insulating film layers and the peak of the emission spectrum of the backlight module at most partially overlap, and / or the valley of the transmission spectrum of the plurality of insulating film layers and the valley of the emission spectrum of the backlight module at most partially overlap, so that the interference is weakened, thereby improving the color unevenness defect. Description of the Drawings

[0025] Figure 1To show the color deviation phenomenon of the product;

[0026] Figure 2 It is an interference model;

[0027] Figure 3 It is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure;

[0028] Figure 4 It is a schematic diagram of a film layer structure in the display area;

[0029] Figure 5 It is a spectrogram of the film layer in the display area before and after optimization;

[0030] Figure 6a It is a spectrogram comparison diagram provided by an embodiment of the present disclosure;

[0031] Figure 6b It is Figure 6a an enlarged spectrogram comparison diagram of;

[0032] Figure 7 It is another spectrogram comparison diagram provided by an embodiment of the present disclosure;

[0033] Figure 8 It is another spectrogram comparison diagram provided by an embodiment of the present disclosure;

[0034] Figure 9 It is another spectrogram comparison diagram provided by an embodiment of the present disclosure;

[0035] Figure 10 It is a curve graph of the difference between the GI SiN film thickness and (Wx - Wy) provided by an embodiment of the present disclosure;

[0036] Figure 11 It is another curve graph of the difference between the GI SiN film thickness and (Wx - Wy) provided by an embodiment of the present disclosure;

[0037] Figure 12 It is another curve graph of the difference between the GI SiN film thickness and (Wx - Wy) provided by an embodiment of the present disclosure;

[0038] Figure 13 It is another curve graph of the difference between the GI SiN film thickness and (Wx - Wy) provided by an embodiment of the present disclosure;

[0039] Figure 14 It is a curve graph of the difference between the ORG film thickness and (Wx - Wy) provided by an embodiment of the present disclosure;

[0040] Figure 15 It is another curve graph of the difference between the ORG film thickness and (Wx - Wy) provided by an embodiment of the present disclosure;

[0041] Figure 16 Another curve graph of the difference between the ORG film thickness and (Wx - Wy) provided by the embodiment of the present disclosure;

[0042] Figure 17 Another curve graph of the difference between the ORG film thickness and (Wx - Wy) provided by the embodiment of the present disclosure;

[0043] Figure 18 A color dot convergence graph provided by the embodiment of the present disclosure;

[0044] Figure 19 Another color dot convergence graph provided by the embodiment of the present disclosure;

[0045] Figure 20 Another color dot convergence graph provided by the embodiment of the present disclosure;

[0046] Figure 21 Another color dot convergence graph provided by the embodiment of the present disclosure;

[0047] Figure 22 Another color dot convergence graph provided by the embodiment of the present disclosure;

[0048] Figure 23 Another color dot convergence graph provided by the embodiment of the present disclosure;

[0049] Figure 24 Another schematic diagram of the film layer structure in the display area;

[0050] Figure 25 Another schematic diagram of the film layer structure in the display area;

[0051] Figure 26 Another schematic diagram of the film layer structure in the display area;

[0052] Figure 27 Another spectrum comparison graph provided by the embodiment of the present disclosure;

[0053] Figure 28 Another curve graph of the difference between the GI SiN film thickness and (Wx - Wy) provided by the embodiment of the present disclosure;

[0054] Figure 29 Another curve graph of the difference between the ORG film thickness and (Wx - Wy) provided by the embodiment of the present disclosure;

[0055] Figure 30 Another curve graph of the difference between the GI SiN film thickness and (Wx - Wy) provided by the embodiment of the present disclosure;

[0056] Figure 31 Another curve graph of the difference between the ORG film thickness and (Wx - Wy) provided by the embodiment of the present disclosure;

[0057] Figure 32 A chromaticity fluctuation diagram provided by an embodiment of the present disclosure;

[0058] Figure 33 Another chromaticity fluctuation diagram provided by an embodiment of the present disclosure;

[0059] Figure 34 Another chromaticity fluctuation diagram provided by an embodiment of the present disclosure;

[0060] Figure 35 A chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0061] Figure 36 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0062] Figure 37 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0063] Figure 38 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0064] Figure 39 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0065] Figure 40 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0066] Figure 41 Another chromaticity fluctuation diagram provided by an embodiment of the present disclosure;

[0067] Figure 42 Another chromaticity fluctuation diagram provided by an embodiment of the present disclosure;

[0068] Figure 43 Another chromaticity fluctuation diagram provided by an embodiment of the present disclosure;

[0069] Figure 44 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0070] Figure 45 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0071] Figure 46 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0072] Figure 47 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0073] Figure 48 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0074] Figure 49 Another chromaticity distribution diagram provided by an embodiment of the present disclosure;

[0075] Figure 50 Another color point convergence diagram provided by an embodiment of the present disclosure;

[0076] Figure 51 Another structural schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0077] Figure 52 Schematic diagram of a gate insulating layer provided with a hollow structure according to an embodiment of the present disclosure;

[0078] Figure 53 Schematic diagram of a film layer structure at the hollow structure provided by an embodiment of the present disclosure;

[0079] Figure 54 Another spectrum comparison diagram provided by an embodiment of the present disclosure;

[0080] Figure 55 Another curve graph of the difference between the ORG film thickness and (Wx - Wy) provided by an embodiment of the present disclosure;

[0081] Figure 56 Another color point convergence diagram provided by an embodiment of the present disclosure. Detailed implementation manners

[0082] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are enlarged for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described in the present disclosure should not be construed as limited to the specific shapes of the regions shown in the present disclosure, but include shape deviations resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features; the sharp corners illustrated may be rounded, etc. Thus, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the exact shape of the regions, do not reflect true proportions, and are only intended to schematically illustrate the content of the present disclosure.

[0083] Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in the description and claims of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "inner", "outer", "upper" and "lower" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0084] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on the other element or layer, directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "disposed on one side of" another element or layer, the element or layer may be directly on one side of the other element or layer, directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0085] Figure 1 To show the color deviation (such as uneven red and green) phenomenon existing in the product. The inventor found that this is an abnormal color deviation caused by the interference of the backlight between different insulating layers on the array substrate. Figure 2 The interference model is shown, and in the interference model, the optical path difference satisfies the following formula:

[0086]

[0087] Wherein, n1 and n2 are the refractive indices of two adjacent insulating layers respectively, θ1 is the incident angle of the light at the interface between two adjacent insulating layers, θ2 is the exit angle of the light at the interface between two adjacent insulating layers, d is the thickness of the insulating layer with refractive index n1, and Ψ is the finally observed angle.

[0088] In addition, according to the plate interference theory, it can be known that: at a certain wavelength λ, the optical path difference of the film layer is equal to an integer multiple of the wavelength λ (that is, the optical path difference = mλ, m is an integer), and coherent superposition occurs, then the transmittance at the wavelength λ increases; at a certain wavelength λ, the optical path difference of the film layer is equal to a non-integer multiple of the wavelength λ (that is, the optical path difference = (2m+1)λ / 2, m is an integer), and coherent reduction occurs, then the transmittance at the wavelength λ decreases, and its complementary color intensity increases accordingly.

[0089] From the above content, it can be seen that when the film thickness and film properties are coherently enhanced with the backlight, color unevenness is likely to occur. Therefore, in order to improve color deviation such as red and green unevenness, the film interference of the array substrate needs to be reduced as much as possible.

[0090] In order to at least improve the above-mentioned poor color deviation, the embodiment of the present disclosure provides an array substrate. Figure 3 A schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the array substrate includes: a base substrate 101, the base substrate 101 includes a display area AA, and a border area BB located on at least one side of the display area AA, wherein a plurality of gate lines GL and a plurality of data lines DL are arranged in the display area AA, and a plurality of sub-pixel areas SPX (including but not limited to red sub-pixel areas, green sub-pixel areas and blue sub-pixel areas) are defined by the plurality of gate lines GL and the plurality of data lines DL, and optionally, the sub-pixel area SPX includes an opening area for passing backlight.

[0091] Figure 4 is a schematic diagram of a film structure in the display area AA, Figure 5 It is the spectrum diagram of the inner membrane layer before and after optimization in the display area AA, where: Figure 5 Curve A in the middle represents the emission spectrum of the backlight unit (BLU) (also referred to as the backlight spectrum), curve B represents the transmission spectrum of the array substrate under the product design value, and curve C represents the transmission spectrum of the array substrate in the actual product. Due to process fluctuations, curves B and C deviate slightly. Figure 4 and Figure 5 It can be seen that the array substrate provided by the present disclosure includes multiple insulating film layers IL. Optionally, the multiple insulating film layers IL are stacked at least in the display area AA. Before optimization, the peaks of the transmission spectra B and C of the multiple insulating layers IL overlap with the peaks of the backlight spectrum A, resulting in enhanced interference, which will cause color deviation. After the present disclosure optimizes the insulating film layers IL, the peaks of the transmission spectra B and C of the multiple insulating film layers IL can overlap with the peaks of the backlight spectrum A at most partially (for example, staggered from each other), and / or the troughs of the transmission spectra B and C of the multiple insulating film layers IL can overlap with the troughs of the backlight spectrum A at most partially (for example, staggered from each other), thereby reducing interference and improving color unevenness.

[0092] Figure 6aand Figure 6b shows the spectrum REF of the array substrate before optimization, the spectrum Case1 of the array substrate after optimization, and the spectrum of the backlight module BLU. It can be seen from the spectrum comparison that in the middle wavelength part (green light band) of 525nm - 550nm and in the high wavelength part (red light band) of 610nm - 650nm, there is an interference enhancement effect between the REF spectrum and the BLU spectrum, while there is an interference weakening effect between the Case1 spectrum of the present disclosure and the BLU spectrum. Therefore, the design before optimization is prone to color deviation defects such as uneven red and green colors, while the present disclosure can effectively improve the color deviation defects of uneven red and green colors.

[0093] In some embodiments, the spectrum data test can be performed using an optical test instrument equipped in the production line. The optical test instrument is equipped with a C light source (standard light source) and can test the spectrum data within the visible light wavelength range (380nm - 780nm). Moreover, the present disclosure can use simulation software to simulate spectrum data. Specifically, according to the actual production line single-film-thickness substrate test film layer thickness and N (refractive index) / K (extinction coefficient) values, these values are input into the simulation software to generate relevant film layers and form a database (Database). Subsequently, based on the existing database, the same array substrate film layer structure can be established for data simulation. By adjusting the changes in different film layer thicknesses, the spectrum of different array substrate film layers and the change ranges of transmittance & color coordinates under different film layer thickness changes are simulated to benchmark / guide product design. For the backlight spectrum, there are generally two ways to obtain it: First, according to the product specification requirements, the customer will provide the physical backlight spectrum of the client, and the film layer can be matched according to this spectrum; Second, the customer provides the physical backlight for in-factory optical testing, and the relevant testing department can be invited to conduct actual measurement of the backlight spectrum, and this actual measured backlight spectrum can be used for matching and confirmation.

[0094] In some embodiments, as Figure 4 shown, a plurality of insulating film layers IL may include a gate insulating layer 102 and a passivation layer 103 arranged in a stacked manner. Optionally, the gate insulating layer 102 is located between the layer where the gate line GL is located and the layer where the data line DL is located, and the passivation layer 103 is located between the layer where the data line DL is located and the layer where the pixel electrode 105 (the refractive index can be 2.06) is located. In some embodiments, the insulating film layer IL may further include a planarization layer 104 (the refractive index can be 1.54) located between the passivation layer 103 and the layer where the pixel electrode 105 is located. The pixel electrode 105 may be located within the sub-pixel region SPX and cover the opening region of the sub-pixel region SPX, and the pixel electrode 105 may be connected to the first pole (source / drain) of the transistor through a via hole that penetrates the passivation layer 103 and the planarization layer 104 outside the opening region of the sub-pixel region SPX.

[0095] Continue to refer to Figure 4It can be seen that in the present disclosure, the gate insulating layer 102 includes a first silicon nitride layer 1021 and a first silicon oxide layer 1022 which are stacked, and the passivation layer 103 includes a second silicon nitride layer 1031. To improve color shift, the present disclosure optimizes the film thicknesses of the first silicon nitride layer 1021, the first silicon oxide layer 1022, and the second silicon nitride layer 1031. Optionally, in the present disclosure, the thickness of the first silicon nitride layer 1021 is 3200 μm to 4000 μm, such as 3575 μm; the thickness of the first silicon oxide layer 1022 is 470 μm to 610 μm, such as 550 μm; the thickness of the second silicon nitride layer 1031 is 1200 μm to 1800 μm, such as 1500 μm.

[0096] Table 1 shows the film thickness data of the stacked film layers in the array substrate, and the film thickness unit is μm. Among them, Array represents the array substrate, REF represents the film thickness data of the stacked film layers of the array substrate in the reference example, and Case1, Case2, and Case3 represent the film thickness data of the stacked film layers of the array substrate in the embodiments of the present disclosure. GI SIN represents the first silicon nitride layer 1021 of the gate insulating layer 102, GISIO represents the first silicon oxide layer 1022 of the gate insulating layer 102, PVX SIO represents the second silicon oxide layer 1032 of the passivation layer 103, PVX SIN represents the second silicon nitride layer 1031 of the passivation layer 103, ORG represents the planarization layer 104, and ITO represents the pixel electrode 105.

[0097] The bold data in Table 1 are the changed data relative to the reference example REF. As can be seen from Table 1, in the embodiment Case1 of the present disclosure, the film thickness of GI SIN is reduced from 4500 μm to 3575 μm, the film thickness of GI SIO is reduced from 700 μm to 550 μm, and the film thickness of PVX SIN is increased from 500 μm to 1500 μm compared with the reference example REF; in the embodiment Case2, the film thickness of PVX SIN is increased from 500 μm to 1500 μm compared with the reference example REF; in the embodiment Case3, the film thickness of GI SIN is reduced from 4500 μm to 3575 μm, the film thickness of GI SIO is reduced from 700 μm to 550 μm, the film thickness of PVX SIN is increased from 500 μm to 1500 μm, and the refractive index of GI SIN is adjusted from 1.89 to 1.8 compared with the reference example REF.

[0098] Table 1

[0099]

[0100] The present disclosure tested the spectra of the reference example REF, the embodiment Case1, the embodiment Case2, and the embodiment Case3, as Figures 7 to 9As shown; and the present disclosure uses simulation software. In Reference Example REF, Example Case 1, Example Case 2, and Example Case 3, with the thickness of the GI SiN film and the thickness of the ORG film as variables respectively, the fluctuation of the contrast color points of the difference (Wx - Wy) is simulated, as Figures 10 to 17 shown.

[0101] From 7 to Figure 9 It can be seen that compared with Reference Example REF, the amplitude of the spectrum oscillation in Example Case 1, Example Case 2, and Example Case 3 of the present disclosure is smaller and the period is larger, which can effectively reduce the degree of color unevenness.

[0102] From Figures 10 to 13 It can be seen that compared with Reference Example REF, in Example Case 1 of the present disclosure, the period of the color point change due to the change in the thickness of the GI SIN film becomes larger and the amplitude is smaller, which is beneficial to the improvement of color unevenness; in Example Case 2, there is no obvious difference in the change period and amplitude of the thickness of the GI SIN film, and the effect of improving unevenness is poor; in Example Case 3, after the refractive index of GI SiNx decreases, the period of the change in the thickness of the GI SiNx film becomes larger and the amplitude change becomes smaller, the color point change is small, and the color unevenness is relatively improved, but due to the decrease in the refractive index, the film-forming ability of the factory decreases and the defective rate increases, so it is not recommended to use.

[0103] From Figures 14 to 17 It can be seen that compared with Reference Example REF, in Example Case 1, Example Case 2, and Example Case 3 of the present disclosure, the amplitude of the color point change due to the change in the thickness of the ORG film is smaller, but the period also becomes smaller, which is not conducive to the improvement of color unevenness. In addition, since the ORG can effectively prevent the intrusion of water, oxygen, etc. into the transistor and is beneficial to maintaining the transistor characteristics, therefore, it is not appropriate to improve the parameters such as the thickness of the ORG layer.

[0104] In some embodiments, the present disclosure also provides color point convergence diagrams of Reference Example REF and Example Case 1 of the present disclosure, as Figure 18 and Figure 19 shown. Among them, the convergence and divergence of color points is a criterion for evaluating color deviation such as red - green unevenness. According to the convergence and divergence of the color coordinates of the panel (Open Cell, OC), the degree of color unevenness is analyzed by comparison. It mainly tests the color coordinates of 8 * 9 = 72 points in the OC, and calculates the convergence and divergence amplitude compared with the average value of the color coordinates, that is Figure 18 and Figure 19 The color coordinate convergence and divergence diagram and the data change amplitude shown. Comparing Figure 18 and Figure 19It can be seen that, compared with the reference example REF, the color point divergence and convergence of the embodiment Case1 of the present disclosure is reduced from (0.008, 0.017) to (0.003, 0.006), and the degree of color unevenness is relatively light; moreover, visually, the degree of color unevenness (Level) of the embodiment Case1 of the present disclosure is reduced from L3 of the reference example REF to L1.5.

[0105] Table 2

[0106]

[0107]

[0108] In some embodiments, the present disclosure also provides data on the OC with different PVX SiN thicknesses and different GI SiN thicknesses and their visually observed color unevenness levels (Level), as shown in Table 2, with the film thickness unit being μm; the present disclosure also synchronously tested the color coordinate data of 72 points in the OC of the embodiments Case1, Case4, Case5, Case6, and Case7 in Table 2, as Figures 19 to 23 shown. Combining Table 2 and Figures 19 to 23 it can be seen that as the GI SIN thickens, the color unevenness worsens, and as the PVX SIN thins, the color unevenness deteriorates. The visually observed color unevenness levels (Level) of the embodiments Case1, Case6, Case4, Case5, and Case7 are L1.5, L2, L2, L2, and L2.5 in sequence, and the color unevenness improvement effects of the embodiments Case1, Case6, Case4, Case5, and Case7 weaken in sequence. Additionally, through verification, it is found that the new process of the embodiment Case1 generates very few defects and is suitable for mass production.

[0109] In some embodiments, as Figure 24 shown, the gate insulating layer 102 may further include a first silicon oxynitride layer 1023 between the first silicon nitride layer 1021 and the first silicon oxide layer 1022. Optionally, the refractive index of the first silicon oxynitride layer 1023 is greater than the refractive index of the first silicon oxide layer 1022 and less than the refractive index of the first silicon nitride layer 1021. For example, the refractive index of the first silicon nitride layer 1021 is 1.89, the refractive index of the first silicon oxide layer 1022 is 1.46, and the first silicon oxynitride layer 1023 is 1.71. This can make the refractive indices of the respective film layers in the gate insulating layer 102 show a gradual change trend, which is beneficial to reducing film layer interference and improving the color deviation defect. In some embodiments, the thickness of the first silicon oxynitride layer 1023 is 850 μm to 2300 μm, such as 1000 μm, 2000 μm, etc.

[0110] Optionally, as Figure 25 andFigure 26 As shown, the passivation layer 103 may include a second silicon oxynitride layer 1033 between the second silicon nitride layer 1031 and the second silicon oxide layer 1032. Optionally, the refractive index of the second silicon oxynitride layer 1033 is greater than that of the second silicon oxide layer 1032 and less than that of the second silicon nitride layer 1031. For example, the refractive index of the second silicon nitride layer 1031 is 1.89, the refractive index of the second silicon oxide layer 1032 is 1.46, and the second silicon oxynitride layer 1033 is 1.71. This can make the refractive indices of the film layers in the gate insulating layer 103 show a gradual change trend, which is beneficial to reducing film layer interference and improving color shift defects. In some embodiments, the thickness of the second silicon oxynitride layer 1033 is 400μm - 600μm, such as 500μm.

[0111] Table 3 shows the film thickness data of the stacked film layers in the array substrates of Reference Example REF, Example Case8 to Example Case11. The bold data in Table 3 are the changed data relative to Reference Example REF. In some embodiments, to ensure better film formation uniformity of the GI layer, in the present disclosure, the sum of the film thicknesses of GI SIN and GI SION is uniformly set to 4500μm.

[0112] Table 3

[0113]

[0114] The present disclosure has tested the spectra of Reference Example REF and Example Case8, as Figure 27 shown; and the present disclosure uses simulation software to simulate the color point fluctuation of the (Wx - Wy) difference by taking the film thicknesses of GI SiN and ORG as variables in Reference Example REF, Example Case8, and Example Case9, as Figures 28 to 31 shown.

[0115] As can be seen from 27, compared with Reference Example REF, the oscillation amplitude of the spectrum of Example Case8 of the present disclosure is smaller and the period is similar, which can effectively reduce the degree of color non-uniformity. From Figure 28 and Figure 30 it can be seen that compared with Figure 10 of Reference Example REF, the color point change period of the changed GI SIN film thickness in Example Case8 and Example Case9 of the present disclosure becomes larger and the amplitude is smaller, which is beneficial to improving color non-uniformity defects. From Figure 29 and Figure 31 it can be seen that compared with Figure 14 of Reference Example REF, the color point change amplitude of the changed ORG film thickness in Example Case8 and Example Case9 of the present disclosure is smaller and the period is similar, which is beneficial to improving color non-uniformity defects. However, in view of the fact that ORG can effectively prevent the intrusion of water, oxygen, etc. into the transistor and is beneficial to maintaining the transistor characteristics, therefore, it is not appropriate to improve the parameters such as the film thickness of the ORG layer.

[0116] In some embodiments, the present disclosure provides chromaticity fluctuation diagrams (as shown in) under C Light for Reference Example REF, Embodiment Case10, and Case11, chromaticity distribution diagrams (as shown in), chromaticity fluctuation diagrams (as shown in) under backlight (e.g., QD BLU), and chromaticity distribution diagrams (as shown in), where the chromaticity distribution diagram may include contour diagrams of Wy versus measurement coordinate Y and measurement coordinate X, and contour diagrams of Wx versus measurement coordinate Y and measurement coordinate X. Wy is the ordinate of the standard color point, and Wx is the abscissa of the standard color point. As can be seen from Figures 32 to 34 shown), chromaticity distribution (mapping) diagrams (as shown in Figures 35 to 40 shown), chromaticity fluctuation diagrams (as shown in Figures 41 to 43 shown) under backlight (e.g., QD BLU), and chromaticity distribution (mapping) diagrams (as shown in Figures 44 to 49 shown), where the chromaticity distribution diagram may include contour diagrams of Wy versus measurement coordinate Y and measurement coordinate X, and contour diagrams of Wx versus measurement coordinate Y and measurement coordinate X. Wy is the ordinate of the standard color point, and Wx is the abscissa of the standard color point. From Figures 32 to 49 it can be seen that through the actual measurement of the large panel color point data, whether it is under C Light or QD BLU, the chromaticity uniformity tends to be good after adding a suitable silicon oxynitride film layer; from the data distribution and chromaticity mapping, the fluctuations of the color coordinates have converged, and the chromaticity uniformity will be significantly improved.

[0117] In addition, the present disclosure also provides a chromaticity point convergence diagram of Embodiment Case10 (as shown in Figure 50 shown). The visual color non-uniformity degree of Embodiment Case10 is L2, which is 1 level lower than the color non-uniformity degree L3 of Reference Example REF; and by comparing the chromaticity point convergence diagram of Embodiment Case10 shown in Figure 50 shown, and the chromaticity point convergence diagram of Reference Example REF shown in Figure 18 shown, it can be seen that the chromaticity point convergence and divergence of Embodiment Case10 are reduced from (0.008, 0.017) of Reference Example REF to (0.007, 0.011), and the color non-uniformity degree is lighter.

[0118] In some embodiments, as shown in Figures 51 to 53 shown, the gate insulating layer 102 includes at least one hollow structure OW, and the hollow structure OW is located in the opening area O of the display area AA, which can effectively reduce the film interference effect and improve the color shift defect. The inventor verified the hollowing out of the passivation layer 103 in the opening area O, and the results showed that the improvement of this scheme for color non-uniformity is limited compared to the hollowing out of the gate insulating layer 102 in the opening area O. At the same time, after removing the passivation layer 103, the moisture-proof ability of the panel becomes poor, and the uniformity of the passivation layer 103 cannot be controlled, so this scheme is not recommended.

[0119] Figure 54 are the spectra of Reference Example REF and Embodiment Case12 (different from Reference Example REF in that the gate insulating layer 102 is hollowed out in the opening area O). From Figure 54Comparing with the measured spectrum of the reference example REF, the oscillation period of the measured spectrum of the embodiment Case 12 becomes larger and the amplitude is smaller, which can effectively reduce the color unevenness degree.

[0120] Since there is no gate insulating layer 102 in the opening area O of the embodiment Case 12, the simulation software is used in the embodiment Case 12 with the ORG film thickness as a variable to simulate the color point fluctuation situation of the (Wx - Wy) difference, as Figure 55 shown. Comparing with the Figure 14 of the reference example REF, and the Figure 55 of the embodiment Case 12, it can be seen that the color point change period of the ORG film thickness change in the present disclosure is larger and the amplitude is smaller, which is beneficial to improving the color unevenness defect.

[0121] In addition, the present disclosure also provides a color point convergence diagram of the embodiment Case 12, as Figure 56 shown. The visual color unevenness degree of the embodiment Case 12 is L1, which is 2 levels lower than the color unevenness degree L3 of the reference example REF; and comparing with the color point convergence diagram of the embodiment Case 12 shown in Figure 56 , and the color point convergence diagram of the reference example REF shown in Figure 18 , it can be seen that the color point convergence and divergence of the embodiment Case 12 is reduced from (0.008, 0.017) of the reference example REF to (0.003, 0.01), and the color unevenness degree is lighter.

[0122] In some embodiments, as Figure 51 and Figure 52 shown, the array substrate includes a plurality of first conductive patterns (such as common electrode lines CL, gate lines GL, data lines DL, transistors TFT, etc.) disposed in the non-opening area of the display area AA. Optionally, the common electrode lines CL, gate lines GL, and the gates of the transistors TFT are provided on the same layer and made of the same material, and are located between the gate insulating layer 102 and the substrate 101; the data lines DL, the first and second poles of the transistors TFT are provided on the same layer and made of the same material, and are located on the side of the gate insulating layer 102 away from the substrate 101; optionally, to ensure the conductive characteristics of the first conductive pattern, the minimum distance d between the positive projection of the first conductive pattern on the substrate 101 and the positive projection of the hollow structure OW on the substrate 101 can be set to 2.5 μm to 5.5 μm, such as 3 μm.

[0123] In some embodiments, as Figure 51 and Figure 52As shown, it may further include a plurality of second conductive patterns (such as discharge lines DSL) located on the side of the gate insulating layer 102 away from the substrate 101. Optionally, the discharge lines DSL are arranged on the same layer and made of the same material as the data lines DL. The orthographic projection of the second conductive pattern (such as the discharge line DSL) on the substrate 101 at least partially overlaps with the orthographic projection of the hollow structure OW on the substrate 101. Since at the edge of the hollow structure OW, the gate insulating layer 102 forms a fault, if the second conductive pattern (such as the discharge line DSL) above it is relatively small, it is easy to break the line at the edge of the hollow structure OW. Therefore, to reduce the risk of line breakage, the present disclosure sets the line width w of the second conductive pattern (such as the discharge line DSL) to be 4 μm to 8 μm, for example 5 μm.

[0124] In some embodiments, as Figure 51 and Figure 52 shown, the common electrode line CL can overlap with the edge portion of the gate line GL, and the middle portion of the common electrode line CL does not overlap with the gate line GL. In this way, the common electrode line CL can effectively shield the signal of the gate line GL, so that the pixel electrode 105 is not interfered by the signal of the gate line GL, but forms a coupling capacitor with the common electrode line CL. The voltage of the common electrode line CL is about 7V (for example 8V), and the voltage difference between the common electrode line CL and the pixel electrode 105 is about 0 to 7V, which is less than the voltage difference of 16V to 30V between the gate line GL and the pixel electrode 105 in the related art. Thus, the phenomenon that the liquid crystal molecules rotate abnormally and light up due to the electric field formed by the large voltage difference can be effectively improved. Moreover, the middle portion of the gate line GL does not overlap with the common electrode line CL, which is beneficial to reducing the load of the gate line GL.

[0125] In some embodiments, as Figure 51 and Figure 52 shown, the edge portion of the gate line GL has an overlapping area with the first pole of the transistor TFT, and at least part of the overlapping area does not overlap with the common electrode line CL. In the process of manufacturing the array substrate, the first pole, the second pole, and the active layer of the transistor TFT may be short-circuited with the gate line GL through the conductive particles (particles) remaining in the process. At this time, the present disclosure can cut off the first pole, the second pole, and the active layer at the short-circuit position to solve the problem of the short circuit between the first pole, the second pole, and the active layer and the gate line GL; moreover, the present disclosure can perform cross-layer connection at the position where the overlapping area does not overlap with the common electrode line CL by using the material of the layer where the common electrode line CL is located to connect the cut-off first pole, second pole, and active layer to ensure the normal operation of the transistor TFT.

[0126] Based on the same inventive concept, embodiments of the present disclosure provide a display panel, including the above-described array substrate provided by the embodiments of the present disclosure, and an opposing substrate disposed opposite to the array substrate; optionally, the opposing substrate includes a black matrix, color filters, and a common electrode sequentially disposed on the side facing the array substrate; wherein, the common electrode is disposed over the entire display area, the black matrix is a grid-like structure, the gate lines and data lines are both within the range of the black matrix, and the color filters are within the mesh holes of the black matrix.

[0127] In some embodiments, the display panel provided by the embodiments of the present disclosure may further include a liquid crystal layer between the array substrate and the opposing substrate, and a first polarizer may be disposed on the side of the array substrate away from the opposing substrate, and a second polarizer may be disposed on the side of the opposing substrate away from the array substrate, and the polarization directions of the first polarizer and the second polarizer are perpendicular to each other. Other essential components in the display panel should be understood by those of ordinary skill in the art and will not be elaborated herein, nor should they be considered as a limitation to the present disclosure.

[0128] Based on the same inventive concept, embodiments of the present disclosure provide a display device, including the above-described display panel provided by the embodiments of the present disclosure, and a backlight module located on the light incident side of the display panel. The backlight module may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include a light bar, a reflective sheet, a light guide plate, a diffusion sheet, a prism group, etc. stacked, and the light bar is located on one side in the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffusion plate, a brightness enhancement film, etc. stacked on the light-emitting side of the matrix light source, and the reflective sheet includes openings disposed opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices. Since there is an effect of enhanced light wave interference between the insulating layer and the backlight spectrum after using quantum dot (QD) backlight, the color non-uniformity abnormality is more obvious. The present disclosure can reduce the interference between the QD backlight and the insulating layer through the above solution, thereby effectively improving the color non-uniformity abnormality.

[0129] In some embodiments, the lamp beads can also be micro light-emitting devices (such as Mini LED, Micro LED), etc. Micro light-emitting devices in the sub-millimeter scale or even the micron scale, like organic light-emitting devices (OLEDs), belong to self-luminous devices. Similar to organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and extremely large viewing angles. And because inorganic light-emitting devices emit light based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices that emit light based on organic substances, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life. Moreover, when the micro light-emitting device is used as a backlight, a more precise dynamic backlight effect can be achieved. While effectively improving the screen brightness and contrast, it can also solve the glare phenomenon caused by traditional dynamic backlights between the bright and dark areas of the screen, optimizing the visual experience.

[0130] In some embodiments, the above-mentioned display device provided by the embodiments of the present disclosure can be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any product or component with a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip, etc. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, and may also include a power module, etc., and realizes the power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include a hardware circuit and computer-executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays, as well as existing semiconductors such as logic chips and transistors, or other discrete components; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, etc. Additionally, the above structure does not constitute a limitation on the above-mentioned display device provided by the embodiments of the present disclosure. In other words, the above-mentioned display device provided by the embodiments of the present disclosure may include more or fewer of the above components, or combine some components, or have different component arrangements.

[0131] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0132] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these changes and modifications.

Claims

1. An array substrate is included in a display device, and the display device includes a backlight module located on the light-incident side of the array substrate, characterized in that, The array substrate includes: a substrate, the substrate including a display area; a plurality of insulating film layers, stacked at least in the display area, wherein a peak of the transmission spectrum of the plurality of insulating film layers overlaps at most partially with a peak of the emission spectrum of the backlight module, and / or a valley of the transmission spectrum of the plurality of insulating film layers overlaps at most partially with a valley of the emission spectrum of the backlight module.

2. The array substrate according to claim 1, wherein The plurality of insulating film layers includes a gate insulating layer and a passivation layer stacked, wherein the gate insulating layer includes a first silicon nitride layer and a first silicon oxide layer stacked, the passivation layer includes a second silicon nitride layer, the thickness of the first silicon nitride layer is 3200μm - 4000μm, the thickness of the first silicon oxide layer is 470μm - 610μm, and the thickness of the second silicon nitride layer is 1200μm - 1800μm.

3. The array substrate according to claim 1, characterized in that, The plurality of insulating film layers includes a gate insulating layer, the gate insulating layer includes a first silicon nitride layer, a first silicon oxynitride layer and a first silicon oxide layer stacked, and the refractive index of the first silicon oxynitride layer is greater than that of the first silicon oxide layer and less than that of the first silicon nitride layer.

4. The array substrate according to claim 3, wherein The thickness of the first silicon oxynitride layer is 850μm - 2300μm.

5. The array substrate according to any one of claims 1 to 4, characterized in that, The plurality of insulating film layers includes a passivation layer, the passivation layer includes a second silicon oxide layer, a second silicon oxynitride layer and a second silicon nitride layer stacked, and the refractive index of the second silicon oxynitride layer is greater than that of the second silicon oxide layer and less than that of the second silicon nitride layer.

6. The array substrate according to claim 5, wherein The thickness of the second silicon nitride layer is 400μm - 600μm.

7. The array substrate according to any one of claims 1 to 4 and 6, characterized in that The plurality of insulating film layers includes a gate insulating layer, the gate insulating layer includes at least one hollow structure, and the hollow structure is located in an opening area of the display area.

8. The array substrate according to claim 7, wherein Further included are a plurality of first conductive patterns located on a side of the gate insulating layer away from the substrate and / or between the gate insulating layer and the substrate; The first conductive pattern is located in a non-opening area of the display area, and the minimum distance between the orthographic projection of the first conductive pattern on the substrate and the orthographic projection of the hollow structure on the substrate is 2.5μm - 5.5μm.

9. The array substrate according to claim 8, wherein, Further included is a pixel electrode covering the opening area of the display area, the plurality of first conductive patterns includes a first pole of a transistor, the plurality of insulating layers includes a passivation layer and a planarization layer located on a side of the layer where the first pole of the transistor is located away from the substrate, and the pixel electrode is connected to the first pole of the transistor through a via hole penetrating the passivation layer and the planarization layer.

10. The array substrate according to claim 7, characterized in that, Further included are a plurality of second conductive patterns located on a side of the gate insulating layer away from the substrate, the orthographic projection of the second conductive pattern on the substrate overlaps at least partially with the orthographic projection of the hollow structure on the substrate, and the line width of the second conductive pattern is 4μm - 8μm.

11. The array substrate according to any one of claims 1 to 4, 6, and 8 to 10, characterized in that The peaks of the transmission spectra of the multiple insulating film layers are offset from the peaks of the emission spectrum of the backlight module, and the valleys of the transmission spectra of the multiple insulating film layers are offset from the valleys of the emission spectrum of the backlight module within the wavelength bands of 525 nm to 550 nm and 610 nm to 650 nm.

12. A display panel, characterized in that, It includes an array substrate according to any one of claims 1 to 11, and an opposing substrate disposed opposite to the array substrate.

13. A display device, characterized in that, It includes a display panel according to claim 12, and a backlight module located on the light incident side of the display panel.

14. The display device according to claim 13, wherein The backlight module includes a quantum dot light-emitting device.

Images