Linear voltage regulator and electronic equipment

Abstract

The invention relates to a linear voltage regulator and electronic equipment, and belongs to the field of electronic circuits. The linear voltage regulator comprises an internal power supply module, an FVF output stage and a control module, the internal power supply module is used for outputting a stable internal power supply according to the reference voltage; the FVF output stage is used for outputting load voltage required by a load; the control module is connected with the internal power supply module and the FVF output stage, and the control module is used for controlling the output voltage of the FVF output stage to be unchanged when the power supply voltage of the linear voltage regulator changes; and when the load of the linear voltage regulator changes, the output voltage of the FVF output stage is controlled to be unchanged. A stable internal power supply is generated through the internal power supply module to supply power to the control module, so that the control module is not affected by power supply electric fluctuation, the output voltage of the FVF output stage is controlled to be unchanged when the power supply voltage of the linear voltage regulator changes and / or the load changes, and the problem that the output voltage of an existing linear voltage regulator is unstable is solved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, and particularly relates to a linear voltage regulator and an electronic device. Background Art

[0002] Almost all electronic circuits require a voltage regulator to provide a stable voltage source to ensure the correct operation of the electronic circuit. And the LDO (Low Dropout Regulator) is one of the voltage regulators. The circuit diagram of a traditional LDO is as Figure 1 shown, including: an error amplifier, a bias voltage generation circuit (V SET Generation), and an FVF (Flipped Voltage Follower) output stage.

[0003] In a traditional LDO, there is a parasitic capacitance between the gate and the drain of the power transistor (M Pass in the figure). For example, when the power supply voltage V IN drops, the gate voltage cannot fully follow it down, resulting in a decrease in its gate-source voltage and a decrease in the output voltage V OUT which can only recover after a certain time. Similarly, when the power supply voltage rises, it will also cause the output voltage to increase. If the LDO is applied to a low-power application, the decrease in the output voltage caused by the drop in the power supply voltage will be more obvious. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a linear voltage regulator and an electronic device to improve the problem of unstable output voltage of the existing linear voltage regulator.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, an embodiment of this application provides a linear voltage regulator, including: an internal power supply module, an FVF output stage, and a control module; the internal power supply module is used to output a stable internal power supply according to a reference voltage; the FVF output stage is used to output a load voltage required by a load; the control module is connected to the internal power supply module and the FVF output stage, and the control module is used to control the output voltage of the FVF output stage to remain unchanged when the power supply voltage of the linear voltage regulator changes; and to control the output voltage of the FVF output stage to remain unchanged when the load of the linear voltage regulator changes.

[0007] In the above embodiments, a stable internal power supply is generated by the internal power supply module to supply power to the control module, so that the control module is not affected by power fluctuations, so that when the power supply voltage of the linear regulator changes and / or the load changes, the output voltage of the FVF output stage remains unchanged, and a stable output voltage can be output to improve the problem of unstable output voltage of the existing linear regulator.

[0008] In a possible implementation manner combining the embodiments of the first aspect, the FVF output stage includes: a first transistor, a second transistor, a third transistor, and an adjustment transistor; the gate of the first transistor is connected to a first bias voltage, the drain of the first transistor is connected to the gate of the second transistor, and the source of the first transistor is connected to the drain of the third transistor; the source of the second transistor is connected to the power supply voltage, the drain of the second transistor is connected to the source of the third transistor, and the drain of the second transistor is used to output the load voltage; the gate of the third transistor is connected to a second bias voltage; wherein, the gate of each adjustment transistor is connected to the control module; the drain of the first transistor is connected to the power supply voltage through one of the adjustment transistors, and / or, the drain of the third transistor is grounded through one of the adjustment transistors.

[0009] In the above embodiments, with the FVF output stage having the above structure, when the drain of the first transistor is connected to the power supply voltage through an adjustment transistor, the gate voltage of the second transistor is adjusted through the adjustment transistor, so that the output voltage can be stabilized. When the drain of the third transistor is grounded through an adjustment transistor, the drain-source current of the second transistor is adjusted through the adjustment transistor to stabilize the output voltage to meet the requirements of different scenarios.

[0010] In a possible implementation manner combining the embodiments of the first aspect, the control module includes: a first detection circuit and a first adjustment circuit; wherein, the first detection circuit is used to detect whether the power supply voltage changes; the first adjustment circuit is used to control the output voltage of the FVF output stage to remain unchanged when the power supply voltage changes.

[0011] In the above embodiments, with the control module having the above structure, the control module can control the output voltage of the FVF output stage to remain unchanged when the power supply voltage of the linear regulator changes, so that a stable output voltage can be output.

[0012] In a possible implementation manner combining with the embodiments of the first aspect, if the drain of the first transistor is connected to the power supply voltage through one of the adjustment transistors; the first detection circuit includes a first capacitor and a first resistor, one end of the first capacitor is connected to the first resistor, the other end of the first capacitor is connected to the internal power supply, and the first resistor is also connected to the first adjustment circuit; the first adjustment circuit includes: a fourth transistor and a fifth transistor; the source of the fourth transistor is connected to the power supply voltage, the gate of the fourth transistor is connected to the gate of the adjustment transistor through the first resistor, the gate of the fourth transistor is also connected to the drain of the fourth transistor, and the gate of the fourth transistor is also grounded through a current source; the source of the fifth transistor is connected to the internal power supply, the gate of the fifth transistor is connected to the gate of the third transistor, the drain of the fifth transistor is connected to the gate of the fifth transistor, and the drain of the fifth transistor is also grounded through a current source; the fifth transistor is used to provide a second bias voltage for the third transistor.

[0013] In the above embodiment, for the control module with the above structure, since the internal power supply is stable, when the power supply voltage drops, because the voltage across the first capacitor cannot change suddenly, the capacitor will make the gate voltage of the fourth transistor drop more slowly than the power supply voltage, thereby reducing the gate-source voltage of the adjustment transistor, and further reducing the current flowing into the gate of the second transistor (power transistor), helping the gate voltage of the second transistor to drop faster, so as to maintain the stability of the output voltage. That is, by making the "gate" voltage of the second transistor drop faster to keep up with the drop speed of the power supply voltage, so that the "gate-source" voltage of the second transistor remains unchanged. The situation of the rising power supply voltage can be deduced by analogy.

[0014] In a possible implementation manner combining with the embodiments of the first aspect, if the drain of the third transistor is grounded through one of the adjustment transistors; the first detection circuit includes a third capacitor and a third resistor, one end of the third capacitor is connected to the power supply voltage, the other end of the third capacitor is connected to the third resistor, and the third resistor is further connected to the first adjustment circuit; the first adjustment circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the source of the fifth transistor is connected to the internal power supply, the gate of the fifth transistor is connected to the gate of the third transistor, the drain of the fifth transistor is connected to the gate of the fifth transistor, and the drain of the fifth transistor is further grounded through a current source; the fifth transistor is used to provide a second bias voltage for the third transistor; the source of the sixth transistor is grounded, the gate of the sixth transistor is connected to the gate of the adjustment transistor, and the gate of the sixth transistor is further connected to the drain of the sixth transistor; the drain of the seventh transistor is connected to the drain of the sixth transistor, the source of the seventh transistor is connected to the internal power supply, and the gate of the seventh transistor is connected to one end of the third resistor; the source of the eighth transistor is connected to the internal power supply, the gate of the eighth transistor is connected to the other end of the third capacitor through the third resistor, the gate of the eighth transistor is further connected to the drain of the eighth transistor, and the drain of the eighth transistor is further grounded through a current source.

[0015] In the above embodiment, for the control module with the above structure, since the voltages on both sides of the third capacitor cannot change suddenly, when the power supply voltage drops, the third capacitor will increase the gate-source voltage of the seventh transistor, increase the current flowing through the seventh transistor, and there will be additional current injected into the sixth transistor, thereby increasing the drain-source current of the adjustment transistor, and further reducing the current flowing into the gate of the power transistor (the second transistor), so that the gate-source voltage of the power transistor remains unchanged when the power supply voltage drops, thus maintaining the stability of the output voltage.

[0016] In a possible implementation manner combining with the embodiments of the first aspect, the control module includes: a second detection circuit and a second adjustment circuit; the second detection circuit is used to detect whether the load of the linear regulator changes; the second adjustment circuit is used to control the output voltage of the FVF output stage to remain unchanged when the load of the linear regulator changes.

[0017] In the above embodiment, for the control module with the above structure, the control module can control the output voltage of the FVF output stage to remain unchanged when the load of the linear regulator changes, so as to output a stable output voltage.

[0018] In a possible implementation manner combining with the embodiments of the first aspect, if the drain of the first transistor is connected to the power supply voltage through one of the regulating transistors; the second detection circuit includes a second capacitor and a second resistor, one end of the second capacitor is connected to the second resistor, the other end of the second capacitor is connected to the source of the third transistor, and the second resistor is also connected to the second regulating circuit; the second regulating circuit includes: a fourth transistor, a fifth transistor, and a first current mirror; the source of the fourth transistor is connected to the power supply voltage, the gate of the fourth transistor is connected to the gate of the regulating transistor, the gate of the fourth transistor is also connected to the drain of the fourth transistor, and the gate of the fourth transistor is connected to the first current mirror; the source of the fifth transistor is connected to the internal power supply, the gate of the fifth transistor is connected to the gate of the third transistor, the drain of the fifth transistor is connected to the gate of the fifth transistor, and the drain of the fifth transistor is also grounded through a current source; the fifth transistor is used to provide a second bias voltage for the third transistor; the gates of the two transistors in the first current mirror are connected through the second resistor.

[0019] In the above embodiment, for the control module with the above structure, on the premise that the power supply voltage remains unchanged, when the load current of the linear regulator LDO increases, the output voltage VOUT will decrease. Since the voltage across the second capacitor cannot change suddenly, when VOUT decreases, the second capacitor will reduce the current of the first current mirror, thereby reducing the current flowing through the regulating transistor, and thus reducing the current flowing into the gate of the power transistor (the second transistor), helping the gate voltage of the power transistor to drop faster, causing VOUT to rise and quickly return to the stable value.

[0020] In a possible implementation manner combining with the embodiments of the first aspect, if the drain of the third transistor is grounded through one of the regulating transistors; the second detection circuit includes: a fourth capacitor and a fourth resistor; one end of the fourth capacitor is connected to the fourth resistor, the other end of the second capacitor is connected to the source of the third transistor, and the fourth resistor is also connected to the second regulating circuit; the second regulating circuit includes: a fifth transistor, a sixth transistor, a ninth transistor, and a tenth transistor; the source of the fifth transistor is connected to the internal power supply, the gate of the fifth transistor is connected to the gate of the third transistor, the drain of the fifth transistor is connected to the gate of the fifth transistor, and the drain of the fifth transistor is also grounded through a current source; the fifth transistor is used to provide a second bias voltage for the third transistor; the source of the sixth transistor is grounded, the gate of the sixth transistor is connected to the gate of the regulating transistor, and the gate of the sixth transistor is also connected to the drain of the sixth transistor; the drain of the ninth transistor is connected to the drain of the sixth transistor, the source of the ninth transistor is connected to the internal power supply, and the gate of the ninth transistor is connected to the gate of the tenth transistor through the fourth resistor; the source of the tenth transistor is connected to the internal power supply, the drain of the tenth transistor is connected to the gate of the tenth transistor, and the drain of the tenth transistor is also grounded through a current source.

[0021] In the above embodiment, for the control module with the above structure, on the premise that the power supply voltage remains unchanged, when the load current of the linear regulator LDO increases, the output voltage VOUT will decrease. Since the voltage across the fourth capacitor cannot change suddenly, when VOUT decreases, the fourth capacitor will cause the gate voltage of the ninth transistor to decrease, and the drain-source current of the ninth transistor will increase. Through the current mirroring of the sixth transistor and the regulating transistor, the current flowing through the regulating transistor increases, so that the current flowing into the gate of the power transistor (the second transistor) decreases, helping the gate voltage of the power transistor to drop faster, making VOUT rise, and quickly restoring to the stable value.

[0022] In a possible implementation manner combining with the embodiments of the first aspect, the internal power supply module includes: a clamping loop and a second current mirror. The clamping loop is used to output a stable internal power supply according to the reference voltage; the second current mirror is used to provide the bias current required for the operation of the clamping loop.

[0023] In the above embodiment, by using the internal power supply module including the clamping loop, the internal power supply can be stabilized through the regulation of the loop, and it is also convenient to adjust.

[0024] In a possible implementation manner combining with the embodiments of the first aspect, the clamping loop includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, and an eighth switching transistor; the gate of the first switching transistor is connected to the second current mirror, the source of the first switching transistor is grounded, and the drain of the first switching transistor is respectively connected to the source of the second switching transistor and the source of the third switching transistor; the gate of the second switching transistor is connected to the reference voltage, and the drain of the second switching transistor is connected to the drain of the fourth switching transistor; the gate of the third switching transistor is connected to the gate of the seventh switching transistor, and the drain of the third switching transistor is connected to the drain of the fifth switching transistor; the gate of the fourth switching transistor is connected to the drain of the fourth switching transistor, the drain of the fourth switching transistor is further connected to the gate of the sixth switching transistor, and the source of the fourth switching transistor is connected to the power supply voltage; the gate of the fifth switching transistor is connected to the drain of the fifth switching transistor, and the source of the fifth switching transistor is connected to the power supply voltage; the source of the sixth switching transistor is connected to the power supply voltage, the drain of the sixth switching transistor is connected to the source of the seventh switching transistor, and the drain of the sixth switching transistor is further used to output the internal power supply; the gate of the seventh switching transistor is further connected to the drain of the seventh switching transistor, the drain of the seventh switching transistor is connected to the source of the eighth switching transistor; the gate of the eighth switching transistor is connected to the drain of the eighth switching transistor, and the drain of the eighth switching transistor is further grounded.

[0025] In the above embodiment, the clamping loop with the above structure is adopted. Among them, the first to fifth switching transistors belong to the operational amplifier circuit, and together with the sixth to eighth switching transistors, they mainly constitute the clamping loop, so that the gate voltage of the third switching transistor is equal to the reference voltage VREF, and further the internal power supply is equal to twice the reference voltage. By adjusting the value of the reference voltage VREF, the value of the internal power supply can be adjusted.

[0026] In a possible implementation manner combining with the embodiments of the first aspect, the control module is further configured to adjust the internal power supply module to keep the internal power supply constant when the power supply voltage changes.

[0027] In the above embodiment, the control module can also adjust the internal power supply module to keep the internal power supply constant when the power supply voltage changes, so as to obtain a stable internal power supply, which can increase the design flexibility of the internal power supply module.

[0028] In a possible implementation manner combining with the embodiments of the first aspect, the control module further includes: a third adjustment circuit connected to the first detection circuit in the control module; the third adjustment circuit is configured to adjust the internal power supply module to keep the internal power supply constant when the power supply voltage changes.

[0029] In the above embodiments, by additionally adding a third adjustment circuit to adjust the internal power supply module to keep the internal power supply constant when the power supply voltage changes, not only the applicability of the solution is increased, but also it is convenient for the control module to be modularly designed, which is beneficial to simplifying the design difficulty of the control module.

[0030] Combined with a possible implementation manner of the first aspect embodiment, if the first detection circuit includes a third capacitor and a third resistor, one end of the third capacitor is connected to the power supply voltage, the other end of the third capacitor is connected to the third resistor, and the third resistor is also connected to the third adjustment circuit; the third adjustment circuit includes: an eighth transistor, an eleventh transistor, and a third current mirror; the source electrode of the eighth transistor is connected to the internal power supply, the gate electrode of the eighth transistor is connected to the gate electrode of the eleventh transistor through the third resistor, the gate electrode of the eighth transistor is also connected to the drain electrode of the eighth transistor, and the drain electrode of the eighth transistor is also connected to the third current mirror; the source electrode of the eleventh transistor is connected to the internal power supply, and the drain electrode of the eleventh transistor is internally connected to the internal power supply module.

[0031] In the above embodiments, for the control module with the above structure, when the power supply voltage drops, the third capacitor increases the gate-source voltage of the eleventh transistor, increases the drain-source current of the eleventh transistor, and further increases the current of the first switching transistor and the current of the fourth switching transistor, so as to increase the drain-source current of the sixth switching transistor to maintain the stability of the internal power supply.

[0032] In a second aspect, an embodiment of the present application further provides an electronic device, including: a linear voltage regulator provided in any implementation manner of the first aspect embodiment as described above.

[0033] Other features and advantages of the present application will be described in the subsequent specification. The objectives and other advantages of the present application can be achieved and obtained through the structures specifically pointed out in the written specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings. As shown in the drawings, the above and other objectives, features, and advantages of the present application will be clearer.

[0035] Figure 1 It is a circuit schematic diagram of an LDO in the prior art.

[0036] Figure 2 It shows a structural schematic diagram of a linear voltage regulator provided by an embodiment of the present application.

[0037] Figure 3a Shows the circuit schematic diagram of the first FVF output stage provided by the embodiment of the present application.

[0038] Figure 3b Shows the circuit schematic diagram of the second FVF output stage provided by the embodiment of the present application.

[0039] Figure 3c Shows the circuit schematic diagram of the third FVF output stage provided by the embodiment of the present application.

[0040] Figure 4a Shows the circuit schematic diagram of the connection between the first control module provided by the embodiment of the present application and the FVF output stage.

[0041] Figure 4b Shows the circuit schematic diagram of the connection between the second control module provided by the embodiment of the present application and the FVF output stage.

[0042] Figure 4c Shows the circuit schematic diagram of the connection between the third control module provided by the embodiment of the present application and the FVF output stage.

[0043] Figure 4d Shows the circuit schematic diagram of the connection between the fourth control module provided by the embodiment of the present application and the FVF output stage.

[0044] Figure 5a Shows the circuit schematic diagram of the first internal power supply module provided by the embodiment of the present application.

[0045] Figure 5b Shows the circuit schematic diagram of the second internal power supply module provided by the embodiment of the present application.

[0046] Figure 6 Shows the circuit schematic diagram of the connection between a control module provided by the embodiment of the present application and the internal power supply module.

[0047] Figure 7 Shows the circuit schematic diagram of a linear voltage regulator provided by the embodiment of the present application. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, but cannot be used to limit the protection scope of the present application. Those skilled in the art can understand that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0049] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, further definition and explanation thereof is not required in subsequent figures. At the same time, in the description of the present application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0050] Furthermore, the term "and / or" in the present application is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0051] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the technical term "connection" may be a direct connection or an indirect connection through an intermediate medium.

[0052] The embodiments of the present application provide a novel linear voltage regulator, which can still output a stable output voltage when the power supply voltage and / or the load of the linear voltage regulator change. The following is combined with Figure 2 The linear voltage regulator provided by the embodiments of the present application will be described. The linear voltage regulator includes: an internal power supply module, an FVF output stage, and a control module. The control module is connected to the internal power supply module and the FVF output stage.

[0053] Among them, the internal power supply module is used to output a stable internal power supply (such as represented by V_internal) according to a reference voltage (such as represented by VREF). The FVF output stage is used to output the load voltage (such as represented by VOUT) required by the load. The control module is used to control the output voltage of the FVF output stage to remain unchanged when the power supply voltage (such as represented by VDD) of the linear voltage regulator changes; and / or, to control the output voltage of the FVF output stage to remain unchanged when the load of the linear voltage regulator changes.

[0054] In some possible embodiments, the FVF output stage includes: a first transistor, a second transistor, a third transistor, and an adjustment transistor. The gate of the first transistor is connected to a first bias voltage, the drain of the first transistor is connected to the gate of the second transistor, and the source of the first transistor is connected to the drain of the third transistor. The source of the second transistor is connected to a power supply voltage, the drain of the second transistor is connected to the source of the third transistor, and the drain of the second transistor is used to output a load voltage. The gate of the third transistor is connected to a second bias voltage. Among them, the number of adjustment transistors can be one or two, and the gate of each adjustment transistor is connected to a control module. The drain of the first transistor is connected to the power supply voltage through an adjustment transistor, and / or the drain of the third transistor is grounded through an adjustment transistor.

[0055] When the number of adjustment transistors is one, as Figure 3a shown, it can be that the drain of the first transistor M23 is connected to the power supply voltage VDD through an adjustment transistor M22. At this time, the drain of the third transistor M25 is grounded through a current source.

[0056] When the number of adjustment transistors is one, as Figure 3b shown, it can be that the drain of the third transistor M25 is grounded through an adjustment transistor M26. At this time, the drain of the first transistor M23 is connected to the power supply voltage VDD through a current source.

[0057] When the number of adjustment transistors is two, as Figure 3c shown, the drain of the first transistor M23 is connected to the power supply voltage VDD through an adjustment transistor M22, and the drain of the third transistor M25 is grounded through an adjustment transistor M26.

[0058] Figure 3a 、 Figure 3b 、 Figure 3c In M23, M27, and M25, M23 represents the first transistor, M27 represents the second transistor, M25 represents the third transistor, and M22 and M26 both represent adjustment transistors.

[0059] In some possible embodiments, the first bias voltage can be the internal power supply V_internal. At this time, Figure 3a 、 Figure 3b 、 Figure 3cThe first bias voltage in [it] is the internal power supply. In some embodiments, the gate of M23 may not be connected to V_internal. As long as the first bias voltage can ensure that M25 and M26 operate in the saturation region. For example, the gate voltage of M23 needs to be greater than the saturation voltage of M26 plus the gate-source voltage of M23, and less than the output voltage VOUT minus the saturation voltage of M25 plus the gate-source voltage of M23. The voltage value of the first bias voltage can be any voltage within this range, that is, (saturation voltage of M26 + gate-source voltage of M23) < first bias voltage < (output voltage - saturation voltage of M25 + gate-source voltage of M23).

[0060] In some possible embodiments, the second bias voltage can be provided by a control module. The functions of the control module are different, and the corresponding circuit structures are also different. For example, the control module may include: a first detection circuit and a first adjustment circuit, and / or, a second detection circuit and a second adjustment circuit. That is to say, the control module may include a first detection circuit and a first adjustment circuit, or, the control module may include a second detection circuit and a second adjustment circuit. In some embodiments, the control module may include both a first detection circuit and a first adjustment circuit as well as a second detection circuit and a second adjustment circuit.

[0061] The first detection circuit is connected to the first adjustment circuit, and the second detection circuit is connected to the second adjustment circuit. Among them, the first detection circuit is used to detect whether the power supply voltage changes; the first adjustment circuit is used to control the output voltage of the FVF output stage to remain unchanged when the power supply voltage changes. The second detection circuit is used to detect whether the load of the linear regulator changes; the second adjustment circuit is used to control the output voltage of the FVF output stage to remain unchanged when the load of the linear regulator changes.

[0062] The structure of the FVF output stage is different, and the structure of the control module can also be different. Correspondingly, the structures of the first adjustment circuit and the second adjustment circuit can also be different.

[0063] For example, if the drain of the first transistor is connected to the power supply voltage through an adjustment transistor, and the control module includes: a first detection circuit and a first adjustment circuit. At this time, the structure of the control module is as Figure 4aAs shown in the figure. Among them, the first detection circuit includes a first capacitor C1 and a first resistor R1. One end of the first capacitor C1 is connected to the first resistor R1, the other end of the first capacitor C1 is connected to the internal power supply V_internal, and the first resistor R1 is also connected to the first adjustment circuit. The first adjustment circuit includes: a fourth transistor M21 and a fifth transistor M24. The source of the fourth transistor M21 is connected to the power supply voltage. The gate of the fourth transistor M21 is connected to the gate of the adjustment transistor M22 through the first resistor R1. The gate of the fourth transistor M21 is also connected to the drain of the fourth transistor M21. The gate of the fourth transistor M21 is also grounded through a current source. The source of the fifth transistor M24 is connected to the internal power supply. The gate of the fifth transistor M24 is connected to the gate of the third transistor M25. The drain of the fifth transistor M24 is connected to the gate of the fifth transistor M24. The drain of the fifth transistor M24 is also grounded through a current source. The fifth transistor M24 is used to provide a second bias voltage for the third transistor M25.

[0064] Figure 4a The structure of the FVF output stage in the schematic diagram shown is as Figure 3a shown, Figure 4a In the figure, C1 represents the first capacitor, and R1 represents the first resistor. M21 represents the fourth transistor, and M24 represents the fifth transistor. The size of M24 is equal to the size of M25 to ensure that the current flowing through M24 is equal to the current flowing through M25. Since the V_internal voltage is stable, when the power supply voltage drops, due to the fact that the voltage across both sides of the first capacitor C1 cannot change suddenly, C1 will cause the gate voltage of M21 to drop more slowly than the power supply voltage, resulting in a decrease in the gate-source voltage of M21 and M22. And the direction of the drain-source current of M22 is from the power supply voltage into the gate node of M27. Therefore, the current flowing into the gate of M27 decreases, helping the gate voltage of M27 to drop faster. By setting the values of C1 and R1, the gate-source voltage of M27 can be kept unchanged when the power supply voltage drops, thereby maintaining the stability of the output voltage. That is, by making the "gate" voltage of M27 drop faster to keep up with the drop speed of the power supply voltage, the "gate-source" voltage of M27 remains unchanged. Among them, the above is only an example of the power supply voltage dropping, and the situation when the power supply voltage rises can be deduced by analogy. For a P-type transistor, if the gate voltage rises, the gate-source voltage drops, and vice versa, if the gate voltage drops, the gate-source voltage rises. And the N-type transistor is opposite to the P-type transistor.

[0065] For another example, if the drain of the first transistor M23 is connected to the power supply voltage through an adjustment transistor M22, and the control module includes: a second detection circuit and a second adjustment circuit. At this time, the structure of the control module is as Figure 4bAs shown. Among them, the second detection circuit includes a second capacitor C2 and a second resistor R2. One end of the second capacitor C2 is connected to the second resistor R2, and the other end of the second capacitor C2 is connected to the source of the third transistor M25. The second resistor R2 is also connected to the second adjustment circuit. The second adjustment circuit includes: a fourth transistor M21, a fifth transistor M24, and a first current mirror (including Figure 4b the current sources I2, M19, and M20 therein). The source of the fourth transistor M21 is connected to the power supply voltage. The gate of the fourth transistor M21 is connected to the gate of the adjustment transistor M22. The gate of the fourth transistor M21 is also connected to the drain of the fourth transistor M21. The gate of the fourth transistor M21 is connected to the first current mirror. For example, the gate of the fourth transistor M21 is connected to the drain of M20 in the first current mirror. The source of the fifth transistor M24 is connected to the internal power supply. The gate of the fifth transistor M24 is connected to the gate of the third transistor M25. The drain of the fifth transistor M24 is connected to the gate of the fifth transistor M24. The drain of the fifth transistor M24 is also grounded through a current source. The fifth transistor M24 is used to provide a second bias voltage for the third transistor M25. The gates of the two transistors (M19 and M20) in the first current mirror are connected through the second resistor R2.

[0066] Figure 4b The structure of the FVF output stage in the schematic diagram shown is as Figure 3a shown, Figure 4b In Figure 4b , C2 represents the second capacitor, and R2 represents the second resistor. M21 represents the fourth transistor, and M24 represents the fifth transistor. The size of M24 is equal to the size of M25 to ensure that the current flowing through M24 is equal to the current flowing through M25. On the premise that the power supply voltage remains unchanged, when the load current of the linear regulator LDO increases, VOUT will decrease. Since the voltage across both sides of the second capacitor C2 cannot change suddenly, when VOUT decreases, C2 will cause the gate voltage of M20 to decrease, and the drain-source current of M20 will decrease. Through the current mirroring of M21 and M22, the current flowing through M22 will decrease, thereby reducing the current flowing into the gate of M27, helping the gate voltage of M27 to drop faster, increasing VOUT, and quickly restoring to the stable value. By setting the values of C2 and R2, the fluctuation of VOUT can be reduced and the recovery speed can be accelerated without affecting the stability of the FVF output loop. Among them, the above only takes the decrease of VOUT of the LDO as an example, and the situation when the VOUT of the LDO rises can be deduced by analogy.

[0067] Another example is that if the drain of the third transistor M25 is grounded through an adjustment transistor M26, and the control module includes: a first detection circuit and a first adjustment circuit. At this time, the structure of the control module is as Figure 4cAs shown in the figure. Among them, the first detection circuit includes a third capacitor C3 and a third resistor R3. One end of the third capacitor C3 is connected to the power supply voltage, the other end of the third capacitor C3 is connected to the third resistor R3, and the third resistor R3 is also connected to the first adjustment circuit. The first adjustment circuit includes: a fifth transistor M24, a sixth transistor M18, a seventh transistor M15, and an eighth transistor M13. The source of the fifth transistor M24 is connected to the internal power supply, the gate of the fifth transistor M24 is connected to the gate of the third transistor M25, the drain of the fifth transistor M24 is connected to the gate of the fifth transistor M24, and the drain of the fifth transistor M24 is also grounded through a current source. The fifth transistor M24 is used to provide a second bias voltage for the third transistor. The source of the sixth transistor M18 is grounded, the gate of the sixth transistor M18 is connected to the gate of the adjustment transistor M26, and the gate of the sixth transistor M18 is also connected to the drain of the sixth transistor M18. The drain of the seventh transistor M15 is connected to the drain of the sixth transistor M18, the source of the seventh transistor M15 is connected to the internal power supply, and the gate of the seventh transistor M15 is connected to one end of the third resistor R3 and the other end of the third capacitor C3. The source of the eighth transistor M13 is connected to the internal power supply, the gate of the eighth transistor M13 is connected to the other end of the third capacitor C3 through the third resistor R3, the gate of the eighth transistor M13 is also connected to the drain of the eighth transistor M13, and the drain of the eighth transistor M13 is also grounded through a current source.

[0068] Figure 4c The structure of the FVF output stage in the schematic diagram shown is as Figure 3b shown, Figure 4c In the figure, C3 represents the third capacitor, and R3 represents the third resistor. M24 represents the fifth transistor, M18 represents the sixth transistor, M15 represents the seventh transistor, and M13 represents the eighth transistor. Since V_internal is stable and unchanged, the voltage across both sides of the third capacitor C3 cannot change suddenly. When the power supply voltage drops, C3 will cause the gate voltage of M15 to drop, thereby increasing the gate-source voltage of M15, increasing the current flowing through M15, and injecting additional current into M18. Through the current mirror including M18 and M26, the drain-source current of M26 is increased, thereby reducing the current flowing into the gate of M27 and helping the gate voltage of M27 to drop faster. By setting the values of C3 and R3, the gate-source voltage of M27 can be kept unchanged when the power supply voltage drops, thereby maintaining the stability of the output voltage. Among them, the above only takes the drop of the power supply voltage as an example, and the situation when the power supply voltage rises can be deduced by analogy.

[0069] For another example, if the drain of the third transistor M25 is grounded through an adjustment transistor M26, and the control module includes: a second detection circuit and a second adjustment circuit. At this time, the structure of the control module is as Figure 4dAs shown in the figure. Among them, the second detection circuit includes: a fourth capacitor C4 and a fourth resistor R4; one end of the fourth capacitor C4 is connected to the fourth resistor R4, the other end of the fourth capacitor C4 is connected to the source of the third transistor M25, and the fourth resistor R4 is also connected to the second adjustment circuit. The second adjustment circuit includes: a fifth transistor M24, a sixth transistor M18, a ninth transistor M17, and a tenth transistor M16. The source of the fifth transistor M24 is connected to the internal power supply, the gate of the fifth transistor M24 is connected to the gate of the third transistor M25, the drain of the fifth transistor M24 is connected to the gate of the fifth transistor M24, and the drain of the fifth transistor M24 is also grounded through a current source; the fifth transistor M24 is used to provide a second bias voltage for the third transistor M25. The source of the sixth transistor M18 is grounded, the gate of the sixth transistor M18 is connected to the gate of the adjustment transistor M26, and the gate of the sixth transistor M18 is also connected to the drain of the sixth transistor M18. The drain of the ninth transistor M17 is connected to the drain of the sixth transistor M18, the source of the ninth transistor M17 is connected to the internal power supply, and the gate of the ninth transistor M17 is connected to the gate of the tenth transistor M16 through the fourth resistor R4. The source of the tenth transistor M16 is connected to the internal power supply, the drain of the tenth transistor M16 is connected to the gate of the tenth transistor M16, and the drain of the tenth transistor M16 is also grounded through a current source.

[0070] Figure 4d The structure of the FVF output stage in the schematic diagram shown is as Figure 3b shown, Figure 4d In the figure, C4 represents the fourth capacitor, R4 represents the fourth resistor. M24 represents the fifth transistor, M18 represents the sixth transistor, M17 represents the ninth transistor, and M16 represents the tenth transistor. On the premise that the power supply voltage remains unchanged, when the load current of the linear regulator LDO increases, VOUT will decrease. Since the voltage across both sides of the fourth capacitor C4 cannot change suddenly, when VOUT decreases, C4 will cause the gate voltage of M17 to decrease, and the drain-source current of M17 will increase. Through the current mirroring of M18 and M26, the current flowing through M26 will increase, thereby reducing the current flowing into the gate of M27, helping the gate voltage of M27 to drop faster, making VOUT rise, and quickly restoring to the stable value. By setting the values of C4 and R4, the fluctuation of VOUT can be reduced and the recovery speed can be accelerated without affecting the stability of the FVF output loop. Among them, the above only takes the decrease of VOUT of the LDO as an example, and the situation when VOUT of the LDO rises can be deduced by analogy.

[0071] Based on the above description, it can be known that the structure of the first adjustment circuit when the structure of the FVF output stage is as Figure 3a shown is different from the structure of the first adjustment circuit when the structure of the FVF output stage is as Figure 3b shown. Similarly, when the structure of the FVF output stage is asFigure 3a The structure of the second adjustment circuit when shown is also different from the structure of the FVF output stage. In addition, Figure 3b The structure of the second adjustment circuit when shown is also different. In addition, Figure 4a , Figure 4b , Figure 4c , Figure 4d The control modules shown can be combined with each other to obtain control modules with different structures. For example, in some embodiments, the control module can simultaneously include Figure 4a , Figure 4b , Figure 4c , Figure 4d At least two or more of the structures shown.

[0072] In a possible embodiment, the internal power supply module can use a conventional power supply module on the market as long as it can output the required voltage. In a possible embodiment, the internal power supply module includes: a clamping loop and a second current mirror. The second current mirror is used to provide the bias current required for the operation of the clamping loop. The clamping loop is used to output a stable internal power supply according to the reference voltage. For example, the internal power supply can be twice the reference voltage, that is, V_internal = 2VREF.

[0073] In a possible embodiment, the schematic diagram of the internal power supply module can be as Figure 5a shown. The clamping loop includes: a first switching transistor M2, a second switching transistor M3, a third switching transistor M4, a fourth switching transistor M5, a fifth switching transistor M6, a sixth switching transistor M7, a seventh switching transistor M8, an eighth switching transistor M9. The gate of the first switching transistor M2 is connected to the second current mirror (including Figure 5ais connected to the current sources I1, M1, and M2 therein. The source of the first switching transistor M2 is grounded, and the drain of the first switching transistor M2 is connected to the sources of the second switching transistor M3 and the third switching transistor M4 respectively. The gate of the second switching transistor M3 is connected to a reference voltage, and the drain of the second switching transistor M3 is connected to the drain of the fourth switching transistor M5. The gate of the third switching transistor M4 is connected to the gate of the seventh switching transistor M8, and the drain of the third switching transistor M4 is connected to the drain of the fifth switching transistor M6. The gate of the fourth switching transistor M5 is connected to the drain of the fourth switching transistor M5, and the drain of the fourth switching transistor M5 is further connected to the gate of the sixth switching transistor M7. The source of the fourth switching transistor M5 is connected to a power supply voltage. The gate of the fifth switching transistor M6 is connected to the drain of the fifth switching transistor M6, and the source of the fifth switching transistor M6 is connected to the power supply voltage. The source of the sixth switching transistor M7 is connected to the power supply voltage. The drain of the sixth switching transistor M7 is connected to the source of the seventh switching transistor M7, and the drain of the sixth switching transistor M7 is further used to output an internal power supply. The gate of the seventh switching transistor M7 is further connected to the drain of the seventh switching transistor M7, and the drain of the seventh switching transistor M7 is connected to the source of the eighth switching transistor M9. The gate of the eighth switching transistor M9 is connected to the drain of the eighth switching transistor M9, and the drain of the eighth switching transistor M9 is further grounded.

[0074] Figure 5a In the above, M2 represents the first switching transistor, M3 represents the second switching transistor, M4 represents the third switching transistor, M5 represents the fourth switching transistor, M6 represents the fifth switching transistor, M7 represents the sixth switching transistor, M8 represents the seventh switching transistor, and M9 represents the eighth switching transistor. Among them, the second current mirror shares M2 to achieve the purpose of cost saving and circuit area reduction. Figure 5a The clamping loop including M2 to M9 therein makes the gate voltage of M4 equal to VREF. The sizes of M8 and M9 are exactly the same, so that V_internal is equal to 2 times VREF. By adjusting the value of the reference voltage VREF, the value of the internal voltage V_internal can be adjusted. Among them, a loop is formed by the gate of M4 -> the source of M4 -> the source of M3 -> the drain of M3 -> the drain of M5 -> the gate of M7 -> the drain of M7 -> the source of M8 -> the drain of M8 -> the gate of M4.

[0075] In some other embodiments, the schematic diagram of the internal power supply module can be as Figure 5b shown. Figure 5b and Figure 5aIn comparison, the difference is that there is an additional fifth capacitor C5. When the power supply voltage VDD drops, VREF may also drop, causing V_internal to drop, and thus causing VOUT to drop, which is not desirable. Therefore, the fifth capacitor C5 is added. When VDD drops, C5 will pull down the gate voltage of M4, thereby offsetting the impact of the drop in VREF. Through C5, the drop in VREF when the power supply voltage drops is compensated. By reasonably setting the value of C5, the gate voltage of M4 can drop at the same rate as the power supply voltage drops, the same rate as VREF drops when the power supply voltage drops, thereby offsetting the impact of VREF dropping as the power supply voltage drops. Thus, V_internal is stabilized. If VREF does not drop as VDD drops, then C5 is not necessary.

[0076] In some other possible embodiments, the control module is further configured to adjust the internal power supply module to keep the internal power supply constant when the power supply voltage changes. In this embodiment, the control module further includes: a third adjustment circuit connected to the first detection circuit in the control module; the third adjustment circuit is configured to adjust the internal power supply module to keep the internal power supply constant when the power supply voltage changes.

[0077] If the first detection circuit includes a third capacitor C3 and a third resistor R3, one end of the third capacitor C3 is connected to the power supply voltage, the other end of the third capacitor C3 is connected to the third resistor R3, and the third resistor R3 is also connected to the third adjustment circuit. At this time, as Figure 6 shown, the third adjustment circuit includes: an eighth transistor M13, an eleventh transistor M12, and a third current mirror (including Figure 6 the current source I2, transistors M10, M11 therein). The source of the eighth transistor M13 is connected to the internal power supply, the gate of the eighth transistor M13 is connected to the gate of the eleventh transistor M12 through the third resistor R3, the gate of the eighth transistor M13 is also connected to the drain of the eighth transistor M13, and the drain of the eighth transistor M13 is also connected to the third current mirror. The source of the eleventh transistor M12 is connected to the internal power supply, and the drain of the eleventh transistor M12 is internally connected to the internal power supply module.

[0078] Figure 6In the illustrated example, M13 represents the eighth transistor and M12 represents the eleventh transistor. When the power supply voltage VDD drops, it is necessary to keep the internal power supply unchanged. Since M7 needs to provide a larger current when the power supply voltage drops, the gate voltage of M7 must drop faster than the power supply voltage. Therefore, the current mirror including M10 - M11 injects additional current into M1. When the power supply voltage drops, C3 increases the gate-source voltage of M12, increasing the drain-source current of M12. The additional current is injected into M1, and through the current mirror including M1 and M2, the current of M2 increases, causing the current of M5 to increase. Through the current mirror of M5 and M7, the drain-source current of M7 will increase to maintain the stability of the V_internal voltage. That is, when the power supply voltage drops, through C3, M12, and M2, an additional tail current is provided for the operational amplifier circuit, increasing the drain-source current of M5, thereby increasing the drain-source current of M7 to maintain the stability of the V_internal voltage.

[0079] In some possible implementation manners, the circuit schematic diagram of the linear voltage regulator shown in the present application may be as Figure 7 shown. Among them, M24 and M25, M26 and M28 are respectively matched to ensure that the current densities of M24 and M25 are equal. At this time, if M24 and M25 operate in the saturation region, the output voltage VOUT of the LDO is equal to the internal voltage V_internal. By adjusting the value of the reference voltage VREF, the internal voltage V_internal can be adjusted to make VOUT equal to the target output value. V_internal requires a relatively large capacitor (C6) to ground to help maintain voltage stability.

[0080] The following describes the circuit operation process when the power supply voltage or the output voltage of the LDO changes. Taking the drop of the power supply voltage or the output voltage of the LDO as an example, the situation when the power supply voltage or the output voltage of the LDO rises can be deduced by analogy.

[0081] When the power supply voltage VDD drops, it is necessary to keep the internal power supply unchanged. The internal power supply can be kept unchanged through the adjustment path of C3 -> M12 -> M1 -> M2 -> M3 -> M5 -> M7. For example, when the power supply voltage drops, C3 increases the gate-source voltage of M12 (for a P-type switching transistor, when the gate voltage drops, the gate-source voltage rises), increasing the drain-source current of M12. The additional current is injected into M1, and through the current mirror of M1 and M2, the current of M2 increases, and correspondingly, the currents of M3 and M5 also increase. Through the current mirror of M5 and M7, the drain-source current of M7 also increases. By making the gate voltage of M7 drop faster to keep up with the drop speed of the power supply voltage, the internal power supply is kept unchanged.

[0082] When the power supply voltage VDD drops, the control module can adjust the FVF output stage through two paths to keep the output voltage VOUT unchanged. The adjustment path 1 is C3 -> M15 -> M18 -> M26 -> M27. For example, when the power supply voltage drops, C3 increases the gate-source voltage of M15, increasing the drain-source current of M15, thereby increasing the drain-source current of M26, which helps the gate voltage of the power transistor M27 to drop faster, thus stabilizing VOUT. The adjustment path 2 is C1 -> M21 -> M22 -> M27. For example, when the power supply voltage drops, the gate voltage of M21 drops more slowly than the power supply voltage because the voltage across the capacitor C1 cannot change suddenly, resulting in a decrease in the gate-source voltage of M21 and M22. The capacitor C1 reduces the gate-source voltage of M22 when the power supply voltage drops, thereby reducing the current flowing into the gate of the power transistor M27, helping the gate voltage of M27 to drop faster, thus stabilizing VOUT.

[0083] On the premise that the power supply voltage remains unchanged, if the load of the LDO changes, the control module can also adjust the FVF output stage through two paths to keep the output voltage VOUT unchanged. The adjustment path 1 is C4 -> M17 -> M18 -> M26 -> M27. For example, when the load current of the LDO increases, VOUT decreases. C4 detects the mutation of VOUT, reduces the gate voltage of M17, increases the drain-source current, and through the current mirror including M18 and M26, increases the current of M26, thereby reducing the current flowing into the gate of the power transistor M27, helping the gate voltage of M27 to drop faster, increasing VOUT, and quickly restoring it to the stable value. The adjustment path 2 is C2 -> M20 -> M21 -> M22 -> M27. For example, when the load current of the LDO increases, VOUT decreases. C2 detects the mutation of VOUT, reduces the gate voltage of M20, reduces the drain-source current, and through the current mirror of M21 and M22, reduces the current of M22. Therefore, the net current flowing out of the gate of M27 helps the gate voltage of M27 to drop, increasing VOUT and restoring it to the stable value.

[0084] If the circuit schematic diagram of the linear regulator is as Figure 7 shown, then Figure 4a 、 Figure 4b the current source under M25 in Figure 7 can be the equivalent current source of I2 + M10 + M14 + M16 + M17 + M18 + M26 connected to M10 in Figure 4a 、 Figure 4b 、 Figure 4c 、 Figure 4d the current source under M24 in Figure 7 can be the equivalent current source of I2 + M10 + M28 in Figure 4a the current source under M21 inFigure 7 The equivalent current source of I2 + M19 + M20 in Figure 4c and Figure 4d The current source above M23 in Figure 7 The equivalent current source of I2 + M19 + M20 + M22 in Figure 4c The current source below M13 in Figure 7 The equivalent current source of I2 + M10 + M11 in Figure 4d The current source below M16 in Figure 7 The equivalent current source of I2 + M10 + M14 in

[0085] The embodiments of the present application also provide an electronic device, which includes the above linear voltage regulator. Among them, the above electronic device includes, but is not limited to, mobile phones, tablets, computers, servers, etc.

[0086] The linear voltage regulator provided by the embodiments of the electronic device has the same implementation principle and technical effects as those of the foregoing linear voltage regulator embodiments. For a brief description, for the parts not mentioned in the embodiments of the electronic device, reference may be made to the corresponding content in the foregoing linear voltage regulator embodiments.

[0087] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0088] In addition, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0089] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A linear voltage regulator, characterized in that, Comprising: An internal power supply module for outputting a stable internal power supply according to a reference voltage; An FVF output stage for outputting a load voltage required by a load; A control module connected to the internal power supply module and the FVF output stage. The control module is configured to control the output voltage of the FVF output stage to remain unchanged when the power supply voltage of the linear voltage regulator changes; and to control the output voltage of the FVF output stage to remain unchanged when the load of the linear voltage regulator changes.

2. The linear voltage regulator according to claim 1, characterized in that, The FVF output stage includes: a first transistor, a second transistor, a third transistor, and an adjustment transistor; The gate of the first transistor is connected to a first bias voltage, the drain of the first transistor is connected to the gate of the second transistor, and the source of the first transistor is connected to the drain of the third transistor; The source of the second transistor is connected to the power supply voltage, the drain of the second transistor is connected to the source of the third transistor, and the drain of the second transistor is used to output the load voltage; the gate of the third transistor is connected to a second bias voltage; Wherein, the gate of each adjustment transistor is connected to the control module; the drain of the first transistor is connected to the power supply voltage through one of the adjustment transistors, and / or, the drain of the third transistor is grounded through one of the adjustment transistors.

3. The linear voltage regulator according to claim 2, characterized in that, The control module includes: a first detection circuit and a first adjustment circuit; wherein, the first detection circuit is configured to detect whether the power supply voltage changes; The first adjustment circuit is configured to control the output voltage of the FVF output stage to remain unchanged when the power supply voltage changes.

4. The linear voltage regulator according to claim 3, wherein, If the drain of the first transistor is connected to the power supply voltage through one of the adjustment transistors; The first detection circuit includes a first capacitor and a first resistor. One end of the first capacitor is connected to the first resistor, the other end of the first capacitor is connected to the internal power supply, and the first resistor is also connected to the first adjustment circuit; The first adjustment circuit includes: a fourth transistor and a fifth transistor; The source of the fourth transistor is connected to the power supply voltage, the gate of the fourth transistor is connected to the gate of the adjustment transistor through the first resistor, the gate of the fourth transistor is also connected to the drain of the fourth transistor, and the gate of the fourth transistor is also grounded through a current source; The source of the fifth transistor is connected to the internal power supply, the gate of the fifth transistor is connected to the gate of the third transistor, the drain of the fifth transistor is connected to the gate of the fifth transistor, and the drain of the fifth transistor is also grounded through a current source; the fifth transistor is used to provide a second bias voltage for the third transistor.

5. The linear voltage regulator according to claim 3, characterized in that, If the drain of the third transistor is grounded through one of the adjustment transistors; The first detection circuit includes a third capacitor and a third resistor. One end of the third capacitor is connected to the power supply voltage, the other end of the third capacitor is connected to the third resistor, and the third resistor is also connected to the first adjustment circuit; The first adjustment circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The source of the fifth transistor is connected to the internal power supply, the gate of the fifth transistor is connected to the gate of the third transistor, the drain of the fifth transistor is connected to the gate of the fifth transistor, and the drain of the fifth transistor is also grounded through a current source; the fifth transistor is used to provide a second bias voltage for the third transistor; The source of the sixth transistor is grounded, the gate of the sixth transistor is connected to the gate of the regulating transistor, and the gate of the sixth transistor is also connected to the drain of the sixth transistor; The drain of the seventh transistor is connected to the drain of the sixth transistor, the source of the seventh transistor is connected to the internal power supply, and the gate of the seventh transistor is connected to one end of the third resistor; The source of the eighth transistor is connected to the internal power supply, the gate of the eighth transistor is connected to the other end of the third capacitor through the third resistor, the gate of the eighth transistor is also connected to the drain of the eighth transistor, and the drain of the eighth transistor is also grounded through a current source.

6. The linear voltage regulator according to claim 2, wherein The control module includes: a second detection circuit and a second adjustment circuit; The second detection circuit is used to detect whether the load of the linear regulator changes; The second adjustment circuit is used to control the output voltage of the FVF output stage to remain unchanged when the load of the linear regulator changes.

7. The linear voltage regulator according to claim 6, wherein If the drain of the first transistor is connected to the power supply voltage through one of the regulating transistors; The second detection circuit includes a second capacitor and a second resistor. One end of the second capacitor is connected to the second resistor, the other end of the second capacitor is connected to the source of the third transistor, and the second resistor is also connected to the second adjustment circuit; The second adjustment circuit includes: a fourth transistor, a fifth transistor, and a first current mirror; The source of the fourth transistor is connected to the power supply voltage, the gate of the fourth transistor is connected to the gate of the regulating transistor, the gate of the fourth transistor is also connected to the drain of the fourth transistor, and the gate of the fourth transistor is connected to the first current mirror; The source of the fifth transistor is connected to the internal power supply, the gate of the fifth transistor is connected to the gate of the third transistor, the drain of the fifth transistor is connected to the gate of the fifth transistor, and the drain of the fifth transistor is also grounded through a current source; the fifth transistor is used to provide a second bias voltage for the third transistor; The gates of the two transistors in the first current mirror are connected through the second resistor.

8. The linear voltage regulator according to claim 6, characterized in that, If the drain of the third transistor is grounded through one of the regulating transistors; The second detection circuit includes: a fourth capacitor and a fourth resistor; one end of the fourth capacitor is connected to the fourth resistor, the other end of the second capacitor is connected to the source of the third transistor, and the fourth resistor is also connected to the second adjustment circuit; The second adjustment circuit includes: a fifth transistor, a sixth transistor, a ninth transistor, and a tenth transistor; The source of the fifth transistor is connected to the internal power supply. The gate of the fifth transistor is connected to the gate of the third transistor. The drain of the fifth transistor is connected to the gate of the fifth transistor. The drain of the fifth transistor is also grounded through a current source. The fifth transistor is used to provide a second bias voltage for the third transistor. The source of the sixth transistor is grounded. The gate of the sixth transistor is connected to the gate of the regulating transistor. The gate of the sixth transistor is also connected to the drain of the sixth transistor. The drain of the ninth transistor is connected to the drain of the sixth transistor. The source of the ninth transistor is connected to the internal power supply. The gate of the ninth transistor is connected to the gate of the tenth transistor through the fourth resistor. The source of the tenth transistor is connected to the internal power supply. The drain of the tenth transistor is connected to the gate of the tenth transistor. The drain of the tenth transistor is also grounded through a current source.

9. The linear voltage regulator according to claim 1, characterized in that, The internal power supply module includes: A clamping loop for outputting a stable internal power supply according to the reference voltage. A second current mirror for providing a bias current required for the operation of the clamping loop.

10. The linear voltage regulator according to claim 9, characterized in that, The clamping loop includes: A first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, and an eighth switching transistor. The gate of the first switching transistor is connected to the second current mirror. The source of the first switching transistor is grounded. The drain of the first switching transistor is respectively connected to the source of the second switching transistor and the source of the third switching transistor. The gate of the second switching transistor is connected to the reference voltage. The drain of the second switching transistor is connected to the drain of the fourth switching transistor. The gate of the third switching transistor is connected to the gate of the seventh switching transistor. The drain of the third switching transistor is connected to the drain of the fifth switching transistor. The gate of the fourth switching transistor is connected to the drain of the fourth switching transistor. The drain of the fourth switching transistor is also connected to the gate of the sixth switching transistor. The source of the fourth switching transistor is connected to the power supply voltage. The gate of the fifth switching transistor is connected to the drain of the fifth switching transistor. The source of the fifth switching transistor is connected to the power supply voltage. The source of the sixth switching transistor is connected to the power supply voltage. The drain of the sixth switching transistor is connected to the source of the seventh switching transistor. The drain of the sixth switching transistor is also used to output the internal power supply. The gate of the seventh switching transistor is also connected to the drain of the seventh switching transistor. The drain of the seventh switching transistor is connected to the source of the eighth switching transistor. The gate of the eighth switching transistor is connected to the drain of the eighth switching transistor. The drain of the eighth switching transistor is also grounded.

11. The linear voltage regulator according to any one of claims 1-10, characterized in that The control module is further configured to, when the power supply voltage changes, adjust the internal power supply module to keep the internal power supply constant.

12. The linear voltage regulator according to claim 11, characterized in that, The control module further includes: a third adjustment circuit connected to the first detection circuit in the control module. The third adjustment circuit is configured to, when the power supply voltage changes, adjust the internal power supply module to keep the internal power supply constant.

13. The linear voltage regulator according to claim 12, wherein If the first detection circuit includes a third capacitor and a third resistor, one end of the third capacitor is connected to the power supply voltage, the other end of the third capacitor is connected to the third resistor, and the third resistor is also connected to the third adjustment circuit; The third adjustment circuit includes: an eighth transistor, an eleventh transistor, and a third current mirror; The source of the eighth transistor is connected to the internal power supply, the gate of the eighth transistor is connected to the gate of the eleventh transistor through the third resistor, the gate of the eighth transistor is also connected to the drain of the eighth transistor, and the drain of the eighth transistor is also connected to the third current mirror; The source of the eleventh transistor is connected to the internal power supply, and the drain of the eleventh transistor is internally connected to the internal power supply module.

14. An electronic device, characterized in that, Including: The linear voltage regulator according to any one of claims 1-13.

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