Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: evaluating the health degree of a first entity unit in a storage device to obtain a health degree evaluation value; in response to a data reading event for the first entity unit, determining whether the health degree evaluation value meets a preset condition or not; if the health degree evaluation value meets a preset condition, performing a conventional reading operation on the first entity unit based on a preset reading voltage so as to respond to a data reading event; and if the health degree evaluation value does not meet a preset condition, under the condition that a conventional reading operation is not executed on the first entity unit, executing a rereading operation on the first entity unit based on at least one rereading voltage to respond to a data reading event, and the preset reading voltage is different from the rereading voltage. Therefore, the access efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and in particular, to a memory management method and a storage device. Background Art

[0002] A NAND flash memory is a non-volatile memory, which is widely used in electronic devices such as memory cards, solid state drives, and portable multimedia players. As a new type of storage medium, a solid state drive uses NAND Flash as a data storage medium, and has been widely used in various fields such as PCs, notebooks, and servers, and has gradually replaced mechanical hard disks to become the mainstream application product in the storage field.

[0003] However, with the increase in the data density of the flash memory medium, its data reliability decreases with each generation, and accordingly, a stronger error correction algorithm and more read voltage levels are required. In addition, multiple reads and the decoding iteration process will greatly lengthen the data reading time, thereby seriously affecting the read performance of the memory.

[0004] Most of the existing read retry schemes focus on finding the optimal read reference voltage of a data page to minimize the number of read retries, but this method will waste a large amount of flash memory bandwidth.

[0005] Therefore, how to effectively improve the access performance (especially the data reading performance) of a storage device under limited system resources is an urgent problem to be solved at present. Summary of the Invention

[0006] The present invention provides a memory management method and a storage device, which can solve the above problems and further improve the access performance of the storage device.

[0007] An embodiment of the present invention provides a memory management method for a storage device, where the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: evaluating the health of a first physical unit among the plurality of physical units to obtain a health evaluation value; in response to a data reading event for the first physical unit, determining whether the health evaluation value meets a preset condition; if the health evaluation value meets the preset condition, performing a normal reading operation on the first physical unit based on a preset reading voltage to respond to the data reading event; and if the health evaluation value does not meet the preset condition, performing a read retry operation on the first physical unit based on at least one read retry voltage without performing the normal reading operation on the first physical unit to respond to the data reading event, where the preset reading voltage is different from the at least one read retry voltage.

[0008] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is configured to: evaluate the health of a first physical unit among the plurality of physical units to obtain a health evaluation value; in response to a data reading event for the first physical unit, determine whether the health evaluation value meets a preset condition; if the health evaluation value meets the preset condition, perform a normal reading operation on the first physical unit based on a preset reading voltage to respond to the data reading event; and if the health evaluation value does not meet the preset condition, perform a rereading operation on the first physical unit based on at least one rereading voltage without performing the normal reading operation on the first physical unit to respond to the data reading event, where the preset reading voltage is different from the at least one rereading voltage.

[0009] Based on the above, evaluate the health of a first physical unit among the plurality of physical units to obtain a health evaluation value; after detecting a data reading event for the first physical unit, according to the health of the first physical unit, a normal reading operation based on a preset reading voltage or a rereading operation based on a rereading voltage can be dynamically performed on the first physical unit to respond to the data reading event. Thus, the access performance of the storage device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention;

[0011] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of a managed memory module shown according to an embodiment of the present invention;

[0013] Figure 4 is a schematic diagram of an operating scenario shown according to an embodiment of the present invention;

[0014] Figure 5 is a flowchart of a memory management method shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention. Please refer to Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCIExpress), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (such as exchanging signals, instructions, and / or data) via the connection interface 121.

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more arrays of memory cells. The memory cells in the memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 can send a sequence of instructions to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 can send a sequence of read instructions to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 can send a sequence of erase instructions to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 can receive the instruction sequence from the memory controller 123 and access the storage units inside the memory module 122 according to this instruction sequence.

[0021] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is the same as the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0025] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used for non-volatile data storage. For example, a physical unit may include one or more physical programming units.

[0026] In one embodiment, a physical programming unit may include a plurality of physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, both the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical requirements, which are not limited in the present invention. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0027] In one embodiment, a physical programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation or a programming operation) on a physical programming unit to write data into this physical programming unit, multiple memory cells in this physical programming unit can be synchronously programmed (i.e., programmed) to store the corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to this physical programming unit to change the threshold voltage of at least some of the memory cells in this physical programming unit. For example, the threshold voltage of a memory cell can reflect the bit data stored in this memory cell.

[0028] In one embodiment, an entity erasing unit may include a plurality of entity programming units. The plurality of entity programming units in an entity erasing unit may be erased synchronously. For example, when performing an erasing operation on an entity erasing unit, an erasing voltage may be applied to the plurality of entity programming units in this entity erasing unit to change the threshold voltages of at least some of the memory cells in these entity programming units. By performing an erasing operation on an entity erasing unit, the data stored in this entity erasing unit can be cleared. In one embodiment, an entity erasing unit may be regarded as an entity block.

[0029] In one embodiment, the memory control circuit 23 may logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any one of the entity units in the data area 31 may store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0030] In one embodiment, if a certain entity unit does not store valid data, this entity unit may be associated with the idle area 32. In addition, the entity units in the idle area 32 may be erased to clear the data in these entity units. In one embodiment, the entity units in the idle area 32 are also referred to as idle entity units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0031] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more entity units from the idle area 32 and instruct the memory module 122 to store the data in the selected entity units. After storing the data in this entity unit, this entity unit may be associated with the data area 31. In other words, one or more entity units may be alternately used between the data area 31 and the idle area 32.

[0032] In one embodiment, the memory control circuit 23 may configure a plurality of logic units 302(1) to 302(C) to map the entity units (i.e., entity units 301(1) to 301(A)) in the data area 31. For example, one logic unit may correspond to one logical block address (LBA) or other logical management units. One logic unit may be mapped to one or more entity units.

[0033] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in this physical unit includes valid data. Conversely, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that this physical unit does not currently store any valid data.

[0034] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as the logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may, according to the information in this management table (i.e., the logical-to-physical mapping table), instruct the memory module 122 to perform operations such as data reading, writing, or erasing.

[0035] In one embodiment, the memory control circuit 23 may evaluate the health of at least one physical unit (also referred to as the first physical unit) in the memory module 122 to obtain an evaluation value (also referred to as the health evaluation value). This health evaluation value may reflect the health of the first physical unit. For example, the health of the first physical unit may be positively correlated with the reliability (or quality) of the first physical unit. That is, if the health of the first physical unit is higher, it means that the reliability (or quality) of the first physical unit is higher.

[0036] In one embodiment, the memory control circuit 23 may monitor the usage status of the first physical unit to obtain a plurality of evaluation parameters (also referred to as status evaluation parameters) corresponding to the first physical unit. In particular, the plurality of status evaluation parameters may reflect the health of the first physical unit from different aspects. Then, the memory control circuit 23 may, according to the plurality of status evaluation parameters, obtain the aforementioned health evaluation value.

[0037] In one embodiment, the plurality of status evaluation parameters may reflect at least two of the bit error rate (also referred to as the bit error ratio), the degree of wear, the number of read retries, the threshold voltage distribution, the data retention time, and the temperature sensitivity of the first physical unit. For example, the plurality of status evaluation parameters may each include one or more parameter values. The memory control circuit 23 may dynamically update the parameter values to real-time reflect two of the bit error rate, the degree of wear, the number of read retries, the threshold voltage distribution, the data retention time, and the temperature sensitivity of the first physical unit.

[0038] In one embodiment, the memory control circuit 23 may, according to the bit error rate of the first physical unit, update one of the status evaluation parameters (also referred to as the first status evaluation parameter) among the plurality of status evaluation parameters. For example, the bit error rate of the first physical unit may be negatively correlated with the health of the first physical unit. That is, if the bit error rate of the first physical unit is higher, it means that the health of the first physical unit is lower.

[0039] In one embodiment, the memory control circuit 23 can evaluate the bit error rate of the first physical unit by monitoring the decoding result of the decoding circuit 25 for the data read from the first physical unit at least once. For example, by monitoring the decoding result of the decoding circuit 25 for the data read from the first physical unit at least once, the memory control circuit 23 can obtain how many bits in the data read from the first physical unit at least once are flipped or corrected (equivalent to how many error bits the read data contains). Then, the memory control circuit 23 can evaluate the bit error rate of the first physical unit according to the number of the flipped or corrected bits.

[0040] In one embodiment, the memory control circuit 23 can update another state evaluation parameter (also referred to as the second state evaluation parameter) among the multiple state evaluation parameters according to the degree of wear of the first physical unit. For example, the degree of wear of the first physical unit can be negatively correlated with the health of the first physical unit. That is, if the degree of wear of the first physical unit is higher, it means that the health of the first physical unit is lower.

[0041] In one embodiment, the memory control circuit 23 can evaluate the degree of wear of the first physical unit according to at least one of the programming count, the erase count, and the read count corresponding to the first physical unit. The programming count corresponding to the first physical unit can reflect how many times the first physical unit has been programmed. The erase count corresponding to the first physical unit can reflect how many times the first physical unit has been erased. The read count corresponding to the first physical unit can reflect how many times the first physical unit has been read. For example, the programming count, the erase count, and the read count corresponding to the first physical unit can be positively correlated with the degree of wear of the first physical unit. That is, if the programming count, the erase count, and / or the read count corresponding to the first physical unit is larger, it means that the degree of wear of the first physical unit is higher.

[0042] In one embodiment, the memory control circuit 23 can update another state evaluation parameter (also referred to as the third state evaluation parameter) among the multiple state evaluation parameters according to the number of read retries of the first physical unit. For example, the number of read retries of the first physical unit can be negatively correlated with the health of the first physical unit. That is, if the number of read retries of the first physical unit is more, it means the health of the first physical unit.

[0043] In one embodiment, the memory control circuit 23 can determine this number of read retries by counting how many times (on average) the first physical unit needs to be reread in at least one data read operation for the first physical unit. For example, assume that in at least one data read operation for the first physical unit, it is counted that (on average) the first physical unit needs to be reread 3 times to complete the data read operation for the first physical unit, then this number of read retries can be set to "3".

[0044] In one embodiment, the memory control circuit 23 may update another state evaluation parameter (also referred to as the fourth state evaluation parameter) among the multiple state evaluation parameters according to the threshold voltage distribution of the first physical unit. For example, the range of the threshold voltage distribution of the first physical unit (also referred to as the voltage coverage range) may be negatively correlated with the reliability (or quality) of the first physical unit. That is, if the range of the threshold voltage distribution of the first physical unit (i.e., the voltage coverage range) is wider, it indicates that the health of the first physical unit is lower.

[0045] In one embodiment, the memory control circuit 23 may determine (or lock) the operation mode of the first physical unit. For example, the operation mode of the first physical unit may include the SLC mode, the MLC mode, the TLC mode, the QLC mode, or other operation modes. In different operation modes, a single storage unit in the first physical unit can be used to store different numbers of bits. For example, in the SLC mode, a single storage unit in the first physical unit can be used to store 1 bit; in the MLC mode, a single storage unit in the first physical unit can be used to store 2 bits; in the TLC mode, a single storage unit in the first physical unit can be used to store 3 bits; in the QLC mode, a single storage unit in the first physical unit can be used to store 4 bits, and so on.

[0046] In one embodiment, after determining (or locking) the operation mode of the first physical unit, when the health of the first physical unit is relatively high, the range of the threshold voltage distribution of the first physical unit (i.e., the voltage coverage range) is narrower; however, when the health of the first physical unit is relatively low, the range of the threshold voltage distribution of the first physical unit (i.e., the voltage coverage range) will be wider (because at least some of the storage units have varying degrees of electron loss, resulting in a wider range of the threshold voltage distribution of the first physical unit). For example, assume that the current operation mode of the first physical unit is the TLC mode. Then, when operating in the TLC mode, the range of the threshold voltage distribution of the first physical unit (i.e., the voltage coverage range) may be negatively correlated with the health of the first physical unit.

[0047] In one embodiment, the memory control circuit 23 may update another state evaluation parameter (also referred to as the fifth state evaluation parameter) among the multiple state evaluation parameters according to the data retention time of the first physical unit. For example, the data retention time of the first physical unit may be negatively correlated with the health of the first physical unit. That is, if the data retention time of the first physical unit is longer, it indicates that the health of the first physical unit is lower. For example, if this data retention time is longer, it may indicate that the current charge loss degree of the first physical unit is higher, thereby reducing the health of the first physical unit.

[0048] In one embodiment, the memory control circuit 23 may monitor the continuous storage time of data in the first physical unit. During this continuous storage time, the data stored in the first physical unit is not updated (e.g., refreshed). Once the data stored in the first physical unit is updated (e.g., refreshed), this continuous storage time may be reset (e.g., set to zero). Then, the memory control circuit 23 may determine the data retention time of the first physical unit according to this continuous storage time. For example, this continuous storage time may be positively correlated with the data retention time of the first physical unit. That is, if this continuous storage time is longer, it means the data retention time of the first physical unit is longer.

[0049] In one embodiment, the memory control circuit 23 may update another state evaluation parameter (also referred to as the sixth state evaluation parameter) among the plurality of state evaluation parameters according to the temperature sensitivity of the first physical unit. For example, the temperature sensitivity of the first physical unit may be negatively correlated with the health of the first physical unit. That is, if the temperature sensitivity of the first physical unit is higher, it means the health of the first physical unit is lower. For example, if the temperature sensitivity of the first physical unit is higher, it means the charge storage state (i.e., voltage state) of each storage unit in the first physical unit is more easily affected by the current ambient temperature change, thereby reducing the health of the first physical unit.

[0050] In one embodiment, the memory control circuit 23 may monitor the voltage offset degree of at least one storage unit in the first physical unit when the temperature changes to evaluate the temperature sensitivity of the first physical unit. For example, this voltage offset degree may be positively correlated with the temperature sensitivity of the first physical unit. That is, if the voltage offset degree of at least one storage unit in the first physical unit is higher when the temperature changes, it means the temperature sensitivity of the first physical unit is higher.

[0051] In one embodiment, the memory control circuit 23 may detect a data read event for the first physical unit. In one embodiment, the data read event may be generated based on a host read operation initiated by the host system 11. This host read operation is used to read data from the first physical unit. For example, the host system 11 may transmit at least one read instruction to the storage device 12. The at least one read instruction may instruct the storage device 12 to perform the host read operation on the first physical unit.

[0052] In one embodiment, the data read event may also be generated based on an internal data consolidation operation (also referred to as a data merging operation) of the storage device 12. This data consolidation operation can be used to read data from a first physical unit. In addition, this data consolidation operation can also be used to store the data read from the first physical unit to another physical unit (also referred to as the second physical unit) in the memory module 122. For example, the data consolidation operation may include a garbage collection (GC) operation.

[0053] In one embodiment, in response to a data read event for a first physical unit, the memory control circuit 23 can determine in real time whether the health assessment value corresponding to the first physical unit meets a preset condition. If the health assessment value corresponding to the first physical unit meets the preset condition, the memory control circuit 23 can perform a normal read operation on the first physical unit based on a preset read voltage to respond to the data read event. For example, the preset read voltage refers to at least one preset read voltage corresponding to the first physical unit.

[0054] However, if the health assessment value corresponding to the first physical unit does not meet the preset condition, without performing the foregoing normal read operation on the first physical unit (i.e., skipping the foregoing normal read operation), the memory control circuit 23 can perform a retry read operation on the first physical unit directly based on at least one retry voltage to respond to the data read event. For example, the at least one retry voltage refers to at least one retry voltage corresponding to the first physical unit. In addition, the preset read voltage is different from the at least one retry voltage.

[0055] In one embodiment, during the normal read operation for the first physical unit, the memory control circuit 23 can send a read instruction sequence (also referred to as the first read instruction sequence) to the memory module 122. The first read instruction sequence can be used to instruct the memory module 122 to perform a data read operation on the first physical unit based on the preset read voltage to read data (also referred to as the first data) from the first physical unit. After obtaining the first data, the decoding circuit 25 can decode the first data to confirm whether there are error bits in the first data and can attempt to correct the error bits. If there are no error bits in the first data or the error bits in the first data have been corrected, the first data can be cached in the buffer memory 24 to respond to the data read event.

[0056] In an embodiment, if there are error bits in the first data and the error bits in the first data cannot be completely corrected, the memory control circuit 23 may initiate a reread operation for the first physical unit. After initiating the reread operation for the first physical unit, the memory control circuit 23 may query at least one management table (also referred to as a voltage management table) to obtain voltage setting information corresponding to the first physical unit. The memory control circuit 23 may determine at least one reread voltage for the reread operation according to this voltage setting information. Thereafter, in the reread operation for the first physical unit, the memory control circuit 23 may send a read instruction sequence (also referred to as a second read instruction sequence) to the memory module 122. The second read instruction sequence may be used to instruct the memory module 122 to perform the reread operation on the first physical unit based on one of the at least one reread voltage to read data (also referred to as second data) from the first physical unit. In particular, since the reread voltage used in the reread operation is different from the preset read voltage corresponding to the first physical unit, the data content of the second data may be different from the data content of the first data. In some cases, by using a reread voltage different from the preset read voltage to read data from the first physical unit, the number of error bits included in the data read from the first physical unit can be effectively reduced.

[0057] In an embodiment, after obtaining the second data, the decoding circuit 25 may decode the second data to confirm whether there are error bits in the second data and may attempt to correct the error bits. If there are no error bits in the second data or the error bits in the second data have been corrected, the second data may be cached in the buffer memory 24 to respond to the data read event. However, if there are error bits in the second data and the error bits in the second data still cannot be completely corrected, the memory control circuit 23 may continue to instruct the memory module 122 to perform the reread operation on the first physical unit based on another one of the at least one reread voltage to read data (also referred to as third data) from the first physical unit. Then, the third data may be decoded by the decoding circuit 25 and the reread operation for the first physical unit may be terminated according to the decoding result.

[0058] In an embodiment, generally, for example, when the health assessment value corresponding to the first physical unit meets the preset conditions, the memory control circuit 23 may perform a conventional read operation on the first physical unit based on the preset read voltage to respond to the data read event. Thus, when it is known or preliminarily determined that the health of the first physical unit is relatively high, the data reading of the first physical unit can be completed along the normal data reading path to maintain the current data reading speed of the first physical unit to be close to (or higher than) the average reading speed of the storage device 12.

[0059] However, in one embodiment, in special cases, for example, when the health assessment value corresponding to the first physical unit does not meet the preset conditions, the memory control circuit 23 may skip (i.e., not execute) the foregoing conventional read operation and directly perform a reread operation on the first physical unit based on the reread voltage in response to the data read event. Thus, when it is known or preliminarily determined that the health of the first physical unit is relatively low, by directly performing a reread operation on the first physical unit, the time originally spent on the conventional read operation with a high probability of failure can be reduced, thereby accelerating the completion of the data read performed on the first physical unit.

[0060] In one embodiment, the memory control circuit 23 may substitute at least two of the plurality of state evaluation parameters into the following formula (1) to obtain the health assessment value corresponding to the first physical unit.

[0061]

[0062] In formula (1), S represents the health assessment value corresponding to the first physical unit, P(i) represents the i-th state evaluation parameter among the plurality of state evaluation parameters, W(i) represents the weight coefficient corresponding to the i-th state evaluation parameter, and N represents the total number of the plurality of state evaluation parameters. In one embodiment, P(1) to P(6) may respectively include the foregoing first state evaluation parameter to the foregoing sixth state evaluation parameter, and N may be "6". In addition, the value of W(i) may be between 0 and 1, and the sum of W(1) to W(n) may be "1".

[0063] It should be noted that the value of S calculated according to formula (1) may be negatively correlated with the health of the first physical unit. That is, if the value of S calculated according to formula (1) is larger, it indicates that the health of the first physical unit is lower. However, in one embodiment, the health assessment value may also be positively correlated with the health of the first physical unit. In addition, formula (1) may also be adjusted according to practical needs, and the present invention is not limited thereto.

[0064] In one embodiment, the memory control circuit 23 may also perform normalization on the plurality of state evaluation parameters (such as P(1) to P(6) in formula (1)) respectively to map the plurality of state evaluation parameters to the target numerical range. For example, this target numerical range may be between 0 and 1.

[0065] In one embodiment, the memory control circuit 23 may normalize the first state evaluation parameter according to the maximum bit error rate corresponding to a single physical unit. For example, this maximum bit error rate may be dynamically set or adjusted according to the error correction capability of the decoding circuit 25. For example, this maximum bit error rate may be positively correlated with the error correction capability of the decoding circuit 25. In one embodiment, the memory control circuit 23 may divide the first state evaluation parameter by the maximum bit error rate to obtain an updated first state evaluation parameter. Thus, the value of the updated first state evaluation parameter may be mapped to a target numerical range (i.e., between 0 and 1).

[0066] In one embodiment, the memory control circuit 23 may normalize the second state evaluation parameter according to the maximum loss degree value corresponding to a single physical unit. For example, this maximum loss degree value may be positively correlated with the service life of a single physical unit. Once the usage degree of a single physical unit exceeds this maximum loss degree value, the memory control circuit 23 may determine this physical unit as a damaged physical unit (also referred to as a bad block) and / or temporarily not use this physical unit. In one embodiment, the memory control circuit 23 may divide the second state evaluation parameter by the maximum loss degree value to obtain an updated second state evaluation parameter. Thus, the value of the updated second state evaluation parameter may be mapped to a target numerical range (i.e., between 0 and 1).

[0067] In one embodiment, the memory control circuit 23 may normalize the third state evaluation parameter according to the maximum number of read retries corresponding to a single physical unit. For example, this maximum number of read retries may be set based on industry standard specifications used by the storage device 12 or adjusted according to practice. In one embodiment, the memory control circuit 23 may divide the third state evaluation parameter by the maximum number of read retries to obtain an updated third state evaluation parameter. Thus, the value of the updated third state evaluation parameter may be mapped to a target numerical range (i.e., between 0 and 1).

[0068] In one embodiment, the memory control circuit 23 may normalize the fourth state evaluation parameter according to the maximum threshold voltage distribution value corresponding to a single physical unit. For example, this maximum threshold voltage distribution value may be set according to industry standard specifications or adjusted according to practice. In one embodiment, the memory control circuit 23 may divide the fourth state evaluation parameter by the maximum threshold voltage distribution value to obtain an updated fourth state evaluation parameter. Thus, the value of the updated fourth state evaluation parameter may be mapped to a target numerical range (i.e., between 0 and 1).

[0069] In one embodiment, the memory control circuit 23 may normalize the fifth state evaluation parameter according to the maximum data retention time corresponding to a single physical unit. For example, this maximum data retention time may be set according to experimental results and may be dynamically adjusted. In one embodiment, the memory control circuit 23 may divide the fifth state evaluation parameter by the maximum data retention time to obtain an updated fifth state evaluation parameter. Thus, the value of the updated fifth state evaluation parameter may be mapped to a target numerical range (i.e., between 0 and 1).

[0070] In one embodiment, the memory control circuit 23 may normalize the sixth state evaluation parameter according to the maximum temperature sensitivity value corresponding to a single physical unit. For example, this maximum temperature sensitivity value may be set according to experimental results (e.g., set to the maximum operating temperature range of the storage device 12, such as 0 to 70 degrees) and may be dynamically adjusted. In one embodiment, the memory control circuit 23 may divide the sixth state evaluation parameter by the maximum temperature sensitivity value to obtain an updated sixth state evaluation parameter. Thus, the value of the updated sixth state evaluation parameter may be mapped to a target numerical range (i.e., between 0 and 1).

[0071] In one embodiment, the values of W(i) in formula (1) are all preset values. For example, i may be from 1 to 6. In one embodiment, the memory control circuit 23 may dynamically determine a parameter group (also referred to as a target parameter group) according to at least one of the operation mode of the first physical unit and the numerical range to which the multiple state evaluation parameters belong. Then, the memory control circuit 23 may set the value of W(i) in formula (1) according to this target parameter group.

[0072] In one embodiment, the memory control circuit 23 may select one candidate parameter group from multiple parameter groups (also referred to as candidate parameter groups) as the target parameter group according to at least one of the operation mode of the first physical unit and the numerical range to which the multiple state evaluation parameters belong. Then, the memory control circuit 23 may set the value of W(i) according to the parameters (such as 6 parameters) carried in this target parameter group. Alternatively, in one embodiment, the memory control circuit 23 may dynamically generate (e.g., calculate in real time) the value of W(i) according to at least one of the operation mode of the first physical unit and the numerical range to which the multiple state evaluation parameters belong.

[0073] In one embodiment, if the operation mode of the first physical unit is a certain operation mode (also referred to as the first operation mode), the memory control circuit 23 may determine a certain parameter group (also referred to as the first parameter group) among the multiple candidate parameter groups as the target parameter group. Alternatively, if the operation mode of the first physical unit is another operation mode (also referred to as the second operation mode), the memory control circuit 23 may determine another parameter group (also referred to as the second parameter group) among the multiple candidate parameter groups as the target parameter group. The first operation mode is different from the second operation mode.

[0074] In one embodiment, in the first operation mode, a storage unit in the first physical unit can be used to store p bits. In the second operation mode, a storage unit in the first physical unit can be used to store q bits. In particular, both p and q are integers greater than zero, and p is different from q. For example, assuming that the first operation mode is one of SLC mode, MLC mode, TLC mode, and QLC mode, the second operation mode can be another one of SLC mode, MLC mode, TLC mode, and QLC mode. In addition, the first operation mode and / or the second operation mode may also include other operation modes, which are not limited in the present invention.

[0075] In one embodiment, if the numerical range to which the multiple state evaluation parameters belong includes a certain numerical range (also referred to as the first numerical range), the memory control circuit 23 may determine a certain parameter group (such as the first parameter group) among the multiple candidate parameter groups as the target parameter group. Alternatively, if the numerical range to which the multiple state evaluation parameters belong includes another numerical range (also referred to as the second numerical range), the memory control circuit 23 may determine another parameter group (such as the second parameter group) among the multiple candidate parameter groups as the target parameter group. The first numerical range is different from the second numerical range.

[0076] Taking the first state evaluation parameter as an example, if the value of the first state evaluation parameter is within the first numerical range, the memory control circuit 23 may determine the first parameter group as the target parameter group. However, if the value of the first state evaluation parameter is within the second numerical range, the memory control circuit 23 may determine the second parameter group as the target parameter group. In one embodiment, the combination of the numerical ranges of at least two state evaluation parameters can also be used to determine or adjust the target parameter group, which will not be elaborated one by one here.

[0077] In one embodiment, after obtaining the health evaluation value corresponding to the first physical unit, the memory control circuit 23 may compare the health evaluation value with a threshold value to obtain a comparison result. For example, this comparison result can show the relative numerical relationship between the health evaluation value and the threshold value. For example, this relative numerical relationship can be that the health evaluation value is greater than, less than, or equal to the threshold value.

[0078] In one embodiment, the memory control circuit 23 may determine whether the health assessment value meets a preset condition according to the comparison result. For example, if the comparison result is a certain result (also referred to as the first result), the memory control circuit 23 may determine that the health assessment value meets the preset condition. However, if the comparison result is another result (also referred to as the second result), the memory control circuit 23 may determine that the health assessment value does not meet the preset condition.

[0079] In one embodiment, assuming that the health assessment value is positively correlated with the health of the first physical unit as an example, the first result may be that the health assessment value is greater than the threshold value, and the second result may be that the health assessment value is not greater than (or less than) the threshold value. Alternatively, in one embodiment, assuming that the health assessment value is negatively correlated with the health of the first physical unit as an example, the first result may be that the health assessment value is not greater than (e.g., less than) the threshold value, and the second result may be that the health assessment value is greater than the threshold value.

[0080] Figure 4 is a schematic diagram of an operating scenario shown according to an embodiment of the present invention. Please refer to Figure 4 , assuming that the memory control circuit 23 obtains the state evaluation parameters 401 to 406 by monitoring the usage status of the first physical unit. The state evaluation parameters 401 to 406 respectively reflect the bit error rate (also referred to as the bit error rate), the loss degree, the read retry times, the threshold voltage distribution, the data retention time, and the temperature sensitivity of the first physical unit. For example, the state evaluation parameters 401 to 406 may be P(1) to P(6) in formula (1) respectively.

[0081] After obtaining the state evaluation parameters 401 to 406, the memory control circuit 23 may input the state evaluation parameters 401 to 406 (i.e., P(1) to P(6) in formula (1)) to the arithmetic unit 41 for arithmetic operations. For example, the arithmetic unit 41 may perform an arithmetic operation identical or similar to formula (1). The memory control circuit 23 may obtain the health assessment value 42 according to the arithmetic result of the arithmetic unit 41. For example, S (i.e., the health assessment value 42) determined according to formula (1) may be negatively correlated with the health of the first physical unit.

[0082] After obtaining the health assessment value 42, the memory control circuit 23 can compare the health assessment value 42 with the threshold value 43. If the comparison result is that the health assessment value 42 is not greater than (e.g., less than) the threshold value 43, the memory control circuit 23 can determine that the health assessment value 42 meets the preset conditions. Then, according to this comparison result, the memory control circuit 23 can subsequently instruct the memory module 122 to perform a normal read operation on the first physical unit using a preset read voltage corresponding to the first physical unit to respond to a data read event for the first physical unit. Thus, when it is known or preliminarily determined that the health of the first physical unit is relatively high, an attempt can be made to maintain the current data read speed for the first physical unit to be close to (or higher than) the average read speed of the storage device 12.

[0083] On the other hand, if the comparison result is that the health assessment value 42 is greater than the threshold value 43, the memory control circuit 23 can determine that the health assessment value 42 does not meet the preset conditions. Then, according to this comparison result, without performing a normal read operation on the first physical unit (i.e., skipping the aforementioned normal read operation), the memory control circuit 23 can directly instruct the memory module 122 to perform a reread operation on the first physical unit using at least one reread voltage to respond to the data read event. Thus, when it is known or preliminarily determined that the health of the first physical unit is relatively low, by directly performing a reread operation on the first physical unit, the time originally spent on normal read operations with a high probability of failure can be reduced, thereby accelerating the completion of the data read for the first physical unit.

[0084] In one embodiment, assume that the normalized P(1) to P(6) are 0.8, 0.83, 0.6, 0.5, 0.5, and 0.29 respectively, W(1) to W(6) are 0.4, 0.2, 0.15, 0.1, 0.1, and 0.05 respectively, and the threshold value is 0.5. After substituting P(1) to P(6) and W(1) to W(6) into formula (1), S can be calculated as 0.6905. Since S (i.e., 0.6905) is greater than the threshold value (i.e., 0.5), the memory control circuit 23 can determine that the health assessment value corresponding to the first physical unit (i.e., S) does not meet the preset conditions and directly trigger a reread operation for the first physical unit. However, in one embodiment, if the threshold value is 0.7, since S (i.e., 0.6905) is not greater than the threshold value (i.e., 0.7), the memory control circuit 23 can determine that the health assessment value corresponding to the first physical unit (i.e., S) meets the preset conditions and does not directly trigger a reread operation for the first physical unit (i.e., first perform a normal read operation on the first physical unit).

[0085] In one embodiment, the memory control circuit 23 can also dynamically adjust the threshold value according to historical misjudgment information (e.g., Figure 4The threshold value in (43). This historical misjudgment information can reflect the misjudgment situation of determining whether to skip the regular read operation according to whether the health assessment value meets the preset conditions in the past period. For example, assume that in a certain read operation for the first physical unit (and / or the remaining physical units in the memory module 122), if (1) it is determined that a regular read operation needs to be performed, but subsequent reread operations are still required to complete data reading and decoding, or (2) it is determined that the regular read operation can be skipped, but in fact, fast data reading and decoding can be completed in the regular read operation, then a count value (also known as the misjudgment count) in the historical misjudgment information can be updated (for example, incremented by 1). Then, the memory control circuit 23 can dynamically adjust the threshold value according to this count value.

[0086] In one embodiment, the memory control circuit 23 can adjust the threshold value according to the following formula (2).

[0087]

[0088] In formula (2), THR is the current threshold value, THR’ is the adjusted threshold value, MS is the misjudgment rate, and K and SI are constants. For example, MS (i.e., the misjudgment rate) can be obtained according to the aforementioned misjudgment count. For example, MS (i.e., the misjudgment rate) can be positively correlated with the aforementioned misjudgment count. It should be noted that formula (2) can also be adjusted according to practical requirements, and the present invention does not limit it. Thus, during the operation of the storage device 12, the threshold value can be dynamically corrected, making subsequent decisions more accurate, thereby further improving the access efficiency of the storage device 12.

[0089] Figure 5 is a flowchart of a memory management method according to an embodiment of the present invention. Please refer to Figure 5 , in step S501, the health of the first physical unit in the memory module is evaluated to obtain a health assessment value. In step S502, a data read event for the first physical unit is detected. In step S503, in response to the data read event, it is determined whether the health assessment value meets the preset conditions. If the health assessment value meets the preset conditions, in step S504, a regular read operation is performed on the first physical unit based on a preset read voltage to respond to the data read event. However, if the health assessment value does not meet the preset conditions, in step S505, without performing a regular read operation on the first physical unit, a reread operation is performed on the first physical unit based on at least one reread voltage to respond to the data read event. In particular, the preset read voltage is different from the at least one reread voltage.

[0090] However, Figure 5 The steps in have been described in detail above and will not be repeated here. It should be noted that,Figure 5 Each step in Figure 5 can be implemented as multiple pieces of code or circuits, and the present invention does not impose any restrictions. In addition, Figure 5 The method of Figure 5 can be used in combination with the above exemplary embodiments or used alone, and the present invention does not impose any restrictions.

[0091] In summary, the memory management method and storage device proposed in the embodiments of the present invention can dynamically determine the optimal read strategy for the first physical unit at present according to the health status of the first physical unit evaluated in real time, whether to perform a conventional read operation on the first physical unit or skip the conventional read operation and directly trigger a reread operation on the first physical unit. Thereby, the access efficiency of the storage device can be effectively improved.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: Evaluating the health of a first physical unit among the plurality of physical units to obtain a health evaluation value; In response to a data read event for the first physical unit, determining whether the health evaluation value meets a preset condition; If the health evaluation value meets the preset condition, performing a normal read operation on the first physical unit based on a preset read voltage to respond to the data read event; and If the health evaluation value does not meet the preset condition, performing a reread operation on the first physical unit based on at least one reread voltage without performing the normal read operation on the first physical unit to respond to the data read event, wherein the preset read voltage is different from the at least one reread voltage.

2. The memory management method according to claim 1, wherein the step of evaluating the health of the first physical unit among the plurality of physical units to obtain the health evaluation value includes: Monitoring the usage status of the first physical unit to obtain a plurality of status evaluation parameters corresponding to the first physical unit, wherein the plurality of status evaluation parameters reflect the health of the first physical unit based on different aspects; And Obtaining the health evaluation value according to the plurality of status evaluation parameters.

3. The memory management method according to claim 2, wherein the plurality of status evaluation parameters reflect at least two of the bit error rate, wear level, read retry count, threshold voltage distribution, data retention time, and temperature sensitivity of the first physical unit.

4. The memory management method according to claim 2, wherein the step of obtaining the health evaluation value according to the plurality of status evaluation parameters includes: Substituting at least two of the plurality of status evaluation parameters into the following formula to obtain the health evaluation value, where S represents the health evaluation value, P(i) represents the i-th status evaluation parameter among the plurality of status evaluation parameters, W(i) represents the weight coefficient corresponding to the i-th status evaluation parameter, and N represents the total number of the plurality of status evaluation parameters.

5. The memory management method according to claim 4, further includes: Performing normalization on the plurality of status evaluation parameters respectively to map the plurality of status evaluation parameters to a target numerical range, wherein the target numerical range is between 0 and 1.

6. The memory management method according to claim 4, further includes: Dynamically determining a target parameter group according to at least one of the operation mode of the first physical unit and the numerical range to which the plurality of status evaluation parameters belong; And Setting the value of W(i) according to the target parameter group.

7. The memory management method according to claim 6, wherein the step of dynamically determining the target parameter group according to at least one of the operation mode of the first physical unit and the numerical range to which the plurality of status evaluation parameters belong includes: If the operation mode of the first entity unit is the first operation mode, determine the first parameter group among the multiple candidate parameter groups as the target parameter group; And If the operation mode of the first entity unit is the second operation mode, determine the second parameter group among the multiple candidate parameter groups as the target parameter group, wherein in the first operation mode, one storage unit in the first entity unit is used to store p bits, and in the second operation mode, one storage unit in the first entity unit is used to store q bits, both p and q are integers greater than zero, and p is different from q.

8. The memory management method according to claim 6, wherein the step of dynamically determining the target parameter group according to at least one of the operation mode of the first entity unit and the numerical range to which the multiple state evaluation parameters belong includes: If the numerical range to which the multiple state evaluation parameters belong includes a first numerical range, determine the first parameter group among the multiple candidate parameter groups as the target parameter group; And If the numerical range to which the multiple state evaluation parameters belong includes a second numerical range, determine the second parameter group among the multiple candidate parameter groups as the target parameter group, wherein the first numerical range is different from the second numerical range.

9. The memory management method according to claim 1, wherein the step of determining whether the health evaluation value meets the preset condition includes: Compare the health evaluation value with a threshold value to obtain a comparison result; If the comparison result is the first result, determine that the health evaluation value meets the preset condition; And If the comparison result is the second result, determine that the health evaluation value does not meet the preset condition.

10. The memory management method according to claim 9 further includes: Dynamically adjust the threshold value according to historical misjudgment information, wherein the historical misjudgment information reflects the misjudgment situation of determining whether to skip the regular read operation according to whether the health evaluation value meets the preset condition in the past period of time.

11. A storage device, characterized in that, Comprising: A connection interface for connecting to a host system; A memory module; And A memory controller connected to the connection interface and the memory module, wherein the memory module includes multiple entity units, and the memory controller is configured to: Evaluate the health of the first entity unit among the multiple entity units to obtain a health evaluation value; In response to a data read event for the first entity unit, determine whether the health evaluation value meets a preset condition; If the health evaluation value meets the preset condition, perform a regular read operation on the first entity unit based on a preset read voltage to respond to the data read event; And If the health evaluation value does not meet the preset condition, perform a reread operation on the first entity unit based on at least one reread voltage without performing the regular read operation on the first entity unit to respond to the data read event, wherein the preset read voltage is different from the at least one reread voltage.

12. The storage device according to claim 11, wherein the operation of the memory controller for evaluating the health of the first physical unit among the plurality of physical units to obtain the health evaluation value includes: Monitoring the usage condition of the first physical unit to obtain a plurality of status evaluation parameters corresponding to the first physical unit, wherein the plurality of status evaluation parameters reflect the health of the first physical unit based on different aspects; And Obtaining the health evaluation value according to the plurality of status evaluation parameters.

13. The storage device according to claim 12, wherein at least two of the plurality of status evaluation parameters reflect the bit error rate, wear level, read retry count, threshold voltage distribution, data retention time, and temperature sensitivity of the first physical unit.

14. The storage device according to claim 12, wherein the operation of the memory controller for obtaining the health evaluation value according to the plurality of status evaluation parameters includes: Substituting at least two of the plurality of status evaluation parameters into the following formula to obtain the health evaluation value, where S represents the health evaluation value, P(i) represents the i-th status evaluation parameter among the plurality of status evaluation parameters, W(i) represents the weight coefficient corresponding to the i-th status evaluation parameter, and N represents the total number of the plurality of status evaluation parameters.

15. The storage device according to claim 14, the memory controller is further configured to: Perform normalization on the plurality of status evaluation parameters respectively to map the plurality of status evaluation parameters to a target numerical range, wherein the target numerical range is between 0 and 1.

16. The storage device according to claim 14, wherein the memory controller is further configured to: Dynamically determine a target parameter group according to at least one of the operation mode of the first physical unit and the numerical range to which the plurality of status evaluation parameters belong; and Set the value of W(i) according to the target parameter group.

17. The storage device according to claim 16, wherein the operation of the memory controller for dynamically determining the target parameter group according to at least one of the operation mode of the first physical unit and the numerical range to which the plurality of status evaluation parameters belong includes: If the operation mode of the first physical unit is the first operation mode, determining the first parameter group among the plurality of candidate parameter groups as the target parameter group; And If the operation mode of the first physical unit is the second operation mode, determining the second parameter group among the plurality of candidate parameter groups as the target parameter group, wherein in the first operation mode, one storage unit in the first physical unit is used to store p bits, and in the second operation mode, one storage unit in the first physical unit is used to store q bits, both p and q are integers greater than zero, and p is different from q.

18. The storage device according to claim 16, wherein the operation of dynamically determining the target parameter group by the memory controller according to at least one of the operation mode of the first physical unit and the numerical range to which the plurality of state evaluation parameters belong includes: If the numerical range to which the plurality of state evaluation parameters belong includes a first numerical range, determining a first parameter group among the plurality of candidate parameter groups as the target parameter group; And If the numerical range to which the plurality of state evaluation parameters belong includes a second numerical range, determining a second parameter group among the plurality of candidate parameter groups as the target parameter group, wherein the first numerical range is different from the second numerical range.

19. The storage device according to claim 11, wherein the operation of the memory controller for determining whether the health evaluation value meets the preset condition includes: Comparing the health evaluation value with a threshold value to obtain a comparison result; If the comparison result is a first result, determining that the health evaluation value meets the preset condition; And If the comparison result is a second result, determining that the health evaluation value does not meet the preset condition.

20. The storage device according to claim 19, wherein the memory controller is further configured to: Dynamically adjust the threshold value according to historical misjudgment information, Wherein the historical misjudgment information reflects the misjudgment situation of determining whether to skip the regular read operation according to whether the health evaluation value meets the preset condition in the past period of time.

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