Block data enable signal phase adjustment method and device
By traced the FIFO and adjusting the relative phase of data and gap, the problems of RAM resource occupation and delay increase caused by FIFO insertion are solved, and RAM resource saving and delay reduction are achieved, and block data enable signal phase adjustment is suitable for digital communication field.
Patent Information
- Application Number
- CN202510333845.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-07-04
AI Technical Summary
The prior art insertion of FIFOs in digital circuit design results in an increase in RAM resource usage and an increase in data delay, especially in the problem of increased workload on FPGA development platforms without read-pre-FIFOs.
By tracing the nearest FIFO, we judge whether to add FIFOs upstream of the extended enable position, and use the upstream processing link to insert gaps, adjust the relative phases of data and gaps, avoid additional read-ahead FIFOs, and control the reading of FIFOs to save RAM resources and reduce delays.
Effectively save RAM resources, reduce data latency, and avoid additional code adaptation work during cross-platform migration, improving the versatility of the design.
Smart Images
Figure CN120255843A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of digital communication technologies, and particularly to a method and apparatus for adjusting the phase of a block data enable signal. Background Art
[0002] In digital circuit design, when data is transferred between modules or flows through processing procedures, an enable signal is usually required to mark its validity. When the enable signal is valid, the corresponding data is valid. In some data processing procedures, the enable signal used to mark the data validity needs to be extended, such as converting large-bitwidth data to small-bitwidth data, or adding FEC (Forward Error Correction) to a section of data.
[0003] These operations usually need to be completed in cooperation with a FIFO (First In First Out). By pausing the FIFO reading at the place where the enable signal needs to be extended, space for inserting the extended enable signal is obtained. However, such a design scheme increases the RAM (Random Access Memory) resource occupation because a level of FIFO needs to be inserted at the place where the enable signal is extended, and the data delay also increases accordingly, which is not friendly to application scenarios with tight RAM resources and sensitive to delay.
[0004] In addition, in order to be able to pause the FIFO output in real time, the FIFO used here is usually a pre-read FIFO. However, some domestic FPGA development platforms do not provide a pre-read FIFO IP core (Intellectual Property Core). Using a non-pre-read FIFO may require some additional adaptation work, and when transplanting the code containing the pre-read FIFO IP core to these FPGA development platforms, it will also bring additional work.
[0005] Therefore, it is desirable to introduce a method and apparatus to solve the problems of increased RAM resource occupation caused by inserting a FIFO in the prior art, or increased workload on development platforms without a pre-read FIFO. Summary of the Invention
[0006] To solve the problems in the above scenarios, the present invention provides a method and apparatus for adjusting the phase of a block data enable signal. Based on its characteristic of regularizing fixed-length block data, it adopts a way of coordinating before and after to make the best use of the existing FIFO as much as possible to save RAM or avoid inserting a pre-read FIFO.
[0007] To achieve the above object, the present application proposes a method for adjusting the phase of a block data enable signal, including the following steps:
[0008] Step 1: Obtain the extension enable position;
[0009] Step 2: Trace back upstream to the nearest traceability FIFO according to the extended enabling position; wherein, the processing link between the extended enabling position and the nearest FIFO is the traceability path.
[0010] Step 3: Determine whether to add a FIFO nearby upstream of the extended enabling position according to the FIFO traceability situation.
[0011] Step 4: Obtain the occupied clock cycle number of the original block data and the enabling extended clock cycle number.
[0012] Step 5: Perform read control on the traceability FIFO or the added FIFO; wherein, after every occupied clock cycle number of the original block data is read, pause for the enabling extended clock cycle number of clock cycles.
[0013] Step 6: Generate a block data mark as appropriate, and pass the generated block data mark or the existing block data mark on the traceability path downstream to the gap phase adjustment module.
[0014] Step 7: Generate a gap phase adjustment control signal according to the block data mark and the block data enabling.
[0015] Step 8: Adjust the relative phase of the data and the gap according to the gap phase adjustment control signal.
[0016] As a further solution, in Step 2, if tracing back upstream to a FIFO, then judge:
[0017] Whether the enabling signal of the current FIFO output data changes in phase when reaching the extended enabling position;
[0018] Whether adjusting the original phase of the current FIFO output data affects downstream processing;
[0019] If there is no phase change, only a fixed delay exists and it does not affect downstream processing, then use the current FIFO as the traceability FIFO.
[0020] As a further solution, in Step 2, if no traceability FIFO can be traced back, or there is a relative phase change between data enabling and non-enabling on the traceability path, then add a FIFO nearby upstream of the extended enabling position.
[0021] As a further solution, in Step 6, if there is no block data mark on the traceability path, then generate a block data mark upstream of the extended enabling position, and pass the generated block data mark or the existing block data mark on the traceability path downstream to the gap phase adjustment module.
[0022] As a further solution, in step 6, the block data is marked by the marker signal for the first clock cycle of the block data marking.
[0023] As a further solution, in step 7, the src_clk_cnt counter and the gap_cnt counter are controlled to count according to the marker signal;
[0024] When the marker signal is valid, the src_clk_cnt counter is set to 2 and incremented by 1 when the block data enable is valid;
[0025] When the marker signal is valid, the gap_cnt counter is set to 0 and incremented by 1 when the block data enable is invalid;
[0026] Among them, the src_clk_cnt counter is for the block data enable count, and the gap_cnt counter is for the gap count.
[0027] As a further solution, when the gap_cnt counter is equal to the enabled extended clock cycle number, the growth of the gap_cnt counter is stopped.
[0028] As a further solution, in step 7, the gap insertion control signal is generated through the following steps:
[0029] When the block data enable signal is valid and the src_clk_cnt counter is equal to the occupied clock cycle number of the original block data, a gap insertion control sub-signal is generated;
[0030] If the enabled extended clock cycle number is greater than 1, multiple gap insertion control sub-signals are generated; among them, the current gap insertion control sub-signal is generated by delaying the previous gap insertion control sub-signal by 1 beat, and the total number of gap insertion control sub-signals is equal to the extended clock cycle number;
[0031] The gap insertion control signal is obtained by performing an OR operation on each gap insertion control sub-signal.
[0032] As a further solution, in step 8, the relative phase of the data and the gap is adjusted through the following specific steps:
[0033] When the gap_cnt counter is equal to 0, the data output delayed by the enabled extended clock cycle number of beats is taken;
[0034] When the gap_cnt counter is equal to 1, the data output delayed by the enabled extended clock cycle number - 1 beat is taken;
[0035] When the gap_cnt counter is greater than 1, as the gap_cnt counter increases, and when the gap_cnt counter is less than the number of enabled extended clock cycles, the data output taken is the data output of the number of beats of the delayed enabled extended clock cycles - the gap_cnt counter, and the smaller the gap_cnt counter, the higher the priority. After the gap_cnt counter is greater than or equal to the number of enabled extended clock cycles, the data output without delay is always taken.
[0036] When the gap insertion control signal is 1, no data is output and the operation priority is the highest.
[0037] On the other hand, the present invention provides a device for adjusting the relative position of gaps based on fixed-length block data, which employs a method for adjusting the phase of the block data enable signal as described in any one of the above. The device for adjusting the relative position of gaps includes:
[0038] A FIFO for caching block data;
[0039] A FIFO read control module for ensuring that there are gaps in the FIFO output data;
[0040] A block data marker generation module that generates block data markers as appropriate;
[0041] A gap phase adjustment module that adjusts the relative phase of the data and the gap according to the block data marker.
[0042] Compared with the related art, a method and a device for adjusting the phase of the block data enable signal provided by the present invention have the following advantages:
[0043] The present invention adjusts the relative phase of the data and the gap based on the block data marker, which facilitates the direct extension of the enable for the downstream module that needs to perform enable extension according to the block data, and as much as possible avoids the increase in RAM resource occupation and the increase in delay caused by adding a FIFO. Even if it is impossible to avoid adding a FIFO, it can also avoid the inconvenience brought by using a pre-read FIFO on some domestic FPGA development platforms. Description of the Drawings
[0044] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments that conform to the present application, and are used together with the specification to explain the principles of the present application.
[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0046] Figure 1Schematic diagram of the steps of a method for adjusting the phase of a block data enable signal provided by the present invention;
[0047] Figure 2 Schematic diagram of data enable expansion provided by the present invention;
[0048] Figure 3 Schematic diagram of a scenario without adding a FIFO provided by the present invention;
[0049] Figure 4 Schematic diagram of a scenario where a FIFO needs to be added provided by the present invention;
[0050] Figure 5 Schematic diagram of adjusting the timing relationship between data and gaps provided by the present invention;
[0051] Figure 6 Schematic diagram of a device for adjusting the relative position of gaps based on fixed-length block data provided by the present invention.
[0052] The implementation, functional features, and advantages of the present application will be further described in conjunction with embodiments and with reference to the accompanying drawings. Detailed implementation manners
[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.
[0054] To better understand the effects required in actual applications and the role played by this solution, the specific implementation of this solution will start from the following real scenario.
[0055] In digital circuit design, there are often situations where block data needs to be processed. Its typical feature is that in some processing links, the size of each input block data is the same, and after processing, the size of each output block data is also the same. If the size of the input block data is different from that of the output block data, it often manifests as the expansion of the data enable signal (when the data bit width remains unchanged).
[0056] For example, in the field of communication, RS-FEC (a type of FEC proposed by Reed and Solomon in 1960) is a commonly used FEC. Its information length is k bits, the check bit length is r bits, and n is the codeword length. The relationship among the three is n = k + r. In a given application scenario, both k and r have definite values. Corresponding to digital circuit design, the data processing bit width of the module is determined. Therefore, k determines the enable width of the input data, and n determines the enable width of the output data, thereby also determining the width of the extended enable.
[0057] Taking RS(255, 239) as an example, its k is 239 bits and n is 255 bits. Assuming the data processing bit width is 16 bits, then the enable width of a block of data before FEC encoding is 15 clock cycles (239 / 16 = 14.9375, rounded up), and the enable width after FEC encoding is 16 clock cycles (255 / 16 = 15.9375, rounded up). Therefore, when performing FEC encoding, it is necessary to extend the enable by 16 - 15 = 1 clock cycle. Figure 2 This is the schematic diagram of the extended enable signal of the corresponding enable signal.
[0058] Since there may be no gap between two adjacent blocks of data input to the FEC encoding module (i.e., the enable signals of two adjacent blocks of data are connected together), it is impossible to insert this 1-clock-cycle extended enable. In this case, it is often necessary to add a level of FIFO here to insert a gap by controlling the reading of adjacent block data. The added FIFO is usually a pre-read FIFO because it can conveniently pause reading immediately when reaching the end of the block data, thereby directly inserting the gap between adjacent blocks of data.
[0059] The present invention contemplates using the FIFO in the upstream processing link to insert a gap, which can avoid adding a FIFO. However, the upstream processing link may not have clearly defined the boundaries of the block data, so the inserted gap may not be located between adjacent blocks of data. The solution of the present invention is to adjust the position of the gap and "move" it between adjacent blocks of data, so that there is no need to add an additional FIFO to insert the gap. Through this cooperation between the upstream and downstream, RAM resources are saved.
[0060] Please refer to Figure 1 , based on the above invention concept, the embodiment of the present application provides a method for adjusting the phase of the enable signal of block data, including the following steps:
[0061] Step 1: Obtain the extended enable position;
[0062] Step 2: Trace back to the nearest traceable FIFO upstream according to the extended enable position; wherein, the processing link between the extended enable position and the nearest FIFO is the traceable path.
[0063] Step 3: Determine whether to add a FIFO nearby upstream of the extended enable position according to the FIFO traceability situation;
[0064] Step 4: Obtain the number of occupied clock cycles of the original block data and the number of enabled extended clock cycles;
[0065] Step 5: Perform read control on the traced FIFO or the added FIFO; wherein, after every number of clock cycles equal to the number of occupied clock cycles of the original block data are read, pause for a number of clock cycles equal to the number of enabled extended clock cycles;
[0066] Step 6: Generate a block data mark as appropriate, and pass the generated block data mark or the existing block data mark on the traceability path downstream to the gap phase adjustment module;
[0067] Step 7: Generate a gap phase adjustment control signal according to the block data mark and the block data enable;
[0068] Step 8: Adjust the relative phase of the data and the gap according to the gap phase adjustment control signal.
[0069] It should be noted that: in the scenario as Figure 3 shown, module x needs extended enable when processing data, and there happens to be a suitable FIFO available upstream. And if there is no suitable FIFO available upstream, then only one level of FIFO can be added. However, even so, the added FIFO is not required to be a pre-read FIFO. Since the present invention will "move" the gap, the output delay of the FIFO will not affect the inserted block data gap, so that possible code modifications caused by cross-platform code transplantation can be avoided. This scenario is as Figure 4 shown, module x needs extended enable when processing data, but no suitable FIFO can be traced, so a level of FIFO needs to be inserted in front of this module.
[0070] First, clarify the position of the module ([module x in Figure 3 , or it can also be a processing link) that needs the extended enable signal in the data processing flow, and trace upstream from this position to the nearest FIFO. This FIFO may be located in other modules or may be at the same level as module x ( Figure 3 i.e., the case of being at the same level). If not, insert one level of FIFO nearby in front of this module (as Figure 4 , the FIFO read delay can be arbitrary);
[0071] If tracing back to the FIFO, it is necessary to determine whether the enable signal for outputting data from the FIFO changes when it reaches the module for the extended enable signal. If there is no phase change, only a fixed delay exists, and adjusting the original phase of the FIFO output data does not affect downstream processing (step 5 will regulate the FIFO data output), then the method described in the present invention can be used to save one - level FIFO. Otherwise, as in the first step, insert one - level FIFO near the front of this module. Additionally, there is another possibility, that is, the traced - back FIFO happens to be exactly before module x, and there are no other modules in between (such as width conversion or cross - clock domain). In this case, it can be regarded as adding FIFO for processing.
[0072] Clarify the size of the block data and the number of clock cycles of the extended enable signal. The number of clock cycles occupied by the original block data is denoted as src_clk_num, the number of clock cycles required for the extended enable signal is denoted as exp_clk_num, and the number of clock cycles occupied by the block data after the extended enable signal is denoted as all_clk_num. It can be known that all_clk_num = src_clk_num + exp_clk_num. In a specific design, both src_clk_num and exp_clk_num are determined values. Taking Figure 5 as an example, its src_clk_num is 6 and exp_clk_num is 1;
[0073] Control the reading of data from the traced - back FIFO or the inserted FIFO. Pause for exp_clk_num clock cycles after every src_clk_num clock cycles of data reading, so as to reserve space for the extended clock enable for "shifting", which can ensure that downstream can definitely "shift" exp_clk_num gaps to the tail of each block of data without damaging the data. Figure 5 In [reference], the high - level of the valid signal is the src_clk_num clock cycles of data reading, while the low - level of the valid signal is the gap of exp_clk_num clock cycles.
[0074] It should be noted that Figure 5 This is only a schematic diagram. In reality, there may be a situation where the src_clk_num clock cycles are not continuously high - level because the FIFO is empty, and more gaps will appear accordingly, but this does not affect the present invention. Here, it should be noted that regardless of whether FIFO is added or not, it must be ensured that there is a block data marker signal before adjusting the gap position. If not, it must be generated at a certain upstream link and transmitted downstream along with the data enable signal to the place where the gap position is adjusted. The marker signal is denoted as marker, which is the marker for the first clock cycle of the block data.
[0075] The counters src_clk_cnt and gap_cnt are counted according to the marker, where the former is the block data enable count and the latter is the gap count.
[0076] When the marker is valid, src_clk_cnt is set to 2 and incremented by 1 when the block data enable is valid;
[0077] In addition, when the marker is valid, gap_cnt is set to 0 and incremented by 1 when the block data enable is invalid.
[0078] As Figure 5 shown, valid and marker affect the counting changes of the two counters. Since the scenario of FIFO empty is not shown in the figure, the low level of valid is only caused by the FIFO read pause. In the actual scenario, the FIFO may be empty, resulting in more low levels of valid, which causes gap_cnt to be larger. To avoid meaningless counting, in the actual design, once gap_cnt is equal to exp_clk_num, it will no longer increase;
[0079] Generate the gap insertion control signal. When the block data enable valid is effective and src_clk_cnt is equal to src_clk_num, generate the gap insertion control signal gap_ins_en_0. If exp_clk_num is greater than 1, multiple gap insertion control signals need to be generated. gap_ins_en_0 is delayed by one beat to get gap_ins_en_1, gap_ins_en_1 is delayed by one beat to get gap_ins_en_2, and so on. A total of exp_clk_num gap insertion control signals need to be obtained through delay, and finally they are ORed to get gap_ins_en. As Figure 5 shown, since exp_clk_num is 1, gap_ins_en_0 is gap_ins_en;
[0080] Adjust the relative phase of the data and the gap,
[0081] When gap_cnt is equal to 0, take the delayed data output,
[0082] If exp_clk_num is 1, take the data delayed by one beat,
[0083] If exp_clk_num is 2, take the data delayed by two beats,
[0084] All in all, take the data output delayed by exp_clk_num beats;
[0085] When gap_cnt equals 1, the data output is taken with a delay of exp_clk_num - 1 beats (if exp_clk_num is 1, the original input data without delay is output).
[0086] When gap_cnt is greater than 1, as gap_cnt increases, and when gap_cnt < exp_clk_num, the data output is taken with a delay of exp_clk_num - gap_cnt beats (the data taken changes with the increase of gap_cnt), and the smaller gap_cnt is, the higher the priority. After gap_cnt >= exp_clk_num, the data output without delay is always taken;
[0087] In addition, when gap_ins_en is 1, no data is output, that is, exp_clk_num gaps are inserted. This operation has the highest priority, higher than all the foregoing assignment operations. Corresponding to Figure 5 in, when gap_ins_en is 1, the low level of the newly generated data enable signal new_valid is the position of the adjusted gap; and the marker signal is the first data of the block data. When gap_cnt is 0, the marker output with a delay of exp_clk_num beats is used to obtain new_marker ( Figure 5 the exp_clk_num in is 1), which is delayed by 2 clock cycles relative to the input marker. In addition, the relationship between the input original block data data, the input block data data_1dly with a delay of one beat, and the data new_data after the gap adjustment can also be seen in the figure. For the input data data, its gray part is the original gap, and its valid signal is invalid here. The data in the subsequent 4 clock cycles is passed to new_data. For data_1dly, its gray part is also the original gap, and the data in the 2 clock cycles before it is passed to new_data. It can be seen that there are at least exp_clk_num gaps after each new block data.
[0088] After the above operation process, the adjustment of the relative phase between the block data and the gaps is completed, ensuring that there are at least exp_clk_num gaps after each block of data, thus facilitating the direct expansion enabling of downstream modules. In the above embodiment, if there is no need to insert a FIFO, RAM resources can be saved and the delay can be reduced. If a FIFO needs to be inserted, since the inserted FIFO does not have to be a pre-read FIFO, it may not be necessary to perform FIFO adaptation during cross-platform code transplantation, and the versatility is better. Additionally, regarding the reduction of delay, taking the end of the block data as a reference, it can be seen from the embodiment that when gap_cnt >= exp_clk_num, the data output without delay is taken, so the output data is at most one clock cycle delayed relative to the input data (using the register output method). However, if a first-level FIFO is inserted, the data delay introduced by links such as the increase of the write address inside the FIFO, the determination of the FIFO not being empty, and the output delay of the RAM is necessarily greater than one clock cycle. Additionally, it should be further noted that the low level of valid that causes gap_cnt to increase may be due to the FIFO being empty rather than a deliberate FIFO read pause. Therefore, the actually "moved" gaps are not the gaps reserved by pausing exp_clk_num clock cycles after reading src_clk_num clock cycles of data from the FIFO, but this does not affect the desired relative phase adjustment result.
[0089] As Figure 6 shown, the present invention also proposes a device for adjusting the relative position of gaps based on fixed-length block data. The device includes a FIFO, a FIFO read control module, a block data marker generation module, and a gap phase adjustment module.
[0090] The FIFO is used to cache data, and its output delay is not restricted by anything.
[0091] The FIFO read control module completes part of the operations in step 5 of the above embodiment, that is, it pauses for exp_clk_num clock cycles after reading src_clk_num clock cycles of data.
[0092] In actual design, the block data marker generation module may not need to be added specifically because if the downstream processes data in block format, generating block data markers is natural. Even the FIFO of this device may have already output block data markers. If not, this module needs to be added, and this operation is also in step 6 of the above embodiment.
[0093] The gap phase adjustment module completes the operations in steps 7 and 8 of the above embodiment.
[0094] For the FIFO read control module, the block data flag generation module, and the gap phase adjustment module, their positions are not necessarily adjacent, and they may not exist in the form of modules. This device is only a schematic description. Additionally, this device is not limited to adjusting only the rated number of gaps after the block data. By modifying the block data flag generation module, pseudo-flags can be generated, and the gap phase adjustment module can "move" the gaps to any desired position according to the pseudo-flags.
[0095] The above are only some embodiments of this application, and do not limit the patent scope of this application. Any equivalent structural transformation made under the technical concept of this application by using the content of the specification and drawings of this application, or any direct / indirect application in other related technical fields, is included in the patent protection scope of this application.
Claims
1. A method for adjusting the phase of a block data enable signal, characterized in that, It includes the following steps: Step 1: Obtain the extension enable position; Step 2: Trace back to the nearest traceability FIFO upstream according to the extension enable position; wherein, the processing link between the extension enable position and the nearest FIFO is the traceability path; Step 3: Judge whether to add a FIFO nearby upstream of the extension enable position according to the FIFO traceability situation; Step 4: Obtain the occupied clock cycle number of the original block data and the enabled extension clock cycle number; Step 5: Perform read control on the traceability FIFO or the added FIFO; wherein, after every occupied clock cycle number of clock cycles of reading the original block data, pause for the enabled extension clock cycle number of clock cycles; Step 6: Generate a block data mark as appropriate, and pass the generated block data mark or the existing block data mark on the traceability path downstream to the gap phase adjustment module; Step 7: Generate a gap phase adjustment control signal according to the block data mark and the block data enable; Step 8: Adjust the relative phase of the data and the gap according to the gap phase adjustment control signal.
2. The method for adjusting the phase of the block data enabling signal according to claim 1, wherein In Step 2, if a FIFO is traced back upstream, then judge: Whether the enable signal of the current FIFO output data changes in phase when it reaches the extension enable position; Whether adjusting the original phase of the current FIFO output data affects downstream processing; If there is no phase change, only a fixed delay exists and it does not affect downstream processing, then use the current FIFO as the traceability FIFO.
3. A method for adjusting the phase of a block data enable signal according to claim 2, characterized in that, In Step 2, if no traceability FIFO can be traced back, or there is a relative phase change between data enable and non-enable on the traceability path, then add a FIFO nearby upstream of the extension enable position.
4. A method for adjusting the phase of a block data enable signal according to claim 1, characterized in that, In Step 6, if there is no block data mark on the traceability path, then generate a block data mark upstream of the extension enable position, and pass the generated block data mark or the existing block data mark on the traceability path downstream to the gap phase adjustment module.
5. A method for adjusting the phase of a block data enabling signal according to claim 1, characterized in that In Step 6, the block data is marked by the marker signal marker, which is used to mark the first clock cycle of the block data.
6. A method for adjusting the phase of a block data enable signal according to claim 5, characterized in that, In Step 7, control the counting of the src_clk_cnt counter and the gap_cnt counter according to the marker signal marker; When the marker signal marker is valid, set the src_clk_cnt counter to 2 and increment it by 1 when the block data enable is valid; When the marker signal marker is valid, set the gap_cnt counter to 0 and increment it by 1 when the block data enable is invalid; Among them, the src_clk_cnt counter is the block data enable count, and the gap_cnt counter is the gap count.
7. A method for adjusting the phase of a block data enable signal according to claim 6, characterized in that, When the gap_cnt counter is equal to the enabled extension clock cycle number, stop the growth of the gap_cnt counter.
8. A method for adjusting the phase of a block data enable signal according to claim 6, characterized in that In Step 7, generate a gap insertion control signal through the following steps: When the block data enable signal is valid and the src_clk_cnt counter is equal to the occupied clock cycle number of the original block data, generate a gap insertion control sub-signal; If the enabled extended clock cycle number is greater than 1, multiple gap insertion control sub-signals are generated; among them, the current gap insertion control sub-signal is generated by delaying the previous gap insertion control sub-signal by 1 beat, and the total number of gap insertion control sub-signals is equal to the extended clock cycle number; The OR operation is performed on each gap insertion control sub-signal to obtain the gap insertion control signal.
9. A method for adjusting the phase of a block data enable signal according to claim 8, characterized in that, In step 8, the relative phase of the data and the gap is adjusted through the following specific steps: When the gap_cnt counter is equal to 0, the data output delayed by the enabled extended clock cycle number of beats is taken; When the gap_cnt counter is equal to 1, the data output delayed by the enabled extended clock cycle number - 1 beat is taken; When the gap_cnt counter is greater than 1, as the gap_cnt counter increases, and when the gap_cnt counter is less than the enabled extended clock cycle number, the data output delayed by the enabled extended clock cycle number - the gap_cnt counter beats is taken, and the smaller the gap_cnt counter, the higher the priority. After the gap_cnt counter is greater than or equal to the enabled extended clock cycle number, the data output without delay is always taken. When the gap insertion control signal is 1, no data is output and the operation priority is the highest.
10. A gap relative position adjusting device based on fixed-length block data, which applies a block data enabling signal phase adjustment method according to any one of claims 1 to 9, characterized in that, The gap relative position adjustment device includes: A FIFO for caching block data; A FIFO read control module for ensuring that there are gaps in the FIFO output data; A block data marker generation module for generating block data markers as appropriate; A gap phase adjustment module for adjusting the relative phase of the data and the gap according to the block data marker.