Digital intercept error optimization circuit and communication equipment

Abstract

The invention provides a digital intercept error optimization circuit and a communication device wherein the digital intercept error optimization circuit comprises: a first adder, a first input end of which is connected with a signal input end; the input end of the bit intercepting circuit is connected with the output end of the first summator, the output end of the bit intercepting circuit is connected with the signal output end, and the bit intercepting circuit is used for performing bit intercepting processing on the signal output by the first summator to obtain a bit intercepting signal; the first input end of the intercept error processing circuit is connected with the output end of the intercept circuit, the second input end of the intercept error processing circuit is connected with the output end of the frequency factor generation circuit, and the third input end of the intercept error processing circuit is connected with the output end of the first adder; and the output end of the intercept error processing circuit is connected with the second input end of the first adder. According to the invention, the effect of improving the in-band signal-to-noise ratio of the signal is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and more particularly, to an optimization circuit for digital truncation error and a communication device. Background Art

[0002] In a digital signal processing circuit, fixed-point processing needs to be performed on the signal bit width. During multiplication and addition operations, the bit width of the calculation result often expands. For example, when an N-bit unsigned number is multiplied by an M-bit unsigned number, the calculation result is N + M bits. If no processing is performed on this result, the bit width of the subsequent link will continue to expand, resulting in an extremely high cost for link implementation. To reduce the link implementation cost, the N + M-bit calculation result is usually truncated to ensure that the resource overhead of the subsequent link is controllable. However, truncating the calculation result is actually equivalent to a process of re-quantization in the digital domain. This process discards the precision of the input data and introduces truncation error. In related technologies, the circuit for optimizing truncation error often brings a large power consumption overhead, reducing its signal-to-noise ratio.

[0003] It can be seen that there is a problem of low signal-to-noise ratio in the circuit for optimizing truncation error in related technologies.

[0004] In view of the above problems existing in related technologies, no effective solution has been proposed yet. Summary of the Invention

[0005] The embodiments of the present invention provide an optimization circuit for digital truncation error and a communication device, so as to at least solve the problem of low signal-to-noise ratio in the circuit for optimizing truncation error in related technologies.

[0006] According to an embodiment of the present invention, an optimization circuit for digital truncation error is provided, including: a first adder, the first input end of the first adder is connected to a signal input end; a truncation circuit, the input end of the truncation circuit is connected to the output end of the first adder, and the output end of the truncation circuit is connected to a signal output end. The truncation circuit is configured to perform truncation processing on the signal output by the first adder to obtain a truncated signal and output the truncated signal to the signal output end; a frequency factor generation circuit, configured to generate a frequency modulation factor based on the carrier frequency point information of the input signal sent by the signal input end; a truncation error processing circuit, the first input end of the truncation error processing circuit is connected to the output end of the truncation circuit, the second input end of the truncation error processing circuit is connected to the output end of the frequency factor generation circuit, the third input end of the truncation error processing circuit is connected to the output end of the first adder, and the output end of the truncation error processing circuit is connected to the second input end of the first adder. The truncation error processing circuit is configured to generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder, and the truncated signal, and send the error adjustment signal to the first adder.

[0007] In an exemplary embodiment, the truncation circuit includes a low-bit truncation circuit.

[0008] In an exemplary embodiment, the truncation error processing circuit includes: a padding circuit, the input end of the padding circuit is connected to the output end of the truncation circuit, and is configured to perform a padding operation on the truncated signal to obtain a padded signal, wherein the bit width of the padded signal is the same as the bit width of the input signal; a second adder, the first input end of the second adder is connected to the output end of the padding circuit, and the second input end of the second adder is connected to the output end of the first adder, and is configured to subtract the signal output by the first adder from the padded signal to obtain an error signal; a first multiplier, the first input end of the first multiplier is connected to the output end of the second adder, the second input end of the first multiplier is connected to the output end of the frequency factor generation circuit, and the output end of the first multiplier is connected to the second input end of the first adder, and is configured to multiply the error signal by the frequency modulation factor to obtain a product signal and input the product signal into the first adder.

[0009] In an exemplary embodiment, the truncation error processing circuit further includes: a first delay circuit, the output end of the second adder is connected to the first multiplier through the first delay circuit.

[0010] In an exemplary embodiment, the optimization circuit for digital truncation error further includes: a judgment circuit, the input end of the judgment circuit is connected to the signal input end, and is configured to receive the input signal and judge whether two adjacent signals in the time domain included in the input signal are the same. In the case of being the same, the truncation error processing circuit is controlled to be turned off, and in the case of being different, the truncation error processing circuit is controlled to be enabled.

[0011] In an exemplary embodiment, the judgment circuit includes: a second delay circuit, the input end of the second delay circuit is connected to the signal input end and is configured to delay the input signal; a judgment sub-circuit, the first input end of the judgment sub-circuit is connected to the signal input end, and the second input end of the judgment sub-circuit is connected to the output end of the second delay circuit, and is configured to judge whether the signal sent by the signal input end is the same as the signal output by the output end of the second delay circuit.

[0012] In an exemplary embodiment, the frequency factor generation circuit generates a frequency modulation factor based on the carrier frequency point information of the input signal sent by the signal input end in the following manner: determining the ratio of the carrier frequency point information to the sampling frequency for sampling the input signal; determining the frequency modulation factor based on the ratio.

[0013] In an exemplary embodiment, the frequency factor generation circuit determines the frequency modulation factor based on the ratio in the following manner: determining the first product of the ratio and the imaginary unit; determining the exponential function with the natural constant as the base and the first product as the exponent as the frequency modulation factor.

[0014] In an exemplary embodiment, the z-transform truncation error optimization transfer function of the optimization circuit for digital truncation error is as follows: ; where X(z) represents the input signal, E(z) represents the truncation error, and Y(z) represents the output signal of the optimization circuit for digital truncation error.

[0015] According to another embodiment of the present invention, an optimization method for digital truncation error is provided, which is applied to the optimization circuit for digital truncation error in any of the above embodiments, and includes: receiving a first signal sent by the signal input end; generating the frequency modulation factor based on the carrier frequency point information of the first signal; performing truncation processing on the first signal to obtain the truncated signal; generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and a second signal, where the second signal is a signal sent by the signal input end after sending the first signal; adjusting a third signal based on the error adjustment signal, where the third signal is a signal sent by the signal input end after sending the second signal, and the input signal includes the first signal, the second signal, and the third signal.

[0016] In an exemplary embodiment, generating the frequency modulation factor based on the carrier frequency point information of the first signal includes: determining the ratio of the carrier frequency point information to the sampling frequency for sampling the input signal; determining the frequency modulation factor based on the ratio.

[0017] In an exemplary embodiment, determining the frequency modulation factor based on the ratio includes: determining a first product of the ratio and the imaginary unit; determining the exponential function with the natural constant as the base and the first product as the exponent as the frequency modulation factor.

[0018] In an exemplary embodiment, generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal includes: padding the truncated signal to obtain a padded signal, where the bit width of the padded signal is the same as the bit width of the input signal; determining the difference between the second signal and the padded signal; determining a second product of the difference and the frequency modulation factor after delaying for a first predetermined time; determining the second product as the error adjustment signal.

[0019] In an exemplary embodiment, adjusting the third signal based on the error adjustment signal includes: performing a summation operation on the third signal and the error adjustment signal to adjust the third signal.

[0020] In an exemplary embodiment, before generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal, the method further includes: obtaining a fourth signal, where the fourth signal is a signal sent by the signal input end before sending the first signal, and the input signal includes the fourth signal; generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal when the first signal is different from the fourth signal.

[0021] According to another embodiment of the present invention, a cascaded digital signal processing circuit is provided, including: a plurality of digital signal processing circuits, a frequency point information configuration circuit, and a plurality of optimization circuits for digital truncation errors as described in any of the above embodiments; the frequency point information configuration circuit is respectively connected to the frequency factor generation circuits of the plurality of optimization circuits for digital truncation errors, and is used to provide carrier frequency point information to the frequency factor generation circuits; the output end of each digital signal processing circuit is connected to an optimization circuit for digital truncation errors, obtaining a plurality of connection circuits, and the optimization circuits for digital truncation errors connected by different digital signal processing circuits are different; the plurality of connection circuits are serially connected to form a multi-stage digital signal processing circuit.

[0022] According to another embodiment of the present invention, a radio frequency transmitting device is further provided, including a first baseband module, a digital-to-analog conversion module, and a cascaded digital signal processing circuit as described in the above embodiment, and the output end of the first baseband module is connected to the input end of the digital-to-analog conversion module through the cascaded digital signal processing circuit.

[0023] According to another embodiment of the present invention, a radio frequency receiving device is further provided, including a second baseband module, an analog-to-digital conversion module, and a cascaded digital signal processing circuit as described in the above embodiment, and the output end of the analog-to-digital conversion module is connected to the input end of the second baseband module through the cascaded digital signal processing circuit.

[0024] According to another embodiment of the present invention, a radio frequency digital-to-analog converter is further provided, including: a filtering circuit, the filtering circuit includes a sampling rate converter and an optimization circuit for digital truncation errors as described in any of the above embodiments, and the output end of the sampling rate converter is connected to the signal input end of the optimization circuit for digital truncation errors; a digital frequency shift circuit, the digital frequency shift circuit includes a second multiplier, a digital control oscillator, and the optimization circuit for digital truncation errors, the first input end of the second multiplier is connected to the output end of the filtering circuit, the second input end of the second multiplier is connected to the digital control oscillator, and the output end of the second multiplier is connected to the input end of the optimization circuit for digital truncation errors; a digital-to-analog converter, the input end of the digital-to-analog converter is connected to the output end of the digital frequency shift circuit; a frequency controller, the frequency controller is connected to the frequency factor generation circuits of each optimization circuit for digital truncation errors, and is used to provide carrier frequency point information to the frequency factor generation circuits.

[0025] In an exemplary embodiment, there are multiple filtering circuits and multiple digital frequency shift circuits. The multiple digital frequency shift circuits are arranged at intervals. The input end of each digital frequency shift circuit is connected to the output end of one of the filtering circuits, and the output end of the digital frequency shift circuit is connected to the input end of other filtering circuits.

[0026] According to another embodiment of the present invention, there is also provided a communication device, which includes the optimization circuit for digital truncation error as described in any one of the above embodiments, or includes the cascaded digital signal processing circuit as described in the above embodiments, or includes the radio frequency transmitting device as described in the above embodiments, or includes the radio frequency receiving device as described in the above embodiments, or includes the radio frequency digital-to-analog converter as described in any one of the above embodiments.

[0027] In an exemplary embodiment, the communication device includes one of the following: a base station set in a satellite, a base station set on the ground, and a terminal device.

[0028] In an exemplary embodiment, the terminal device includes: a mobile phone, a vehicle, and a ship.

[0029] Through the present invention, since the frequency factor generation circuit can generate a frequency modulation factor according to the carrier frequency point information of the input signal, the truncation error processing circuit can generate an error adjustment signal according to the frequency modulation factor, the signal output by the first adder, and the truncation signal, the first adder can add the error adjustment signal to the input signal, input the added signal into the truncation circuit, and the truncation circuit can perform truncation processing on the added signal and output it, realizing the adjustment of the error shaping frequency domain response curve according to the actual frequency point where the carrier is located, thereby improving the signal-to-noise ratio within the signal band. Therefore, the problem of low signal-to-noise ratio of the optimization truncation error circuit in the related art can be solved, and the effect of improving the signal-to-noise ratio within the signal band can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a structural diagram of the optimization circuit for digital truncation error according to an embodiment of the present invention;

[0031] Figure 2 is a specific structural diagram of the optimization circuit for digital truncation error according to an embodiment of the present invention;

[0032] Figure 3 is an optimization effect diagram of the total integrated energy of the truncation error noise within different bandwidths deviating from the signal center frequency point according to an embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of the application effect in a single-stage module according to an embodiment of the present invention;

[0034] Figure 5It is a structural block diagram of a cascaded digital signal processing circuit according to an embodiment of the present invention;

[0035] Figure 6 It is a structural block diagram of a radio frequency transmitting device according to an embodiment of the present invention;

[0036] Figure 7 It is a specific structural schematic diagram of a radio frequency transmitting device according to an embodiment of the present invention;

[0037] Figure 8 It is a structural block diagram of a radio frequency receiving device according to an embodiment of the present invention;

[0038] Figure 9 It is a specific structural schematic diagram of a radio frequency receiving device according to an embodiment of the present invention;

[0039] Figure 10 It is a structural block diagram of a radio frequency digital-to-analog converter according to an embodiment of the present invention;

[0040] Figure 11 It is a specific structural schematic diagram of a radio frequency digital-to-analog converter according to an embodiment of the present invention;

[0041] Figure 12 It is a schematic diagram of the input test signal spectrum input to the radio frequency digital-to-analog converter according to an embodiment of the present invention;

[0042] Figure 13 It is a schematic diagram of the digital signal spectrum at the DAC input according to an embodiment of the present invention. Detailed implementation manners

[0043] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in conjunction with the embodiments.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0045] In this embodiment, an optimization circuit for digital truncation error is provided. Figure 1 It is a structural diagram of the optimization circuit for digital truncation error according to an embodiment of the present invention, as Figure 1 shown. The optimization circuit for digital truncation error includes:

[0046] A first adder 12, the first input end of the first adder is connected to the signal input end;

[0047] Truncation circuit 14, the input end of the truncation circuit is connected to the output end of the first adder, the output end of the truncation circuit is connected to the signal output end, and the truncation circuit is used to perform truncation processing on the signal output by the first adder to obtain a truncated signal and output the truncated signal to the signal output end;

[0048] Frequency factor generation circuit 16, which is used to generate a frequency modulation factor based on the carrier frequency point information of the input signal sent by the signal input end;

[0049] Truncation error processing circuit 18, the first input end of the truncation error processing circuit is connected to the output end of the truncation circuit, the second input end of the truncation error processing circuit is connected to the output end of the frequency factor generation circuit, the third input end of the truncation error processing circuit is connected to the output end of the first adder, and the output end of the truncation error processing circuit is connected to the second input end of the first adder. The truncation error processing circuit is used to generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder, and the truncated signal, and send the error adjustment signal to the first adder.

[0050] In the above embodiment, the truncation error may be an error generated by truncating the bit width of the signal in the digital signal processing circuit. Usually, the low bit data bits of the data are irrelevant to the envelope information and are random. The truncation error can be approximately equivalent to Gaussian noise and exhibits a uniform distribution characteristic in the frequency domain. The formula for calculating the truncation error power can be expressed as:

[0051] Pn = 10*log10((1 / 2^(b - 1)) / 12) (1)

[0052] Where b is the data bit width after truncation, with the unit of dBfs. If considering calculating the truncation error power spectral density, the formula is:

[0053] Pn_Hz = 10*log10((1 / 2^(b - 1)) / 12) - 10*log10(fs) (2)

[0054] Where fs is the digital sampling rate, and the unit of the error power spectral density is dBfs / Hz. It can be found from Equation (2) that when the sampling rate is high and there is a large oversampling ratio relative to the signal, since the truncation error is uniformly distributed in the entire sampling frequency band, the impact on the signal-to-noise ratio (SNR) of the effective signal becomes lower.

[0055] In the above embodiments, the first adder may be a digital logic circuit for performing addition operations on two or more signals. The first input terminal of the first adder may be connected to the signal input terminal. The signal input terminal inputs an input signal to the first adder. The input signal may be a discrete digital signal in the time domain. It may also be a high-bit-width signal processed by a previous digital module. The bit width of the high-bit-width signal may be truncated by a truncation circuit to ensure that the resource overhead of the subsequent link is controllable.

[0056] In the above embodiments, the truncation circuit may be a circuit that realizes truncation by rounding the signal, or may also be a circuit that realizes direct truncation of the signal. When the truncation circuit is a direct truncation circuit, the truncation circuit may truncate the bit width of the received signal according to a fixed length, where the fixed length may be a pre-configured length.

[0057] In the above embodiments, the frequency factor generation circuit may generate a frequency modulation factor according to the carrier frequency point information of the input signal sent by the signal input terminal. The carrier frequency point information may be pre-configured in the frequency factor generation circuit. The frequency modulation factor may be expressed as exp(jω c / ω s ), where ω c is the carrier frequency point information of the input signal, that is, the carrier frequency point information configured by the user, and ω s is the signal sampling rate at this node position. Among them, the frequency factor generation circuit may be implemented by digital signal processing (DSP / FPGA) to output the frequency modulation factor exp(jω c / ω s ).

[0058] In the above embodiments, the truncation error processing circuit may fill in the truncated signal, subtract the filled signal from the high-precision signal before truncation to obtain an error signal, and process and back-fill the error signal to the input signal. Through the optimization circuit of the digital truncation error, the truncation error energy within the effective bandwidth of the signal can be reduced, and the frequency domain response of the circuit can be adjusted according to the frequency point where the signal is located, thereby improving the signal-to-noise ratio within the signal band. This circuit also has an automatic protection function for special scenarios to ensure that no performance degradation occurs.

[0059] In the above embodiment, in digital signal processing, truncation operation is a common data compression method, but it will introduce errors. The error is adjusted by the frequency modulation factor, which effectively reduces the truncation error and improves the accuracy of signal processing. For example, in a radio frequency communication system, the carrier frequency point information is a key parameter. The frequency modulation factor generated by using this information can accurately compensate for the frequency response changes caused by truncation and ensure the integrity of the signal. In addition, this technical solution is not only applicable to radio frequency communication, but also to any system that requires digital signal processing, including but not limited to audio processing, image processing, etc.

[0060] Through the present invention, since the frequency factor generating circuit can generate a frequency modulation factor according to the carrier frequency point information of the input signal, the truncation error processing circuit can generate an error adjustment signal according to the frequency modulation factor, the signal output by the first adder and the truncation signal, the first adder can add the error adjustment signal to the input signal, and input the added signal to the truncation circuit, and the truncation circuit can perform truncation processing on the added signal and output it, it is realized that the error shaping frequency domain response curve is adjusted according to the actual frequency point of the carrier, thereby improving the signal-to-noise ratio in the signal band. Therefore, the problem of low signal-to-noise ratio of the optimized truncation error circuit existing in the related art can be solved, and the effect of improving the signal-to-noise ratio in the signal band can be achieved.

[0061] In an exemplary embodiment, the truncation circuit includes a low-bit truncation circuit. In this embodiment, the low-bit truncation circuit can truncate the signal output by the first adder from the low bit, truncate N bits, and obtain a truncation signal, wherein N can be a natural number such as 1, 2, 3, 5, etc., and N can be specifically designed according to the application scenario. The present invention does not limit the specific value of N.

[0062] In an exemplary embodiment, the truncation error processing circuit includes: a padding circuit, the input end of the padding circuit is connected to the output end of the truncation circuit, and is used to perform a padding operation on the truncation signal to obtain a padding signal, wherein the bit width of the padding signal is the same as the bit width of the input signal; a second adder, the first input end of the second adder is connected to the output end of the padding circuit, the second input end of the second adder is connected to the output end of the first adder, and is used to subtract the signal output by the first adder from the padding signal to obtain an error signal; a first multiplier, the first input end of the first multiplier is connected to the output end of the second adder, the second input end of the first multiplier is connected to the output end of the frequency factor generation circuit, the output end of the first multiplier is connected to the second input end of the first adder, and is used to multiply the error signal with the frequency modulation factor to obtain a product signal, and input the product signal into the first adder. In this embodiment, the specific structure diagram of the digital truncation error optimization circuit can be found in the attachedFigure 2 , as Figure 2 shown, the optimization circuit for digital truncation error includes a first adder 12, a truncation circuit (i.e., Figure 2 the truncation Nbit in Figure 2 ) 14, a frequency factor generation circuit (i.e., Figure 2 the frequency factor generation in

[0063] ) 16, and a truncation error processing circuit 18. Among them, the truncation error processing circuit 18 may include a padding circuit (i.e.,

[0064] the low-bit padding 0 Nbit in Figure 2 ) 1802, a second adder 1804, and a first multiplier 1806. The padding circuit may be a low-bit zero-padding circuit, which can perform low-bit zero-padding on the truncated signal to obtain a padded signal. The second adder can subtract the padded signal from the input signal to obtain an error signal, multiply the error signal by the frequency modulation factor to obtain a product signal, and input the product signal into the first adder. Among them, the error signal can be directly multiplied by the frequency modulation factor, or can be multiplied by the frequency modulation factor after being delayed.

[0065] In the above embodiments, the introduction of the delay circuit is to ensure the temporal alignment of the error signal and the frequency modulation factor, and to avoid inaccurate error compensation caused by asynchronous signal processing timings. For example, in high-speed digital signal processing, the timing of the signal has a significant impact on the processing result. The first delay circuit can ensure the precise temporal matching of the error adjustment signal and the original signal, thereby improving the accuracy of error compensation. The use of this technical feature solves the problem of timing synchronization in signal processing and is applicable not only to radio frequency communication but also to any digital signal processing system that requires precise timing control, including but not limited to real-time audio processing, video coding, etc.

[0066] In an exemplary embodiment, the optimization circuit for digital truncation error further includes: a judgment circuit, the input end of the judgment circuit is connected to the signal input end, and is configured to receive the input signal and judge whether two temporally adjacent signals included in the input signal are the same. In the case of being the same, the truncation error processing circuit is controlled to be turned off, and in the case of being different, the truncation error processing circuit is controlled to be enabled. In this embodiment, continue to refer to the appendix Figure 2 , the optimization circuit for digital truncation error further includes a judgment circuit ( Figure 2 input signal judgment in 1810), configured to judge whether two input signals are the same. When they are the same, the truncation error processing circuit is controlled to be turned off, and when they are different, the truncation error processing circuit is controlled to be enabled. The judgment circuit is used to judge whether the input signals of two adjacent samples in the time domain are exactly the same. If they are the same, the function of the truncation error processing circuit needs to be turned off; this is because when the input signal exhibits the characteristics of DC input, the truncation error distribution does not conform to the random characteristics of white noise, and this truncation optimization circuit may generate periodic temporal errors, resulting in spurs in the output signal. Therefore, a judgment module needs to be added as a monitoring protection.

[0067] In the above embodiments, the introduction of the judgment circuit is to intelligently control error processing, avoid unnecessary error compensation when the signal change is not significant, thereby saving power resources and improving the energy efficiency of the device. The use of this technical feature solves the problem of energy waste in traditional signal processing and is applicable not only to radio frequency communication but also to any digital signal processing device that requires energy-saving optimization, including but not limited to mobile phones, portable audio players, etc.

[0068] In an exemplary embodiment, the determination circuit includes: a second delay circuit, the input end of the second delay circuit is connected to the signal input end, and is used for delaying the input signal; a determination sub-circuit, the first input end of the determination sub-circuit is connected to the signal input end, and the second input end of the determination sub-circuit is connected to the output end of the second delay circuit, and is used for determining whether the signal sent by the signal input end is the same as the signal output by the output end of the second delay circuit. In this embodiment, continue to refer to the appendix Figure 2 The determination circuit 1810 may further include a second delay circuit 1812. The second delay circuit may delay the input signal so that the determination circuit can determine whether two adjacent signals in the time domain are the same.

[0069] In the above embodiment, through delay and comparison, the determination circuit can accurately identify the change of the signal, and intelligently control the switch of the truncation error processing circuit, so as to save power resources when the signal change is not significant.

[0070] In the above embodiment, the truncation error optimization transfer function (Z-transform expression) of the digital truncation error optimization circuit may be: , where X(z) is the input signal, E(z) is the truncation error, and Y(z) is the output signal. ω c represents the carrier center frequency point normalized to the range of -π to π. Taking the general case where the carrier is at the baseband 0 frequency, that is, ω c =0 for analysis; when |1 - z -1 | < 1, the corresponding frequency band range is -π / 3 to π / 3; that is, within the range of -π / 3 to π / 3 deviating from the carrier center, the optimized truncation error power spectral density is less than the normal truncation. Considering the full frequency band range of -π to π, that is, from the perspective of the full frequency band, this truncation optimization method does not bring a reduction in the total power of the truncation error, but optimizes the truncation error spectral density in a specific frequency band to achieve a shaping effect. The optimization effect diagram of the total integrated energy of the truncation error noise in different bandwidths deviating from the signal center frequency point can be seen in the appendix Figure 3 , as Figure 3 shown, the integration bandwidth is normalized to 0 to π, and it can be inferred that in the oversampling scenario (the sampling rate is much larger than the carrier bandwidth scenario), the digital truncation error optimization circuit has particularly obvious benefits.

[0071] In the above embodiment, the digital truncation error optimization circuit can be applied in a single-stage module. The schematic diagram of the application effect in the single-stage module can be seen in the appendix Figure 4 , as Figure 4As shown, two sine waves with a 10M separation are input, with the center frequency point at 25M and a sampling rate of 245.76M; the first curve is the 16-bit input signal; the second curve is the output signal directly truncated to 12 bits using nearest; the third curve is the output signal truncated to 12 bits using the optimized circuit for digital truncation error. It can be observed that the background noise within and near the effective signal band is significantly reduced.

[0072] In an exemplary embodiment, the frequency factor generation circuit generates a frequency modulation factor based on the carrier frequency point information of the input signal sent from the signal input end in the following manner: determining the ratio of the carrier frequency point information to the sampling frequency for sampling the input signal; determining the frequency modulation factor based on the ratio. In this embodiment, the frequency generation factor circuit can generate a frequency modulation factor according to the carrier frequency point information of the input signal. For example, when the carrier frequency point information is , and the sampling frequency is w s , the frequency modulation factor can be determined according to / w s . Generating the frequency modulation factor according to the carrier frequency point information and the sampling frequency ensures that the frequency modulation factor can be dynamically adjusted according to the frequency characteristics of the signal, improving the adaptability of error compensation.

[0073] In an exemplary embodiment, the frequency factor generation circuit determines the frequency modulation factor based on the ratio in the following manner: determining the first product of the ratio and the imaginary unit; determining the exponential function with the natural constant as the base and the first product as the exponent as the frequency modulation factor. In this embodiment, the frequency modulation factor can be expressed as exp(jw c / w s ). Where j is the imaginary unit. Generating the frequency modulation factor through mathematical operations ensures its precise match with the signal frequency characteristics. For example, by calculating the product of the ratio of the signal frequency to the sampling frequency and the imaginary unit, and then using the exponential function of the natural constant e, a modulation factor closely related to the signal frequency characteristics can be obtained, thereby improving the accuracy and effectiveness of error compensation.

[0074] In an exemplary embodiment, the z-transform truncation error optimization transfer function of the optimized circuit for digital truncation error is as follows: ; where X(z) represents the input signal, E(z) represents the truncation error, and Y(z) represents the output signal of the optimized circuit for digital truncation error. In this embodiment, w c can represent the carrier center frequency point normalized to the range of -π to π. Through the z-transform transfer function, the performance of the circuit at different frequencies can be analyzed to guide the optimization of circuit parameters, thereby achieving better signal processing effects in practical applications.

[0075] In this embodiment, an optimization method for digital truncation error is provided, which can be applied to the optimization circuit for digital truncation error in any of the above embodiments. The method includes:

[0076] Receiving a first signal sent by the signal input terminal;

[0077] Generating the frequency modulation factor based on the carrier frequency point information of the first signal;

[0078] Performing a truncation process on the first signal to obtain the truncated signal;

[0079] Generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and a second signal, where the second signal is a signal sent by the signal input terminal after sending the first signal;

[0080] Adjusting a third signal based on the error adjustment signal, where the third signal is a signal sent by the signal input terminal after sending the second signal, and the input signal includes the first signal, the second signal, and the third signal.

[0081] In this embodiment, the input signal can be a digital signal or a discrete signal, and the signal input terminal can send a digital signal. When the first signal in the input signal is received, the frequency modulation factor can be generated according to the carrier frequency point information of the first signal. When other signals have been input by the signal input terminal before the first signal, the first error adjustment signal can be generated according to the other signals. The first signal passes through a first adder, is added to the first error adjustment signal to obtain the added signal, which is then input to the truncation circuit. The truncation circuit performs a truncation process on the added signal. When no other signals have been input by the signal input terminal before the first signal, there is no first error adjustment signal. The first signal passes through the first adder and is input to the truncation circuit, and the truncation circuit performs a truncation process on the first signal to obtain the truncated signal. Therefore, the truncated signal can be a signal directly obtained by performing a truncation process on the first signal, or a signal obtained by performing a truncation process on the added signal.

[0082] In this embodiment, the error adjustment signal can also be generated according to the frequency modulation factor, the truncated signal, and the second signal, and the third signal is adjusted according to the obtained error adjustment signal. After the third signal is adjusted, a truncation process is performed on the adjusted third signal and then output.

[0083] In this embodiment, the above method can be a method that is executed cyclically. Through a dynamic adjustment mechanism, effective compensation for truncation error is achieved, and the accuracy and stability of signal processing are improved.

[0084] Through the present invention, since a frequency modulation factor can be generated according to the carrier frequency point information of the input signal, an error adjustment signal is generated according to the frequency modulation factor, the second signal and the truncated signal, and after the third signal is truncated by the error adjustment signal and output, the error shaping frequency domain response curve is adjusted according to the actual frequency point where the carrier is located, thereby improving the signal-to-noise ratio within the signal band. Therefore, the problem of low signal-to-noise ratio of the optimized truncation error circuit in the related art can be solved, and the effect of improving the signal-to-noise ratio within the signal band can be achieved.

[0085] In an exemplary embodiment, generating the frequency modulation factor based on the carrier frequency point information of the first signal includes: determining a ratio of the carrier frequency point information to a sampling frequency for sampling the input signal; determining the frequency modulation factor based on the ratio. In this embodiment, the frequency generation factor circuit can generate a frequency modulation factor according to the carrier frequency point information of the input signal. For example, when the carrier frequency point information is and the sampling frequency is w s , the frequency modulation factor can be determined according to / w s . Generating the frequency modulation factor according to the carrier frequency point information and the sampling frequency ensures that the frequency modulation factor can be dynamically adjusted according to the frequency characteristics of the signal, improving the adaptability of error compensation.

[0086] In an exemplary embodiment, determining the frequency modulation factor based on the ratio includes: determining a first product of the ratio and the imaginary unit; determining an exponential function with the natural constant as the base and the first product as the exponent as the frequency modulation factor. In this embodiment, the frequency modulation factor can be expressed as exp(jw c / w s ). Where j is the imaginary unit. Generating the frequency modulation factor through mathematical operations ensures its precise matching with the signal frequency characteristics. For example, by calculating the product of the ratio of the signal frequency to the sampling frequency and the imaginary unit, and then using the exponential function of the natural constant e, a modulation factor closely related to the signal frequency characteristics can be obtained, thereby improving the accuracy and effectiveness of error compensation.

[0087] In an exemplary embodiment, generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal includes: padding the truncated signal to obtain a padded signal, where the bit width of the padded signal is the same as the bit width of the input signal; determining a difference between the second signal and the padded signal; after delaying for a first predetermined time, determining a second product of the difference and the frequency modulation factor; and determining the second product as the error adjustment signal.

[0088] In an exemplary embodiment, adjusting the third signal based on the error adjustment signal includes: performing a summation operation on the third signal and the error adjustment signal to adjust the third signal. In this embodiment, the third signal and the error adjustment signal can be subjected to a summation operation to obtain an adjusted signal, the adjusted information can be subjected to a truncation process, and the truncated signal can be output. Error compensation for the signal is achieved through simple mathematical operations, improving the efficiency and accuracy of signal processing.

[0089] In an exemplary embodiment, before generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal, the method further includes: obtaining a fourth signal, where the fourth signal is a signal sent by the signal input end before sending the first signal, and the input signal includes the fourth signal; in a case where the first signal is different from the fourth signal, generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal. In this embodiment, before adjusting the signal, it can be determined whether two adjacent samples included in the input signal, that is, the first signal and the fourth signal, are the same. If they are the same, there is no need to adjust the signal, that is, there is no need to generate an error adjustment signal. This is because the truncation error distribution does not conform to the white noise random characteristic when the input signal exhibits a DC input characteristic. When the two are different, an error adjustment signal is generated to adjust the signal through the error adjustment signal. Through conditional judgment, precise detection of signal changes is achieved, providing a basis for the intelligent start and stop of error compensation. For example, in signal processing, by detecting the difference between the current signal and the previous signal, it can be accurately determined whether it is necessary to start the error processing mechanism, avoiding unnecessary calculations and improving the response speed and stability of the system.

[0090] Figure 5 is a structural block diagram of a cascaded digital signal processing circuit according to an embodiment of the present invention, as Figure 5 shown, the device includes:

[0091] a plurality of digital signal processing circuits 52, a frequency point information configuration circuit 54, and a plurality of optimization circuits for digital truncation errors in any of the above embodiments;

[0092] The frequency point information configuration circuit is respectively connected to the frequency factor generation circuits of the plurality of optimization circuits for digital truncation errors, and is configured to provide carrier frequency point information to the frequency factor generation circuits;

[0093] The output end of each digital signal processing circuit is connected to an optimization circuit for digital truncation errors, obtaining a plurality of connection circuits, and the optimization circuits for digital truncation errors connected by different digital signal processing circuits are different;

[0094] Multiple of the connection circuits are connected in series to form a multi-stage digital signal processing circuit.

[0095] In the above embodiment, an optimization circuit for digital truncation error can be connected after each digital signal processing circuit to optimize the error of the signal output by the digital signal processing circuit. A frequency point information configuration circuit can be configured for multiple optimization circuits for digital truncation error. The frequency point information configuration circuit can provide carrier frequency point information for the frequency factor generation circuit in multiple optimization circuits for digital truncation error.

[0096] In the above embodiment, the frequency point information configuration circuit can perform parameter calculation according to the carrier center frequency points corresponding to each node in the link. By optimizing each truncation part of the digital module in the cascaded digital signal processing circuit, the SNR improvement effect within the effective signal band can be achieved. The introduction of the cascaded structure can handle complex signal processing links and effectively reduce the error accumulation in multi-stage processing.

[0097] Figure 6 It is a structural block diagram of a radio frequency transmitting device according to an embodiment of the present invention, as Figure 6 shown. The device includes: a first baseband module 62, a digital-to-analog conversion module 64, and a cascaded digital signal processing circuit as in the above embodiment. The output end of the first baseband module is connected to the input end of the digital-to-analog conversion module through the cascaded digital signal processing circuit. In this embodiment, the radio frequency transmitting device can be the radio frequency transmitting device in a radio frequency direct sampling architecture signal transceiver (RF transceiver), such as an antenna.

[0098] In the above embodiment, a specific structural schematic diagram of the radio frequency transmitting device can be referred to in the appendix Figure 7 , as Figure 7 shown. The first baseband module outputs signal data to the cascaded digital signal processing circuit, and the cascaded digital signal processing circuit sends the output signal to the digital-to-analog conversion module. Among them, Module 1 and Module 2 are the digital signal processing circuits, and Truncation Error Optimization 1 and Truncation Error Optimization 2 are the optimization circuits for digital truncation error. Baseband is the first baseband module, digital-to-analog conversion is the digital-to-analog conversion module, and Module-Level Frequency Point Information Configuration is the frequency point information configuration circuit.

[0099] In a radio frequency transmitting device, the baseband signal is converted into an analog signal after being processed through multiple stages. The introduction of a cascaded digital signal processing circuit can effectively reduce the truncation error during the signal processing process and ensure the high quality of the transmitted signal. For example, in a 5G communication system, the processing of high-speed baseband signals requires extremely high precision. The cascaded optimization circuit can significantly improve the accuracy and stability of signal processing and reduce the distortion of the transmitted signal. This technical solution solves the problem of signal processing accuracy in radio frequency transmitting devices and is applicable not only to 5G communication but also to any scenario that requires high-quality signal transmission, including but not limited to satellite communication, radar systems, etc.

[0100] Figure 8 is a structural block diagram of a radio frequency receiving device according to an embodiment of the present invention. As Figure 8 shown, the radio frequency receiving device includes a second baseband module 82, an analog-to-digital conversion module 84, and a cascaded digital signal processing circuit as in the above embodiment. The output end of the analog-to-digital conversion module is connected to the input end of the second baseband module through the cascaded digital signal processing circuit. In this embodiment, the radio frequency receiving device can be the radio frequency receiving device in a radio frequency direct sampling architecture signal transceiver (RF transceiver), such as an antenna.

[0101] In the above embodiment, for the specific structural schematic diagram of the radio frequency receiving device, reference can be made to the appendix Figure 9 , as Figure 9 shown, the signal output by the analog-to-digital conversion module is input and sent to the cascaded digital signal processing circuit, and the cascaded digital signal processing circuit sends the output signal to the second baseband module. Among them, Module 1 and Module 2 are the digital signal processing circuits, and Truncation Error Optimization 1 and Truncation Error Optimization 2 are the optimization circuits for digital truncation errors. The baseband is the second baseband module, the analog-to-digital conversion is the analog-to-digital conversion module, and the Module-Level Frequency Point Information Configuration is the frequency point information configuration circuit.

[0102] In a radio frequency receiving device, after the analog signal is converted into a baseband signal, multiple stages of digital signal processing are required. The cascaded digital signal processing circuit can effectively reduce the truncation error during the processing process and improve the accuracy of the received signal. For example, at the receiving end of wireless communication, the received signal may deteriorate in quality due to interference during transmission. The cascaded optimization circuit can restore the original quality of the signal through precise error compensation. This technical solution solves the problem of signal processing accuracy in radio frequency receiving devices and is applicable not only to wireless communication but also to any scenario that requires high-quality signal reception, including but not limited to cable TV signal reception, sonar signal processing, etc.

[0103] Figure 10 is a structural block diagram of a radio frequency digital-to-analog converter according to an embodiment of the present invention. As Figure 10 shown, the radio frequency digital-to-analog converter includes:

[0104] A filter circuit 1002, the filter circuit including a sample rate converter and an optimization circuit for digital truncation error in any of the above embodiments, an output end of the sample rate converter being connected to a signal input end of the optimization circuit for digital truncation error;

[0105] A digital frequency shift circuit 1004, the digital frequency shift circuit including a second multiplier, a numerically controlled oscillator, and the optimization circuit for digital truncation error, a first input end of the second multiplier being connected to an output end of the filter circuit, a second input end of the second multiplier being connected to the numerically controlled oscillator, and an output end of the second multiplier being connected to an input end of the optimization circuit for digital truncation error;

[0106] A digital-to-analog converter 1006, an input end of the digital-to-analog converter being connected to an output end of the digital frequency shift circuit;

[0107] A frequency controller 1008, the frequency controller being connected to the frequency factor generation circuit of each of the optimization circuits for digital truncation error, and being configured to provide carrier frequency point information to the frequency factor generation circuit.

[0108] In the above embodiments, an input end of the sample rate converter is an input end of the filter circuit, and an output end of the optimization circuit for digital truncation error connected to the output end of the sample rate converter is an output end of the filter circuit. A first input end of the second multiplier is a first input end of the digital frequency shift circuit, a second input end of the second multiplier is a second input end of the digital frequency shift circuit, and an output end of the numerically controlled oscillator connected to an output end of the second multiplier circuit is an output end of the digital frequency shift circuit.

[0109] In the above embodiments, there may be one or more filter circuits. There may be one or more digital frequency shift circuits.

[0110] Wherein, the sample rate converter SRC (Sample rate converter) is configured to convert a baseband signal sample rate to a digital-to-analog converter (DAC) sample rate, and the numerically controlled oscillator may be an NCO (numerically controlled oscillator), and is configured to convert a signal frequency point from a baseband frequency band to a radio frequency band.

[0111] In an exemplary embodiment, there are multiple filtering circuits and multiple digital frequency shift circuits. The multiple digital frequency shift circuits are arranged at intervals. The input end of each digital frequency shift circuit is connected to the output end of one of the filtering circuits, and the output end of the digital frequency shift circuit is connected to the input ends of the other filtering circuits. In this embodiment, when there are multiple filtering circuits, the multiple filtering circuits can be connected in series to obtain a serial link, and the output end of the serial link is connected to the input end of the digital frequency shift circuit. In the above embodiment, for the specific structural schematic diagram of the radio frequency digital-to-analog converter, please refer to Appendix Figure 11 , such as Figure 11 shown. The radio frequency digital-to-analog converter includes a 4-stage interpolation filtering module, that is, a sampling rate converter, and each interpolation filter performs 2-fold upsampling. The frequency control module is used to generate the frequency point modulation information required by each truncation optimization circuit. The input signal is a high-precision 16-bit signal, and the data bit width of the output of each subsequent digital processing module is truncated to 12 bits. For the schematic diagram of the input test signal spectrum input to the radio frequency digital-to-analog converter, please refer to Appendix Figure 12 . After 4-stage interpolation filtering, the output of each stage is truncated to 12 bits; the output of the last stage is frequency shifted to the center frequency of 1.84G through a digital NCO. Comparing the truncation methods of the optimization circuit for normal truncation and digital truncation errors, finally, for the schematic diagram of the digital signal spectrum at the DAC input, please refer to Appendix Figure 13 , such as Figure 13 shown. The fourth curve is the signal spectrum optimized by the optimization circuit for digital truncation errors; the fifth curve is the spectrum of the ordinary truncation method. By paying attention to the in-band noise floor in the 200M range between two single-tone signals, it can be found that after being optimized by the optimization circuit for digital truncation errors, the signal noise floor shows the characteristics of in-band decline and out-of-band elevation. The out-of-band noise deterioration can be filtered out by the subsequent analog filter and does not affect the system performance. Under the optimization of the optimization circuit for digital truncation errors, the in-band average SNR of the signal is increased by about 10dB. Each interpolation filter and digital frequency shift module apply the truncation error optimization circuit to achieve the optimization effect of the total digital noise in the effective signal band. Observe the last digital node of the DAC or the analog pin of the DAC output, input a single-tone signal at a specific frequency point, and adjust the frequency point configuration information to observe the noise distribution. The noise optimization will show frequency point tracking.

[0112] In the above embodiments, the radio frequency digital-to-analog converter may include a plurality of filtering circuits and a plurality of digital frequency shift circuits. When the number of filtering circuits is the same as that of the digital frequency shift circuits, the filtering circuits and the digital frequency shift circuits may be arranged at intervals. The output end of one filtering circuit is connected to the input end of one digital frequency shift circuit, and the output end of the digital frequency shift circuit is then connected to the input end of another filtering circuit. For example, when the filtering circuit is A and the digital frequency shift circuit is B and their numbers are the same, the connection relationship may be ABABAB... When the number of filtering circuits is greater than the number of digital frequency shift circuits, multiple filtering circuits may be connected in series and then connected to one digital frequency shift circuit. For example, when the filtering circuit is A and the digital frequency shift circuit is B and the number of A is greater than that of B, the connection relationship may be AAABABAB...

[0113] In the foregoing embodiments, the optimization circuit for digital truncation error may configure the signal frequency point information of the link position where each truncation optimization circuit is located by the user. This interface is visible externally and can be judged through the product user manual. The optimization circuit for digital truncation error can be used for the overall truncation noise optimization in the digital cascade architecture, and has the function of freely adjusting the frequency point. It can adjust the error shaping frequency domain response curve according to the actual frequency point where the carrier is located, and has the characteristics of low cost and low power consumption.

[0114] An embodiment of the present invention further provides a communication device, which may include one or more of an optimization circuit for digital truncation error, a cascaded digital signal processing circuit, a radio frequency transmitting device, a radio frequency receiving device, and a radio frequency digital-to-analog converter. In this embodiment, the communication device may be a radio frequency direct sampling architecture signal transceiver (RF transceiver), etc.

[0115] In an exemplary embodiment, the communication device includes one of the following: a base station disposed in a satellite, a base station disposed on the ground, and a terminal device. In this embodiment, the communication device may be a device in a satellite, such as a base station in a satellite. It may also be a device on the ground, such as a base station on the ground. It may also be a terminal device, such as a mobile phone, an automobile (electric vehicle, fuel vehicle), a ship, an airplane, etc. In the foregoing embodiments, by shaping the truncation error of each processing module at all levels of the digital link, the overall in-band signal-to-noise ratio (SNR) after cascading of each module is improved, and the involved error shaping process can flexibly match the frequency point where the signal is located, achieving the performance improvement effect with a small circuit cost.

[0116] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An optimized circuit for digital truncation error, characterized in that, Including: A first adder, wherein a first input terminal of the first adder is connected to a signal input terminal; A truncation circuit, wherein an input terminal of the truncation circuit is connected to an output terminal of the first adder, and an output terminal of the truncation circuit is connected to a signal output terminal. The truncation circuit is configured to perform a truncation process on a signal output by the first adder to obtain a truncated signal, and output the truncated signal to the signal output terminal; A frequency factor generation circuit, configured to generate a frequency modulation factor based on carrier frequency point information of an input signal transmitted by the signal input terminal; A truncation error processing circuit, wherein a first input terminal of the truncation error processing circuit is connected to an output terminal of the truncation circuit, a second input terminal of the truncation error processing circuit is connected to an output terminal of the frequency factor generation circuit, a third input terminal of the truncation error processing circuit is connected to an output terminal of the first adder, and an output terminal of the truncation error processing circuit is connected to a second input terminal of the first adder. The truncation error processing circuit is configured to generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder, and the truncated signal, and send the error adjustment signal to the first adder.

2. The optimized circuit for digital truncation error according to claim 1, characterized in that The truncation circuit includes a low-bit truncation circuit.

3. The optimized circuit for digital truncation error according to claim 1, wherein The truncation error processing circuit includes: A padding circuit, wherein an input terminal of the padding circuit is connected to an output terminal of the truncation circuit, and is configured to perform a padding operation on the truncated signal to obtain a padded signal, wherein a bit width of the padded signal is the same as a bit width of the input signal; A second adder, wherein a first input terminal of the second adder is connected to an output terminal of the padding circuit, and a second input terminal of the second adder is connected to an output terminal of the first adder, and is configured to subtract the signal output by the first adder from the padded signal to obtain an error signal; A first multiplier, wherein a first input terminal of the first multiplier is connected to an output terminal of the second adder, a second input terminal of the first multiplier is connected to an output terminal of the frequency factor generation circuit, and an output terminal of the first multiplier is connected to a second input terminal of the first adder, and is configured to multiply the error signal by the frequency modulation factor to obtain a product signal, and input the product signal into the first adder.

4. The optimized circuit for digital truncation error according to claim 3, wherein The truncation error processing circuit further includes: A first delay circuit, wherein an output terminal of the second adder is connected to the first multiplier through the first delay circuit.

5. The optimized circuit for digital truncation error according to claim 1, characterized in that, The digital truncation error optimization circuit further includes: A judgment circuit, wherein an input terminal of the judgment circuit is connected to the signal input terminal, and is configured to receive the input signal and judge whether two temporally adjacent signals included in the input signal are the same. In the case of being the same, control the truncation error processing circuit to be turned off, and in the case of being different, control the truncation error processing circuit to be enabled.

6. The optimized circuit for digital truncation error according to claim 5, characterized in that, The judgment circuit includes: A second delay circuit, wherein an input terminal of the second delay circuit is connected to the signal input terminal, and is configured to delay the input signal; A judgment sub - circuit, the first input terminal of the judgment sub - circuit is connected to the signal input terminal, and the second input terminal of the judgment sub - circuit is connected to the output terminal of the second delay circuit, and is used to judge whether the signal sent by the signal input terminal is the same as the signal output by the output terminal of the second delay circuit.

7. The optimized circuit for digital truncation error according to claim 1, wherein The frequency factor generation circuit generates a frequency modulation factor based on the carrier frequency point information of the input signal sent by the signal input terminal in the following way: determining the ratio of the carrier frequency point information to the sampling frequency for sampling the input signal; Determining the frequency modulation factor based on the ratio.

8. The optimized circuit for digital truncation error according to claim 7, characterized in that, The frequency factor generation circuit determines the frequency modulation factor based on the ratio in the following way: determining the first product of the ratio and the imaginary unit; determining the exponential function with the natural constant as the base and the first product as the exponent as the frequency modulation factor.

9. The optimized circuit for digital truncation error according to claim 1, wherein The z - transform truncation error optimization transfer function of the digital truncation error optimization circuit is as follows: ； Where, X(z) represents the input signal, E(z) represents the truncation error, and Y(z) represents the output signal of the digital truncation error optimization circuit.

10. An optimization method for digital truncation error, characterized in that, Applied to the digital truncation error optimization circuit according to any one of claims 1 to 9, it includes: Receiving the first signal sent by the signal input terminal; Generating the frequency modulation factor based on the carrier frequency point information of the first signal; Performing a truncation process on the first signal to obtain the truncated signal; Generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal, where the second signal is the signal sent by the signal input terminal after sending the first signal; Adjusting the third signal based on the error adjustment signal, where the third signal is the signal sent by the signal input terminal after sending the second signal, and the input signal includes the first signal, the second signal, and the third signal.

11. The optimization method for digital truncation error according to claim 10, characterized in that Generating the frequency modulation factor based on the carrier frequency point information of the first signal includes: Determining the ratio of the carrier frequency point information to the sampling frequency for sampling the input signal; determining the frequency modulation factor based on the ratio.

12. The optimization method for digital truncation error according to claim 11, characterized in that, Determining the frequency modulation factor based on the ratio includes: Determining the first product of the ratio and the imaginary unit; Determining the exponential function with the natural constant as the base and the first product as the exponent as the frequency modulation factor.

13. The optimization method for digital truncation error according to claim 10, wherein Generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal includes: Complementing the truncated signal to obtain a complemented signal, where the bit - width of the complemented signal is the same as the bit - width of the input signal; Determining the difference between the second signal and the complemented signal; After delaying for a first predetermined time, determining the second product of the difference and the frequency modulation factor; Determining the second product as the error adjustment signal.

14. The optimization method for digital truncation error according to claim 10, wherein, Adjusting the third signal based on the error adjustment signal includes: Performing a summation operation on the third signal and the error adjustment signal to adjust the third signal.

15. The optimization method for digital truncation error according to claim 10, wherein Before generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal, the method further includes: Obtaining a fourth signal, where the fourth signal is a signal sent by the signal input end before sending the first signal, and the input signal includes the fourth signal; In the case where the first signal is different from the fourth signal, generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal.

16. A cascaded digital signal processing circuit, characterized in that, Comprising: A plurality of digital signal processing circuits, a frequency point information configuration circuit, and a plurality of optimization circuits for digital truncation error as described in any one of claims 1 to 9; The frequency point information configuration circuit is respectively connected to the frequency factor generation circuit of a plurality of the optimization circuits for digital truncation error, and is configured to provide carrier frequency point information to the frequency factor generation circuit; The output end of each digital signal processing circuit is connected to an optimization circuit for digital truncation error, obtaining a plurality of connection circuits, and the optimization circuits for digital truncation error connected by different digital signal processing circuits are different; A plurality of the connection circuits are serially connected to form a multi-stage digital signal processing circuit.

17. A radio frequency transmitting device, characterized in that, Comprising: A first baseband module, a digital-to-analog conversion module, and a cascaded digital signal processing circuit as described in claim 16, and an output end of the first baseband module is connected to an input end of the digital-to-analog conversion module through the cascaded digital signal processing circuit.

18. A radio frequency receiving device, characterized in that, Comprising a second baseband module, an analog-to-digital conversion module, and a cascaded digital signal processing circuit as described in claim 16, and an output end of the analog-to-digital conversion module is connected to an input end of the second baseband module through the cascaded digital signal processing circuit.

19. A radio frequency digital-to-analog converter, characterized in that, Comprising: A filtering circuit, the filtering circuit includes a sampling rate converter and an optimization circuit for digital truncation error as described in any one of claims 1 to 9, and an output end of the sampling rate converter is connected to a signal input end of the optimization circuit for digital truncation error; A digital frequency shift circuit, the digital frequency shift circuit includes a second multiplier, a numerically controlled oscillator, and the optimization circuit for digital truncation error, a first input end of the second multiplier is connected to an output end of the filtering circuit, a second input end of the second multiplier is connected to the numerically controlled oscillator, and an output end of the second multiplier is connected to an input end of the optimization circuit for digital truncation error; A digital-to-analog converter, and an input end of the digital-to-analog converter is connected to an output end of the digital frequency shift circuit; A frequency controller, the frequency controller is connected to the frequency factor generation circuit of each optimization circuit for digital truncation error, and is configured to provide carrier frequency point information to the frequency factor generation circuit.

20. The radio frequency digital-to-analog converter according to claim 19, wherein There are a plurality of the filtering circuits, and a plurality of the digital frequency shift circuits. The plurality of digital frequency shift circuits are arranged at intervals, an input end of each digital frequency shift circuit is connected to an output end of one of the filtering circuits, and an output end of the digital frequency shift circuit is connected to an input end of another filtering circuit.

21. A communication device, characterized in that, Comprising the optimization circuit for digital truncation error as described in any one of claims 1 to 9, or comprising the cascaded digital signal processing circuit as described in claim 16, or comprising the radio frequency transmitting device as described in claim 17, or comprising the radio frequency receiving device as described in claim 18, or comprising the radio frequency digital-to-analog converter as described in any one of claims 19 to 20.

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