Pim-dram compatible computing system

Abstract

The application belongs to the technical field of semiconductors and specifically relates to a PIM-DRAM compatible with a computing system, which comprises a PIM-Channel address configurator configured to process address mapping conversion between a memory channel and a DIMM level according to an address mapping function; a PIM-Rank address configurator configured to process address mapping conversion between a Rank level and a Bank level according to the address mapping function; and a PIM-Local address configurator configured to isolate data of PIM tasks and host system tasks in a DRAM Bank according to the address mapping conversion; wherein the address mapping function is a reversible function of a mapping relationship between a system original address and a PIM task address. The application realizes compatibility between the computing system and the PIM-DRAM without closing the memory interleaving.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor technology, and particularly relates to a PIM-DRAM compatible with a computing system. BACKGROUND

[0002] The existing computer system adopts a memory interleaving technology to disperse data to different physical levels (memory channels, DIMMs, ranks, chips, and banks) to improve the bandwidth. However, PIM (Processing-in-Memory)-DRAM requires that the associated data be stored in the same physical area to achieve efficient computing. The contradiction between the two results in that the PIM-DRAM cannot be directly deployed in the existing system, and closing the memory interleaving will significantly reduce the system performance.

[0003] That is, the DRMA-PIM requires that the associated data be placed in the same physical area as much as possible, while the memory interleaving of the computer system will disperse the associated data to different memory channels, DIMMs, ranks, chips, and different banks, resulting in a contradiction between the data storage mode required by the PIM-DRAM and the data storage mode of the computer system, which is incompatible, resulting in that the PIM-DRAM cannot be deployed on the computing system.

[0004] The existing solution is to close the memory interleaving in the computing system, which although meets the memory access requirement of the PIM-DRAM, but will significantly reduce the memory access performance of the computing system. SUMMARY

[0005] The present application aims to provide a PIM-DRAM compatible with a computing system to solve the technical problem that the memory interleaving adopted by the computing system is incompatible with the PIM-DRAM.

[0006] In order to solve the foregoing technical problem, the present application provides a PIM-DRAM compatible with a computing system, which comprises:

[0007] A PIM-Channel address configurator connected with a CPU and a memory management unit respectively, configured to process the address mapping conversion between the memory channel and the DIMM level according to an address mapping function;

[0008] A PIM-Rank address configurator connected with the PIM-Channel address configurator, configured to process the address mapping conversion between the Rank level and the Bank level according to an address mapping function;

[0009] a PIM-Local address configurator connected with the PIM-Rank address configurator and a DRAM controller respectively, configured to isolate data of the PIM task and the main system task in the DRAM Bank according to address mapping conversion;

[0010] The address mapping function is a reversible function of the mapping relationship between the system original address and the PIM task address.

[0011] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Channel address configurator and the PIM-Rank address configurator each comprise:

[0012] An original address reverse reading module configured to retain and read back the interleaved hardware address information of the memory of the computing system to obtain an original address mapping table of the current memory interleaving strategy of the system.

[0013] A PIM address feature extraction module configured to generate a theoretical address mapping meeting the data centralized storage requirement according to the PIM computing requirement.

[0014] A page table function fitting module configured to fit the original address mapping table and the theoretical address mapping to generate a reversible function, i.e., an address mapping function, to realize address conversion.

[0015] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM address feature extraction module monitors the memory access request of the PIM task, counts the data distribution characteristics of the PIM task, and generates a theoretical address mapping meeting the data centralized storage requirement.

[0016] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Channel address configurator is located on the motherboard side, and the PIM address feature extraction module in the PIM-Channel address configurator serves as a motherboard side PIM address feature extraction module configured to generate a theoretical address mapping meeting the data centralized storage requirement according to the access characteristics of the memory channel or the DIMM level.

[0017] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Rank address configurator is located on the memory side, and the PIM address feature extraction module of the PIM-Rank address configurator serves as a memory side PIM address feature extraction module configured to generate a theoretical address mapping meeting the data centralized storage requirement according to the access characteristics of the Rank level or the Bank level.

[0018] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-DRAM comprises a 3D stacked DRAM storage layer and a logical computing layer, and the PIM-Local address configurator and the DRAM controller are both located in the logical computing layer.

[0019] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Local address configurator distinguishes PIM task data from main system data according to address mapping conversion, stores PIM task data in the same DRAM Bank or DRAM Chip to avoid memory interleaving interference, and triggers the PIM operation unit to perform calculation.

[0020] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Local address configurator distinguishes PIM task data from main system data by marking PIM task data with a label or metadata to distinguish PIM task data from main system data.

[0021] The positive progress effect of the present application is that:

[0022] 1. The present application realizes compatibility of the computing system and the PIM-DRAM without closing the memory interleaving by adding the multi-level memory controller group composed of the PIM-Channel address configurator, the PIM-Rank address configurator and the PIM-Local address configurator.

[0023] 2. The present application can balance the PIM performance and the overall throughput of the system by adjusting the address mapping function in real time according to the calculation requirement of the PIM task. BRIEF DESCRIPTION OF DRAWINGS

[0024] The disclosure of the present application will be more apparent with reference to the drawings. It should be understood that the drawings are only for the purpose of illustration, and are not intended to limit the scope of protection of the present application. In the drawings:

[0025] Figure 1 It is a schematic diagram of a connection relationship of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be described below through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied through other different specific embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0027] It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] In the description of the present application, it should be noted that, for the orientation words, such as the terms "outer side", "middle section", "inner", "outer", etc. indicate the orientation and positional relationship based on the orientation or positional relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, and not to indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as limiting the specific protection scope of the present application.

[0029] In addition, if the terms "first", "second" are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. Therefore, the "first", "second" features defined can explicitly or implicitly include one or more features, and in the description of the present application, the meaning of "several", "several" is two or more, unless otherwise explicitly specified.

[0030] The embodiment of the present application provides a compatible computing system PIM-DRAM, which comprises a multi-level memory controller group, and the compatible computing system PIM-DRAM is realized by the multi-level memory controller group without closing the memory interleaving.

[0031] Referring to Figure 1 , the multi-level memory controller group comprises a PIM-Channel address configurator (MAPA-C), a PIM-Rank address configurator (MAPA-R) and a PIM-Local address configurator (MAPA-B).

[0032] The PIM-Channel address configurator is connected with a CPU (central processing unit) and a memory management unit (MMU) respectively, and the PIM-Channel address configurator is used for processing address mapping conversion of the memory channel and the DIMM level according to an address mapping function. That is to say, the address information collected and converted by the PIM-Channel address configurator is the Rank level (memory channel, DIMM level).

[0033] The PIM-Rank address configurator is connected with the PIM-Channel address configurator and the PIM-Local address configurator respectively, and the PIM-Rank address configurator is used for processing address mapping conversion of the Rank level and the Bank level according to an address mapping function. That is to say, the address information collected and converted by the PIM-Rank address configurator is the Rank level and the Bank level.

[0034] The above-mentioned address mapping function is a reversible function of the mapping relationship between the system original address and the PIM task address.

[0035] The PIM-Local address configurator is connected with the PIM-Rank address configurator and a DRAM controller (MC), and is used for isolating data of the PIM task and the main system task in the DRAM Bank according to address mapping conversion.

[0036] The application can reserve the hardware address information of the memory interweaving in the computing system by the multi-level memory controller group, the hardware address information is provided by the MMU, the MMU converts the virtual address created by the CPU into the physical address in the computer memory, and the physical address is the hardware address information, also called the system original address. According to the mapping relationship between the hardware address information and the PIM task address obtained according to the address mapping function, the PIM task data and the main system task data are effectively isolated to avoid the memory interweaving interference problem, and finally the purpose of compatibility of the computing system and the PIM-DRAM is realized.

[0037] In some embodiments, the PIM-Channel address configurator and the PIM-Rank address configurator each include an original address reverse reading module for system original address mapping acquisition, a PIM address feature extraction module for PIM task data memory address arrangement characteristic extraction, and a page table function fitting module for page table function fitting, and the three modules realize the dynamic address conversion purpose.

[0038] The original address reverse reading module is used for reserving and reading back the hardware address information after memory interweaving of the computing system, and obtaining the original address mapping table (PT1) of the current memory interweaving strategy of the system.

[0039] The PIM address feature extraction module is used for generating a theoretical address mapping (PT2) meeting the data centralized storage requirement according to the PIM computing requirement.

[0040] The page table function fitting module is used for fitting the original address mapping table and the theoretical address mapping to generate a reversible function, that is, an address mapping function, to realize address conversion.

[0041] Specifically, by linear / nonlinear fitting of PT1 and PT2, a mapping function F1=PT2=f1(PT1) and an inverse function F2=PT1=f2(PT2) are generated. The mapping function and the inverse function are the address mapping function.

[0042] In some embodiments, the PIM address feature extraction module monitors the memory access request of the PIM task, and generates a theoretical address mapping meeting the data centralized storage requirement by counting the PIM task data distribution characteristics.

[0043] Specifically, the PIM task data distribution features include continuity and locality, etc. The theoretical address distribution table is generated by analyzing the access mode of the PIM task, and the theoretical address mapping is obtained. This process can be implemented by using existing technologies such as time series analysis based on sliding window.

[0044] Through the above design, the address mapping function can be adjusted in real time according to the calculation requirements of the PIM task, and the PIM performance and the overall throughput of the system are balanced.

[0045] In some embodiments, the PIM-Channel address configurator is located on the mainboard side, that is, the PIM-Channel address configurator is deployed on the mainboard. The PIM address feature extraction module in the PIM-Channel address configurator is a mainboard-side PIM address feature extraction module, which is used to generate a theoretical address mapping that meets the requirements of data centralized storage according to the access features of the memory channel or the DIMM level.

[0046] In some embodiments, the PIM-Rank address configurator is located on the memory side, that is, the PIM-Rank address configurator is deployed on the DIMM. The PIM address feature extraction module of the PIM-Rank address configurator is a memory-side PIM address feature extraction module, which is used to generate a theoretical address mapping that meets the requirements of data centralized storage according to the access features of the Rank level or the Bank level.

[0047] In some embodiments, the PIM-DRAM includes 3D stacked DRAM storage layers and logical computing layers, and the PIM-Local address configurator and the DRAM controller are located in the logical computing layer. That is, the PIM-Local address configurator and the DRAM controller are deployed in the logical computing layer of the PIM-DRAM 3D chip.

[0048] As shown in Figure 1 In the logical computing layer, there can be several processor cores NPU, and in the DRAM storage layer, there are several RAMs stacked in DRAM layers, each RAM has a corresponding MC to realize control, and each MC is connected with its corresponding NPU, MAPA-B, and MMU.

[0049] In some embodiments, the PIM-Local address configurator distinguishes PIM task data and main system data according to address mapping conversion, stores the PIM task data in a specific row (Row) or DRAM Chip (chip) of the same DRAM Bank to avoid memory interleaving interference, and triggers the PIM operation unit to perform calculation. While the main system data and other task data remain the original interleaving strategy.

[0050] The PIM-Local address configurator of the embodiment implements data distinguishing, rearrangement and local computing scheduling functions.

[0051] In some embodiments, the PIM-Local address configurator distinguishes PIM task data from main system data by marking the PIM task data with a tag or metadata.

[0052] The above embodiment of the present application is described in detail with reference to the accompanying drawings, and those skilled in the art can make various changes to the present application according to the above description. Thus, some details in the embodiment should not constitute a limitation on the present application, and the present application will be protected within the scope defined by the appended claims.

Claims

1. A PIM-DRAM compatible computing system, comprising: The PIM-DRAM of the compatible computing system comprises: a PIM-Channel address configurator connected with a CPU and a memory management unit respectively, configured to process address mapping conversion between a memory channel and a DIMM level according to an address mapping function; a PIM-Rank address configurator connected with the PIM-Channel address configurator, configured to process address mapping conversion between a Rank level and a Bank level according to an address mapping function; a PIM-Local address configurator connected with the PIM-Rank address configurator and a DRAM controller respectively, configured to isolate data of a PIM task and a main system task in a DRAM Bank according to address mapping conversion; wherein the address mapping function is a reversible function of a mapping relationship between a system original address and a PIM task address; the PIM-Channel address configurator and the PIM-Rank address configurator each comprise: an original address reverse reading module configured to retain and read back hardware address information after interleaving of a memory of a computing system, to obtain an original address mapping table of a current memory interleaving strategy of the system; a PIM address feature extraction module configured to generate a theoretical address mapping meeting data centralized storage requirements according to PIM computing requirements; a page table function fitting module configured to fit the original address mapping table and the theoretical address mapping, to generate a reversible function, i.e., an address mapping function, to realize address conversion.

2. The PIM-DRAM for a compatible computing system of claim 1, wherein, The PIM address feature extraction module monitors a memory access request of a PIM task, and statistically obtains data distribution characteristics of the PIM task, to generate a theoretical address mapping meeting data centralized storage requirements.

3. The PIM-DRAM for a compatible computing system of claim 2, wherein, The PIM-Channel address configurator is located at a mainboard side, and the PIM address feature extraction module in the PIM-Channel address configurator is a mainboard side PIM address feature extraction module, configured to generate a theoretical address mapping meeting data centralized storage requirements according to access characteristics of a memory channel or a DIMM level.

4. The PIM-DRAM for a compatible computing system of claim 2, wherein, The PIM-Rank address configurator is located at a memory side, and the PIM address feature extraction module of the PIM-Rank address configurator is a memory side PIM address feature extraction module, configured to generate a theoretical address mapping meeting data centralized storage requirements according to access characteristics of a Rank level or a Bank level.

5. The PIM-DRAM for a compatible computing system of claim 1, wherein, The PIM-DRAM comprises 3D stacked DRAM storage layers and logical computing layers, and the PIM-Local address configurator and the DRAM controller are both located at the logical computing layers.

6. The PIM-DRAM for a compatible computing system of claim 1, wherein, The PIM-Local address configurator distinguishes PIM task data from main system data according to address mapping conversion, stores PIM task data in the same DRAM Bank or DRAM Chip to avoid memory interleaving interference, and triggers the PIM operation unit to perform calculation.

7. The PIM-DRAM for a compatible computing system of claim 6, wherein, The PIM-Local address configurator distinguishes PIM task data from main system data by marking PIM task data with a label or metadata to distinguish PIM task data from main system data.

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