Method, medium, device and product for data transmission

Abstract

The present application discloses a method, medium, device and product for data transmission, relating to the technical field of non-volatile memory host controller interface. The method includes determining the acquisition order of multiple DMA descriptors according to different priorities and descriptor acquisition times when multiple DMA engines are enabled. The descriptors corresponding to the DMA engine with the first priority are acquired before the descriptors corresponding to the DMA engines with other priorities. When the number of times the descriptors corresponding to the DMA engine with the second priority are acquired exceeds a preset first number, the DMA engine with the second priority is temporarily skipped and the descriptors corresponding to the DMA engine with the third priority are acquired. The actual data transmission is performed according to the descriptor sequence determined by the acquisition order. This solves the problem that the acquisition of DMA descriptors by polling may cause increased data transmission delay, and achieves the effect of giving priority to the transmission of key data.

Description

Technical Field

[0001] The present application relates to the technical field of non-volatile memory host controller interface, and in particular to methods, media, devices and products for data transmission. Background Art

[0002] In modern computer systems, NVMe controllers manage data transfers between non-volatile storage devices and the host system. DMA technology plays a crucial role in this process. To improve data transfer efficiency, NVMe controllers may have one or more built-in DMA engines.

[0003] In the related art, a polling method is generally used to obtain DMA descriptors. This means that when there are multiple DMA requests, even if some tasks have high priority, they need to wait for processing in the polling order, which may increase data transmission delay. Summary of the Invention

[0004] The present application provides a method, medium, device and product for data transmission, in order to at least solve the problem in the related art that a polling method is used to obtain DMA descriptors. When there are multiple DMA requests, even if some tasks have high priority, they need to wait for processing in the polling order, which may lead to increased data transmission delay.

[0005] The present application provides a method for data transmission, comprising: when multiple direct memory access engines are enabled based on a transfer instruction, determining an acquisition order for acquiring direct memory access descriptors based on the priorities of the direct memory access engines; wherein the descriptors corresponding to the direct memory access engines configured with a first priority are acquired before the descriptors corresponding to the direct memory access engines configured with other priorities; if there is no descriptor corresponding to the direct memory access engine of the first priority, acquiring the descriptors corresponding to the direct memory access engine of the second priority; if the number of times the descriptors corresponding to the direct memory access engine of the second priority are acquired is greater than a preset first number, acquiring the descriptors corresponding to the direct memory access engine of the third priority; and performing data transmission based on the acquisition order.

[0006] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above methods for data transmission when executing the computer program.

[0007] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above methods for data transmission are implemented.

[0008] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above methods for data transmission when executed by a processor.

[0009] Through the present application, when multiple DMA engines are enabled, the acquisition order of multiple DMA descriptors is determined according to different priorities and descriptor acquisition times. The descriptors corresponding to the DMA engine of the first priority are acquired before the descriptors corresponding to the DMA engines of other priorities. When the number of times the descriptors corresponding to the DMA engine of the second priority are acquired exceeds the preset first number, the DMA engine of the second priority is temporarily skipped and the descriptors corresponding to the DMA engine of the third priority are acquired. The actual data transmission is performed according to the descriptor sequence determined by the above acquisition order. Therefore, the problem in the related art that DMA descriptors are acquired in a polling manner and that, when there are multiple DMA requests, even if some tasks have high priorities, need to wait for processing in the polling order, which may cause increased data transmission delays, can be solved. The effect of multiple DMA engines working in parallel, fully utilizing hardware resources, and ensuring that the transmission of critical data is completed first based on the priority mechanism can be achieved. At the same time, the resource allocation between tasks of different priorities can be balanced. By presetting the first number, low-priority tasks can be prevented from not being executed for a long time. In addition, high-priority tasks can be responded to quickly, which is suitable for application scenarios that are sensitive to delays. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 A schematic diagram of the application environment architecture of the method for data transmission provided by the present application is shown;

[0012] Figure 2 A schematic diagram showing a flow chart of a method for data transmission provided by the present application is shown;

[0013] Figure 3 A flow chart showing the order of obtaining direct memory access descriptors;

[0014] Figure 4 A schematic diagram showing a flow chart of a DMA engine processing a first instruction according to an embodiment of the present application is shown;

[0015] Figure 5 A schematic structural diagram of a device for data transmission according to an embodiment of the present application is shown;

[0016] Figure 6 A schematic structural diagram of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0018] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0019] The following is an introduction to the concepts involved in this application. The Non-Volatile Memory Express (NVMe) host controller interface specification is a technical standard for managing data transmission between non-volatile storage devices, such as solid-state drives, and host systems. NVMe defines a set of instruction sets and interface specifications that significantly improve data transmission speed and efficiency and reduce latency compared to traditional storage interfaces. In modern computer systems, the NVMe controller is responsible for coordinating the interaction between non-volatile storage devices and host systems in accordance with this standard and is a key component for achieving efficient data storage and reading.

[0020] The Central Processing Unit (CPU) is the core component of a computer, also known as the brain of the computer. The CPU is responsible for executing instructions in computer programs and performing various data operations and logical judgments. During the data transmission process, traditional data transmission methods require the CPU to frequently participate in operations such as reading data from storage devices and then transferring it to memory. However, this consumes a large amount of CPU resources and affects the efficiency of the CPU in handling other tasks. The emergence of technologies such as direct memory access is intended to reduce the CPU's burden on data transmission, allowing the CPU to focus more on complex calculations and logical processing.

[0021] Direct Memory Access (DMA) is a technology that allows external devices (such as hard drives or network cards) to exchange data directly with system memory. A DMA controller is a unique peripheral device that transfers data within the system. It can be thought of as a controller that connects internal and external memory to each DMA-capable peripheral device through a set of dedicated buses.

[0022] In this way, during the data interaction process, there is no need for frequent CPU intervention. The DMA controller can autonomously transfer data directly to the memory or read data from the memory, which can reduce CPU overhead and significantly improve the data transmission efficiency of NVMe devices.

[0023] To improve data transfer efficiency, the NVMe controller may have one or more embedded DMA engines. Based on the host's instructions, the firmware can configure the DMA engine descriptor address through registers and prepare the DMA engine descriptor or a linked list of DMA engine descriptors in local memory. The DMA engine first obtains the DMA engine descriptor and then performs data transfer based on the information described in the DMA engine descriptor.

[0024] For NVMe controller architectures involving multiple DMA engines, multiple DMA engines can access common resources, such as the cache used by the NVMe controller to interact with the host, or the cache used by the NVMe controller to interact with local memory. When an NVMe controller architecture involving multiple DMA engines is enabled, arbitration is usually required. Common arbitration methods include round-robin arbitration and weighted round-robin arbitration, and priority can be configured through firmware. Each DMA engine can execute tasks issued by the host based on priority order and DMA engine descriptor instructions.

[0025] However, in the related art, the following problems exist in the DMA data transmission mechanism in the NVMe controller, which may affect the overall performance of data transmission and the immediacy of data processing.

[0026] First, in related technologies, polling is generally used to obtain DMA descriptors. This means that when there are multiple DMA requests, even if some tasks have high priority, they need to wait for processing in the polling order, which may increase data transmission delays, especially when the bus task is busy or stuck, which will greatly affect data transmission efficiency.

[0027] Second, when the NVMe controller processes a large number of host commands, after parsing the host commands, the firmware will configure the DMA descriptor list based on the commands and place the configured DMA descriptor list in local memory. The processing of specific commands, especially read and write commands, generally takes a long time, and there are multiple commands that need to queue up and wait for the assigned DMA engine to process. At the same time, in the case of an urgent command, the DMA engine needs to wait until the current DMA descriptor list is executed before processing the urgent command, resulting in a slow response speed of the NVMe controller to the urgent command, which will also affect the real-time performance and reliability of the system.

[0028] Third, the NVMe controller can execute and read the commands / data sent by the host through the host interaction common port or the local interaction common port, return data / completion information after the reading is completed, read local DMA descriptors / data, or write local data / descriptors, etc. The aforementioned common port will adopt a polling method when arbitrating multiple requests, so that all transmission requests are treated equally. However, in actual applications, different tasks may have different importance and timeliness requirements, and a simple polling method cannot meet diverse needs. In addition, although data / metadata and its pointer are output or read from the same port, they are divided into two ports when the common port is requested. The arbitration mechanism in the relevant technology does not fully consider this structural feature, which may lead to uneven data transmission and inefficiency.

[0029] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0030] Figure 1 The following is a schematic diagram showing an application environment architecture of the method for data transmission provided by the present application: Figure 1 As shown, the specific application environment architecture or specific hardware architecture on which the execution of the method for data transmission provided by the present application depends includes: a central processing unit 10, and a non-volatile memory host controller interface specification (Non-Volatile Memory Express, abbreviated as NVMe) controller 11 for data interaction with the central processing unit 10. Figure 1 The bidirectional arrows in the figure indicate that there are two data transmission paths. For example, the bidirectional arrows between the central processing unit 10 and the NVMe controller 11 indicate that there is a path for data transmission from the central processing unit 10 to the NVMe controller 11, and a path for data transmission from the NVMe controller 11 to the central processing unit 10.

[0031] The NVMe controller 11 includes a High-speed Advanced eXtensible Interface (AXI H) read interface 1101 for interacting with the host, a High-speed Advanced eXtensible Interface (AXI H) write interface 1102 for interacting with the host, a Memory-Mapped Advanced eXtensible Interface (AXI M) write interface 1103 for interacting with local memory, and a Memory-Mapped Advanced eXtensible Interface (AXI M) read interface 1104 for interacting with local memory.

[0032] The NVMe controller 11 exchanges data with the first bus 14 based on the AXI H read interface 1101 and the AXI H write interface 1102. The NVMe controller 11 also exchanges data with the second bus 15 based on the AXI M write interface 1103 and the AXI M read interface 1104.

[0033] The first bus 14 includes a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) 13 and a host 12. The second bus 15 includes a Double Data Rate SDRAM (DDR) 16.

[0034] The NVMe controller 11 further includes multiple embedded direct memory access engines, such as a first direct memory access (DMA) engine 1105, a second DMA engine 1106, and a third DMA engine 1107. The NVMe controller 11 further includes a submission queue management 1108 and a completion queue management 1109. The submission queue management 1108 is connected to the AXI H read interface 1101 and the AXI H write interface 1102, and the completion queue management 1109 is connected to the AXI H read interface 1101. It should be noted that in order to reduce Figure 1 The cross lines in Figure 1 The connection line between the submission queue management 1108 and the AXI H write interface 1102 is not labeled.

[0035] The NVMe controller 11 also includes a Direct Memory Access (DMA) descriptor acquisition module 1110. This module includes a first DMA engine enabling unit 1111, a second DMA engine enabling unit 1112, and a third DMA engine enabling unit 1113. The DMA descriptor acquisition module 1110 transmits the acquired DMA descriptors to the corresponding DMA engines. The DMA descriptor acquisition module 1110 is connected to the first DMA engine 1105, the second DMA engine 1106, and the third DMA engine 1107, respectively.

[0036] Each DMA engine also performs data transmission with the AXI H read interface 1101, the AXI H write interface 1102, the AXI M write interface 1103, and the AXI M read interface 1104. For example, the first DMA engine 1105 performs data transmission with the AXI H read interface 1101, the AXI H write interface 1102, the AXI M write interface 1103, and the AXI M read interface 1104. It should be noted that in order to reduce Figure 1 The cross lines in Figure 1 The connection lines between the second DMA engine 1106 and the AXI H read interface 1101, AXI H write interface 1102, AXI M write interface 1103, and AXI M read interface 1104 are not labeled. Similarly, the connection lines between the third DMA engine 1107 and the AXI H read interface 1101, AXI H write interface 1102, AXI M write interface 1103, and AXI M read interface 1104 are not labeled.

[0037] The embodiment of the present application provides a method for data transmission. Figure 2 FIG. 1 shows a flow chart of a method for data transmission provided by the present application. Figure 2 As shown, the method for data transmission includes:

[0038] Step S201, when multiple direct memory access engines are enabled based on a transfer instruction, determining an order for obtaining direct memory access descriptors based on the priorities of the direct memory access engines; wherein the descriptors corresponding to the direct memory access engines configured with the first priority are obtained before the descriptors corresponding to the direct memory access engines configured with other priorities; if there is no descriptor corresponding to the direct memory access engine of the first priority, the descriptors corresponding to the direct memory access engine of the second priority are obtained; if the number of times the descriptors corresponding to the direct memory access engine of the second priority are obtained is greater than a preset first number, the descriptors corresponding to the direct memory access engine of the third priority are obtained.

[0039] In this step, the NVMe controller embeds multiple DMA engines, and the NVMe controller processes data transfer commands and other commands issued by the host. The NVMe controller's processing flow includes the NVMe controller transparently passing the host's commands to the firmware through an interface that interacts with the firmware. After the firmware parses the command, it combines the DMA descriptors obtained based on the command parsing to form a DMA descriptor linked list, which is then stored in a specific area of local memory.

[0040] The firmware configures the corresponding DMA engine control registers to enable the DMA engine. On the hardware side, once the DMA is enabled, it reads the descriptor according to the previously configured DMA descriptor address and executes the corresponding command. It is important to note that when the NVMe controller is initialized, the firmware notifies the NVMe controller of the address of the DMA descriptor (or linked list) by configuring the DMA descriptor address register.

[0041] Transfer instructions are used to represent data transfer commands that require direct access to host memory. The order in which DMA descriptors are retrieved is determined by the configured DMA engine priority. If the first-priority DMA engine is enabled, the descriptors corresponding to the first-priority DMA engine are retrieved first. If no first-priority DMA engine is enabled, or if all descriptors corresponding to the first-priority DMA engine have been executed, the descriptors corresponding to the second-priority DMA engine are retrieved.

[0042] If no second-priority DMA engine is enabled, or the number of times the descriptor corresponding to the second-priority DMA engine is obtained is greater than the preset first number, the descriptor corresponding to the third-priority direct memory access engine is obtained.

[0043] Step S202: Data transmission is performed based on the acquisition order.

[0044] In this step, if the DMA engine of the first priority is enabled, the descriptor corresponding to the DMA engine of the first priority is obtained first, and data transmission is performed based on the descriptor corresponding to the DMA engine of the first priority.

[0045] If no DMA engine of the first priority is enabled, or all descriptors corresponding to the DMA engine of the first priority are executed, the descriptors corresponding to the DMA engine of the second priority are obtained, and data transmission is performed based on the descriptors corresponding to the DMA engine of the second priority.

[0046] If no second-priority DMA engine is enabled, or the number of times the descriptor corresponding to the second-priority DMA engine is obtained is greater than the preset first number, the descriptor corresponding to the third-priority direct memory access engine is obtained, and data transmission is performed based on the descriptor corresponding to the third-priority direct memory access engine.

[0047] Through the present application, since a priority is assigned to each DMA engine when at least one DMA engine is enabled, the acquisition order of multiple DMA descriptors is determined according to different priorities and the number of descriptor acquisitions. When the descriptor corresponding to the second-priority DMA engine is acquired and exceeds the preset first number, the second-priority DMA engine will be temporarily skipped, and the descriptor corresponding to the third-priority DMA engine will be acquired, and actual data transmission will be performed according to the descriptor sequence determined by the above acquisition order. Therefore, the problem in the related art that DMA descriptors are acquired in a polling manner and that, in the presence of multiple DMA requests, even if some tasks have high priority, they need to wait for processing in a polling order, which may cause increased data transmission delays, can be solved. The effect of multiple DMA engines working in parallel, fully utilizing hardware resources, and ensuring that the transmission of critical data is completed first based on the priority mechanism can be achieved. At the same time, the resource allocation between tasks of different priorities can be balanced. By presetting the first number, low-priority tasks can be prevented from not being executed for a long time. In addition, high-priority tasks can be responded to quickly, which is suitable for application scenarios that are sensitive to delays.

[0048] In some optional embodiments, the aforementioned method for data transmission further includes: configuring priorities, and an acquisition order corresponding to each priority; configuring the priorities to include a first priority, a second priority, and a third priority, wherein the descriptor corresponding to the direct memory access engine of the first priority is acquired before the descriptors corresponding to the direct memory access engines of other priorities.

[0049] In this embodiment, the priority of each DMA engine can be configured based on registers. By configuring the priority of the DMA engine, when multiple DMA engines are working simultaneously, arbitration is performed based on the DMA engine priority before obtaining common resources. The common resources here can be the cache used by the NVMe controller to interact with the host, or the cache used by the NVMe controller to interact with local memory, etc.

[0050] Specifically, a DMA descriptor control register can be added, and the priority of each DMA engine can be configured based on the DMA descriptor control register. The attributes of the DMA descriptor control register are readable and writable. The priority of the DMA engine can be represented based on the two-bit first field [1:0]. In the embodiment of the present application, the method for data transmission in the embodiment of the present application is exemplified using the two-bit first field. [1:0] is used to represent bit0 and bit1 in the first field. The first field can be configured to 00b, 01b, 10b or 11b, and b is used to represent binary.

[0051] If the first field corresponding to the target DMA engine is configured as 11b, the target DMA engine is a DMA engine of the first priority, indicating Urgent priority. If the first field corresponding to the target DMA engine is configured as 10b, the target DMA engine is a DMA engine of the second priority, indicating High priority. If the first field corresponding to the target DMA engine is configured as 01b, the target DMA engine is a DMA engine of the third priority, indicating Medium priority. If the first field corresponding to the target DMA engine is configured as 00b, the target DMA engine is a DMA engine of the fourth priority, indicating Low priority.

[0052] Among them, the first priority takes precedence over the second priority, the second priority takes precedence over the third priority, and the third priority takes precedence over the fourth priority, that is, the first priority is the highest priority in the current priority mechanism.

[0053] Priority status signals can be added, including the first priority state (urgent_state), the second priority state (high_state), the third priority state (medium_state), and the fourth priority state (low_state). The bit width of the priority status signal is equal to the number of DMA engines embedded in the NVMe controller, and the reset value is zero. The priority of each DMA engine can be characterized based on the priority status signal. For example, if the priority of DMA0 is configured as 11b, that is, the first (urgent) priority, the bit corresponding to the first priority state (urgent_state) of DMA0 is set high. If the priority of DMA1, DMA2, and DMA3 is configured as non-11b, the first priority state urgent_state signal corresponding to DMA3, DMA2, DMA1, and DMA0 is 0001b.

[0054] Similarly, if DMA1's priority is configured as 10b, the second (high) priority, and DMA0, DMA2, and DMA3's priorities are not configured as 10b, the high_state signals corresponding to the second priority state of DMA3, DMA2, DMA1, and DMA0 are 0010b. The firmware configures the DMA descriptor priority to be consistent with the DMA engine's priority, and the DMA descriptor acquisition module retrieves DMA descriptors from high to low priority.

[0055] Compared to the polling method used in related technologies, assigning the highest priority to the high-priority DMA engine ensures that critical tasks always receive descriptors first, meeting the low-latency requirements of hard real-time systems. Furthermore, different tasks can be assigned different priorities, enabling fine-grained control over task execution. Furthermore, strictly following the priority order of descriptors eliminates conflicts caused by multiple DMA engines accessing the descriptor list simultaneously.

[0056] In some optional embodiments, the aforementioned method for data transmission further includes: configuring preset weights for direct memory access engines of each target priority, the direct memory access engines of each target acquisition priority including direct memory access engines of the second priority and the third priority; based on the preset weights, after characterizing the descriptors corresponding to the direct memory access engines of the target priority acquired a preset number of times, acquiring the descriptors corresponding to the direct memory access engines of the next priority level of the target priority.

[0057] In this embodiment, the preset weight of the DMA engine of each target priority can be configured based on a register. A DMA weight register can be added, and the preset weight of the DMA engine of each target priority can be configured based on the DMA weight register. Since the DMA descriptor of the first priority is always obtained before the DMA descriptors of other priorities, the DMA engine of the target priority in this embodiment does not include the DMA engine of the first priority.

[0058] Specifically, the preset weight of the fourth priority level, i.e., the third preset number, can be represented based on bits [9:0] in the second field; the preset weight of the third priority level, i.e., the second preset number, can be represented based on bits [19:10] in the second field; and the preset weight of the second priority level, i.e., the first preset number, can be represented based on bits [29:20] in the second field. An independent counter can be configured for each priority level, and the counter starts counting from zero. When a DMA descriptor command of the target priority level is executed, the target priority counter performs an increment operation. If the count value of the target priority counter is equal to the preset weight of the target priority level minus one, the count value of the target priority counter is reset to zero. Bits [31:30] in the second field are reserved.

[0059] This allows for precise bandwidth control of non-critical tasks by configuring weights for DMA engines at all priorities except the first. Furthermore, by enforcing that requests at the next priority level below the target must be processed after a predetermined number of acquisitions, as represented by a predetermined weight, complete blocking of low-priority tasks can be avoided.

[0060] In some optional embodiments, based on the priority of each direct memory access engine, the order of obtaining direct memory access descriptors is determined, and data transmission based on the order includes: determining whether there is a direct memory access engine with a first priority among the enabled direct memory access engines; if there is a direct memory access engine with a first priority, obtaining the descriptor of the direct memory access engine with the first priority, and performing data transmission based on the descriptor of the direct memory access engine with the first priority.

[0061] In this embodiment, the enable status of the priority status signal is continuously monitored. If the first-priority DMA engine is enabled, the descriptor corresponding to the first-priority DMA engine is selected. An interface for configuring the priority and weight values of DMA descriptors can be provided in the firmware. During system startup or operation, the priority and weight values obtained by each DMA descriptor can be flexibly configured based on actual needs through this interface to ensure that the hardware can arbitrate according to the set rules.

[0062] In this way, the first-priority DMA descriptor acquisition delay is low, which can meet the industrial real-time requirements. When the bus task is busy, the first-priority DMA task can be processed first, reducing data transmission delay.

[0063] In some optional embodiments, based on the priority of each direct memory access engine, determining the order of obtaining direct memory access descriptors, and performing data transmission based on the order further includes: determining whether there is a direct memory access engine of the first priority among the enabled direct memory access engines; if there is no direct memory access engine of the first priority, determining whether there is a direct memory access engine of the second priority among the enabled direct memory access engines; if there is a direct memory access engine of the second priority, determining whether the number of times descriptors corresponding to the direct memory access engine of the second priority are obtained is greater than a preset first number; if the number of times descriptors corresponding to the direct memory access engine of the second priority are obtained is less than or equal to the preset first number, obtaining the descriptors corresponding to the direct memory access engine of the target number among the direct memory access engines of the second priority, performing data transmission based on the descriptors corresponding to the direct memory access engine of the target number, and increasing the number of times descriptors corresponding to the direct memory access engine of the second priority by one.

[0064] Figure 3 FIG. 1 shows a flow chart of the order of obtaining direct memory access descriptors. Figure 3 As shown, in this embodiment, the process of obtaining the order of DMA descriptors includes:

[0065] Step S301, determine whether any direct memory access engine is enabled, if not enabled, go to step S301, if there is an enabled DMA engine, go to step S302.

[0066] Step S302, determine whether to perform weighted polling arbitration, if not, go to step S303, if yes, go to step S304, specifically, weighted polling arbitration is to determine the order of obtaining direct memory access descriptors based on the priority of each direct memory access engine.

[0067] Step S303: determining the order of obtaining direct memory access descriptors by polling.

[0068] Step S304 , determining whether there is a first-priority DMA engine among the enabled DMA engines, if so, proceeding to step S305 , if not, proceeding to step S306 .

[0069] Step S305 , polling the arbitration first-priority direct memory access engine, determining the first-priority direct memory access engine with the target number, and then proceeding to step S304 .

[0070] Specifically, if there is only one direct memory access engine of the first priority, the direct memory access engine of the first priority is selected, and based on the direct memory access descriptor acquisition module, the descriptor corresponding to the direct memory access engine of the first priority is obtained; if there are multiple direct memory access engines of the first priority, the multiple direct memory access engines of the first priority are polled, and the direct memory access engine of the first priority with a target number is determined among the multiple direct memory access engines of the first priority, the descriptor corresponding to the direct memory access engine of the first priority with the target number is obtained, and the pointer is pointed to the direct memory access engine of the first priority with the next number, wherein the target number is used to represent the direct memory access engine with the smallest number or the direct memory access engine with the largest number among the multiple direct memory access engines.

[0071] Step S306 , determining whether there is a second priority DMA engine among the enabled DMA engines; if so, proceeding to step S307 ; if not, proceeding to step S308 .

[0072] Step S307 , determining whether the number of times the descriptor corresponding to the second priority direct memory access engine is obtained is greater than the preset first number, if so, proceeding to step S308 , if not, proceeding to step S309 .

[0073] Step S308 , determining whether there is a third priority DMA engine among the enabled DMA engines; if so, proceed to step S310 ; if not, proceed to step S311 .

[0074] Step S309: poll the arbitration second-priority DMA engine, determine the second-priority DMA engine with the target number, and then go to step S304.

[0075] Specifically, if there is only one direct memory access engine of the second priority, the direct memory access engine of the second priority is selected, and based on the direct memory access descriptor acquisition module, the descriptor corresponding to the direct memory access engine of the second priority is obtained; if there are multiple direct memory access engines of the second priority, the multiple direct memory access engines of the second priority are polled, and the direct memory access engine of the second priority with a target number is determined among the multiple direct memory access engines of the second priority, and the descriptor corresponding to the direct memory access engine of the second priority with the target number is obtained, and the number of times the descriptor corresponding to the direct memory access engine of the second priority is obtained is increased by one.

[0076] Step S310 , determining whether the number of times the descriptor corresponding to the third priority direct memory access engine is obtained is greater than a preset second number, if so, proceeding to step S311 , if not, proceeding to step S312 .

[0077] Step S311, determining whether there is a fourth priority direct memory access engine among the enabled direct memory access engines; if so, proceeding to step S313; if not, proceeding to step S304.

[0078] Step S312: poll the DMA engines with the third priority in arbitration, determine the DMA engine with the third priority of the target number, and then go to step S304.

[0079] Specifically, if there is only one direct memory access engine of the third priority, the direct memory access engine of the third priority is selected, and based on the direct memory access descriptor acquisition module, the descriptor corresponding to the direct memory access engine of the third priority is obtained; if there are multiple direct memory access engines of the third priority, the multiple direct memory access engines of the third priority are polled, and the direct memory access engine of the third priority with a target number is determined among the multiple direct memory access engines of the third priority, and the descriptor corresponding to the direct memory access engine of the third priority with the target number is obtained, and the number of times the descriptor corresponding to the direct memory access engine of the third priority is obtained is increased by one.

[0080] Step S313, determining whether the number of times the descriptor corresponding to the fourth priority direct memory access engine is obtained is greater than the preset third number, if so, proceeding to step S304, if not, proceeding to step S314.

[0081] Step S314: poll the DMA engines with the fourth priority in arbitration, determine the DMA engine with the fourth priority of the target number, and then go to step S304.

[0082] Specifically, if there is only one direct memory access engine of the fourth priority, the direct memory access engine of the fourth priority is selected, and based on the direct memory access descriptor acquisition module, the descriptor corresponding to the direct memory access engine of the fourth priority is obtained; if there are multiple direct memory access engines of the fourth priority, the multiple direct memory access engines of the fourth priority are polled, and the direct memory access engine of the fourth priority with a target number is determined among the multiple direct memory access engines of the fourth priority, and the descriptor corresponding to the direct memory access engine of the fourth priority with a target number is obtained, and the number of times the descriptor corresponding to the direct memory access engine of the fourth priority is obtained is increased by one.

[0083] Among them, if there are multiple descriptors for each DMA with the same priority, they are polled and selected once in order of number from small to large or from large to small, and then the remaining DMA descriptors are selected.

[0084] In this way, a multi-level priority mechanism is adopted to ensure that high-priority tasks can always seize bandwidth, which can reduce the delay of high-priority tasks. Dynamic fairness control is performed by presetting weights. When the second priority continuously obtains more than the preset first number of descriptors, the bus is forcibly released to the third priority to ensure system-level fairness.

[0085] In some optional embodiments, the aforementioned method for data transmission further includes: obtaining a first instruction, and configuring a first descriptor corresponding to a target direct memory access engine based on the first instruction, wherein the first instruction is executed before the transmission instruction; determining whether there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine being executed in the target direct memory access engine; if there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine being executed, determining whether the descriptor corresponding to the direct memory access engine being executed is the last descriptor in the transmission instruction; if it is the last descriptor in the transmission instruction, or if there is no transmission instruction for obtaining a descriptor corresponding to the direct memory access engine being executed, obtaining the first descriptor corresponding to the target direct memory access engine and performing data transmission.

[0086] In this implementation, an emergency command, such as an emergency termination or firmware commit command, is represented by a first instruction. An emergency command control register (emergency_cmd_ctrl), a first descriptor address register, and first instruction processing logic can be added to the hardware. The firmware receives multiple first instructions representing emergency commands and configures a first descriptor (E-DMA) corresponding to the DMA engine for each first instruction, obtaining a first descriptor linked list. The first descriptor linked list can be placed at the first descriptor address, and the firmware maintains the first descriptor (E-DMA) linked list.

[0087] In the emergency command control register, bit [0] indicates the first instruction processing phase when it is set high, and bits [31:1] indicate the number of first instructions to be processed. The number of emergency command control registers is the same as the number of DMA engines.

[0088] The first descriptor address register is used to represent the address where the first instruction descriptor is placed and can be configured when the NVMe controller is initialized. The number of first descriptor address registers is the same as the number of DMA engines.

[0089] The first instruction processing logic includes a first signal, a second signal, a third signal, and a fourth signal. The first signal (emergency_cmd_flag) indicates whether there is a first instruction to be processed, the second signal (emergency_cmd_cnt) indicates the number of first instructions currently being processed, the third signal (dma_desc_pending_addr) stores the address of the descriptor to be executed in the interrupted DMA linked list, and the fourth signal (dma_desc_pending_flag) indicates the presence of a pending DMA command.

[0090] Figure 4 FIG. 4 shows a flow chart of the DMA engine processing the first instruction according to an embodiment of the present application. Figure 4 As shown, the process of the DMA engine processing the first instruction includes:

[0091] Step S401: The firmware receives a plurality of first instructions representing emergency commands.

[0092] Step S402: selecting a target direct memory access engine to process the first instruction.

[0093] Step S403: configure the first descriptor linked list, and place the first descriptor linked list at the address of the first descriptor linked list corresponding to the target direct memory access engine.

[0094] Step S404 , configuring bit 0 of the emergency command control register to be 1, configuring bits 1 to 31 of the emergency command control register to represent the number of emergency commands in step S401 , and enabling the target direct memory access engine.

[0095] Step S405: configure the first signal of the target direct memory access engine to be in an enabled state.

[0096] Specifically, when the hardware senses that bit [0] of the emergency command control register (emergency_cmd_ctrl) is set high, the first signal (emergency_cmd_flag) is pulled high.

[0097] Step S406, determining whether there is a transfer instruction being executed in the target direct memory access engine, if yes, proceeding to step S407, if not, proceeding to step S408.

[0098] Step S407, wait for the transmission instruction being executed to be completed, and go to step S409.

[0099] Step S408, the pointer for obtaining the descriptor address is pointed to the first descriptor address, and the process goes to step S411.

[0100] Step S409, determine whether the end field of the transfer instruction being executed is zero, if it is zero, go to step S410, if not zero, go to step S408.

[0101] Specifically, if the target DMA engine has a command in the configuration DMA descriptor linked list being executed, determine whether the end field (end of chain, abbreviated as EOC) in the descriptor corresponding to the target DMA engine is zero, where the EOC field in each DMA descriptor in the linked list indicates whether the descriptor is the last descriptor in the DMA descriptor linked list. If it is zero, that is, the transfer instruction being executed is not the last command in the configuration DMA descriptor linked list; if it is one, that is, the transfer instruction being executed is the last command in the configuration DMA descriptor linked list.

[0102] Step S410: store the address of the next direct memory access descriptor in the direct memory access descriptor linked list into the third signal register, and then go to step S408.

[0103] Specifically, the target DMA engine suspends the command in the configuration DMA descriptor linked list being executed, stores the address of the next direct memory access descriptor in the direct memory access descriptor linked list into the dma_desc_pending_addr register, and pulls up the dma_desc_pending_flag signal.

[0104] Step S411, execute the first instruction, and go to step S412.

[0105] Specifically, the target DMA engine preferentially obtains the descriptor in the E-DMA linked list and executes the emergency task represented by the first instruction. After each execution, emergency_cmd_cnt performs an increment operation until the [31:1] field value indicated by the emergency_cmd_ctrl register reaches -1, indicating that all emergency tasks are completed.

[0106] Step S412: After the execution of the first instruction is completed, the transmission instruction indicated by the previously interrupted descriptor linked list is continued to be executed.

[0107] Specifically, the descriptor is obtained from the address indicated by the dma_desc_pending_addr register, and the command in the descriptor linked list that was previously interrupted is continued to be processed, while the dma_desc_pending_flag signal is pulled low at the same time.

[0108] In this way, by designing a special emergency command processing mechanism, adding emergency command control registers, E-DMA descriptor address registers and corresponding processing logic, it is ensured that when an emergency command arrives, the current task can be quickly suspended and the emergency command can be processed first. After the processing is completed, the original task can be seamlessly restored, which greatly enhances the system's responsiveness and real-time performance to emergency commands.

[0109] In some optional embodiments, configuring the first descriptor corresponding to the target direct memory access engine includes any of the following methods: if there are multiple priorities in the direct memory access engine, determining the direct memory access engine with the highest priority as the target direct memory access engine, and allocating the first descriptor to the direct memory access engine with the highest priority; if the direct memory access engines have the same priority, determining any one of the direct memory access engines as the target direct memory access engine, and allocating the first descriptor to the target direct memory access engine.

[0110] In this embodiment, when assigning urgent commands, if multiple DMA engines have different priorities, the urgent task can be preferentially assigned to the DMA engine with the highest priority, and the DMA engine with the highest priority can be used as the target DMA engine. If all DMA engines have the same priority, a DMA engine can be randomly selected to execute the urgent task, for example, DMA0 can be selected as the target DMA engine to execute the urgent task.

[0111] In this way, through reasonable scheduling of the DMA engine, the waste of hardware resources can be reduced and the processing flexibility of the urgent task represented by the first instruction can be improved.

[0112] In some optional embodiments, configuring the first descriptor corresponding to the target direct memory access engine also includes, if a dynamic direct memory access engine exists in the direct memory access engines, determining the dynamic direct memory access engine as the target direct memory access engine, and if a first instruction exists, allocating the first descriptor to the dynamic direct memory access engine; if the first instruction does not exist, enabling the dynamic direct memory access engine based on the transfer instruction.

[0113] In this embodiment, the DMA engine embedded in the NVMe controller is divided into a normal DMA engine (N-DMA) and a dynamic DMA engine (D-DMA). The D-DMA is used to process normal transfer instructions and the first instruction. If the first instruction is not available, it functions as the N-DMA. If the first instruction is available, it is prioritized. The dynamic DMA engine can be identified by a preset bit in the hardware status register.

[0114] In this way, the normal descriptors and the first descriptor corresponding to the dynamic DMA engine share the descriptor storage area, which can reduce memory usage and improve hardware resource utilization. Based on the first instruction, the dynamic DMA engine parameters can be dynamically reconfigured, such as the burst address increment, which can improve the system's flexible configuration capabilities.

[0115] In some optional embodiments, the aforementioned method for data transmission further includes: if the descriptor corresponding to the direct memory access engine being executed is not the last descriptor in the transfer instruction, interrupting the execution of the transfer instruction, and storing the descriptor corresponding to the next direct memory access engine in the sequence to a preset location; obtaining the first descriptor corresponding to the target direct memory access engine and performing data transmission; after the execution of the first descriptor corresponding to the first instruction is completed, reading the descriptor corresponding to the next direct memory access engine in the sequence from the preset location and continuing the execution of the transfer instruction.

[0116] In this embodiment, the end field of the descriptor list can be detected in real time through a hardware comparator. When it is determined that the descriptor corresponding to the direct memory access engine being executed is not the last descriptor in the transfer instruction, an interrupt of the executing task is triggered, and the next descriptor can be pre-stored in a preset cache area.

[0117] Emergency command processing logic is added to each DMA engine circuit. This circuit monitors the status of the emergency_cmd_ctrl register. When an emergency command is detected, it follows the established processing flow to pause the executing task, retrieve the E-DMA descriptor list, and resume subsequent tasks. A dedicated address register circuit is also designed to store the dma_desc_pending_addr register and the E-DMA descriptor address.

[0118] In this way, the processing mechanism of the emergency command represented by the first instruction ensures that the system can respond quickly and process the emergency command with priority when faced with an emergency command, thereby improving the real-time performance and reliability of the system.

[0119] The common bus port is used to arbitrate multiple requests from the NVMe controller. For example, the AXI read port, which interfaces with the host, handles requests such as fetch submission queue command requests, fetch submission queue command address requests, DMA read data requests, DMA read metadata requests, DMA read data address requests, DMA read metadata address requests, and fetch completion queue address requests. Polling ensures that all transfer requests are treated equally. However, in real applications, different tasks may have varying importance and timeliness requirements, and a simple polling approach cannot meet these diverse needs.

[0120] In some optional embodiments, the aforementioned method for data transmission also includes: determining a preset request weight corresponding to the request type based on the request type of the transmission instruction; determining the next transmission instruction for data transmission based on the preset request weight and the number of transmissions of the transmission instructions of each request type; if the transmission instruction corresponding to the transmission target request type is greater than the preset number of transmissions, determining the next transmission instruction for data transmission based on the transmission instructions corresponding to other request types.

[0121] In this embodiment, a preset request weight can be assigned to each request type of a transmission instruction. The first request type is used to represent high-priority requests with high timeliness requirements; the second request type is used to represent medium-priority requests with large data volumes; and the third request type is used to represent low-priority requests with lower timeliness requirements.

[0122] Specifically, the public port module arbitration process includes: when the system is initialized, an initial preset request weight is configured for each request type and a weight counter is initialized; the arbitrator selects the next request to be processed based on the weight value and counter status of each request type based on a weighted polling algorithm. The higher the weight value, the greater the probability of being selected; when a request of a certain request type is selected and processed, its corresponding counter is incremented by 1. When the counter reaches the weight value, the counter returns to zero and the priority of the request type is reduced.

[0123] This changes the arbitration method used in the AXI transmission module in related technologies from simple round-robin arbitration to weighted round-robin arbitration, assigning different weights to different requests. By flexibly setting weights based on factors such as the importance, timeliness, and data volume of each request, high-priority requests receive more transmission opportunities during arbitration, thereby improving overall data transmission efficiency.

[0124] In some optional embodiments, the aforementioned method for data transmission also includes: configuring a preset request weight corresponding to the request type; configuring the preset request weight corresponding to the first request type as a first preset number of transmissions; configuring the preset request weight corresponding to the second request type as a second preset number of transmissions; based on the preset request weight, after the transmission instruction corresponding to the transmission target request type is greater than the preset number of transmissions, determining the next transmission instruction for data transmission among the transmission instructions corresponding to other request types.

[0125] In this embodiment, a first preset request weight can be configured for a transmission instruction of the first request type, a second preset request weight can be configured for a transmission instruction of the second request type, and a third preset request weight can be configured for a transmission instruction of the third request type. A separate weight counter can be set for each request type. When the counter for a request type reaches its weight value, the priority of that request type is lowered, and other request types are given arbitration opportunities.

[0126] Specifically, the preset request weight for a submit queue command request can be configured as a first preset number of transmissions; the preset request weight for a DMA read data request or a DMA read metadata request can be configured as a second preset number of transmissions; and the preset request weight for a completion queue address request can be configured as a third preset number of transmissions. The first preset number of transmissions is greater than the second preset number of transmissions, and the second preset number of transmissions is greater than the third preset number of transmissions. For example, the first preset number of transmissions can be set to 5, the second preset number of transmissions can be set to 3, and the third preset number of transmissions can be set to 2.

[0127] This prevents a single request type from monopolizing the bus and ensures fairness in the execution of each request.

[0128] In some optional embodiments, the aforementioned method for data transmission also includes: adjusting the preset request weight corresponding to the request type; if the request response time of the transmission instruction of the target request type is greater than the preset time threshold, increasing the preset request weight corresponding to the target request type.

[0129] In this embodiment, the preset request weights can be dynamically adjusted based on factors such as the importance, timeliness, and data volume of the request. The weight values of each request type can also be dynamically adjusted based on the real-time load of the system and the execution status of the task.

[0130] Specifically, when the system detects that the response time of a command request submitted to the queue exceeds a preset threshold, it can temporarily increase its weight value and pass the new weight value to the hardware weight register to implement dynamic weight adjustment to ensure that it can obtain arbitration opportunities first.

[0131] In this way, high-priority requests can be guaranteed to obtain arbitration opportunities in a timely manner.

[0132] In related technologies, each DMA engine needs two request ports to obtain data, metadata, data address or metadata address, which greatly prolongs the arbitration time of the common port, especially when there are a large number of DMA engines.

[0133] In some optional embodiments, the aforementioned method for data transmission further includes: merging an instruction for transmitting target data and an instruction for transmitting a storage address of the target data into a target data transmission instruction; and enabling a direct memory access engine based on the target data transmission instruction to perform data transmission.

[0134] In this embodiment, compliant instruction encoding can be used to implement an instruction fusion architecture. The hardware execution process includes an instruction decoding phase, an address generation phase, and a transfer trigger phase. During the instruction decoding phase, opcode verification and address alignment checks can be completed within a preset clock cycle based on dedicated hardwired logic.

[0135] This can reduce the arbitration time of the public port, improve data transmission efficiency and hardware resource utilization efficiency. At the same time, a reasonable scheduling mechanism makes full use of hardware resources and reduces resource waste.

[0136] In some optional implementations, the firmware, as a key part of controlling hardware behavior, needs to implement and optimize corresponding functions.

[0137] The firmware provides an interface for configuring DMA descriptor priorities and weights. During system startup or operation, this interface allows you to flexibly configure the priorities and weights of each DMA descriptor based on actual needs, ensuring that the hardware can arbitrate according to the set rules.

[0138] For emergency command processing, the firmware is responsible for maintaining information related to emergency commands, such as creating and managing a linked list of E-DMA descriptors. When an emergency command is detected, the firmware immediately configures DMA descriptors for it, forms a linked list of E-DMA descriptors, and places the linked list at the specified E-DMA descriptor address. Furthermore, the firmware interacts with the hardware, notifying it of the emergency command by setting the emergency_cmd_ctrl register and other operations.

[0139] In the public port module arbitration mechanism, the firmware is responsible for dynamically adjusting the weights of various request types based on the system's real-time load and task execution. For example, by monitoring parameters such as the response time of queued command requests, if the response time exceeds a preset threshold, the firmware promptly increases the weight and transmits the new weight to the hardware weight register, achieving dynamic weight adjustment.

[0140] In some optional implementations, at the hardware level, with respect to the aforementioned DMA descriptor acquisition arbitration mechanism, urgent command processing, and common port module arbitration mechanism, the DMA descriptor acquisition arbitration mechanism: The priority signals (urgent_state, high_state, medium_state, low_state) of each DMA engine are connected to an arbitration circuit. The arbitration circuit generates a selection signal based on the priority and weight value to determine which DMA descriptor to acquire next.

[0141] To handle emergency commands, an emergency command processing logic circuit is added to each DMA engine circuit. This circuit monitors the status of the emergency_cmd_ctrl register. When an emergency command is detected, it follows the established processing flow to pause the executing task, retrieve the E-DMA descriptor list, and resume subsequent tasks. A dedicated address register circuit is also designed to store the dma_desc_pending_addr register and the E-DMA descriptor address.

[0142] For the common port module arbitration mechanism, an independent weight register and a counter register are set for each request type. The arbitration circuit selects the next request to be processed based on the values of these registers and the weighted polling algorithm.

[0143] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0144] The embodiment of the present application also provides a device for data transmission, Figure 5 FIG. 1 shows a schematic diagram of a structure of a device for data transmission according to an embodiment of the present application. Figure 5 As shown, the apparatus for data transmission includes: a descriptor sequence acquisition module 501, which is used to determine the acquisition order of direct memory access descriptors based on the priority of each direct memory access engine when multiple direct memory access engines are enabled based on a transfer instruction; wherein the descriptors corresponding to the direct memory access engine configured with the first priority are acquired before the descriptors corresponding to the direct memory access engines configured with other priorities; if there is no descriptor corresponding to the direct memory access engine of the first priority, the descriptors corresponding to the direct memory access engine of the second priority are acquired; if the number of times the descriptors corresponding to the direct memory access engine of the second priority are acquired is greater than a preset first number, the descriptors corresponding to the direct memory access engine of the third priority are acquired; and a transmission module 502, which is used to perform data transmission based on the acquisition order.

[0145] In some optional embodiments, the aforementioned device for data transmission also includes: a first configuration module, used to configure priorities, and the acquisition order corresponding to each priority; the priorities are configured to include a first priority, a second priority, and a third priority, wherein the descriptor corresponding to the direct memory access engine of the first priority is acquired before the descriptors corresponding to the direct memory access engines of other priorities.

[0146] In some optional embodiments, the aforementioned device for data transmission also includes: a second configuration module, used to configure preset weights of direct memory access engines of each target priority, and the direct memory access engines of each target priority include direct memory access engines of the second priority and direct memory access engines of the third priority; based on the preset weights, after representing the descriptors corresponding to the direct memory access engines of the target priority obtained a preset number of times, the descriptors corresponding to the direct memory access engines of the next priority level of the target priority are obtained.

[0147] In some optional embodiments, the descriptor sequence acquisition module includes: a first descriptor sequence acquisition unit, used to determine whether there is a first-priority direct memory access engine among the enabled direct memory access engines; if there is a first-priority direct memory access engine, obtain the descriptor of the first-priority direct memory access engine, and perform data transmission based on the descriptor of the first-priority direct memory access engine.

[0148] In some optional embodiments, the descriptor sequence acquisition module further includes: a second descriptor sequence acquisition unit, configured to determine whether there is a first-priority direct memory access engine among the enabled direct memory access engines; if there is no first-priority direct memory access engine, determine whether there is a second-priority direct memory access engine among the enabled direct memory access engines; if there is a second-priority direct memory access engine, determine whether the number of times descriptors corresponding to the second-priority direct memory access engine are acquired is greater than a preset first number; if the number of times descriptors corresponding to the second-priority direct memory access engine are acquired is less than or equal to the preset first number, acquire the descriptor corresponding to the target-numbered direct memory access engine among the second-priority direct memory access engines, perform data transmission based on the descriptor corresponding to the target-numbered direct memory access engine, and increase the number of times descriptors corresponding to the second-priority direct memory access engine are acquired by one.

[0149] In some optional embodiments, the aforementioned device for data transmission further includes: a first instruction execution module, configured to obtain a first instruction, and based on the first instruction, configure a first descriptor corresponding to the target direct memory access engine, wherein the first instruction is executed before the transmission instruction; determine whether there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine being executed in the target direct memory access engine; if there is a transmission instruction for obtaining a descriptor corresponding to the direct memory access engine being executed, determine whether the descriptor corresponding to the direct memory access engine being executed is the last descriptor in the transmission instruction; if it is the last descriptor in the transmission instruction, or if there is no transmission instruction for obtaining a descriptor corresponding to the direct memory access engine being executed, obtain the first descriptor corresponding to the target direct memory access engine and perform data transmission.

[0150] In some optional embodiments, the first instruction execution module includes: a first instruction execution configuration unit, configured to configure the first descriptor corresponding to the target direct memory access engine including any of the following methods: if there are multiple priorities in the direct memory access engine, determining the direct memory access engine with the highest priority as the target direct memory access engine, and allocating the first descriptor to the direct memory access engine with the highest priority; if the direct memory access engines have the same priority, determining any one of the direct memory access engines as the target direct memory access engine, and allocating the first descriptor to the target direct memory access engine.

[0151] In some optional embodiments, the aforementioned device for data transmission also includes: a second instruction execution module, which is used to interrupt the execution of the transfer instruction if the descriptor corresponding to the direct memory access engine being executed is not the last descriptor in the transfer instruction, and store the descriptor corresponding to the next direct memory access engine in the sequence to a preset location; obtain the first descriptor corresponding to the target direct memory access engine and perform data transmission; after the execution of the first descriptor corresponding to the first instruction is completed, read the descriptor corresponding to the next direct memory access engine in the sequence from the preset location and continue the execution of the transfer instruction.

[0152] In some optional embodiments, the aforementioned device for data transmission also includes: an arbitration module, which is used to determine a preset request weight corresponding to a request type based on the request type of the transmission instruction; determine the next transmission instruction for data transmission based on the preset request weight and the number of transmissions of the transmission instructions of each request type; if the transmission instruction corresponding to the transmission target request type is greater than the preset number of transmissions, determine the next transmission instruction for data transmission based on the transmission instructions corresponding to other request types.

[0153] In some optional embodiments, the aforementioned device for data transmission also includes: an arbitration configuration module, used to configure the preset request weight corresponding to the request type; configure the preset request weight corresponding to the first request type as a first preset number of transmissions; configure the preset request weight corresponding to the second request type as a second preset number of transmissions; based on the preset request weight, after the transmission instruction corresponding to the transmission target request type is greater than the preset number of transmissions, determine the next transmission instruction for data transmission among the transmission instructions corresponding to other request types.

[0154] In some optional embodiments, the aforementioned device for data transmission also includes: an adjustment module for adjusting the preset request weight corresponding to the request type; if the request response time of the transmission instruction of the target request type is greater than the preset time threshold, the preset request weight corresponding to the target request type is increased.

[0155] In some optional embodiments, the aforementioned device for data transmission also includes: a merging module, used to merge the instructions for transmitting target data and the instructions for transmitting the storage address of the target data into a target data transmission instruction; based on the target data transmission instruction, enabling the direct memory access engine to perform data transmission.

[0156] For the description of the features in the embodiments corresponding to the apparatus for data transmission, reference can be made to the relevant description of the embodiments corresponding to the method for data transmission, which will not be repeated here.

[0157] An embodiment of the present application further provides an electronic device, Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown in FIG. Figure 6 As shown, it includes a memory 60 and a processor 20, wherein the memory 60 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps of any of the above-mentioned method embodiments for data transmission.

[0158] The electronic device further includes an input device 30 and an output device 40. The processor 20, the memory 60, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 6 The bus connection is taken as an example.

[0159] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned method embodiments for data transmission when running.

[0160] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0161] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned method embodiments for data transmission are implemented.

[0162] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned method embodiments for data transmission are implemented.

[0163] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0164] The above describes in detail a method, medium, device, and product for data transmission provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for data transmission, characterized in that include: In a case where a plurality of direct memory access engines are enabled based on a transfer instruction, determining an acquisition order of acquiring direct memory access descriptors based on a priority of each direct memory access engine; wherein the descriptor corresponding to the direct memory access engine configured as the first priority is obtained before the descriptors corresponding to the direct memory access engines configured as the other priorities; if there is no descriptor corresponding to the direct memory access engine of the first priority, the descriptor corresponding to the direct memory access engine of the second priority is obtained; if the number of times the descriptor corresponding to the direct memory access engine of the second priority is obtained is greater than a preset first number, the descriptor corresponding to the direct memory access engine of the third priority is obtained; performing data transmission based on the acquisition order; Obtaining a first instruction, and configuring a first descriptor corresponding to a target direct memory access engine based on the first instruction, wherein the first instruction is executed before the transfer instruction; Determining whether there is a transfer instruction for obtaining a descriptor corresponding to the direct memory access engine being executed in the target direct memory access engine; If there is a transfer instruction for obtaining a descriptor corresponding to the direct memory access engine being executed, determining whether the descriptor corresponding to the direct memory access engine being executed is the last descriptor in the transfer instruction; If it is the last descriptor in the transfer instruction, or if there is no transfer instruction for obtaining the descriptor corresponding to the direct memory access engine being executed, obtaining the first descriptor corresponding to the target direct memory access engine and performing data transmission; If the descriptor corresponding to the executing direct memory access engine is not the last descriptor in the transfer instruction, interrupting the execution of the transfer instruction and storing the descriptor corresponding to the next direct memory access engine in the sequence to a preset location; Obtaining a first descriptor corresponding to the target direct memory access engine and performing data transmission; After the execution of the first descriptor corresponding to the first instruction is completed, the descriptor corresponding to the next direct memory access engine in the sequence is read from the preset position to continue the execution of the transfer instruction.

2. The method for data transmission according to claim 1, characterized in that The method further comprises: Configure the priorities and the acquisition order corresponding to the priorities; The priorities are configured to include a first priority, a second priority, and a third priority, wherein the descriptor corresponding to the direct memory access engine of the first priority is obtained before the descriptors corresponding to the direct memory access engines of other priorities.

3. The method for data transmission according to claim 1 or 2, characterized in that The method further comprises: configuring a preset weight of a direct memory access engine of each target priority, wherein the direct memory access engine of each target priority includes the direct memory access engine of the second priority and the direct memory access engine of the third priority; Based on the preset weight, after obtaining the descriptors corresponding to the direct memory access engine of the target priority a preset number of times, obtaining the descriptors corresponding to the direct memory access engine of the next priority level to the target priority level.

4. The method for data transmission according to claim 1, characterized in that Determining an order of acquiring direct memory access descriptors based on the priorities of the direct memory access engines, and performing data transmission based on the order includes: Determining whether there is a direct memory access engine of the first priority among the enabled direct memory access engines; If a direct memory access engine of the first priority exists, a descriptor of the direct memory access engine of the first priority is obtained, and data transmission is performed based on the descriptor of the direct memory access engine of the first priority.

5. The method for data transmission according to claim 1, characterized in that Determining an order of acquiring direct memory access descriptors based on the priorities of the direct memory access engines, and performing data transmission based on the order further comprises: Determining whether there is a first-priority direct memory access engine among the enabled direct memory access engines; If the direct memory access engine of the first priority does not exist, determining whether there is a direct memory access engine of the second priority among the enabled direct memory access engines; If a direct memory access engine of the second priority level exists, determining whether the number of times the descriptor corresponding to the direct memory access engine of the second priority level is obtained is greater than the preset first number; If the number of times the descriptor corresponding to the direct memory access engine of the second priority is obtained is less than or equal to the preset first number, the descriptor corresponding to the direct memory access engine of the target number among the direct memory access engines of the second priority is obtained, and data is transmitted based on the descriptor corresponding to the direct memory access engine of the target number, and the number of times the descriptor corresponding to the direct memory access engine of the second priority is obtained is increased by one.

6. The method for data transmission according to claim 1, characterized in that Configuring the first descriptor corresponding to the target direct memory access engine includes any one of the following methods: If there are multiple priorities in the direct memory access engine, determining the direct memory access engine with the highest priority as the target direct memory access engine, and allocating the first descriptor to the direct memory access engine with the highest priority; If the direct memory access engines have the same priority, any one of the direct memory access engines is determined as the target direct memory access engine, and the first descriptor is allocated to the target direct memory access engine.

7. The method for data transmission according to claim 1, characterized in that The method further comprises: Determining a preset request weight corresponding to the request type based on the request type of the transmission instruction; Determining a next transmission instruction for data transmission based on the preset request weight and the number of transmissions of the transmission instructions of each request type; If the transmission instruction corresponding to the transmission target request type is greater than the preset number of transmissions, a transmission instruction for performing the next data transmission is determined based on the transmission instructions corresponding to other request types.

8. The method for data transmission according to claim 7, characterized in that The method further comprises: Configure the preset request weight corresponding to the request type; Configuring a preset request weight corresponding to the first request type as a first preset number of transmissions; Configuring the preset request weight corresponding to the second request type as a second preset number of transmissions; Based on the preset request weight, after the transmission instruction corresponding to the transmission target request type is greater than the preset number of transmissions, the next transmission instruction for data transmission is determined from the transmission instructions corresponding to other request types.

9. The method for data transmission according to claim 7 or 8, characterized in that The method further comprises: Adjusting the preset request weight corresponding to the request type; If the request response time of the transmission instruction of the target request type is greater than the preset time threshold, the preset request weight corresponding to the target request type is increased.

10. The method for data transmission according to claim 7, characterized in that The method further comprises: Combining an instruction for transmitting target data and an instruction for transmitting the storage address of the target data into a target data transmission instruction; Based on the target data transmission instruction, a direct memory access engine is enabled to perform data transmission.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for data transmission according to any one of claims 1 to 10 are implemented.

12. A computer device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for data transmission according to any one of claims 1 to 10 when executing the computer program.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for data transmission according to any one of claims 1 to 10 are implemented.

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