Modular integrated circuit unit, distributed storage unit access method and system

Abstract

The application provides a modular integrated circuit unit, a distributed storage unit access method and system, and the modular integrated circuit unit comprises at least one memory controller, which sends a storage address access request to a storage unit; at least one storage unit, which provides uniform memory access for the storage address access request, and the storage unit comprises a local storage unit and a virtual remote storage unit; at least one computing unit, which initiates the storage address access request; and at least one on-chip interconnection network, which interweaves a storage address indicated by the storage address access request to generate an interwoven storage address distribution and determines a corresponding target storage unit. By setting the local storage unit and the virtual remote storage unit, using the address interweaving technology and the virtual storage mapping, the distributed storage units on multiple modular integrated circuit units can realize uniform address access and load balancing, the resource utilization rate is improved, and the performance and the ease of use of the distributed storage system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer storage, and in particular to a modular integrated circuit unit, a distributed storage unit access method and system. BACKGROUND

[0002] In order to improve the available storage capacity and bandwidth of the entire computing system, multiple independent storage device units are generally placed in the system, and in order to provide a unified memory access at the computing level, the address interleaving method is used to manage the access to these independent storage units. At the same time, with the development of Chiplet technology and the emergence of new storage devices, a large number of storage units are placed on multiple different chiplets or chips, resulting in a distributed feature of the storage devices on the system. Even if the address interleaving of the prior art is applied to the distributed storage units, the information of the storage units across the chiplets or chips cannot be directly obtained, thereby causing a non-uniform memory access to the computing system, and the non-uniform memory access has problems of uneven delay, high complexity and low resource utilization, which limits the performance and ease of use of the distributed storage system. SUMMARY

[0003] An object of the present application is to provide a modular integrated circuit unit, by setting a local storage unit and a virtual remote storage unit, using address interleaving technology and virtual storage mapping to realize unified address access and load balancing of the distributed storage units on multiple chiplets, ensuring a unified memory access to the computing system, balancing the access delay of each storage unit, reducing complexity, improving resource utilization, and improving the performance and ease of use of the distributed storage system. Another object of the present application is to provide a distributed storage unit access method. Still another object of the present application is to provide a distributed storage unit access system. Still another object of the present application is to provide a computer device.

[0004] In order to achieve the above objects, the present application discloses a modular integrated circuit unit, comprising:

[0005] at least one computing unit, at least one memory controller, at least one on-chip interconnection network and at least one storage unit;

[0006] The memory controller is configured to send a storage address access request sent by the on-chip interconnection network to the storage unit;

[0007] The storage unit is configured to provide a unified memory access to the storage address access request sent by the memory controller, and the storage unit comprises a local storage unit and a virtual remote storage unit. The local storage unit is distributed on the current modular integrated circuit unit, and the virtual remote storage unit is distributed on the modular integrated circuit unit other than the current modular integrated circuit unit.

[0008] The computing unit is configured to initiate a storage address access request;

[0009] The on-chip interconnection network is configured to interleave the storage address indicated by the storage address access request sent by the computing unit, to generate an interleaved storage address distribution; according to the interleaved storage address distribution, the target storage unit corresponding to the storage address access request is determined, and the storage address access request is sent to the corresponding target storage unit through the memory controller, the target storage unit being a target local storage unit or a target virtual remote storage unit.

[0010] Preferably, the modular integrated circuit unit is a core in a multi-core package or a chip in a computing system composed of independent chipsets.

[0011] Preferably, the on-chip interconnection network is specifically configured to divide the storage address according to a preset interleaving granularity, to obtain a plurality of interval storage address distributions; and the plurality of interval storage address distributions are uniformly mapped to different storage units on different modular integrated circuit units, to obtain the interleaved storage address distribution.

[0012] Preferably, the on-chip interconnection network is specifically configured to send, according to the interleaved storage address distribution, the storage address access request distributed on the current modular integrated circuit unit where the on-chip interconnection network is located to the target local storage unit through the memory controller, or send the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit where the on-chip interconnection network is located to the target virtual remote storage unit through the interconnection interface.

[0013] The application further discloses a distributed storage unit access method, which comprises the following steps:

[0014] The computing unit initiates a storage address access request to the on-chip interconnection network;

[0015] The on-chip interconnection network interleaves the storage address indicated by the storage address access request, to generate an interleaved storage address distribution;

[0016] The on-chip interconnection network determines the target storage unit corresponding to the storage address access request according to the interleaved storage address distribution, and sends the storage address access request to the memory controller in the corresponding modular integrated circuit unit;

[0017] The memory controller sends the storage address access request to the target storage unit, the target storage unit being a target local storage unit or a target virtual remote storage unit.

[0018] The storage units include local storage units and virtual remote storage units, the local storage units are distributed on the current modular integrated circuit unit, and the virtual remote storage units are distributed on the modular integrated circuit units other than the current modular integrated circuit unit.

[0019] Preferably, the on-chip interconnection network interleaves the storage address indicated by the storage address access request to generate an interleaved storage address distribution, including:

[0020] The on-chip interconnection network divides the storage address according to a preset interleaving granularity to obtain a plurality of interval storage address distributions; and maps the plurality of interval storage address distributions to different storage units on different modular integrated circuit units uniformly to obtain the interleaved storage address distribution.

[0021] Preferably, the on-chip interconnection network sends the storage address access request to the memory controller in the corresponding modular integrated circuit unit according to the interleaved storage address distribution, including:

[0022] The on-chip interconnection network sends the storage address access request distributed on the current modular integrated circuit unit to the corresponding memory controller, or sends the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit to the memory controller in the corresponding modular integrated circuit unit through the interconnection interface.

[0023] Preferably, the interleaved storage address distribution includes the storage address distribution of each storage unit corresponding interval;

[0024] The on-chip interconnection network sends the storage address access request distributed on the current modular integrated circuit unit to the corresponding memory controller according to the interleaved storage address distribution, including:

[0025] The on-chip interconnection network matches the storage address indicated by the storage address access request distributed on the current modular integrated circuit unit with the storage address distribution of each storage unit corresponding interval in the storage address distribution, determines the target local storage unit, and sends the storage address access request distributed on the current modular integrated circuit unit to the corresponding memory controller.

[0026] Preferably, the memory controller sends the storage address access request to the target storage unit, including:

[0027] The memory controller sends the storage address access request to the target local storage unit.

[0028] Preferably, the on-chip interconnection network stores the interconnection interface bound by each storage unit;

[0029] The memory address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit is sent to the memory controller in the corresponding modular integrated circuit unit through the interconnection interface, comprising:

[0030] The on-chip interconnection network matches the memory address indicated by the memory address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit with the memory address distribution of each memory unit corresponding interval in the memory address distribution, and determines the target interconnection interface bound by the target remote modular integrated circuit unit;

[0031] The memory address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit is sent to the target remote modular integrated circuit unit through the target interconnection interface, so that the target remote modular integrated circuit unit sends the memory address access request to the corresponding memory controller.

[0032] Preferably, the memory controller sends the memory address access request to the target memory unit, comprising:

[0033] The memory controller sends the memory address access request to the target virtual remote memory unit.

[0034] The application also discloses a distributed memory unit access system, which comprises a plurality of modular integrated circuit units as described above, and the plurality of modular integrated circuit units are connected in communication through an interconnection interface, wherein the interconnection interface comprises an inter-chiplet interconnection interface or an inter-chip interconnection interface.

[0035] If the modular integrated circuit unit is a chiplet in a multi-chiplet package, the chiplets are connected in communication through the inter-chiplet interconnection interface.

[0036] If the modular integrated circuit unit is a chip in a computing system composed of independent chips, the chips are connected in communication through the inter-chip interconnection interface.

[0037] The application also discloses a computer device comprising the distributed memory unit access system as described above.

[0038] The application discloses a modular integrated circuit unit, which comprises at least one computing unit, at least one memory controller, at least one on-chip interconnection network and at least one storage unit. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0040] Figure 1 A storage interleaving access schematic diagram provided by the embodiment of the present application;

[0041] Figure 2 A storage unit organization form schematic diagram composed of one independent chip provided by the embodiment of the present application;

[0042] Figure 3 A storage unit organization form schematic diagram composed of two chips provided by the embodiment of the present application;

[0043] Figure 4 A storage unit organization form schematic diagram composed of two chiplets provided by the embodiment of the present application;

[0044] Figure 5 A storage unit organization form schematic diagram composed of five chiplets provided by the embodiment of the present application;

[0045] Figure 6 A structural schematic diagram of a distributed storage unit access system provided for an embodiment of the present application;

[0046] Figure 7 A structural schematic diagram of a modular integrated circuit unit provided for an embodiment of the present application;

[0047] Figure 8 A flowchart of a distributed storage unit access method provided for an embodiment of the present application;

[0048] Figure 9 A flowchart of another distributed storage unit access method provided for an embodiment of the present application;

[0049] Figure 10 A schematic diagram of storage address distribution of multiple intervals provided for an embodiment of the present application;

[0050] Figure 11 A structural schematic diagram of a distributed storage unit access system under a die 0 perspective provided for an embodiment of the present application;

[0051] Figure 12 A schematic diagram of interleaved storage address distribution under a die 0 perspective provided for an embodiment of the present application;

[0052] Figure 13 A structural schematic diagram of a distributed storage unit access system under a die 1 perspective provided for an embodiment of the present application;

[0053] Figure 14 A schematic diagram of interleaved storage address distribution under a die 1 perspective provided for an embodiment of the present application;

[0054] Figure 15 A structural schematic diagram of a distributed storage unit access system under a die 2 perspective provided for an embodiment of the present application;

[0055] Figure 16 A schematic diagram of interleaved storage address distribution under a die 2 perspective provided for an embodiment of the present application;

[0056] Figure 17 A structural schematic diagram of a distributed storage unit access system under a die 3 perspective provided for an embodiment of the present application;

[0057] Figure 18 A schematic diagram of interleaved storage address distribution under a die 3 perspective provided for an embodiment of the present application;

[0058] Figure 19A schematic structural diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0060] In order to facilitate the understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below. A complete computing system includes components such as computing, storage, input and output devices. An ideal storage device should be able to provide unlimited storage capacity and bandwidth, but in reality, for various types of storage devices that can be implemented, such as dynamic random access memory (DRAM) or static random access memory (SRAM), they can only provide limited capacity and bandwidth. Therefore, multiple independent storage device units are placed in the system to increase the available storage capacity and bandwidth of the entire computing system. Storage access interleaving technology determines the specific storage unit to be accessed based on the access address. Its main purpose is to balance the access traffic to the storage unit and provide a unified memory access (UMA) abstraction for computing. Figure 1 A schematic diagram of storage interleaving access provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown in the figure, based on the address interleaving algorithm and the preset interleaving granularity, the address range is divided, and the access requests of different addresses are sent to different storage units, thereby abstracting a unified memory access, which can improve the concurrency and efficiency of data access. Figure 1 As shown in the figure, there are four memory cells in the system, namely MEM 0, MEM 1, MEM 2 and MEM 3; the addresses from 0x0 to 0xfff are mapped to MEM 0, the addresses from 0x1000 to 0x1fff are mapped to MEM 1, the addresses from 0x2000 to 0x2fff are mapped to MEM 2, and the addresses from 0x3000 to 0x3fff are mapped to MEM 3. This interleaving pattern determines the specific memory cell based on the high bits of the address. Figure 1In the present embodiment, the highest bit of the address determines which memory unit it is mapped to, specifically, if the highest bit of the address is 0, the address is mapped to MEM 0; if the highest bit is 1, the address is mapped to MEM 1, and so on. By distributing the address access requests to different memory units, it is possible to avoid all requests from being concentrated on one memory unit, thereby balancing the load of each memory unit. When multiple processors or cores access the memory at the same time, the interleaving technique can reduce the latency, because different memory units can handle different access requests at the same time.

[0061] The current memory unit forms include one independent chip, multiple chips interconnected, and multiple chiplets interconnected. Figure 2 A schematic diagram of a memory unit organization form composed of one independent chip provided by the present embodiment is shown in FIG. 1. Figure 2 As shown in FIG. 1, the computing system is composed of one independent chip, which integrates two memory controllers (MEM CTRL). It is worth mentioning that the number of memory controllers can be set according to actual needs; the chip also integrates N memory units, which are MEM 0, …, MEM N-1, and generally N is within 8; the addresses of the N memory units are interleaved for in-chip access.

[0062] Figure 3 A schematic diagram of a memory unit organization form composed of two chips provided by the present embodiment is shown in FIG. 2. Figure 3 As shown in FIG. 2, the computing system is composed of two chips, which are chip 0 and chip 1; each chip integrates two memory controllers (MEM CTRL). It is worth mentioning that the number of memory controllers can be set according to actual needs; the two chips are interconnected through chip-to-chip (C2C) interconnection; each chip integrates N memory units, which are MEM 0, …, MEM N-1, and generally N is within 8; the N memory units of each chip are interleaved, and the computing system composed in this way is called non-uniform memory access (NUMA).

[0063] Figure 4 A schematic diagram of a memory unit organization form composed of two chiplets provided by the present embodiment is shown in FIG. 3. Figure 4As shown, the computing system is composed of 2 dies, die 0 and die 1; each die is integrated with 2 memory controllers (MEM CTRL). It is worth noting that the number of memory controllers can be set according to actual needs; the 2 dies are interconnected through M die-to-die (D2D) interconnections; each die is integrated with N memory units, MEM 0, …, MEM N-1, generally N == M; the N memory units on the 2 dies are interleaved together, which presents a unified memory access to the computing unit; because N == M, the remote storage target on different dies can be simulated through the D2D interface, that is, the access address of the remote storage target is sent to the D2D interface. Therefore, the number of storage devices that can be supported by such a system is limited.

[0064] Figure 5 A schematic diagram of a 5-die-composed memory unit organization form provided for an embodiment of the present application is shown in FIG. 4. Figure 5 As shown, the computing system is composed of 5 dies, die 0, die 1, die 2, die 3 and die 4; different dies are interconnected through D2D; the N memory units are all located on one die, die 0, and are respectively MEM 0, …, MEM N / 2-1, MEM N / 2, …, MEM N-1; the remaining dies do not have memory units; therefore, this organization form and Figure 2 Similar to the above, the memory units are interleaved on one die, and the access of the memory units on the remaining dies is all sent to die 0 through D2D and is specifically interleaved and accessed by die 0.

[0065] With the development of technology, the demand for high-performance computing, the chip is now developing towards multi-die interconnection, for example, a chip with distributed memory units, Figure 6 A structure schematic diagram of a distributed memory unit access system provided for an embodiment of the present application is shown in FIG. 5. Figure 6 As shown, the system is composed of 4 dies, die 0, die 1, die 2 and die 3, and different dies are interconnected through D2D; each die is integrated with 2 memory controllers (MEM CTRL). It is worth noting that the number of memory controllers can be set according to actual needs; each die is integrated with 2 memory controllers (MEM CTRL); each die is also integrated with a plurality of computing units, computing unit 0, …, computing unit N; each die is integrated with an on-chip interconnection network, Figure 6The on-chip interconnection network is shown in black straight lines. The computing unit can initiate a request to the on-chip interconnection network, and the on-chip interconnection network can send the request to the memory controller. Each core particle is integrated with N storage units, namely MEM 0, …, MEM N-1. At the same time, due to the demand for storage bandwidth and other needs, three-dimensional dynamic random access memory (3DDRAM) and other storage devices have been developed. Due to the physical implementation of 3DDRAM and other factors, the intuitive result on the system is that the number of storage units N will be more than the traditional storage units. These factors combined result in the distributed characteristics of the storage units on the system. In order to abstract a unified memory access model for computing systems and other systems, it is necessary to address the large number of distributed storage units within and across core particles.

[0066] It is worth noting that the distributed storage unit access system includes a plurality of modular integrated circuit units, which are core particles in a multi-core particle package or chips in a computing system composed of multiple chips; the core particles are connected through D2D communication; the chips are connected through C2C communication. The technical solution of the present application can be applied to a computing system containing a plurality of interconnected distributed modular integrated circuit units, including but not limited to a chip using a multi-core particle package, or a computing system composed of multiple chips, and the storage unit can use double data rate memory (DDR) or 3DDRAM and other different storage media.

[0067] In view of the current need for uniform address interleaving of a large number of distributed storage units within and across core particles, the present application proposes the concept of local storage unit (LMT) and virtual remote storage unit (VRMT). Using virtual remote storage units, the distributed storage units on multiple core particles can provide unified address access functions through address interleaving, thereby avoiding the problem of non-uniform memory access to the computing system.

[0068] A modular integrated circuit unit includes at least one computing unit, at least one memory controller (MEM CTRL), at least one on-chip interconnect network, and at least one storage unit (MEM). The memory controller is used to send storage address access requests sent by the on-chip interconnect network to the storage unit. The storage unit (MEM) is used to provide unified memory access for storage address access requests sent by the memory controller. The computing unit is used to initiate storage address access requests to the on-chip interconnect network. The on-chip interconnect network is used to interleave the storage addresses indicated by the storage address access requests sent by the computing unit to generate an interleaved storage address distribution. Based on the interleaved storage address distribution, the target storage unit corresponding to the storage address access request is determined, and the storage address access request is sent to the corresponding target storage unit via the memory controller. The target storage unit is a target LMT or target VRMT. A modular integrated circuit unit is a chip in a computing system composed of a chip in a multi-chip package or an independent chip.

[0069] Figure 7 A schematic structural diagram of a modular integrated circuit unit provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the modular integrated circuit unit includes multiple computing units (computing unit 0, ..., computing unit N), an on-chip interconnect network, multiple memory controllers (MEM CTRL), multiple storage units (MEM 0, ..., MEM N), and a D2D interface. The computing units can initiate storage address access requests to the on-chip interconnect network. The on-chip interconnect network is used to interleave the storage addresses indicated in the storage address access requests sent by the computing units to generate an interleaved storage address distribution. Based on the interleaved storage address distribution, the target storage unit corresponding to the storage address access request is determined and sent to the corresponding target storage unit via the memory controller. The memory controller is used to send the storage address access request sent by the on-chip interconnect network to the target storage unit for access. The modular integrated circuit unit can also communicate with other modular integrated circuit units via the D2D interface. The storage unit is used to provide unified memory access for the storage address access requests sent by the memory controller.

[0070] The storage unit includes a local storage unit and a virtual remote storage unit. The local storage unit is distributed on the current modular integrated circuit unit, and the virtual remote storage unit is distributed on modular integrated circuit units other than the current modular integrated circuit unit.

[0071] The on-chip interconnect network is specifically used to divide the storage addresses according to a preset interleaving granularity to obtain storage address distributions in multiple intervals; and evenly map the storage address distributions in multiple intervals to different storage units on different modular integrated circuit units to obtain interleaved storage address distributions.

[0072] The on-chip interconnection network is specifically used for sending the storage address access request distributed on the current modular integrated circuit unit where the on-chip interconnection network is located to a target local storage unit through a memory controller according to the interleaved storage address distribution, or sending the storage address access request distributed on a modular integrated circuit unit other than the current modular integrated circuit unit where the on-chip interconnection network is located to a target virtual remote storage unit through an interconnection interface.

[0073] It is worth noting that the modular integrated circuit unit is also applied to Figure 8 to Figure 10 Any one of the distributed storage unit access methods shown, the embodiments of the present application will not be described here.

[0074] The implementation process of the distributed storage unit access method provided by the embodiments of the present application is described below.

[0075] Figure 8 A flowchart of a distributed storage unit access method provided by the embodiments of the present application is shown in Figure 8 The method comprises:

[0076] Step 101, the computing unit initiates a storage address access request to the on-chip interconnection network.

[0077] In the embodiments of the present application, the storage address access request is initiated by the computing unit, and the storage address access request refers to the processor or the memory controller accessing adjacent storage units in sequence according to the order of the memory addresses when processing data. This mode usually occurs in the case of processing a large amount of continuous data, such as array operation, file reading and writing, or multimedia data processing, etc.

[0078] Step 102, the on-chip interconnection network interleaves the storage address indicated by the storage address access request to generate an interleaved storage address distribution.

[0079] In the embodiments of the present application, the storage address access request is sent by the computing unit to the on-chip interconnection network, the storage address access request includes continuous storage addresses, based on the address interleaving algorithm, the address space of the storage addresses is divided into multiple segments according to the preset interleaving granularity, the storage addresses indicated by the storage address access request are matched with the divided segment address spaces, and the storage addresses of the multiple intervals are uniformly mapped to different storage units on different modular integrated circuit units to generate an interleaved storage address distribution. The interleaved storage address distribution includes the number identification of the multiple storage units and the storage address distribution of the corresponding interval of each storage unit. The on-chip interconnection network stores an interconnection interface bound to each storage unit, and the interconnection interface includes a D2D interface or a C2C interface. The interconnection interface is used to realize the interaction across the modular integrated circuit units.

[0080] Step 103, the on-chip interconnection network determines the target storage unit corresponding to the storage address access request according to the interleaved storage address distribution, and sends the storage address access request to the memory controller in the corresponding modular integrated circuit unit.

[0081] Specifically, the on-chip interconnection network sends the storage address access request distributed on the current modular integrated circuit unit to the corresponding memory controller according to the interleaved storage address distribution, or sends the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit to the memory controller in the corresponding modular integrated circuit unit through the interconnection interface.

[0082] Step 104, the memory controller sends the storage address access request sent by the on-chip interconnection network to the target storage unit, and the target storage unit is a target LMT or a target VRMT.

[0083] In the embodiment of the application, the storage address access request is sent by the on-chip interconnection network to the memory controller.

[0084] Specifically, if the target storage unit is the target LMT, the memory controller sends the storage address access request to the target LMT.

[0085] Specifically, if the target storage unit is the target VRMT, the memory controller sends the storage address access request to the target VRMT.

[0086] In the embodiment of the application, the modular integrated circuit unit includes at least one storage unit, the storage unit includes an LMT and a VRMT, the LMT is distributed on the current modular integrated circuit unit, the VRMT is distributed on the modular integrated circuit unit other than the current modular integrated circuit unit, the VRMT is invisible to the current modular integrated circuit unit, and the binding relationship between the VRMT and the interconnection interface is visible to the modular integrated circuit unit, so that the system can dynamically adjust or expand the storage resource without affecting the existing architecture. This design enhances the flexibility and scalability of the system, facilitating future upgrade or expansion.

[0087] In the embodiment of the application, the modular integrated circuit unit is a core particle in a multi-core package or a chip in a computing system composed of independent chipsets, the core particles are connected through D2D, and the chips are connected through C2C. It should be noted that the specific interconnection mode of D2D can be interconnection through a D2D interface, and the specific interconnection mode of C2C can be interconnection through a C2C interface.

[0088] In the technical scheme provided by the embodiment of the present application, the computing unit initiates a storage address access request to the on-chip interconnection network; the on-chip interconnection network interleaves a storage address indicated by the storage address access request to generate an interleaved storage address distribution; the on-chip interconnection network determines a target storage unit corresponding to the storage address access request according to the interleaved storage address distribution, and sends the storage address access request to a memory controller in the corresponding modular integrated circuit unit; the memory controller sends the storage address access request to the target storage unit, and the target storage unit is a target local storage unit or a target virtual remote storage unit; the storage unit includes a local storage unit and a virtual remote storage unit, the local storage unit is distributed on the current modular integrated circuit unit, and the virtual remote storage unit is distributed on a modular integrated circuit unit other than the current modular integrated circuit unit; by setting the local storage unit and the virtual remote storage unit, the distributed storage units on multiple cores are unified for address access and load balancing by using address interleaving technology and virtual storage mapping, unified memory access to the computing system is ensured, access delay of each storage unit is balanced, complexity is reduced, resource utilization is improved, and performance and ease of use of the distributed storage system are improved.

[0089] Figure 9 A flowchart of another distributed storage unit access method provided by the embodiment of the present application is shown in FIG. 2, and the method includes the following steps. Figure 9

[0090] In step 201, the on-chip interconnection network divides the storage address according to a preset interleaving granularity to obtain a storage address distribution of multiple intervals.

[0091] In the embodiment of the present application, the continuous storage address is divided according to the interleaving granularity M to generate a storage address distribution of multiple intervals, and the storage address distribution of multiple intervals includes multiple intervals and a storage address corresponding to each interval.

[0092] In the embodiment of the present application, the interleaving granularity M in the address interleaving algorithm can be adjusted according to the type of the storage unit, and the storage unit includes DDR or 3DDRAM.

[0093] Further, the allocation strategy in the address interleaving algorithm is adjusted in real time according to the storage access load of each modular integrated circuit unit to optimize the access bandwidth and delay.

[0094] The present application divides the storage address according to a preset interleaving granularity, and dynamically adjusts the storage address distribution according to requirements, thereby improving the recovery capability of the system when facing faults and the flexibility of adapting to different application scenarios.

[0095] ​In step 202, the on-chip interconnection network uniformly maps the storage addresses of the plurality of intervals to different storage units on different modular integrated circuit units to obtain an interleaved storage address distribution.

[0096] In the embodiment of the present application, the modular integrated circuit unit is a core particle in a multi-core particle package or a chip in a computing system composed of independent chips, and the modular integrated circuit unit is distributed with a plurality of storage units. For each modular integrated circuit unit, the storage units distributed on the current modular integrated circuit unit are LMTs, and the storage units distributed on other modular integrated circuit units are VRMTs, and the VRMTs are invisible to the current modular integrated circuit unit, and the binding relationship between the VRMTs and the interconnection interface is visible to the modular integrated circuit unit.

[0097] Specifically, the storage address of each interval is mapped to a storage unit, and subsequent access requests for the storage addresses in the interval are processed by the storage unit; the storage address distribution of the plurality of intervals is respectively mapped to different storage units on different modular integrated circuit units in sequence to obtain an interleaved storage address distribution, and the interleaved storage address distribution includes the number identification of the plurality of storage units and the storage address distribution of the corresponding interval of each storage unit. The on-chip interconnection network stores the interconnection interface bound to each storage unit.

[0098] It is worth noting that the sequence of the storage addresses of the plurality of intervals is a sequence divided according to the interleaving granularity, and the sequence of the storage units can be sorted according to the number identification of the storage units, which is not limited in the embodiment of the present application.

[0099] The present application can reduce the conflict during data access, improve the data read / write speed, and further improve the overall performance by interleaving the continuous storage addresses and uniformly distributing them to different storage units; allows the allocation of storage resources among a plurality of modular integrated circuit units, supports the addition of more storage units without affecting the system performance, and enhances the expansion capability of the system.

[0100] In step 203, the on-chip interconnection network matches the storage address indicated by the storage address access request distributed on the current modular integrated circuit unit with the storage address distribution of the corresponding interval of each storage unit in the storage address distribution to determine the target LMT, and sends the storage address access request distributed on the current modular integrated circuit unit to the corresponding memory controller.

[0101] In the embodiment of the present application, for the current modular integrated circuit unit, based on the number identification of the storage unit, the distribution order of the interleaved storage address distribution is taken as the matching order, if the storage address in the interval corresponding to the mapped LMT is matched, the determined LMT is determined as the target LMT; the storage address access request distributed on the current modular integrated circuit unit is sent to the memory controller corresponding to the target LMT. Taking the distribution order of the interleaved storage address distribution as the matching order makes the accessed storage units of the modular integrated circuit unit under different perspectives consistent, thereby realizing unified memory access and ensuring the consistency of the access of the storage units from different perspectives of the different modular integrated circuit units. This way enables the system to provide a unified memory access interface, simplifying the memory management complexity.

[0102] Further, the memory controller sends the storage address access request to the target LMT, and the target LMT processes the storage address access request subsequently.

[0103] The present application provides a unified memory access interface for the computing unit, so that the developer does not need to care about the complexity of the underlying storage structure, reduces the development difficulty and improves the development efficiency.

[0104] Step 204, the on-chip interconnection network matches the storage address indicated by the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit with the storage address distribution of each storage unit corresponding interval in the storage address distribution, and determines the target interconnection interface bound by the target remote modular integrated circuit unit.

[0105] In the embodiment of the present application, if the interleaved storage address distribution matching according to the indicated storage address queries the storage address in the interval corresponding to the mapped VRMT, the matched VRMT is determined as the target VRMT; the corresponding bound interconnection interface is determined according to the target VRMT, and the interconnection interface is the target interconnection interface.

[0106] In the embodiment of the present application, if the modular integrated circuit unit is a core particle, the interconnection interface is a D2D interface; if the modular integrated circuit unit is a chip, the interconnection interface is a C2C interface.

[0107] The present application simplifies the communication management between the cross modular integrated circuit units by clearly defining the binding relationship between the interconnection interface and the VRMT. The developer only needs to focus on how to send the request through the interface, without deep understanding of the underlying communication details, thereby reducing the development complexity.

[0108] Step 205, send the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit to the target remote modular integrated circuit unit through the target interconnection interface, so that the target remote modular integrated circuit unit sends the storage address access request to the corresponding memory controller.

[0109] In the embodiment of the application, the on-chip interconnection network sends the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit to the target VRMT-bound target interconnection interface, and the target interconnection interface is used for communication between the modular integrated circuit units; the target interconnection interface is used for communication with the target remote modular integrated circuit unit, and the storage address access request is routed to the corresponding memory controller.

[0110] Further, the memory controller of the target remote modular integrated circuit unit sends the storage address access request to the target VRMT, which is subsequently processed by the target VRMT.

[0111] The application determines the target VRMT by matching the storage address with the interleaved storage address distribution, and then communicates by using the target interconnection interface bound to the VRMT, thereby ensuring efficient and accurate data access even for remote storage resources. The method of determining the target VRMT based on the interleaved storage address distribution helps to more reasonably allocate storage resources and may promote load balancing to avoid the situation that some nodes are overloaded while other nodes are idle.

[0112] The application can more efficiently utilize the storage resources on each modular integrated circuit unit by uniformly managing the local and remote storage units, thereby avoiding resource waste. The application is suitable for application scenarios that need to process a large amount of data, such as big data analysis, artificial intelligence, etc. By effective storage management and access strategy, the application meets the demand of these applications for high-performance storage access. Through the innovative storage access method, the performance of a single modular integrated circuit unit is improved, and the collaborative work between multiple units is greatly promoted, thereby providing strong support for building an efficient and flexible large-scale distributed storage system.

[0113] The application takes a computing system composed of four cores as an example, and the computing system schematic diagram can refer to Figure 6, that is, the modular integrated circuit unit is the core particle, and the concepts of LMT and VRMT storage units are used to describe the specific implementation process of the distributed storage unit access method. For a computing system composed of 4 core particles, the goal is to organize the distributed storage on the 4 core particles into a unified storage. That is, for continuous storage address access, the system needs to evenly distribute different addresses to the storage units on different core particles according to the interleaving algorithm to achieve unified memory access. Taking the interleaving granularity of M as an example, Figure 10 A schematic diagram of the storage address distribution of multiple intervals provided by an embodiment of the present invention is shown in FIG. Figure 10 As shown:

[0114] There are N memory units integrated on chip die 0, namely MEM 0, MEM 1, ..., MEM N-2, MEM N-1. The addresses from 0×M to 1×M-1 are mapped to MEM 0, the addresses from 1×M to 2×M-1 are mapped to MEM 1, the addresses from (N-2)×M to (N-1)×M-1 are mapped to MEM N-2, and the addresses from (N-1)×M to N×M-1 are mapped to MEM N-1.

[0115] There are N memory units integrated on the chip die 1, namely MEM 0, MEM 1, ..., MEM N-2, MEM N-1. The addresses from N×M to (N+1)×M-1 are mapped to MEM 0, the addresses from (N+1)×M to (N+2)×M-1 are mapped to MEM1, the addresses from (2N-2)×M to (2N-1)×M-1 are mapped to MEM N-2, and the addresses from (2N-1)×M to 2N×M-1 are mapped to MEM N-1.

[0116] There are N memory units integrated on the chip die 2, namely MEM 0, MEM 1, ..., MEM N-2, MEM N-1. The addresses from 2N×M to (2N+1)×M-1 are mapped to MEM 0, the addresses from (2N+1)×M to (2N+2)×M-1 are mapped to MEM 1, the addresses from (3N-2)×M to (3N-1)×M-1 are mapped to MEM N-2, and the addresses from (3N-1)×M to 3N×M-1 are mapped to MEM N-1.

[0117] The die 3 is integrated with N storage units, respectively MEM 0, MEM 1, …, MEM N-2, MEM N-1, the addresses from 3N*M to (3N+1)*M-1 are mapped to MEM 0, the addresses from (3N+1)*M to (3N+2)*M-1 are mapped to MEM 1, the addresses from (4N-2)*M to (4N-1)*M-1 are mapped to MEM N-2, and the addresses from (4N-1)*M to 4N*M-1 are mapped to MEM N-1.

[0118] Figure 11 A structure schematic diagram of a distributed storage unit access system under the perspective of a die 0 is provided for the embodiment of the present application, as shown in the figure. Figure 11 Under the perspective of the die 0, the N storage units (MEM 0, MEM 1, …, MEM N-2, MEM N-1) in the die 0 are local storage units (LMT), namely LMT 0, LMT 1, …, LMT N-2, LMT N-1; the storage units of the die 1, the die 2 and the die 3 are all virtual remote storage units (VRMT), namely VRMT 0, …, VRMT N-1, …, VRMT N, …, VRMT 2N-1, …, VRMT 2N, …, VRMT 3N-1.

[0119] Specifically, for the die 0, in order to realize the unified address memory access, the access will be interleaved in the order of {LMT 0, LMT 1, …, LMT N-2, LMT N-1, VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1}, that is, according to the address of the accessed storage unit and the specific interleaving algorithm, the access of the storage unit is evenly distributed on {LMT 0, LMT 1, …, LMT N-2, LMT N-1, VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1}. For LMT 0 to LMT N-1, the application sends the corresponding access request to the corresponding storage unit of the die (die 0); and for VRMT 0 to VRMT 3N-1, the application sends the corresponding access request to the D2D, and routes to other dies (die 1, die 2 and die 3) through the D2D until the final storage unit.

[0120] It is worth noting that the address interleaving of the address access request is performed on the on-chip interconnection network, and the on-chip interconnection network and the computing unit are not shown in the figure for the sake of clear illustration.

[0121] Figure 12 A storage address distribution diagram after interleaving from the perspective of the die 0 provided by the embodiment of the application is shown as follows: Figure 12

[0122] In the perspective of the die 0, the storage unit on the die 0 is a local storage unit, and the local storage unit is respectively: LMT 0, LMT 1, …, LMT N-2, LMT N-1, the addresses from 0xM to 1xM-1 are mapped to LMT 0, the addresses from 1xM to 2xM-1 are mapped to LMT 1, the addresses from (N-2)xM to (N-1)xM-1 are mapped to LMT N-2, and the addresses from (N-1)xM to NxM-1 are mapped to LMT N-1.

[0123] ​In the perspective of the core die 0, the storage units on the core die 1 are virtual remote storage units, and the virtual remote storage units are respectively VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, the addresses from NxM to (N+1)xM-1 are mapped to VRMT 0, the addresses from (N+1)xM to (N+2)xM-1 are mapped to VRMT 1, the addresses from (2N-2)xM to (2N-1)xM-1 are mapped to VRMT N-2, and the addresses from (2N-1)xM to 2NxM-1 are mapped to VRMT N-1.

[0124] In the perspective of the core die 0, the storage units on the core die 2 are virtual remote storage units, and the virtual remote storage units are respectively VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, the addresses from 2NxM to (2N+1)xM-1 are mapped to VRMT N, the addresses from (2N+1)xM to (2N+2)xM-1 are mapped to VRMT N+1, the addresses from (3N-2)xM to (3N-1)xM-1 are mapped to VRMT 2N-2, and the addresses from (3N-1)xM to 3NxM-1 are mapped to VRMT 2N-1.

[0125] In the perspective of the core die 0, the storage units on the core die 3 are virtual remote storage units, and the virtual remote storage units are respectively VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1, the addresses from 3NxM to (3N+1)xM-1 are mapped to VRMT 2N, the addresses from (3N+1)xM to (3N+2)xM-1 are mapped to VRMT 2N+1, the addresses from (4N-2)xM to (4N-1)xM-1 are mapped to VRMT 3N-2, and the addresses from (4N-1)xM to 4NxM-1 are mapped to VRMT 3N-1.

[0126] The storage access corresponding to the storage address on the core die 0 is sent to the storage unit on the core die 0 through the interleaving algorithm, and the storage access corresponding to the storage address on the other core die is sent to the D2D bound with the VRMT through the interleaving algorithm.

[0127] It is worth noting that the VRMT is not located on the core die 0 and is invisible to the computing unit on the core die 0, and the VRMT is shown in a black frame in the figure.

[0128] Figure 13 A structure schematic diagram of a distributed storage unit access system in the perspective of the core die 1 provided by the embodiment of the application is shown in FIG. 2. Figure 13As shown, in the perspective of the die 1, the N memory units (MEM 0, MEM 1, …, MEM N-2, MEM N-1) in the die 1 are local memory units (LMT), i.e., LMT 0, LMT 1, …, LMT N-2, LMT N-1; the memory units of the die 0, the die 2 and the die 3 are virtual remote memory units (VRMT), i.e., VRMT 0, …, VRMT N-1, …, VRMT N, …, VRMT 2N-1, …, VRMT 2N, …, VRMT 3N-1.

[0129] Specifically, for the die 1, in order to realize the unified address memory access, the access is interleaved in the order of {VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, LMT 0, LMT 1, …, LMT N-2, LMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1}, i.e., according to the address of the accessed memory unit and the specific interleaving algorithm, the access of the memory unit is distributed on {VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, LMT 0, LMT 1, …, LMT N-2, LMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1}. For LMT 0 to LMT N-1, the application sends the corresponding access request to the corresponding memory unit of the die (die 1); and for VRMT 0 to VRMT 3N-1, the application sends the corresponding access request to the D2D, and routes to other dies (die 0, die 2 and die 3) through the D2D until the final memory unit.

[0130] It is worth noting that the address interleaving of the address access request is performed on the on-chip interconnection network, and the on-chip interconnection network and the computing unit are not shown in the figure for the sake of clear illustration.

[0131] Figure 14 A distribution diagram of the interleaved memory address in the perspective of the die 1 provided by the embodiment of the application is shown as follows. Figure 14

[0132] ​In the perspective of the core die 1, the storage units on the core die 1 are local storage units, and the local storage units are respectively: LMT 0, LMT 1, …, LMT N-2, LMT N-1, the addresses from NxM to (N+1)xM-1 are mapped to LMT 0, the addresses from (N+1)xM to (N+2)xM-1 are mapped to LMT 1, the addresses from (2N-2)xM to (2N-1)xM-1 are mapped to LMT N-2, and the addresses from (2N-1)xM to 2NxM-1 are mapped to LMT N-1.

[0133] In the perspective of the core die 1, the storage units on the core die 0 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, the addresses from 0xM to 1xM-1 are mapped to VRMT 0, the addresses from 1xM to 2xM-1 are mapped to VRMT 1, the addresses from (N-2)xM to (N-1)xM-1 are mapped to VRMT N-2, and the addresses from (N-1)xM to NxM-1 are mapped to VRMT N-1.

[0134] In the perspective of the core die 1, the storage units on the core die 2 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, the addresses from 2NxM to (2N+1)xM-1 are mapped to VRMT N, the addresses from (2N+1)xM to (2N+2)xM-1 are mapped to VRMT N+1, the addresses from (3N-2)xM to (3N-1)xM-1 are mapped to VRMT 2N-2, and the addresses from (3N-1)xM to 3NxM-1 are mapped to VRMT 2N-1.

[0135] In the perspective of the core die 1, the storage units on the core die 3 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1, the addresses from 3NxM to (3N+1)xM-1 are mapped to VRMT 2N, the addresses from (3N+1)xM to (3N+2)xM-1 are mapped to VRMT 2N+1, the addresses from (4N-2)xM to (4N-1)xM-1 are mapped to VRMT 3N-2, and the addresses from (4N-1)xM to 4NxM-1 are mapped to VRMT 3N-1.

[0136] The storage access corresponding to the storage address on the core die 1 is sent to the storage unit on the core die 1 through the interleaving algorithm; the storage access corresponding to the storage address on the other core die is sent to the D2D bound with the VRMT through the interleaving algorithm.

[0137] It is worth mentioning that the VRMT is not located on the core die 1 and is invisible to the computing unit on the core die 1, and the VRMT is shown in a black frame in the figure; in the view of the core die 1, the storage units and the core die 0 are consistent for the same address access.

[0138] Figure 15 A structure diagram of a distributed storage unit access system in the view of the core die 2 provided by the embodiment of the application is shown in the figure. Figure 15 As shown in the figure, in the view of the core die 2, the N storage units (MEM 0, MEM 1, …, MEM N-2, MEM N-1) in the core die 2 are local storage units (LMT), that is, LMT 0, LMT 1, …, LMT N-2, LMT N-1; the storage units of the core die 0, the core die 1 and the core die 3 are all virtual remote storage units (VRMT), that is, VRMT 0, …, VRMT N-1, …, VRMT N, …, VRMT 2N-1, …, VRMT 2N, …, VRMT 3N-1.

[0139] Specifically, for the die 2, in order to realize the uniform address memory access, the access will be interleaved in the order of {VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, LMT 0, LMT 1, …, LMT N-2, LMT N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1}, that is, according to the address of the accessed storage unit and the specific interleaving algorithm, the access of the storage unit is distributed on {VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, LMT 0, LMT 1, …, LMT N-2, LMT N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1} in a balanced manner. For LMT 0 to LMT N-1, the application sends the corresponding access request to the corresponding storage unit of the die (die 2); and for VRMT 0 to VRMT 3N-1, the application sends the corresponding access request to D2D, and routes to other dies (die 0, die 1 and die 3) through D2D until the final storage unit.

[0140] Figure 16 A storage address distribution diagram after interleaving from the perspective of the die 2 provided by the embodiment of the application is shown in the following figure: Figure 16

[0141] In the perspective of the die 2, the storage units on the die 2 are local storage units, and the local storage units are LMT 0, LMT 1, …, LMT N-2, LMT N-1, respectively. The addresses from 2N×M to (2N+1)×M-1 are mapped to LMT 0, the addresses from (2N+1)×M to (2N+2)×M-1 are mapped to LMT 1, the addresses from (3N-2)×M to (3N-1)×M-1 are mapped to LMT N-2, and the addresses from (3N-1)×M to 3N×M-1 are mapped to LMT N-1.

[0142] ​In the perspective of the core die 2, the storage units on the core die 0 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, the addresses from 0XM to 1XM-1 are mapped to the VRMT 0, the addresses from 1XM to 2XM-1 are mapped to the VRMT 1, the addresses from (N-2)XM to (N-1)XM-1 are mapped to the VRMT N-2, and the addresses from (N-1)XM to NXM-1 are mapped to the VRMT N-1.

[0143] In the perspective of the core die 2, the storage units on the core die 1 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, the addresses from NXM to (N+1)XM-1 are mapped to the VRMT N, the addresses from (N+1)XM to (N+2)XM-1 are mapped to the VRMT N+1, the addresses from (2N-2)XM to (2N-1)XM-1 are mapped to the VRMT 2N-2, and the addresses from (2N-1)XM to 2NXM-1 are mapped to the VRMT 2N-1.

[0144] In the perspective of the core die 2, the storage units on the core die 3 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1, the addresses from 3NXM to (3N+1)XM-1 are mapped to the VRMT 2N, the addresses from (3N+1)XM to (3N+2)XM-1 are mapped to the VRMT 2N+1, the addresses from (4N-2)XM to (4N-1)XM-1 are mapped to the VRMT 3N-2, and the addresses from (4N-1)XM to 4NXM-1 are mapped to the VRMT 3N-1.

[0145] The storage access corresponding to the storage address on the core die 2 is sent to the storage unit on the core die 2 through the interleaving algorithm, and the storage access corresponding to the storage address on the other core die is sent to the D2D bound with the VRMT.

[0146] It is worth noting that the VRMT is not located on the core die 2 and is invisible to the computing unit on the core die 2, and the VRMT is shown in a black frame in the figure; in the perspective of the core die 2, the storage units for the same address access are consistent in the core die 0 and the core die 1.

[0147] Figure 17A structure diagram of a distributed storage unit access system under a die 3 perspective is provided for an embodiment of the present application, as shown in the figure. Figure 17 As shown in the figure, under the die 3 perspective, the N storage units (MEM 0, MEM 1, …, MEM N-2, MEM N-1) in the die 3 are local storage units (LMT), namely: LMT 0, LMT 1, …, LMT N-2, LMT N-1; the storage units of the die 0, the die 1 and the die 2 are all virtual remote storage units (VRMT), namely: VRMT 0, …, VRMT N-1, …, VRMT N, …, VRMT 2N-1, …, VRMT 2N, …, VRMT 3N-1.

[0148] Specifically, for the die 3, in order to realize the unified address memory access, the access will be interleaved in the order of {VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1, LMT 0, LMT 1, …, LMT N-2, LMT N-1}, namely: according to the address of the accessed storage unit and the specific interleaving algorithm, the access of the storage unit is evenly distributed on {VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1, LMT 0, LMT 1, …, LMT N-2, LMT N-1}. For LMT 0 to LMT N-1, the present application sends the corresponding access request to the corresponding storage unit of the die (the die 2); and for VRMT 0 to VRMT 3N-1, the present application sends the corresponding access request to the D2D, and routes to other dies (the die 0, the die 1 and the die 2) through the D2D until the final storage unit.

[0149] It is worth noting that the address interleaving of the address access request is performed on the on-chip interconnection network, and the on-chip interconnection network and the computing unit are not shown in the figure for the convenience of clearly showing the diagram.

[0150] Figure 18 A storage address distribution diagram after interleaving under a die 3 perspective is provided for an embodiment of the present application, as shown in the figure. Figure 18 ​

[0151] In the perspective of the core die 3, the storage units on the core die 3 are local storage units, and the local storage units are respectively: LMT 0, LMT 1, …, LMT N-2, LMT N-1, the addresses from 3NXM to (3N+1)XM-1 are mapped to LMT 0, the addresses from (3N+1)XM to (3N+2)XM-1 are mapped to LMT 1, the addresses from (4N-2)XM to (4N-1)XM-1 are mapped to LMT N-2, and the addresses from (4N-1)XM to 4NXM-1 are mapped to LMT N-1.

[0152] In the perspective of the core die 3, the storage units on the core die 0 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT 0, VRMT 1, …, VRMT N-2, VRMT N-1, the addresses from 0XM to 1XM-1 are mapped to VRMT 0, the addresses from 1XM to 2XM-1 are mapped to VRMT 1, the addresses from (N-2)XM to (N-1)XM-1 are mapped to VRMT N-2, and the addresses from (N-1)XM to NXM-1 are mapped to VRMT N-1.

[0153] In the perspective of the core die 3, the storage units on the core die 1 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT N, VRMT N+1, …, VRMT 2N-2, VRMT 2N-1, the addresses from NXM to (N+1)XM-1 are mapped to VRMT N, the addresses from (N+1)XM to (N+2)XM-1 are mapped to VRMT N+1, the addresses from (2N-2)XM to (2N-1)XM-1 are mapped to VRMT 2N-2, and the addresses from (2N-1)XM to 2NXM-1 are mapped to VRMT 2N-1.

[0154] In the perspective of the core die 3, the storage units on the core die 2 are virtual remote storage units, and the virtual remote storage units are respectively: VRMT 2N, VRMT 2N+1, …, VRMT 3N-2, VRMT 3N-1, the addresses from 2NXM to (2N+1)XM-1 are mapped to VRMT 2N, the addresses from (2N+1)XM to (2N+2)XM-1 are mapped to VRMT 2N+1, the addresses from (3N-2)XM to (3N-1)XM-1 are mapped to VRMT 3N-2, and the addresses from (3N-1)XM to 3NXM-1 are mapped to VRMT 3N-1.

[0155] The storage access corresponding to the storage address on the core die 3 is sent to the storage unit on the core die 3 through the interleaving algorithm; the storage access corresponding to the storage address on the other core die is sent to the D2D bound with the VRMT through the interleaving algorithm.

[0156] It is worth noting that the VRMT is not located on the core die 3 and is invisible to the computing unit on the core die 3, and the VRMT is shown in a black frame in the figure; in the perspective of the core die 3, the storage unit for the same address access is consistent in the core die 0, the core die 1 and the core die 2.

[0157] In summary, by dividing the LMT and the VRMT for the storage units distributed on different core dies in the perspective of each core die, a unified storage unit organization can be formed, so that unified memory access can be realized.

[0158] It is worth noting that the acquisition, storage, use, processing and the like of data in the technical solutions in the present application comply with the relevant provisions of laws and regulations. The user information in the embodiments of the present application is obtained through a legal and compliant way, and the acquisition, storage, use, processing and the like of the user information are authorized and agreed by the client.

[0159] It is worth noting that the information collected in the present application is information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data comply with the relevant laws, regulations and standards of the country and region, necessary security measures are taken, do not violate public order and good customs, and provide corresponding operation entrances for the user to choose authorization or refusal.

[0160] It is worth noting that the technical solutions provided by the present application provide corresponding operation entrances for the user to choose to agree or refuse the automatic decision result; if the user chooses to refuse, the expert decision process is entered.

[0161] The technical scheme of the distributed storage unit access method provided by the embodiment of the application comprises the following steps: a computing unit initiates a storage address access request to an on-chip interconnection network; the on-chip interconnection network interleaves a storage address indicated by the storage address access request, and generates an interleaved storage address distribution; the on-chip interconnection network determines a target storage unit corresponding to the storage address access request according to the interleaved storage address distribution, and sends the storage address access request to a memory controller in a corresponding modular integrated circuit unit; the memory controller sends the storage address access request to the target storage unit, and the target storage unit is a target local storage unit or a target virtual remote storage unit; the storage unit comprises a local storage unit and a virtual remote storage unit, the local storage unit is distributed on a current modular integrated circuit unit, and the virtual remote storage unit is distributed on a modular integrated circuit unit other than the current modular integrated circuit unit; by setting the local storage unit and the virtual remote storage unit, unified address access and load balancing of the distributed storage units on multiple cores are realized by using address interleaving technology and virtual storage mapping, unified memory access to the computing system is ensured, access delay of each storage unit is balanced, complexity is reduced, resource utilization is improved, and the performance and ease of use of the distributed storage system are improved.

[0162] The system, module or unit illustrated in the above embodiment can be specifically implemented by a computer chip or entity, or by a product having certain functions. A typical implementation device is a computer device, and specifically, the computer device can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an electronic mail device, a game console, a tablet computer, a wearable device or a combination of any of these devices.

[0163] The embodiment of the application provides a computer device comprising the distributed storage unit access system described above, and specific descriptions can be referred to the above-described embodiments of the distributed storage unit access system.

[0164] Reference is made below to Figure 19 which shows a structural schematic diagram of a computer device 600 suitable for being used to implement the embodiments of the application.

[0165] As Figure 19As shown, the computer device 600 includes a central processing unit (CPU) 601 which can perform various appropriate works and processes according to programs stored in a read only memory (ROM) 602 or programs loaded from a storage section 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the computer device 600 are also stored. The CPU 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0166] Connected to the I / O interface 605 are an input section 606 including a keyboard, a mouse, and the like; an output section 607 including a display device such as a cathode ray tube (CRT), a liquid crystal display (LCD), and the like, and a speaker, and the like; a storage section 608 including a hard disk, and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, and the like. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as necessary. A removable recording medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like is attached to the drive 610 as necessary, so that a computer program read therefrom is installed in the storage section 608 as necessary.

[0167] For the convenience of description, the above device is described in various units by function and is described separately. Of course, the functions of the units can be implemented in hardware when implementing the present application.

[0168] It should also be noted that the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles, or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or other elements inherent to such processes, methods, articles, or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article, or device including the element.

[0169] The acquisition, storage, use, processing, and the like of data in the technical solutions of the present application comply with the relevant provisions of national laws and regulations.

[0170] It should be noted that in the embodiments of the present application, some software, components, models, and the like of the prior art can be mentioned, which should be considered as exemplary, and the purpose is only to illustrate the feasibility of the implementation of the technical solutions of the present application, but does not mean that the applicant has or will necessarily use the scheme.

[0171] Those skilled in the art will appreciate that embodiments of the application can be devised for a method or system. Accordingly, the present application can take the form of an entirely hardware embodiment or an embodiment combining software and hardware aspects.

[0172] Various embodiments in the present specification are described in progressive manner, and the same or similar parts between embodiments can be mutually referred to, and each embodiment focuses on the difference from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiments.

[0173] The above only describes the embodiments of the present application and is not intended to limit the present application. Various modifications and changes can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the claims of the present application.

Claims

1. A modular integrated circuit unit, characterized by The modular integrated circuit unit comprises at least one computing unit, at least one memory controller, at least one on-chip interconnection network and at least one storage unit; The memory controller is configured to send a storage address access request sent by the on-chip interconnection network to the storage unit; The storage unit is configured to provide uniform memory access for the storage address access request sent by the memory controller, and the storage unit comprises local storage units and virtual remote storage units, the local storage units are distributed on the current modular integrated circuit unit, the virtual remote storage units are distributed on the modular integrated circuit units other than the current modular integrated circuit unit, and the virtual remote storage units are invisible to the current modular integrated circuit unit; The computing unit is configured to initiate the storage address access request; The on-chip interconnection network is configured to interleave a storage address indicated by the storage address access request sent by the computing unit to generate an interleaved storage address distribution, determine a target storage unit corresponding to the storage address access request according to the interleaved storage address distribution, and send the storage address access request to the target storage unit through the memory controller, the target storage unit being a target local storage unit or a target virtual remote storage unit; The on-chip interconnection network is specifically configured to divide the storage address according to a preset interleave granularity to obtain a plurality of interval storage address distributions, uniformly map the plurality of interval storage address distributions to different storage units on different modular integrated circuit units to obtain the interleaved storage address distribution, and the interleaved storage address distribution comprises a number identifier of the plurality of storage units and a storage address distribution of each storage unit corresponding to an interval; based on the number identifier of the storage unit, the distribution order of the interleaved storage address distribution is taken as a matching order, if a target local storage unit corresponding to the interval storage address mapped by the indicated storage address is matched, the determined target local storage unit is determined as the target local storage unit; if a virtual remote storage unit corresponding to the interval storage address mapped by the indicated storage address is matched according to the interleaved storage address distribution, the matched virtual remote storage unit is determined as the target virtual remote storage unit; and a corresponding bound interconnection interface is determined according to the target virtual remote storage unit, the interconnection interface being a target interconnection interface, and the target interconnection interface being used for communication between the modular integrated circuit units. The on-chip interconnection network stores the interconnection interface bound by each storage unit, and the binding relationship between the virtual remote storage unit and the interconnection interface is visible to the modular integrated circuit unit.

2. The modular integrated circuit cell of claim 1, wherein, The modular integrated circuit unit is a core particle in a multi-core particle package or a chip in a computing system composed of independent chips.

3. The modular integrated circuit cell of claim 1, wherein, The on-chip interconnection network is specifically configured to send, according to the interleaved storage address distribution, a storage address access request distributed on a current modular integrated circuit unit where the on-chip interconnection network is located to a target local storage unit through the memory controller, or send a storage address access request distributed on a modular integrated circuit unit other than the current modular integrated circuit unit where the on-chip interconnection network is located to a target virtual remote storage unit through an interconnection interface.

4. A method of accessing distributed storage units, characterized by, The method comprises: The computing unit initiates a storage address access request to the on-chip interconnection network; The on-chip interconnection network interleaves the storage address indicated by the storage address access request, and generates an interleaved storage address distribution; The on-chip interconnection network determines a target storage unit corresponding to the storage address access request according to the interleaved storage address distribution, and sends the storage address access request to a memory controller in the corresponding modular integrated circuit unit; The memory controller sends the storage address access request to the target storage unit, which is a target local storage unit or a target virtual remote storage unit; The storage unit comprises a local storage unit and a virtual remote storage unit, the local storage unit is distributed on the current modular integrated circuit unit, the virtual remote storage unit is distributed on a modular integrated circuit unit other than the current modular integrated circuit unit, and the virtual remote storage unit is invisible to the current modular integrated circuit unit; The on-chip interconnection network interleaves the storage address indicated by the storage address access request, and generates an interleaved storage address distribution, which comprises: The on-chip interconnection network divides the storage address according to a preset interleaving granularity, obtains a plurality of interval storage address distributions, uniformly maps the plurality of interval storage address distributions to different storage units on different modular integrated circuit units, and obtains an interleaved storage address distribution, the interleaved storage address distribution comprises a number identifier of each storage unit and a storage address distribution of a corresponding interval of each storage unit; based on the number identifier of the storage unit, the distribution order of the interleaved storage address distribution is taken as a matching order, if the target local storage unit corresponding to the mapped storage address of the interval is matched according to the indicated storage address, the determined target local storage unit is determined as the target local storage unit; if the virtual remote storage unit corresponding to the mapped storage address of the interval is matched according to the indicated storage address, the matched virtual remote storage unit is determined as the target virtual remote storage unit; a corresponding bound interconnection interface is determined according to the target virtual remote storage unit, the interconnection interface is a target interconnection interface, and the target interconnection interface is used for communication between modular integrated circuit units; The on-chip interconnection network stores the interconnection interface bound to each storage unit, and the binding relationship between the virtual remote storage unit and the interconnection interface is visible to the modular integrated circuit unit.

5. The method of claim 4, wherein, The on-chip interconnection network sends the storage address access request to the memory controller in the corresponding modular integrated circuit unit according to the interleaved storage address distribution, which comprises: The on-chip interconnection network sends the storage address access request distributed on the current modular integrated circuit unit to the corresponding memory controller, or sends the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit to the memory controller in the corresponding modular integrated circuit unit through the interconnection interface.

6. The method of claim 5, wherein, The interleaved storage address distribution comprises a storage address distribution of a corresponding interval of each storage unit; The on-chip interconnection network sends the storage address access request distributed on the current modular integrated circuit unit to the corresponding memory controller according to the interlaced storage address distribution, and the method comprises the steps of: The on-chip interconnection network matches the storage address indicated by the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit with the storage address distribution of each storage unit corresponding interval in the storage address distribution, determines the target remote modular integrated circuit unit binding target interconnection interface, and sends the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit to the target remote modular integrated circuit unit through the target interconnection interface.

7. The method of claim 6, wherein, The memory controller sends the storage address access request to the target storage unit. The on-chip interconnection network stores the interconnection interface bound by each storage unit.

8. The method of claim 6, wherein, The on-chip interconnection network matches the storage address indicated by the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit with the storage address distribution of each storage unit corresponding interval in the storage address distribution, determines the target remote modular integrated circuit unit binding target interconnection interface, and sends the storage address access request distributed on the modular integrated circuit unit other than the current modular integrated circuit unit to the target remote modular integrated circuit unit through the target interconnection interface. The memory controller sends the storage address access request to the target storage unit. The memory controller sends the storage address access request to the target virtual remote storage unit. The system comprises a plurality of modular integrated circuit units according to any one of claims 1-3, and the plurality of modular integrated circuit units are communicatively connected through interconnection interfaces, wherein the interconnection interfaces comprise inter-chiplet interconnection interfaces or inter-chip interconnection interfaces.

9. The method of claim 8, wherein, If the modular integrated circuit unit is a chiplet in a multi-chiplet package, the chiplets are communicatively connected through inter-chiplet interconnection interfaces. If the modular integrated circuit unit is a chip in a computing system composed of independent chips, the chips are communicatively connected through inter-chip interconnection interfaces.

10. A distributed storage unit access system, characterized by, The distributed storage unit access system comprises the modular integrated circuit unit according to claim 10. The distributed storage unit access system comprises the modular integrated circuit unit according to claim 10. ​ 11. A computer device, comprising: ​

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