Circuit simulation optimization method

Abstract

The invention relates to a circuit simulation optimization method, and the method comprises the steps: obtaining the circuit information of a target circuit according to a netlist file of the target circuit, and the circuit information comprises the circuit topology and circuit parameters of the target circuit; injecting a noise model into a target node of the circuit topology to obtain updated circuit information; circuit simulation is carried out on the updated circuit information, a simulation result is obtained, and the simulation result comprises an output signal waveform of an output node of the target circuit; and optimizing and adjusting the circuit information according to a simulation result until the simulation result of the updated circuit information reaches an expected effect. According to the embodiment of the invention, the anti-interference efficiency of the target circuit can be improved, automatic optimization of simulation design is realized, and the anti-interference capability of the target circuit is improved more efficiently.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic design automation technology, and particularly to a circuit simulation optimization method. Background Art

[0002] Analog circuits play an important role in modern electronic systems and are widely used in fields such as communication, automotive electronics, medical devices, and industrial control. However, with the increase in circuit complexity, the impact of external electromagnetic interference (EMI) on circuit performance has become increasingly significant, and electrical fast transient burst (EFT) is a typical form of interference. EFT usually originates from the switching operations of inductive loads (such as relays, switching power supplies), and is conducted to the circuit through power lines or signal lines, which may cause voltage fluctuations, signal distortion, and logic errors.

[0003] The current anti-interference process mainly relies on manual simulation and debugging, with low efficiency and difficulty in covering the multi-parameter design space. Moreover, the existing methods are difficult to dynamically adjust circuit design parameters according to changes in the EFT noise environment. EDA tools are also mostly used for circuit simulation, lacking a close combination with optimization algorithms and being difficult to achieve design automation.

[0004] In view of this, it is necessary to propose a new circuit simulation optimization method to improve the anti-interference efficiency, achieve simulation design automation, and enhance the anti-interference ability of the target circuit. Summary of the Invention

[0005] In view of this, the present disclosure proposes a circuit simulation optimization method, which includes:

[0006] Obtaining circuit information of the target circuit according to the netlist file of the target circuit, where the circuit information includes the circuit topology and circuit parameters of the target circuit;

[0007] Injecting a noise model into the target node of the circuit topology to obtain updated circuit information;

[0008] Performing circuit simulation on the updated circuit information to obtain a simulation result, where the simulation result includes the output signal waveform of the output node of the target circuit;

[0009] Optimally adjusting the circuit information according to the simulation result until the simulation result of the updated circuit information reaches the expected effect.

[0010] In a possible implementation manner, the simulation result of the updated circuit information reaching the expected effect includes at least one of the following:

[0011] The voltage fluctuation of the output signal of the output node is reduced to a preset voltage range;

[0012] The frequency offset of the output signal of the output node is reduced to a preset frequency offset range;

[0013] The total harmonic distortion of the output signal of the output node is reduced to a preset percentage range.

[0014] In a possible implementation, the optimizing and adjusting the circuit information according to the simulation result until the simulation result of the updated circuit information reaches the expected effect includes:

[0015] Determine at least one target circuit parameter among the circuit parameters;

[0016] Adjust the target circuit parameter by using a preset optimization model until the simulation result of the updated circuit information reaches the expected effect.

[0017] In a possible implementation, the preset optimization model is obtained based on one or more of a neural network, a genetic algorithm, a particle swarm optimization algorithm, and a stochastic algorithm.

[0018] Among them, adjusting the target circuit parameter by using a preset optimization model includes:

[0019] Input the circuit information and the target circuit parameter into the preset optimization model, and determine the adjusted target circuit parameter by using the output result of the preset optimization model.

[0020] In a possible implementation, the adjusting the target circuit parameter by using a preset optimization model includes:

[0021] For the target circuit parameter, randomly generate multiple groups of initial parameter combinations;

[0022] Obtain the fitness corresponding to each group of parameters according to at least one of the voltage fluctuation, frequency offset, and total harmonic distortion of the output signal of the output node and the corresponding weight coefficient;

[0023] Use the initial parameter combinations with fitness greater than the preset fitness as parents, and perform crossover and mutation on the parents to generate offspring parameter combinations;

[0024] Based on the offspring parameter combinations, obtain the updated circuit information, and re-execute the steps of circuit simulation and subsequent steps for the updated circuit information until the fitness is reduced to the preset range or the number of iterations reaches the preset number of times.

[0025] In a possible implementation, the fitness function is:

[0026] F = ω1·Ripple + ω2·Δf + ω3·THD,

[0027] Among them, F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation Ripple of the output signal of the output node, ω2 represents the weight coefficient corresponding to the frequency offset Δf of the output signal of the output node, and ω3 represents the weight coefficient corresponding to the total harmonic distortion THD of the output signal of the output node.

[0028] In a possible implementation manner, the adjusting the target circuit parameters by using the preset optimization model includes:

[0029] Generating multiple groups of initial parameter combinations randomly for the target circuit parameters;

[0030] Obtaining the fitness corresponding to each group of parameters according to at least one of the voltage fluctuation of the output signal of the target circuit in simulation, the voltage fluctuation of the output signal of the physical circuit with the same structure as the target circuit in actual operation, the frequency offset, and the total harmonic distortion, and the corresponding weight coefficients;

[0031] Selecting the initial parameter combinations with fitness greater than the preset fitness as parents, and performing crossover and mutation to generate offspring parameter combinations,

[0032] Based on the offspring parameter combinations, obtaining the updated circuit information, and re-executing the steps of circuit simulation and subsequent steps for the updated circuit information until the fitness drops to the preset range or the number of iterations reaches the preset number.

[0033] In a possible implementation manner, the fitness function is:

[0034] F = ω1·(α·Ripple sim +(1 - α)·Ripple measured ) + ω2·Δf measured +

[0035] ω3·THD measured ,

[0036] Among them, F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation of the output signal, Ripple sim represents the voltage fluctuation of the output signal in simulation, Ripple measured represents the voltage fluctuation of the output signal in actual operation, α represents the weight coefficient of the voltage fluctuation of the output signal in the simulation data, (1 - α) represents the weight coefficient of the voltage fluctuation of the output signal in the actual operation data, ω2 represents the weight coefficient corresponding to the frequency offset Δf measured of the output signal in actual operation, and ω3 represents the weight coefficient corresponding to the total harmonic distortion THD measured of the output signal in actual operation.

[0037] In a possible implementation, the method further includes:

[0038] Establish an EFT noise source according to a preset noise source establishment standard;

[0039] Modify the EFT noise source according to historical measured data to establish the noise model, where the historical measured data is obtained from the measured noise waveform signal of a physical circuit with the same circuit structure as the target circuit.

[0040] In a possible implementation, the modifying the EFT noise source according to historical measured data includes:

[0041] Extract features from the historical measured data to obtain a target feature combination, and each feature parameter in the target feature combination is related to EFT noise;

[0042] Perform data processing on each feature parameter in the target feature combination;

[0043] Determine at least one correction parameter according to the processed target feature combination and preset simulation data, and use the correction parameter to correct the EFT noise source, where the correction parameter represents the noise signal deviation between the actual operation and the simulation operation of the target circuit, and the correction coefficient includes a waveform rise time correction parameter and a peak voltage correction coefficient.

[0044] According to an aspect of the present disclosure, there is provided a circuit simulation optimization device, the device includes:

[0045] An acquisition module, configured to acquire circuit information of a target circuit according to a netlist file of the target circuit, where the circuit information includes the circuit topology and circuit parameters of the target circuit;

[0046] An injection module, configured to inject a noise model into a target node of the circuit topology to obtain updated circuit information;

[0047] A simulation module, configured to perform circuit simulation on the updated circuit information to obtain a simulation result, where the simulation result includes the output signal waveform of an output node of the target circuit;

[0048] An optimization module, configured to optimize and adjust the circuit information according to the simulation result until the simulation result of the updated circuit information reaches the expected effect.

[0049] Embodiments of the present disclosure obtain circuit information of a target circuit according to a netlist file of the target circuit, inject a noise model into a target node of the circuit topology to obtain updated circuit information, which can improve the anti-interference efficiency of the target circuit, perform circuit simulation on the updated circuit information to obtain a simulation result, and optimize and adjust the circuit information according to the simulation result, which can realize automatic optimization of the simulation design, thereby more efficiently improving the anti-interference ability of the target circuit.

[0050] Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings included in and constituting a part of this specification, together with the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and are used to explain the principles of the present disclosure.

[0052] Figure 1 FIG. shows a flowchart of a circuit simulation optimization method according to an embodiment of the present disclosure.

[0053] Figure 2 FIG. shows a flowchart of a circuit simulation optimization method according to an embodiment of the present disclosure.

[0054] Figure 3 FIG. shows a schematic diagram of correcting the EFT noise source in a circuit simulation optimization method according to an embodiment of the present disclosure.

[0055] Figure 4 FIG. shows a schematic diagram of adjusting a target circuit according to an embodiment of the present disclosure.

[0056] Figure 5 FIG. shows a block diagram of a circuit simulation optimization device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0058] As used herein, the terms "comprising", "including", "having", or variations thereof are open-ended and include one or more stated features, wholes, elements, steps, components, or functions, but do not exclude the existence or addition of one or more other features, wholes, elements, steps, components, functions, or groups thereof.

[0059] When an element is referred to as being "connected", "coupled", "responsive" or variations thereof to another element, it can be directly connected, coupled or responsive to the other element, or intervening elements may be present.

[0060] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Thus, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments without departing from the teachings of the inventive concept.

[0061] As used herein, the term "exemplary" means "serving as an example, instance, or illustration". Any embodiment described herein as "exemplary" should not necessarily be construed as superior to or better than other embodiments.

[0062] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present disclosure can be implemented without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0063] Please refer to Figure 1 , Figure 1 which shows a flowchart of a circuit simulation optimization method according to an embodiment of the present disclosure.

[0064] As Figure 1 shown, the method includes:

[0065] Step S11, obtaining circuit information of the target circuit according to a netlist file of the target circuit, where the circuit information includes a circuit topology and circuit parameters of the target circuit;

[0066] Step S12, injecting a noise model into a target node of the circuit topology to obtain updated circuit information;

[0067] Step S13, performing circuit simulation on the updated circuit information to obtain a simulation result, where the simulation result includes an output signal waveform of an output node of the target circuit;

[0068] Step S14, optimizing and adjusting the circuit information according to the simulation result until the simulation result of the updated circuit information reaches an expected effect.

[0069] In an embodiment of the present disclosure, circuit information of a target circuit is obtained according to a netlist file of the target circuit, a noise model is injected into a target node of the circuit topology to obtain updated circuit information, the actual interference is simulated by using the noise model, the anti-interference efficiency of the target circuit can be improved, circuit simulation is performed on the updated circuit information to obtain a simulation result, and the circuit information is optimized and adjusted according to the simulation result, so that automatic optimization of the simulation design can be realized, and thus the anti-interference ability of the target circuit can be improved more efficiently.

[0070] The embodiments of the present disclosure do not limit the specific implementation manners of each step, and those skilled in the art can adopt appropriate technical means according to the actual situation and needs.

[0071] The embodiments of the present disclosure do not limit the type of the target circuit, and those skilled in the art can set it according to the actual situation and needs. For example, the target circuit can be various types of analog circuits, such as an RC oscillator.

[0072] The embodiments of the present disclosure do not limit the specific implementation manner of obtaining the circuit information of the target circuit according to the netlist file of the target circuit in step S11, and those skilled in the art can adopt appropriate technical means according to the actual situation and needs.

[0073] The embodiments of the present disclosure do not limit the acquisition method and format of the netlist file. The netlist format can include SPICE format, Spectre format, etc. The embodiments of the present disclosure can export the netlist file of the target circuit through various types of electronic design automation (EDA) tools. Among them, the EDA tools include, for example, Cadence Virtuoso, Altium Designer, Cadence OrCAD, PSpice, etc. These tools can perform operations such as circuit schematic design, PCB (printed circuit board) design, and circuit simulation. After the circuit design is completed, the netlist file can be exported by using its built-in function, or the circuit design file stored in the memory can be imported into the EDA tool, and the corresponding netlist file can be exported by using the EDA tool.

[0074] Among them, the netlist file is a text format file that records information such as the connection relationship and component parameters of each component in the circuit, and is an important intermediate file for the circuit design from the schematic diagram to subsequent manufacturing, simulation and other links. The netlist file formats generated by different EDA tools may be different, but basically all contain two parts: component definition and connection relationship description. For example, in a SPICE netlist file, components are defined in a specific statement format. For example, the resistor component "R1 1 2 10k" represents a resistor named R1, connecting node 1 and node 2, with a resistance value of 10 kiloohms; the node is used to identify the connection point of the component pins in the circuit.

[0075] Exemplarily, the content of the netlist file can be read by writing a program (such as using scripting languages like Python or Perl). According to the file format rules, the component names, connected node information, etc. can be identified, and then data structures (such as graph structures, linked lists, etc.) can be used to store and represent these connection relationships. For example, the NetworkX library in Python can be used to conveniently construct and process the circuit topology graph, regarding components as nodes and the connections between components as edges. Among them, circuit parameters refer to the specific parameter values of each component in the circuit, such as the resistance value of a resistor, the capacitance value of a capacitor, the size and model parameters of a transistor, etc. Similarly, by reading the netlist file and finding the definition part of the component parameters according to the file format, the corresponding parameter values can be extracted. For some complex component models, it may be necessary to further parse the relevant model parameter files. For example, in a SPICE netlist, the transistor model parameters are given in specific model definition statements and need to be extracted according to the rules. Therefore, through the netlist file exported from the EDA tool in the embodiments of the present disclosure, the circuit topology and parameter configuration of the target circuit can be extracted.

[0076] It should be understood that the noise model can be established in advance according to the actual situation and needs. When it is necessary to perform simulation optimization on the target circuit, the already established noise model can be directly called. Of course, the noise model can also be established in real time during simulation optimization, and the embodiments of the present disclosure do not make any limitations in this regard.

[0077] The embodiments of the present disclosure do not limit the specific implementation manner of injecting the noise model into the target node of the circuit topology in step S12, nor do they limit the specific selection manner of the target node, and those skilled in the art can set it according to the actual situation and needs. Exemplarily, the target node can be a key node or path in the circuit topology. For example, the power input terminal, signal transmission path, etc. Of course, the specific target node can be selected according to needs.

[0078] Exemplarily, in the embodiments of the present disclosure, an automated script can be used to identify the target node of the circuit topology by the noise model and add the noise model to the target node, so as to use the noise model to affect the circuit performance of the target node and realize the simulation of noise interference. Among them, "injection" in the embodiments of the present disclosure can refer to adding the noise model to the target node and superimposing the noise signal on the target node.

[0079] The embodiments of the present disclosure do not limit the type and establishment method of the noise model, and those skilled in the art can set it according to the actual situation and needs. For example, an EFT noise model can be established for electrical fast transient pulse groups (EFT) to improve the efficiency of the target circuit against EFT interference, realize automatic optimization of the simulation design, and thus more efficiently improve the EFT interference resistance ability of the target circuit.

[0080] An exemplary introduction to the establishment of the noise model is given below.

[0081] Please refer to Figure 2 , Figure 2 which shows a flowchart of a circuit simulation optimization method according to an embodiment of the present disclosure.

[0082] In a possible implementation manner, as Figure 2 shown, the method may further include:

[0083] Step S100, establishing an EFT noise source according to a preset noise source establishment standard;

[0084] Step S200, correcting the EFT noise source according to historical measured data to establish the noise model, where the historical measured data is obtained from the measured noise waveform signal of a physical circuit having the same target circuit structure.

[0085] In the embodiment of the present disclosure, an EFT noise source is established according to a preset noise source establishment standard, and then the EFT noise source is corrected according to historical measured data to establish the noise model, which can make the noise model closer to the actual situation and further improve the anti-EFT effect of the target circuit.

[0086] The embodiment of the present disclosure does not limit the selection of the preset noise source establishment standard, and those skilled in the art can select according to the actual situation and needs. For example, the preset noise source establishment standard can be the international standard IEC61000-4-4, etc.

[0087] Exemplarily, embodiments of the present disclosure may first generate a standard EFT noise source according to the international standard IEC61000-4-4. The pulse width, repetition frequency, duration, amplitude range, etc. of the EFT noise source can be set according to the actual situation and requirements, as long as it is within the fixed range of this standard. Among them, the international standard IEC61000-4-4 stipulates that the rise time of a single EFT pulse is (5±1.5) ns, and the pulse duration is (50±15) ns. This means that the time for the pulse to rise from the starting amplitude to the peak is between 3.5 ns and 6.5 ns, and the duration for the entire pulse to maintain a certain amplitude is between 35 ns and 65 ns. The repetition frequency range is usually (5k±20%) Hz or (100k±20%) Hz. In general tests, the duration of a single EFT pulse train is 15 ms±3 ms (5 kHz), 0.75 ms±0.15 ms (100 kHz), which ensures that it consists of 75 pulses in a group, repeats every 300 ms, and has a duration of one minute. Positive and negative polarity EFT pulses are injected during the test. The open-circuit voltage level of the EFT noise source can be set to 0.5 kV, 1 kV, 2 kV, 4 kV for the power port; 0.25 kV, 0.5 kV, 1 kV, 2 kV for the signal / control port. Referring to the basic technical index content of the pulse generator, in order to pursue the transience of the pulse, the rise time and fall time are set as short as possible, the pulse duration is set as long as possible, and circuit simulation software (such as Virtuoso, PSpice, LTspice, etc.) is used to simulate and generate an EFT signal that meets the standard by setting parameters and simulation conditions for the EFT noise generation circuit.

[0088] Embodiments of the present disclosure introduce historical measured data to specifically correct the noise transmission path. Of course, embodiments of the present disclosure do not limit the specific form of the historical measured data. The historical measured data may include the waveforms presented by the measured noise signals on the physical circuit, as well as the waveform signals that the physical circuit may output, etc.

[0089] Embodiments of the present disclosure do not limit the specific implementation manner of correcting the EFT noise source according to historical measured data in step S200 and establishing the noise model. Those skilled in the art can adopt appropriate technical means according to the actual situation and requirements as long as they can correct the EFT noise source using historical measured data.

[0090] The embodiments of the present disclosure can perform multiple simulation optimizations on the target circuit. Exemplarily, for the first simulation optimization of the target circuit, a physical circuit of the target circuit can be manufactured first to obtain historical measured data for the first simulation optimization (for example, the output signal of the physical circuit can be compared with the rated signal to obtain the waveform of the noise signal); after the first optimization is completed (the simulation result in this simulation optimization reaches the expected effect), a physical circuit of the target circuit after the first optimization is manufactured, and historical measured data for the second simulation optimization is obtained to perform the second simulation optimization. By performing multiple simulation optimizations in this way, the embodiments of the present disclosure can iteratively optimize the anti-interference performance of the target circuit and gradually improve the anti-interference performance of the target circuit.

[0091] Please refer to Figure 3 , Figure 3 which shows a schematic diagram of correcting the EFT noise source in the circuit simulation optimization method according to an embodiment of the present disclosure.

[0092] In a possible implementation manner, as Figure 3 shown, step S200 of correcting the EFT noise source according to the historical measured data may include:

[0093] Step S201, extracting features from the historical measured data to obtain a target feature combination, where each feature parameter in the target feature combination is related to the EFT noise;

[0094] Step S202, performing data processing on each feature parameter in the target feature combination;

[0095] Step S203, determining at least one correction parameter according to the processed target feature combination and preset simulation data, and correcting the EFT noise source by using the correction parameter, where the correction parameter represents the noise signal deviation between the actual operation and the simulation operation of the target circuit, and the correction coefficient includes a waveform rise time correction parameter and a peak voltage correction coefficient.

[0096] Exemplarily, the target feature combination may include parameters such as the frequency, amplitude, and phase of the signal. Of course, it may also include the response characteristics of the physical circuit under different working conditions. Through signal processing techniques such as Fourier Transform and wavelet transform, the time-domain signal can be converted into a frequency-domain signal, so as to more intuitively analyze the frequency components and energy distribution of the signal. Exemplarily, the waveform data can be stored in CSV or TXT format.

[0097] The embodiments of the present disclosure do not limit the specific manner of feature extraction. Those skilled in the art can adopt appropriate technical solutions according to the actual situation and needs. For example, feature extraction can be performed through devices such as oscilloscopes and spectrum analyzers.

[0098] The embodiments of the present disclosure do not limit the specific manner of data processing. Exemplarily, the data processing manner may include denoising, normalization processing, etc. After obtaining the key features, the embodiments of the present disclosure perform denoising processing (such as clutter denoising) and normalization processing (scaling the amplitude to the dimension corresponding to the simulation model) on the data. Of course, the data can also be cleaned to remove outliers and noise. In this way, the embodiments of the present disclosure can improve the effectiveness and reliability of the data.

[0099] The embodiments of the present disclosure do not limit the specific implementation manner of determining at least one correction parameter according to the processed target feature combination and the preset simulation data in step S203 and correcting the EFT noise source by using the correction parameter. Those skilled in the art can adopt appropriate technical means according to the actual situation and needs to implement it.

[0100] For example, the embodiments of the present disclosure can establish an objective function in advance and fit to obtain the required correction parameters; or compare the noise waveform in the simulation with the noise waveform in the physical circuit to obtain the required correction parameters through waveform comparison. Of course, a correction parameter determination model can also be established in advance, input the processed target feature combination and the preset simulation data into the correction parameter determination model, and determine the correction parameters according to the output result of the parameter determination model.

[0101] Exemplarily, the correction parameters may include time-domain features such as pulse width deviation, rise time deviation, peak voltage deviation, etc. Of course, they may also include frequency-domain features such as the amplitude difference and frequency offset of the main harmonic components. The embodiments of the present disclosure do not limit this.

[0102] Exemplarily, taking the correction coefficient k1 for the correction parameter selection of rise time deviation ΔT rise and the correction coefficient k2 for peak voltage deviation V peak as an example, an objective function as shown in Formula 1 can be constructed, where the rise time deviation ΔT rise can be the difference between the rise time of the noise signal in the simulation from a lower amplitude (such as the valley value) to a higher amplitude (such as the peak value) and the rise time of the noise signal in the physical circuit from a lower amplitude (such as the valley value) to a higher amplitude (such as the peak value). The peak voltage deviation V peak can be the difference between the peak value of the noise signal in the simulation and the peak value of the noise signal in the physical circuit.

[0103]

[0104] where N≥1 and is an integer, V sim(i) (t) represents the i-th noise signal in the simulation, and V measured(i) represents the i-th noise signal in the physical circuit.

[0105] In the embodiments of the present disclosure, various sampling methods can be used to sample the noise signals V sim(i) (t) in multiple simulations and the noise signals V measured(i) (t) in multiple physical circuits to confirm the correction parameters. For example, the embodiments of the present disclosure can use the Latin Hypercube Sampling (LHS) method to determine the number N of EFT simulation frequency samples to be extracted, divide the range of the probability distribution (usually from 0 to 1) into N equal parts with the same probability for each interval, randomly select a value in each interval, and map these sample points uniformly distributed in the (0, 1) interval to the probability distribution of the actual parameters through the inverse transformation method. Additionally, to remove the correlation between data, the sample points can be re-ordered using the method of random sorting. Using hypercube sampling can make each sample point in the frequency selection be independently selected without mutual correlation, which helps reduce the mutual influence between parameters and provides better parameter independence, avoiding repeated selection of samples and repeated simulations, optimizing complex simulation samples, and improving simulation efficiency.

[0106] Of course, this sampling method can also be applied to each step that requires data sampling. Exemplarily, using Latin hypercube sampling to extract key circuit performance indicators (such as node voltage fluctuation, signal distortion, frequency drift) and perform simulations can obtain the sample values at the tail with fewer samplings, which makes it particularly effective when dealing with large-scale data. And compared with Monte Carlo sampling, LHS reduces the number of iterations because it uses the method of uniform sampling to sample variables. The generated samples reflect the true underlying distribution and often require a much smaller sample size than simple random sampling, which can significantly improve efficiency when dealing with data with a large number of dimensions.

[0107] The embodiments of the present disclosure do not limit the specific method for calculating the correction coefficient k1 and the correction coefficient k2. Those skilled in the art can adopt a suitable method according to the actual situation and needs. For example, after sampling data using the above sampling method, the arithmetic expression of the measured waveform above can be quickly fitted by the least squares method, and the correction coefficients k1 and k2 of the objective function can be solved by the gradient descent method.

[0108] Of course, the above introduction of the objective function is exemplary and should not be regarded as a limitation to the embodiments of the present disclosure. Those skilled in the art can set the corresponding objective function according to the actual situation and needs, set the required correction coefficients, and calculate the corresponding correction coefficients using a suitable calculation method.

[0109] After injecting the noise model into the target node of the circuit topology in the embodiments of the present disclosure, the updated circuit information can be run using an EDA tool to perform circuit simulation, and the output signal waveform of the simulation output of the output node of the target circuit can be obtained. Of course, the specific simulation method is not limited in the embodiments of the present disclosure, and those skilled in the art can implement it using relevant technologies according to the actual situation and needs.

[0110] The embodiments of the present disclosure can analyze the output signal of the output node of the target circuit. For example, analyze the voltage fluctuation, frequency offset, and signal integrity (total harmonic distortion) of the output signal. For example, in a waveform viewer, measure the peak-to-peak value and the effective value of the output signal under the action of EFT noise and compare them with the threshold of the logic level. Compare the spectra of the output signal with and without EFT noise to determine whether there is a frequency offset. The frequency offset may affect the signal transmission quality and the normal operation of the circuit. The waveform shape of the output signal can be checked to observe whether there are phenomena such as distortion, overshoot, and ringing. These phenomena may affect the correct transmission of the signal and the reliability of the circuit. The rising time, falling time, and pulse width of the signal can also be measured and compared with the parameters under normal conditions to evaluate the change in signal integrity.

[0111] Exemplarily, in the case where the simulation result of the updated circuit information does not meet the expected effect, the embodiments of the present disclosure can optimize and adjust the circuit information, and perform simulation on the adjusted circuit information, and judge whether the expected effect is achieved according to the simulation operation result. This cycle continues until the simulation result of the updated circuit information reaches the expected effect or the number of iterations reaches the preset number. Here, one circuit information simulation run and the comparison between the simulation result and the expected effect are one iteration. In each iteration, if it is judged that the number of iterations has not reached the preset number and the simulation result has not reached the expected effect, the circuit information is optimized and adjusted according to the simulation result, and the next iteration is executed until the simulation result of the updated circuit information reaches the preset effect or the number of iterations has not reached the preset number.

[0112] The embodiments of the present disclosure do not limit the specific size of the number of iterations, and those skilled in the art can set it according to the actual situation and needs.

[0113] The embodiments of the present disclosure do not limit the specific setting of the expected effect, and those skilled in the art can set it according to the actual situation and needs. In one possible implementation manner, the simulation result of the updated circuit information reaching the expected effect may include at least one of the following:

[0114] The voltage fluctuation of the output signal of the output node is reduced to a preset voltage range;

[0115] The frequency offset of the output signal of the output node is reduced to a preset frequency offset range;

[0116] The total harmonic distortion of the output signal of the output node is reduced to a preset percentage range.

[0117] Of course, it can also be expected that the effect can be set according to other waveform characteristics of the output signal, such as waveform rise time, fall time, etc.

[0118] The calculation methods of voltage fluctuation, frequency offset, and total harmonic distortion are introduced exemplarily below.

[0119] Exemplarily, the maximum voltage deviation between the output signal and the rated voltage can be calculated by Formula 2 to represent the magnitude of voltage fluctuation.

[0120] Ripple=max{|V OUT -V nominal |} Formula 2

[0121] Among them, Ripple represents the maximum voltage deviation, V OUT represents the output signal, and V nominal represents the rated voltage signal.

[0122] Exemplarily, the output signal can be subjected to a fast Fourier transform FFT to extract the frequency of the output signal and compare it with the target frequency to determine the frequency offset, as shown in Formula 3.

[0123] Δf=|f measured -f nominal | Formula 3

[0124] Among them, Δf represents the magnitude of the frequency offset, f measured represents the frequency of the output signal, and f nominal represents the target frequency.

[0125] Exemplarily, the total harmonic distortion of the output signal can be determined by Formula 4.

[0126]

[0127] Among them, THD represents the total harmonic distortion, V1 is the fundamental frequency amplitude, and V2, V3, V4... are harmonic components.

[0128] It should be noted that the above formulas are exemplary and should not be regarded as a limitation of the embodiments of the present disclosure. Those skilled in the art can adjust the above formulas or use other formulas to calculate the corresponding parameters.

[0129] In a possible implementation manner, as Figure 2 shown, step S14 optimizes and adjusts the circuit information according to the simulation result until the simulation result of the updated circuit information reaches the expected effect, and may include:

[0130] Step S140, determine at least one target circuit parameter among the circuit parameters;

[0131] Step S141, use a preset optimization model to adjust the target circuit parameter until the simulation result of the updated circuit information reaches the expected effect.

[0132] The embodiments of the present disclosure do not limit the specific setting of the target circuit parameter. Those skilled in the art can set and select according to the actual situation and needs. For example, the target circuit parameter can be the capacitance value of one or more capacitors, the resistance value of one or more resistors, the inductance value of one or more inductors, etc.

[0133] The embodiments of the present disclosure do not limit the specific implementation manner of the preset optimization model. Those skilled in the art can implement it according to the actual situation and needs. For example, in a possible implementation manner, the preset optimization model is obtained based on one or more of neural networks, genetic algorithms, particle swarm optimization algorithms, random algorithms, etc.

[0134] The embodiments of the present disclosure do not limit the specific establishment manner and training manner of establishing the preset optimization model using the above algorithms. Those skilled in the art can implement it according to the relevant technologies.

[0135] In a possible implementation manner, step S141 using the preset optimization model to adjust the target circuit parameter may include:

[0136] Input the circuit information and the target circuit parameter into the preset optimization model, and use the output result of the preset optimization model to determine the adjusted target circuit parameter.

[0137] Exemplarily, the preset optimization model can be an intelligent circuit design tool based on a neural network. Taking the target circuit parameters as resistors, capacitors, inductors, etc. as an example, the preset optimization model can efficiently optimize the parameters of key components such as resistors, capacitors, and inductors by learning the mapping relationship between circuit characteristics and performance parameters. The training process of this model includes: converting the circuit information into a numerical feature vector (such as an adjacency matrix), obtaining the target parameters (such as gain, bandwidth) of the original circuit through simulation as labels, constructing a prediction model using a multi-layer perceptron or a convolutional neural network, and performing iterative training through a mean square error loss function and an Adam optimization algorithm, etc. When new circuit information and the selected target circuit parameters (such as the unique identification information of one or more resistors, capacitors, inductors) are input, the model can output the adjusted values of the resistors, capacitors, and inductors.

[0138] Exemplarily, the preset optimization model can be established by a memory genetic algorithm.

[0139] Please refer to Figure 4, Figure 4 It shows a schematic diagram of adjusting a target circuit according to an embodiment of the present disclosure.

[0140] In a possible implementation, as Figure 4 shown, step S141 of adjusting the target circuit parameters by using a preset optimization model may include:

[0141] Step S1411: For the target circuit parameters, randomly generate multiple groups of initial parameter combinations; Exemplarily, if the target circuit parameters are resistance and capacitance, the embodiments of the present disclosure may randomly generate multiple groups (such as 20 to 50 groups) of initial parameter combinations according to the preset resistance range and capacitance range. Each initial parameter combination includes a resistance value and a capacitance value. Through this step, the initialization of the population can be achieved, and each initial parameter combination represents an individual in the initialized population.

[0142] Step S1412: Obtain the fitness corresponding to each group of parameters according to at least one of the voltage fluctuation, frequency offset, and total harmonic distortion of the output signal of the output node and the corresponding weight coefficient;

[0143] Step S1414: Use the initial parameter combinations with fitness greater than the preset fitness as the parent generation, and perform crossover and mutation on the parent generation to generate offspring parameter combinations;

[0144] Step S1415: Based on the offspring parameter combinations, obtain the updated circuit information, and re - execute the steps of circuit simulation and subsequent steps for the updated circuit information until the fitness drops to the preset range or the number of iterations reaches the preset number.

[0145] Through the above method, the embodiments of the present disclosure can quickly realize the adjustment and optimization of the target circuit parameters by using the genetic algorithm.

[0146] The embodiments of the present disclosure do not limit the setting method of the fitness function. Those skilled in the art can set it according to the actual situation and needs. Exemplarily, in a possible implementation, the fitness function may be:

[0147] F = ω1·Ripple + ω2·Δf + ω3·THD,

[0148] where F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation Ripple of the output signal of the output node, ω2 represents the weight coefficient corresponding to the frequency offset Δf of the output signal of the output node, and ω3 represents the weight coefficient corresponding to the total harmonic distortion THD of the output signal of the output node.

[0149] The embodiments of the present disclosure do not limit the manner of setting each weight coefficient, and those skilled in the art may set the weight coefficient according to actual conditions and needs.

[0150] The embodiments of the present disclosure do not limit the specific methods of crossover and mutation, and those skilled in the art can refer to relevant technical implementations according to actual conditions and needs. For example, crossover can select single-point crossover, multi-point crossover, uniform crossover, etc., to explore new areas in the search space, and try to combine the excellent genes of different parent individuals, so as to find a better solution. Mutation, for example, can include bit-flip mutation, real-valued mutation, etc., to increase the diversity of the population and avoid the algorithm from converging to the local optimal solution too early during the search process. In the embodiments of the present disclosure, crossover and mutation cooperate with each other to jointly promote the evolution of the population. The crossover operation is mainly responsible for combining the excellent genes already in the current population to explore potential better solutions; while the mutation operation is responsible for introducing new gene information to prevent the algorithm from falling into the local optimum.

[0151] In one possible implementation, Figure 4 As shown, the adjusting the target circuit parameters by using a preset optimization model may include:

[0152] Step S1411, randomly generating multiple groups of initial parameter combinations for the target circuit parameters;

[0153] Step S1413, obtaining the fitness corresponding to each group of parameters according to the voltage fluctuation of the output signal of the target circuit in simulation, the voltage fluctuation of the output signal of the physical circuit with the same structure as the target circuit in actual operation, the frequency offset, at least one of the total harmonic distortion and the corresponding weight coefficient;

[0154] Step S1414, select the initial parameter combination with a fitness greater than the preset fitness as the parent generation, perform crossover and mutation to generate the offspring parameter combination,

[0155] Step S1415, obtaining updated circuit information based on the child parameter combination, re-executing circuit simulation for the updated circuit information and subsequent steps until the fitness is reduced to a preset range or the number of iterations reaches a preset number.

[0156] Compared with the method of adjusting the target circuit parameters using the preset optimization model introduced previously, this example uses a different fitness function, introduces the waveform data of the physical circuit, and reconstructs the fitness function by weighted fusion of the output signal of the physical circuit and the simulation result, which can accelerate the simulation convergence, improve the simulation efficiency, and enhance the anti-interference performance of the circuit.

[0157] In a possible implementation, the fitness function can be:

[0158] F = ω1·(α·Ripple sim +(1 - α)·Ripple measured ) + ω2·Δf measured +

[0159] ω3·THD measured ,

[0160] where F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation of the output signal, Ripple sim represents the voltage fluctuation of the output signal in the simulation, Ripple measured represents the voltage fluctuation of the output signal during actual operation, α represents the weight coefficient of the voltage fluctuation of the output signal in the simulation data, (1 - α) represents the weight coefficient of the voltage fluctuation of the output signal in the actual operation data, ω2 represents the weight coefficient corresponding to the frequency offset Δf measured of the output signal during actual operation, and ω3 represents the weight coefficient corresponding to the total harmonic distortion THD measured of the output signal during actual operation.

[0161] The specific magnitudes of the respective weight coefficients are not limited in the embodiments of the present disclosure, and those skilled in the art can set them according to actual situations and needs. Among them, the weight coefficient α of the voltage fluctuation of the output signal in the simulation data can be set to be inversely related to the number of iterations, that is, the larger the number of iterations, the smaller α, which can further accelerate the simulation convergence.

[0162] The following takes the target circuit as an RC oscillator circuit for exemplary introduction.

[0163] For the RC oscillator circuit, its netlist information includes:

[0164] Voltage source, VCC node, GND node, voltage;

[0165] R <name> <node1> <node2> <resistance value>;

[0166] C <name> <node1> <node2> <capacitance value>;

[0167] X <name> <external node list> <subcircuit name>.

[0168] Suppose the key part of the obtained RC oscillator circuit netlist file is as follows:

[0169] VDD VCC 0 DC 12V

[0170] R1 VCC N001{Rvalue}; Suppose the resistance of R1 is defined as an optimization variable

[0171] C1 N001 0{Cvalue}; Suppose the capacitance of C1 is defined as an optimization variable

[0172] XOSC N001 N002 OSC_TEMPLATE

[0173] In the above netlist, the resistance value {Rvalue} of the resistor R1 and the capacitance value {Cvalue} of the capacitor C1 are two optimizable parameters.

[0174] Exemplarily, suppose the parameters in the noise model include:

[0175] V <name> <node1> <node2>PULSE( <v1> <v2> <tf> <pw> <per> )， <v1>: Low-level voltage. Among them, the meanings of the parameters are respectively: V <name>: Noise source name; node1: Node 1; node2: Node 2; PULSE(): Noise waveform; <v1>: Low-level voltage; <v2>: High-level voltage; : Delay time; : Rise time; <tf>: Fall time; <pw>: Pulse width; <per>: Period.

[0176] Suppose a noise model obtained by the method according to an embodiment of the present disclosure is an EFT pulse voltage source defined as follows: V_EFT EFT 0 PULSE(0 2000mV 0 5ns 5ns 50ns 200us).

[0177] Exemplarily, the target nodes for noise injection can be selected:

[0178] 1. Power input terminal: Simulate the influence of EFT noise conducted to the circuit through the power supply system.

[0179] 2. Signal transmission path: Analyze the interference of noise on key signal lines.

[0180] 3. Ground loop: Evaluate the influence of ground coupling on the overall circuit performance.

[0181] The embodiment of the present disclosure can inject the noise model into the power input terminal, signal transmission path, and ground loop through a pre-written noise model injection script.

[0182] In this way, the embodiment of the present disclosure can dynamically generate a netlist file through a Python script and call an EDA tool to run a simulation.

[0183] After completing the update of the circuit information, the embodiment of the present disclosure can run a simulation tool to perform a simulation and perform multiple iterative optimizations according to the foregoing introduction.

[0184] Exemplarily, when optimizing, the optimization range can be defined:

[0185] Resistance range: 10Ω to 10kΩ;

[0186] Capacitance range: 1pF to 1μF.

[0187] According to the actual test results, in this example, the performance of the optimized RC oscillator is significantly improved in an EFT noise environment, the voltage fluctuation range changes from ±150mV to ±30mV; the frequency offset changes from ±5% to ±1%; the total harmonic distortion changes from 10% to 3%. The optimization results prove the effectiveness of the present method in a complex EFT interference environment.

[0188] The execution subject of the method may be a device. For example, the method may be executed by a terminal device, a server, or other processing devices. Among them, the terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: mobile phone (MobilePhone), tablet computer, laptop computer, palmtop computer, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control (Industrial Control), wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid (Smart Grid), wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, wireless terminal in vehicle-to-everything, etc. For example, the server may be a local server or a cloud server.

[0189] In some possible implementation manners, the method may be implemented by a processing component calling computer-readable instructions stored in a memory. In one example, the processing component includes, but is not limited to, a single processor, or discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device that has a function of executing instructions, and the processor may be implemented in any suitable manner. For example, it is implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0190] Please refer to Figure 5 , Figure 5 which shows a block diagram of a circuit simulation optimization device according to an embodiment of the present disclosure.

[0191] As Figure 5 shown, the device includes:

[0192] An acquisition module 10, configured to acquire circuit information of a target circuit according to a netlist file of the target circuit, where the circuit information includes a circuit topology and circuit parameters of the target circuit;

[0193] An injection module 20, configured to inject a noise model into a target node of the circuit topology to obtain updated circuit information;

[0194] A simulation module 30, configured to perform circuit simulation on the updated circuit information to obtain a simulation result, where the simulation result includes an output signal waveform of an output node of the target circuit;

[0195] An optimization module 40, configured to optimize and adjust the circuit information according to the simulation result until the simulation result of the updated circuit information reaches an expected effect.

[0196] In an embodiment of the present disclosure, circuit information of a target circuit is acquired according to a netlist file of the target circuit, a noise model is injected into a target node of the circuit topology to obtain updated circuit information, which can improve the anti-interference efficiency of the target circuit. Circuit simulation is performed on the updated circuit information to obtain a simulation result, and the circuit information is optimized and adjusted according to the simulation result, which can realize automatic optimization of simulation design, thereby more efficiently improving the anti-interference ability of the target circuit.

[0197] In a possible implementation manner, the simulation result of the updated circuit information reaching the expected effect includes at least one of the following:

[0198] The voltage fluctuation of the output signal of the output node is reduced to a preset voltage range;

[0199] The frequency offset of the output signal of the output node is reduced to a preset frequency offset range;

[0200] The total harmonic distortion of the output signal of the output node is reduced to a preset percentage range.

[0201] In a possible implementation manner, the optimizing and adjusting the circuit information according to the simulation result until the simulation result of the updated circuit information reaches the expected effect includes:

[0202] Determine at least one target circuit parameter in the circuit parameters;

[0203] Adjust the target circuit parameter by using a preset optimization model until the simulation result of the updated circuit information reaches the expected effect.

[0204] In a possible implementation manner, the preset optimization model is obtained based on one or more of a neural network, a genetic algorithm, a particle swarm optimization algorithm, and a random algorithm.

[0205] Among them, adjusting the target circuit parameters by using a preset optimization model includes:

[0206] Inputting the circuit information and the target circuit parameters into the preset optimization model, and determining the adjusted target circuit parameters by using the output result of the preset optimization model.

[0207] In a possible implementation manner, adjusting the target circuit parameters by using a preset optimization model includes:

[0208] Generating multiple groups of initial parameter combinations randomly for the target circuit parameters;

[0209] Obtaining the fitness corresponding to each group of parameters according to at least one of the voltage fluctuation, frequency offset, and total harmonic distortion of the output signal of the output node and the corresponding weight coefficient;

[0210] Taking the initial parameter combinations with fitness greater than the preset fitness as the parent generation, and performing crossover and mutation on the parent generation to generate offspring parameter combinations;

[0211] Based on the offspring parameter combinations, obtaining the updated circuit information, and re-executing the steps of circuit simulation and subsequent steps for the updated circuit information until the fitness drops to the preset range or the number of iterations reaches the preset number.

[0212] In a possible implementation manner, the fitness function is:

[0213] F = ω1·Ripple + ω2·Δf + ω3·THD,

[0214] Among them, F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation Ripple of the output signal of the output node, ω2 represents the weight coefficient corresponding to the frequency offset Δf of the output signal of the output node, and ω3 represents the weight coefficient corresponding to the total harmonic distortion THD of the output signal of the output node.

[0215] In a possible implementation manner, adjusting the target circuit parameters by using a preset optimization model includes:

[0216] Generating multiple groups of initial parameter combinations randomly for the target circuit parameters;

[0217] Obtaining the fitness corresponding to each group of parameters according to at least one of the voltage fluctuation of the output signal of the target circuit in the simulation, the voltage fluctuation of the output signal of the physical circuit with the same structure as the target circuit in actual operation, frequency offset, and total harmonic distortion and the corresponding weight coefficient;

[0218] Selecting the initial parameter combinations with fitness greater than the preset fitness as the parent generation, and performing crossover and mutation to generate offspring parameter combinations,

[0219] Based on the obtained updated circuit information from the combination of the offspring parameters, re - execute the steps of circuit simulation and subsequent steps on the updated circuit information until the fitness decreases to a preset range or the number of iterations reaches a preset number.

[0220] In a possible implementation, the fitness function is:

[0221] F = ω1·(α·Ripple sim +(1 - α)·Ripple measured ) + ω2·Δf measured +

[0222] ω3·THD measured ,

[0223] where F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation of the output signal, Ripple sim represents the voltage fluctuation of the output signal in the simulation, Ripple measured represents the voltage fluctuation of the output signal during actual operation, α represents the weight coefficient of the voltage fluctuation of the output signal in the simulation data, (1 - α) represents the weight coefficient of the voltage fluctuation of the output signal in the actual operation data, ω2 represents the weight coefficient corresponding to the frequency offset Δf measured of the output signal during actual operation, and ω3 represents the weight coefficient corresponding to the total harmonic distortion THD measured of the output signal during actual operation.

[0224] In a possible implementation, the device further includes a noise source establishment module for:

[0225] Establish an EFT noise source according to a preset noise source establishment standard;

[0226] Modify the EFT noise source according to historical measured data to establish the noise model, where the historical measured data is obtained from the measured noise waveform signal of a physical circuit with the same target circuit structure.

[0227] In a possible implementation, the modifying the EFT noise source according to historical measured data includes:

[0228] Extract features from the historical measured data to obtain a target feature combination, where each feature parameter in the target feature combination is related to the EFT noise;

[0229] Perform data processing on each feature parameter in the target feature combination;

[0230] Determine at least one correction parameter according to the processed target feature combination and preset simulation data, and use the correction parameter to correct the EFT noise source, where the correction parameter represents the noise signal deviation between the actual operation and the simulation operation of the target circuit, and the correction coefficient includes a waveform rise time correction parameter and a peak voltage correction coefficient.

[0231] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0232] The embodiments of the present disclosure further provide a circuit simulation optimization device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the above method.

[0233] The embodiments of the present disclosure further provide a non-volatile computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0234] The embodiments of the present disclosure further provide a computer program product, including a computer program, or a non-volatile computer-readable storage medium carrying the computer program. When the computer program is executed by a processor, the steps of the above method are implemented.

[0235] The above has described the embodiments of the present disclosure. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.< / per> < / pw> < / tf> < / name> < / per> < / pw> < / tf> < / v2> < / v1> < / node1> < / name>

Claims

1. A circuit simulation optimization method, characterized in that, The method includes: Obtaining circuit information of a target circuit according to a netlist file of the target circuit, where the circuit information includes the circuit topology and circuit parameters of the target circuit; Injecting a noise model into a target node of the circuit topology to obtain updated circuit information; Performing circuit simulation on the updated circuit information to obtain a simulation result, where the simulation result includes the output signal waveform of an output node of the target circuit; Optimally adjusting the circuit information according to the simulation result until the simulation result of the updated circuit information reaches an expected effect.

2. The method according to claim 1, wherein The simulation result of the updated circuit information reaching the expected effect includes at least one of the following: Reducing the voltage fluctuation of the output signal of the output node to a preset voltage range; Reducing the frequency offset of the output signal of the output node to a preset frequency offset range; Reducing the total harmonic distortion of the output signal of the output node to a preset percentage range.

3. The method according to claim 1 or 2, characterized in that, The optimally adjusting the circuit information according to the simulation result until the simulation result of the updated circuit information reaches the expected effect includes: Determining at least one target circuit parameter among the circuit parameters; Adjusting the target circuit parameter by using a preset optimization model until the simulation result of the updated circuit information reaches the expected effect.

4. The method according to claim 3, characterized in that, The preset optimization model is obtained based on one or more of a neural network, a genetic algorithm, a particle swarm optimization algorithm, and a stochastic algorithm. Among them, adjusting the target circuit parameter by using the preset optimization model includes: Inputting the circuit information and the target circuit parameter into the preset optimization model, and determining the adjusted target circuit parameter by using the output result of the preset optimization model.

5. The method according to claim 3, characterized in that Adjusting the target circuit parameter by using the preset optimization model includes: Randomly generating multiple groups of initial parameter combinations for the target circuit parameter; Obtaining the fitness corresponding to each group of parameters according to at least one of the voltage fluctuation, frequency offset, and total harmonic distortion of the output signal of the output node and the corresponding weight coefficient; Taking the initial parameter combinations with fitness greater than a preset fitness as parents, and performing crossover and mutation on the parents to generate offspring parameter combinations; Based on the offspring parameter combinations, obtaining updated circuit information, and re-performing the steps of performing circuit simulation on the updated circuit information and subsequent steps until the fitness is reduced to a preset range or the number of iterations reaches a preset number of times.

6. The method according to claim 5, characterized in that, The fitness function is: F = ω1·Ripple + ω2·Δf + ω3·THD, where F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation Ripple of the output signal of the output node, ω2 represents the weight coefficient corresponding to the frequency offset Δf of the output signal of the output node, and ω3 represents the weight coefficient corresponding to the total harmonic distortion THD of the output signal of the output node.

7. The method according to claim 3, characterized in that, Adjusting the target circuit parameter by using the preset optimization model includes: Randomly generating multiple groups of initial parameter combinations for the target circuit parameter; Obtain the fitness corresponding to each set of parameters based on at least one of the voltage fluctuation of the output signal of the target circuit in simulation, the voltage fluctuation, frequency offset, and total harmonic distortion of the output signal of the physical circuit with the same structure as the target circuit in actual operation and the corresponding weight coefficients; Select the initial parameter combinations with fitness greater than the preset fitness as the parent generation, and perform crossover and mutation to generate offspring parameter combinations, Based on the offspring parameter combinations, obtain the updated circuit information, and re-execute the steps of circuit simulation and subsequent steps for the updated circuit information until the fitness drops to the preset range or the number of iterations reaches the preset number.

8. The method according to claim 7, wherein The fitness function is: F = ω1·(α·Ripple sim +(1 - α)·Ripple measured ) + ω2·Δf measured + ω3·THD measured , Among them, F represents the fitness, ω1 represents the weight coefficient corresponding to the voltage fluctuation of the output signal, Ripple sim represents the voltage fluctuation of the output signal in the simulation, Ripple measured represents the voltage fluctuation of the output signal during actual operation, α represents the weight coefficient of the voltage fluctuation of the output signal in the simulation data, (1-α) represents the weight coefficient of the voltage fluctuation of the output signal in the actual operation data, ω2 represents the frequency offset Δf of the output signal during actual operation measured corresponding weight coefficient, ω3 represents the total harmonic distortion THD of the output signal during actual operation measured corresponding weight coefficient.

9. The method according to claim 1, wherein The method further includes: Establish an EFT noise source according to the preset noise source establishment standard; Correct the EFT noise source according to the historical measured data to establish the noise model, where the historical measured data is obtained from the measured noise waveform signal of the physical circuit with the same structure as the target circuit.

10. The method according to claim 9, characterized in that, The correcting the EFT noise source according to the historical measured data includes: Extract features from the historical measured data to obtain a target feature combination, and each feature parameter in the target feature combination is related to the EFT noise; Perform data processing on each feature parameter in the target feature combination; Determine at least one correction parameter according to the processed target feature combination and the preset simulation data, and use the correction parameter to correct the EFT noise source, where the correction parameter represents the noise signal deviation between the actual operation and the simulation operation of the target circuit, and the correction coefficient includes a waveform rise time correction parameter and a peak voltage correction coefficient.

Images