Display module and display terminal

Abstract

The invention relates to a display module and a display terminal. The display module comprises a data driver and a time schedule controller, the time schedule controller is connected with the data driver, the time schedule controller is used for sending a display signal to the data driver, and the display signal comprises a data signal and a mark signal; the data driver is used for controlling a target module in the data driver to enter a first preset mode with relatively low power consumption when the mark signal is a first mark signal; the first mark signal is sent to the data driver by the time schedule controller when the synchronization signal received by the time schedule controller enters a blanking period. According to the invention, when the synchronization signal received by the time schedule controller enters the blanking period, the first mark signal in the display signal is utilized to control the target module in the data driver to enter the first preset mode with relatively low power consumption, so that the power consumption of the data driver is reduced, and the energy efficiency of the display module is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display module and a display terminal. Background Art

[0002] In panel display technologies, technologies such as thin film transistor liquid crystal display (TFT-LCD) occupy an important position in the panel display market due to their advantages such as low operating voltage, long lifespan, no radiation, and low cost.

[0003] However, the power consumption of these panel display technologies is usually high, resulting in low energy efficiency of display products such as televisions (TVs), monitors (MNTs), and notebook computers (NBs). Summary of the Invention

[0004] Embodiments of this application provide a display module and a display terminal, which can reduce power consumption and improve the energy efficiency of the display module.

[0005] Embodiments of this application provide a display module, including:

[0006] A data driver; and

[0007] A timing controller, connected to the data driver, for sending a display signal to the data driver, where the display signal includes a data signal and a flag signal;

[0008] Wherein, the data driver is used to control a target module in the data driver to enter a first preset mode when the flag signal is a first flag signal, and the power consumption of the target module in the first preset mode is less than the power consumption of the target module in a second preset mode; the first flag signal is sent by the timing controller to the data driver when the synchronization signal received by the timing controller enters the blanking period.

[0009] In an embodiment of this application, the data driver is further used to control the target module in the data driver to exit the first preset mode when the flag signal is a second flag signal, where the second flag signal is sent by the timing controller to the data driver when the synchronization signal exits the blanking period.

[0010] In an embodiment of this application, the timing controller includes a sending module, and the data driver further includes a receiving module and a data register, and the sending module is used to send the display signal to the data register through the receiving module;

[0011] Wherein, the data register controls the target module to enter or exit the first preset mode based on the flag signal.

[0012] In an embodiment of the present application, the receiving module and the transmitting module are communicatively connected through a differential pair.

[0013] In an embodiment of the present application, the target module includes at least one of a latch unit, a level conversion unit, a digital-to-analog conversion unit, and an output buffer unit.

[0014] In an embodiment of the present application, the data driver further includes a first preset pin and a switching device connected between the data register and the target module;

[0015] Wherein, when the flag signal is the first flag signal, the data register turns on the switching device through the first preset pin to enable the target module to enter the first preset mode;

[0016] When the flag signal is the second flag signal, the data register turns off the switching device through the first preset pin to enable the target module to exit the first preset mode.

[0017] In an embodiment of the present application, the timing controller is further configured to:

[0018] After the timing controller sends the first flag signal to the data driver, control the transmitting module to enter the sleep state; and

[0019] When the synchronization signal exits the blanking period, control the transmitting module to exit the sleep state.

[0020] In an embodiment of the present application, when the target module is in the first preset mode, the receiving module and the data register are in the working state.

[0021] In an embodiment of the present application, the display module includes a plurality of the data drivers, and the timing controller is respectively connected to the plurality of data drivers for respectively sending the display signal to the plurality of data drivers

[0022] In an embodiment of the present application, the blanking period includes at least one of a horizontal blanking period and a vertical blanking period.

[0023] According to the above object of the present application, an embodiment of the present application further provides a display terminal, including a housing and the display module according to any one of the above, the housing has an accommodation space, and the display module is disposed in the accommodation space.

[0024] An embodiment of the present application provides a display module and a display terminal. The display module includes a data driver and a timing controller. When the synchronization signal received by the timing controller enters the blanking period, the timing controller can use the first flag signal in the display signal to control the target module in the data driver to enter a first preset mode with lower power consumption, thereby reducing the power consumption of the data driver and improving the energy efficiency of the display module.

[0025] Other features and advantages of the present application will be described in detail in the following specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0027] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals in the following description represent the same parts.

[0028] Figure 1 Schematic diagram of the implementation method of the low-power mode provided in the related art (rotated 90° counterclockwise);

[0029] Figure 2 Schematic diagram of a structure of the display module provided in the embodiment of the present application;

[0030] Figure 3 Another schematic diagram of the structure of the display module provided in the embodiment of the present application;

[0031] Figure 4 Another schematic diagram of the structure of the display module provided in the embodiment of the present application;

[0032] Figure 5 Another schematic diagram of the structure of the display module provided in the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0034] Based on the problems mentioned in the foregoing background art, in the related art, the China Standard Point-to-Point Interface (CSPI) protocol can be adopted to implement the display of the panel. The CSPI protocol proposes an implementation method for reducing power consumption in a Variable Power Saving (VPS) mode. Specifically, referring to Figure 1 , during the blanking (BK) period of the Start Vertical (STV) signal, the Timing Controller (TCON) pulls down the level of the VPS pin connected to the Source Driver (SD), that is, Figure 1 the level of the wake signal in is pulled down. After receiving the low-level signal of the VPS pin, the data driver enters the low-power mode. However, this implementation method for reducing power consumption in VPS requires an additional VPS pin between the timing controller and the data driver to control the entry and exit of the low-power mode. Moreover, after the data driver exits the low-power mode, the timing controller needs to re-perform link training on the data driver, resulting in an increase in communication delay and power consumption between the timing controller and the data driver.

[0035] In response to this, the present application provides a display module and a display terminal to at least partially solve the above problems.

[0036] According to the first aspect of the present application, referring to Figures 2 to 5 , a display module is provided. Specifically, the display module is used to implement an image display function and includes a data driver SD and a timing controller TCON, and the timing controller TCON is connected to the data driver SD. The timing controller TCON functions to perform timing management on the display signal in the display module, and is used to send a display signal to the data driver SD. The display signal includes a Data signal and a flag signal. The data signal may include frame picture data, and the frame picture data contains information such as pixel data required to present a correct image on the display screen, and is used to control the picture display of the panel. The flag signal is used to instruct a target module in the data driver SD to enter a first preset mode.

[0037] The power consumption of the target module in the first preset mode is less than that in the second preset mode. It can be seen that the first preset mode is a mode with lower power consumption, that is, the low-power mode. The low-power mode is a pre-set working mode. For example, in the low-power mode, the supply voltage of the target module is lower than the set voltage threshold, or the target module is directly turned off, so that the power consumption of the target module is lower than the set power consumption threshold. Among them, the turning off of the target module can be achieved by disconnecting the connection with the target module to stop supplying power to the target module.

[0038] It can be seen that the supply voltage of the target module in the first preset mode is less than that in the second preset mode, or the target module is turned off when in the first preset mode and not turned off when in the second preset mode, so that the power consumption of the target module in the first preset mode can be less than that in the second preset mode.

[0039] The data signal and the flag signal can be sent to the data driver SD by the timing controller TCON at different times respectively, that is, the data signal and the flag signal share the same data channel time-division multiplexing. For example, the data signal can be sent by the timing controller TCON to the data driver SD when the synchronization signal received by the timing controller TCON does not enter the blanking period. And the flag signal can be sent by the timing controller TCON to the data driver SD when the synchronization signal received by the timing controller TCON is in the blanking period. "When the synchronization signal received by the timing controller TCON is in the blanking period" can be any moment when the synchronization signal received by the timing controller TCON is in the blanking period. Among them, the synchronization signal is a signal used to ensure that each part of the display terminal can work synchronously when displaying an image. For example, the synchronization signal can ensure that the display of each row of pixels starts and ends at the correct time, and the display of each frame can also be switched at the correct time.

[0040] The data driver SD is used to control the target module in the data driver SD to enter the first preset mode when the flag signal is the first flag signal. The first flag signal can be a signal including the first flag, and the first flag can be, for example, the value 1. By setting the value of the preset fixed position in the flag signal (such as the blank bit at a certain fixed position in the flag signal) to the first flag, the flag signal becomes the first flag signal. The data driver SD can judge whether the flag signal is the first flag signal by reading the value of the preset fixed position.

[0041] When the synchronization signal received by the timing controller TCON enters the blanking period, the timing controller TCON sends the first flag signal to the data driver SD. For example, when the synchronization signal enters the blanking period, the timing controller TCON detects this change in state and then generates the first flag signal according to the pre-set logic. The first flag signal is then sent to the data driver SD. After receiving the first flag signal, the data driver SD controls the target module to enter the first preset mode, so that the display module can make the target module enter the first preset mode during the blanking period when pixel data display operations are not required, thereby achieving the purpose of energy saving.

[0042] "When the synchronization signal received by the timing controller TCON enters the blanking period" can be either when the synchronization signal received by the timing controller TCON enters the blanking period simultaneously or at a certain moment after the synchronization signal received by the timing controller TCON enters the blanking period. For example, since the synchronization signal received by the timing controller TCON changes from low level to high level when entering the blanking period, "when the synchronization signal received by the timing controller TCON enters the blanking period" can be either simultaneously when the synchronization signal changes from low level to high level or at a preset delay moment after the synchronization signal changes from low level to high level. This preset delay moment can be, for example, 1 millisecond after the synchronization signal changes from low level to high level.

[0043] It can be seen that the timing controller TCON in this embodiment can, when the synchronization signal received by the timing controller TCON enters the blanking period, use the first flag signal in the display signal to control the target module in the data driver SD to enter the first preset mode, thereby reducing the power consumption of the data driver SD and improving the energy efficiency of the display module. For example, in some mobile devices (such as smartphones, tablets, etc.), it can effectively extend the battery life of the device. Moreover, the target module in the data driver SD enters the first preset mode during the blanking period, so it does not affect the display function of the display module itself. In addition, compared with the method of adding an extra VPS pin between the timing controller TCON and the data driver SD, this software control method using the first flag signal in the display signal can reduce the number of pins between the timing controller TCON and the data driver SD, thereby saving the hardware cost of the display module.

[0044] In some embodiments, referring to Figure 1, The IC state is the status signal of the timing controller TCON, indicating whether the data driver SD needs to be controlled. For example, in the Rest mode phase, the timing controller TCON does not need to control the data driver SD; in the Power on and ready phase, the timing controller TCON needs to send a control (command) signal to the data driver SD to enable the data driver SD to perform the preliminary preparation work for screen display; in the Receive data and output data phase, the timing controller TCON needs to receive data signals and send them to the data driver SD to enable the data driver SD to perform pixel control related to screen display.

[0045] In some embodiments, an exit strategy for the first preset mode of the target module in the data driver SD is also provided. Specifically, the data driver SD is further configured to control the target module in the data driver SD to exit the first preset mode when the flag signal is the second flag signal. The second flag signal may be a signal including a second flag, and the second flag may be, for example, the value 0. By setting the value of a preset fixed position (such as a blank bit at a certain fixed position in the flag signal) in the flag signal to the second flag, the flag signal becomes the second flag signal. The data driver SD can determine whether the flag signal is the second flag signal by reading the value of the preset fixed position. The second flag signal is sent by the timing controller TCON to the data driver SD when the synchronization signal received by the timing controller TCON exits the blanking period.

[0046] "When the synchronization signal received by the timing controller TCON exits the blanking period" can be either when the synchronization signal received by the timing controller TCON exits the blanking period or at a certain moment before the synchronization signal received by the timing controller TCON exits the blanking period. For example, since the synchronization signal received by the timing controller TCON jumps from a high level to a low level when exiting the blanking period, "when the synchronization signal received by the timing controller TCON exits the blanking period" can be either at the same time when the synchronization signal jumps from a high level to a low level or at a preset early moment before the synchronization signal jumps from a high level to a low level. The preset early moment can be, for example, 1 millisecond before the synchronization signal jumps from a high level to a low level. Taking the blanking period duration as 12 milliseconds as an example, the preset early moment can be 11 milliseconds after the synchronization signal enters the blanking period.

[0047] In some embodiments, the timing controller TCON includes a transmit module TX (Transmit), and the data driver SD further includes a receive module RX (Receive) and a data register DR (Data register). The transmit module TX is connected to the receive module RX, and the receive module RX is connected to the data register DR. In this way, the transmit module TX can send a display signal to the data register DR through the receive module RX. When the display signal includes a flag signal, the data register DR can control the target module to enter or exit a first preset mode based on the flag signal. For example, the data register DR can control the target module to enter the first preset mode based on a first flag signal, or for another example, the data register DR can control the target module to exit the first preset mode based on a second flag signal.

[0048] In some embodiments, the receive module RX and the transmit module TX are communicatively connected through a differential pair, that is, the receive module RX is connected to the transmit module TX through differential signal lines, and the display signal is transmitted between the transmit module TX and the receive module RX in the form of differential signals. Based on the differential pair communication connection, before sending the display signal, the transmit module TX needs to encode the display signal first, and after receiving the encoded display signal, the transmit module TX needs to decode the encoded display signal first. The differential signal lines are, for example Figures 2 to 5 the two signal lines DataP and DataN. The signals transmitted on these two lines are equal in magnitude and opposite in polarity. In this transmission mode, the differential signal can suppress common-mode noise interference and ensure the accurate reception of the display signal.

[0049] In some embodiments, the target module includes at least one of a latch unit Latch, a level shift unit LS (Level Shift), a digital-to-analog conversion unit DAC (Digital-to-Analog Conversion, DAC), and an output buffer unit OB (Output Buffer). For example Figures 2 to 4 as shown, the data driver SD includes a receive module RX, a data register DR, a latch unit Latch, a level shift unit LS, a digital-to-analog conversion unit DAC, and an output buffer unit OB connected in sequence. The data register DR can control the latch unit Latch, the level shift unit LS, the digital-to-analog conversion unit DAC, and the output buffer unit OB to enter or exit the first preset mode based on the flag signal simultaneously.

[0050] Among them, the latch unit Latch is used to temporarily store data in the display module. During the display process, data needs to be accurately processed and transmitted at the appropriate moment. The latch unit Latch can temporarily store this data to ensure the stability and accuracy of the data. For example, during the process of the timing controller TCON transmitting data signals to the data driver SD, the data may arrive sequentially according to a certain timing sequence. The latch unit Latch can lock this data at a specific moment to prevent data loss or errors, providing a stable data source for subsequent processing steps.

[0051] The level shift unit LS is used to convert the input level signal. Since different circuit parts may require signals of different levels to work properly, in the display module, the input signal level may not be suitable for direct use by some units. For example, some data may be input in the form of a digital signal with a lower level, but the subsequent digital-to-analog conversion unit DAC and output buffer unit OB may require signals of a higher level to work properly. The level shift unit LS can convert the low-level signal into an appropriate high-level signal to meet the requirements of subsequent units.

[0052] The digital-to-analog conversion unit DAC is used to convert digital signals into analog signals because display terminals often require analog signals to drive the display. The data signals transmitted from the timing controller TCON are usually digital signals. The digital-to-analog conversion unit DAC can convert these digital signals into analog signals so that the image can be correctly displayed on the display terminal.

[0053] The output buffer unit OB is used to cache and optimize the signals to be output to ensure stable signal output. For example, in the display module, the analog signals output from the digital-to-analog conversion unit DAC may have some fluctuations or instabilities. The output buffer unit OB can cache these signals and improve the signal quality through some optimization measures, such as signal smoothing. The signals processed by the output buffer unit OB can be output more stably, thereby improving the quality and stability of the display.

[0054] In some embodiments, the first preset mode of the latch unit Latch, the level conversion unit LS, the digital-to-analog conversion unit DAC, and the output buffer unit OB is described. Specifically, taking the latch unit Latch as an example, during normal operation, the latch unit Latch needs to continuously latch the input data, which consumes a certain amount of electrical energy. When entering the first preset mode, the latch unit Latch can stop or reduce some unnecessary operations, thereby reducing the power consumption. Taking the level conversion unit LS as an example, in the first preset mode, the level conversion unit LS may stop some unnecessary level conversion detection or adjustment operations. Taking the digital-to-analog conversion unit DAC as an example, in the first preset mode, the digital-to-analog conversion unit DAC can pause or perform digital-to-analog conversion operations at a lower frequency. Taking the output buffer unit OB as an example, the output buffer unit OB can also reduce the cache update frequency or pause some cache management operations, etc.

[0055] In some embodiments, the implementation manner of the data register DR controlling the target module to enter or exit the first preset mode is described. Specifically, referring to Figure 2 , the data driver SD further includes a first preset pin, the first preset pin is the low-power pin LP (Low power), and a switching device connected between the data register DR and the target module, and the switching device is connected to the low-power pin LP. Referring to Figure 3 , when the flag signal is the first flag signal, the data register DR opens the switching device through the low-power pin LP, so that the target module enters the first preset mode. For example, the data register DR can pull down the level of the low-power pin LP, so that the switching device is opened. In this way, the connection between the data register DR and the target module will also be disconnected, so that the target module enters the first preset mode. Referring to Figure 4 , when the flag signal is the second flag signal, the data register DR closes the switching device through the low-power pin LP, so that the target module exits the first preset mode. For example, the data register DR can pull up the level of the low-power pin LP, so that the switching device is closed. In this way, the data register DR and the target module will also be reconnected, so that the target module exits the first preset mode. Referring to Figure 5 , taking the target module including the latch unit Latch as an example, the data register DR opens the switching device through the low-power pin LP, so that the latch unit Latch enters the first preset mode, or the data register DR closes the switching device through the low-power pin LP, so that the latch unit Latch exits the first preset mode.

[0056] In some embodiments, a first preset mode of the timing controller TCON is further provided. Specifically, the timing controller TCON can also be used to: after the timing controller TCON sends a first flag signal to the data driver SD, control the transmission module TX to enter the sleep state; and when the synchronization signal received by the timing controller TCON exits the blanking period, control the transmission module TX to exit the sleep state. It can be seen that when the synchronization signal received by the timing controller TCON is in the blanking period, the transmission module TX of the timing controller TCON is in the sleep state, so it will not affect the display function of the display module itself, thereby saving the power consumption of the timing controller TCON and further improving the energy efficiency of the display module.

[0057] In some embodiments, when the target module in the data driver SD is in the first preset mode, the receiving module RX and the data register DR in the data driver SD are in the working state. In this way, since the receiving module RX remains in the working state, after the target module exits the first preset mode, the transmission module TX of the timing controller TCON can directly send data signals to the receiving module RX without re-performing link training on the receiving module RX, avoiding communication delay and increased power consumption between the timing controller TCON and the data driver SD, and ensuring the stability of the display terminal's screen at a high refresh rate. Among them, the goal of link training is to dynamically adjust link parameters so that the transmission module TX and the receiving module RX are consistent in electrical characteristics (such as signal strength, clock synchronization, etc.) and protocol layer (such as rate, number of channels, etc.), thereby optimizing signal quality and reducing the bit error rate (BER).

[0058] In addition, the communication between the data driver SD and the timing controller TCON can be implemented based on the CSPI protocol. In the CSPI protocol, in addition to being communicatively connected through differential pairs between the receiving module RX of the data driver SD and the transmission module TX of the timing controller TCON, they are also connected through Link Status pins. When the target module in the data driver SD is in the first preset mode, the link status pin of the receiving module RX is maintained at a high level to indicate that the link training of the receiving module RX is completed. In this way, the transmission module TX of the timing controller TCON can directly send data signals to the receiving module RX according to the high level state of the link status pin without re-performing link training on the receiving module RX.

[0059] In some embodiments, a display module includes a plurality of data drivers. The timing controller is respectively connected to the plurality of data drivers and is configured to send display signals to the plurality of data drivers respectively, so as to control target modules in the plurality of data drivers to enter a first preset mode with lower power consumption respectively, reduce the power consumption of the plurality of data drivers, and further improve the energy efficiency of the display module.

[0060] In some embodiments, since no pixel data display operation needs to be performed by the display terminal during the horizontal blanking (HBlank) period and the vertical blanking (VBlank) period, the target module in the data driver SD entering the first preset mode during the horizontal blanking period and the vertical blanking period will not affect the display function of the display module itself. Therefore, the above blanking period may be at least one of the horizontal blanking period and the vertical blanking period, that is, in this embodiment, the control of the target module in the data driver SD and the sending module TX of the timing controller TCON is applicable to both the horizontal blanking period and the vertical blanking period, so as to reduce the power consumption of the display module to a greater extent and further improve the energy efficiency of the display module.

[0061] Among them, the horizontal blanking period refers to a period during which some additional processing needs to be performed after the acquisition of each line of image data to prepare for the acquisition of the next line of data. The vertical blanking period refers to a period during which preparations related to screen switching (such as adjustments related to frame synchronization, etc.) need to be performed after the acquisition of each field of image data.

[0062] According to a second aspect of the present application, a display terminal is provided, including a housing and the display module described in any of the embodiments. The housing has an accommodation space, and the display module is disposed in the accommodation space. The display terminal may be, for example, a display product such as a television (TV), a monitor (MNT), or a notebook computer (NB). The display terminal has all the beneficial effects of the above display module, and details are not described herein again.

[0063] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0064] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0065] Among the embodiments, implementation manners and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0066] The above are only the preferred embodiments of the present application, and do not impose any formal restrictions on the present application. However, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display module, characterized in that, Comprising: A data driver; And A timing controller, connected to the data driver, for sending a display signal to the data driver, the display signal including a data signal and a flag signal; Wherein, the data driver is used to control a target module in the data driver to enter a first preset mode when the flag signal is a first flag signal, and the power consumption of the target module in the first preset mode is less than the power consumption of the target module in a second preset mode; the first flag signal is sent by the timing controller to the data driver when the synchronization signal received by the timing controller enters the blanking period.

2. The display module according to claim 1, wherein The data driver is further used to control the target module in the data driver to exit the first preset mode when the flag signal is a second flag signal, wherein the second flag signal is sent by the timing controller to the data driver when the synchronization signal exits the blanking period.

3. The display module according to claim 2, wherein The timing controller includes a sending module, and the data driver further includes a receiving module and a data register, and the sending module is used to send the display signal to the data register through the receiving module; Wherein, the data register controls the target module to enter or exit the first preset mode based on the flag signal.

4. The display module according to claim 3, wherein The receiving module and the sending module are communicatively connected through a differential pair.

5. The display module according to claim 3, wherein The target module includes at least one of a latch unit, a level conversion unit, a digital-to-analog conversion unit, and an output buffer unit.

6. The display module according to claim 3, wherein The data driver further includes a first preset pin and a switching device connected between the data register and the target module; Wherein, when the flag signal is the first flag signal, the data register turns on the switching device through the first preset pin to enable the target module to enter the first preset mode; When the flag signal is the second flag signal, the data register turns off the switching device through the first preset pin to enable the target module to exit the first preset mode.

7. The display module according to claim 3, wherein The timing controller is further used for: After the timing controller sends the first flag signal to the data driver, controlling the sending module to enter a sleep state; and When the synchronization signal exits the blanking period, controlling the sending module to exit the sleep state.

8. The display module according to claim 3, wherein When the target module is in the first preset mode, the receiving module and the data register are in a working state.

9. The display module according to claim 1, wherein The display module includes a plurality of the data drivers, and the timing controller is respectively connected to the plurality of data drivers for respectively sending the display signal to the plurality of data drivers.

10. The display module according to any one of claims 1 to 9, characterized in that, The blanking period includes at least one of a horizontal blanking period and a vertical blanking period.

11. A display terminal, characterized in that, Including a housing and the display module according to any one of claims 1 to 10, the housing has an accommodating space, and the display module is disposed in the accommodating space.

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