Drive module and display device

Abstract

This application belongs to the field of display, and specifically relates to a driving module and a display device. The driving module includes a data driving unit, a selection unit, a polarity partition detection unit, a voltage adjustment unit, and an input control unit. The selection unit includes a first selection unit and a second selection unit. The first selection unit is connected to the first signal line through a first branch line and a second branch line. The second selection unit is connected to the second signal line through a third branch line and a fourth branch line. At least one voltage adjustment unit is disposed on the fourth branch line. The input control unit is connected to the polarity partition detection unit. In the polarity symmetric mode, the first branch line and the fourth branch line form a group, and the second branch line and the third branch line form a group, and data voltages are output alternately line by line. Since the data voltage output on the fourth branch line is lowered, the brightness of the green sub-pixels controlled by the data lines connected to the fourth branch line is reduced, so that color deviation can be improved or eliminated, and the display image quality of the display panel can be improved.

Description

Technical Field

[0001] This application belongs to the field of displays, and particularly relates to a driving module and a display device. Background Art

[0002] When a liquid crystal display is in use, a liquid crystal capacitor (Clc) is formed by a pixel electrode on one side of the array substrate and a common electrode on one side of the counter substrate to drive the deflection of liquid crystal molecules, and the brightness of each sub-pixel is controlled to achieve image display. If an electric field in a single direction is applied to the liquid crystal molecules for a long time, the liquid crystal molecules may become polarized, resulting in a decrease in the display effect and even damage to the liquid crystal material. By reversing the polarity and alternately changing the direction of the electric field, the polarization of the liquid crystal molecules can be effectively avoided.

[0003] The data line provides a data voltage for the pixel electrode. When the polarity is reversed, the data voltage is greater than or less than the voltage of the common electrode. The coupling capacitance (Cdc) formed between the data line and the pixel electrode will cause the data voltage to shift, resulting in crosstalk, which affects the display effect of the liquid crystal display. The liquid crystal display can be divided into multiple display areas. Making the polarities of adjacent display areas symmetrical can cancel the coupling, thereby improving or eliminating lateral crosstalk.

[0004] However, when the polarities of adjacent display areas are symmetrical, all the pixels in a column at the junction always have all positive polarities or all negative polarities and will not change. Color deviation will occur in the area where this column is located, affecting the display image quality of the liquid crystal display. Summary of the Invention

[0005] The purpose of this application is to provide a driving module and a display device to improve or eliminate color deviation and enhance the display image quality of the liquid crystal display.

[0006] To achieve the above objective, this application provides a driving module, including a data driving unit. The driving module further includes:

[0007] A polarity partition detection unit connected to a first signal line and a second signal line, both the first signal line and the second signal line are connected to the data driving unit;

[0008] A selection unit, including a first selection unit and a second selection unit. The first selection unit is connected to the first signal line through a first branch line and a second branch line, and is used to control one of the first branch line and the second branch line to output a data voltage. The second selection unit is connected to the second signal line through a third branch line and a fourth branch line, and is used to control one of the third branch line and the fourth branch line to output a data voltage;

[0009] A voltage adjustment unit, with at least one voltage adjustment unit provided on the fourth branch line or in the data driving unit;

[0010] An input control unit, connected to the polarity partition detection unit. In the normal polarity mode, the data voltage polarities of the first signal line and the second signal line are opposite. The input control unit controls the selection unit to operate, so that the first selection unit and the second selection unit output data voltages. In the polarity symmetric mode, the data voltage polarities of the first signal line and the second signal line are the same. The input control unit controls the selection unit to operate, and at least the second branch line and the fourth branch line alternately output data voltages line by line.

[0011] Optionally, the first selection unit includes a first transistor and a second transistor. The first end of the first transistor is connected to the first branch line, and the second end of the first transistor is used to connect to a first data line. The first end of the second transistor is connected to the second branch line, and the second end of the second transistor is used to connect to the first data line. One of the first transistor and the second transistor is a P-channel transistor and the other is an N-channel transistor;

[0012] The second selection unit includes a third transistor and a fourth transistor. The first end of the third transistor is connected to the third branch line, and the second end of the third transistor is used to connect to a second data line. The first end of the fourth transistor is connected to the fourth branch line, and the second end of the fourth transistor is used to connect to the second data line. One of the third transistor and the fourth transistor is a P-channel transistor and the other is an N-channel transistor, and the channel types of the first transistor and the third transistor are different.

[0013] Optionally, the input control unit includes a signal generator, a fifth transistor, a sixth transistor, and a seventh transistor. The signal generator is connected to the frame start signal line, and the signal generator is used to output a high-level signal and a low-level signal that alternate line by line;

[0014] The first end of the fifth transistor is connected to the signal generator, the second end of the fifth transistor is connected to the control ends of the first transistor, the second transistor, the third transistor, and the fourth transistor, and the control end of the fifth transistor is connected to the polarity partition detection unit;

[0015] The first end of the sixth transistor is connected to a first power supply, the first power supply outputs the high-level signal, the second end of the sixth transistor is connected to the control ends of the first transistor and the second transistor, and the control end of the sixth transistor is connected to the polarity partition detection unit;

[0016] A first end of the seventh transistor is connected to a second power supply which outputs the low-level signal. A second end of the seventh transistor is connected to control ends of the third transistor and the fourth transistor. A control end of the seventh transistor is connected to the polarity partition detection unit;

[0017] Wherein, the fifth transistor is an N-channel transistor, the sixth transistor and the seventh transistor are P-channel transistors, or the fifth transistor is a P-channel transistor, and the sixth transistor and the seventh transistor are N-channel transistors.

[0018] Optionally, the voltage adjustment unit is arranged on the fourth branch line and is configured to lower the data voltage on the fourth branch line.

[0019] Optionally, the voltage adjustment unit is further arranged on the second branch line and is configured to lower the data voltage on the second branch line.

[0020] Optionally, the voltage adjustment unit is further arranged on the second branch line and is configured to raise the data voltage on the second branch line.

[0021] Optionally, the first selection unit further includes an eighth transistor and a ninth transistor. A first end of the eighth transistor is connected to the first signal line. A second end of the eighth transistor is connected to the first branch line and the second branch line. A first end of the ninth transistor is connected to the first signal line. A second end of the ninth transistor is connected to the first data line. The voltage adjustment unit is arranged on the first branch line. The voltage adjustment unit on the second branch line is configured to lower the data voltage, and the voltage adjustment unit on the first branch line is configured to raise the data voltage;

[0022] The second selection unit further includes a tenth transistor and an eleventh transistor. A first end of the tenth transistor is connected to the second signal line. A second end of the tenth transistor is connected to the third branch line and the fourth branch line. A first end of the eleventh transistor is connected to the second signal line. A second end of the eleventh transistor is connected to the second data line. The voltage adjustment unit is arranged on the third branch line. The voltage adjustment unit on the fourth branch line is configured to lower the data voltage, and the voltage adjustment unit on the third branch line is configured to raise the data voltage;

[0023] Wherein, the eighth transistor and the tenth transistor are N-channel transistors, the ninth transistor and the eleventh transistor are P-channel transistors, or the eighth transistor and the tenth transistor are P-channel transistors, and the ninth transistor and the eleventh transistor are N-channel transistors.

[0024] Optionally, the input control unit includes a signal generator, a fifth transistor, a sixth transistor, and a seventh transistor, the signal generator is connected to the frame start signal line, and the signal generator is used to output a high level signal and a low level signal alternately row by row;

[0025] A first end of the fifth transistor is connected to the signal generator, a second end of the fifth transistor is connected to the control ends of the first transistor, the second transistor, the third transistor, and the fourth transistor, and a control end of the fifth transistor is connected to the polarity partition detection unit;

[0026] A first end of the sixth transistor is connected to a first power supply, which outputs the high-level signal; a second end of the sixth transistor is connected to control ends of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor; and a control end of the sixth transistor is connected to the polarity partition detection unit;

[0027] A first end of the seventh transistor is connected to a second power supply, which outputs the low-level signal; a second end of the seventh transistor is connected to control ends of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor; and a control end of the seventh transistor is connected to the polarity partition detection unit;

[0028] The fifth transistor and the seventh transistor are N-channel transistors, and the sixth transistor is a P-channel transistor; or the fifth transistor and the seventh transistor are P-channel transistors, and the sixth transistor is an N-channel transistor.

[0029] Optionally, the polarity partition detection unit includes an XOR gate circuit or an XNOR gate circuit.

[0030] The present application also provides a display device, comprising:

[0031] The driving module;

[0032] The display panel is connected to the driving module.

[0033] The driving module and display device disclosed in this application have the following beneficial effects:

[0034] In this application, the driving module includes a data driving unit, a selection unit, a polarity partition detection unit, a voltage adjustment unit, and an input control unit. Both the first signal line and the second signal line are connected to the data driving unit. The polarity partition detection unit is connected to the first signal line and the second signal line. The selection unit includes a first selection unit and a second selection unit. The first selection unit is connected to the first signal line through a first branch line and a second branch line. The second selection unit is connected to the second signal line through a third branch line and a fourth branch line. At least one voltage adjustment unit is disposed on the fourth branch line. The input control unit is connected to the polarity partition detection unit. In the polarity symmetric mode, the data voltage polarities of the first signal line and the second signal line are the same. The polarity partition detection unit controls the operation of the selection unit through the input control unit, so that the first branch line and the fourth branch line form a group, and the second branch line and the third branch line form a group, and the data voltage is output alternately line by line. Since the data voltage output by the fourth branch line is lowered, the brightness of the green sub-pixels controlled by the data lines connected to the fourth branch line is reduced, which can improve or eliminate color deviation and improve the display quality of the display panel.

[0035] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part from the practice of the present application.

[0036] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and cannot limit the present disclosure. Brief Description of the Drawings

[0037] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 is a schematic structural diagram of the driving module in Embodiment 1 of the present application.

[0039] Figure 2 is a schematic structural diagram of the display panel in Embodiment 1 of the present application.

[0040] Figure 3 is a schematic diagram of the data voltage increase or decrease of the sub-pixels in Embodiment 1 of the present application.

[0041] Figure 4 is a schematic structural diagram of the driving module in Embodiment 2 of the present application.

[0042] Figure 5 is a schematic diagram of the data voltage increase or decrease of the sub-pixels in Embodiment 2 of the present application.

[0043] Figure 6 It is a schematic structural diagram of the driving module in the third embodiment of the present application.

[0044] Figure 7 It is a schematic diagram of the data voltage of the sub-pixel increasing or decreasing in the third embodiment of the present application.

[0045] Figure 8 It is a schematic structural diagram of the display device in the fourth embodiment of the present application.

[0046] Explanation of reference numerals:

[0047] 100, display panel; 101, first display area; 102, second display area; 110, sub-pixel;

[0048] 200, driving module; 210, first selection unit; 211, first transistor; 212, second transistor; 213, eighth transistor; 214, ninth transistor;

[0049] 220, second selection unit; 221, third transistor; 222, fourth transistor; 223, tenth transistor; 224, eleventh transistor;

[0050] 230, polarity partition detection unit; 240, voltage adjustment unit;

[0051] 250, input control unit; 251, signal generator; 252, fifth transistor; 253, sixth transistor; 254, seventh transistor;

[0052] 261, first signal line; 262, second signal line; 263, third signal line; 264, fourth signal line;

[0053] 271, first branch line; 272, second branch line; 273, third branch line; 274, fourth branch line; 275, fifth branch line; 276, sixth branch line; 277, seventh branch line; 278, eighth branch line;

[0054] 281, first power supply; 282, second power supply;

[0055] 291, third selection unit; 292, fourth selection unit. Detailed implementation manners

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0057] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0058] The present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as limiting the present application.

[0059] Embodiment 1

[0060] The present application provides a driving module 200 for driving a display panel 100. Refer to Figure 1 As shown, the driving module 200 includes a data driving unit, a selection unit, a polarity partition detection unit 230, a voltage adjustment unit 240, and an input control unit 250. The data driving unit is used to provide a data voltage V. Both the first signal line 261 and the second signal line 262 are connected to the data driving unit and are used to output the data voltage provided by the data driving unit to the display panel 100.

[0061] It should be understood that the polarity of the data voltage is positive or negative. When the data voltage is greater than the common electrode voltage, the data voltage is positive polarity, and when the data voltage is less than the common electrode voltage, the data voltage is negative polarity. By reversing the polarity, alternately changing the polarity of the data voltage and alternately changing the direction of the electric field driving the liquid crystal to rotate can effectively avoid the polarization of liquid crystal molecules.

[0062] The polarity partition detection unit 230 is connected to the first signal line 261 and the second signal line 262. When the polarities of the data voltages on the first signal line 261 and the second signal line 262 are the same, the polarity partition detection unit 230 outputs a high-level signal. When the polarities of the data voltages on the first signal line 261 and the second signal line 262 are different, the polarity partition detection unit 230 outputs a low-level signal. Vice versa, that is, when the polarities of the data voltages on the first signal line 261 and the second signal line 262 are the same, the polarity partition detection unit 230 outputs a low-level signal. When the polarities of the data voltages on the first signal line 261 and the second signal line 262 are different, the polarity partition detection unit 230 outputs a high-level signal.

[0063] The selection unit includes a first selection unit 210 and a second selection unit 220. The first selection unit 210 is connected to the first signal line 261 through a first branch line 271 and a second branch line 272, and is used to control one of the first branch line 271 and the second branch line 272 to output a data voltage. The second selection unit 220 is connected to the second signal line 262 through a third branch line 273 and a fourth branch line 274, and is used to control one of the third branch line 273 and the fourth branch line 274 to output a data voltage.

[0064] At least one voltage adjustment unit 240 is disposed on the fourth branch line 274. The voltage adjustment unit 240 can lower or raise the data voltage V. The raised data voltage is denoted as V+, and the lowered data voltage is denoted as V-. It should be noted that the voltage adjustment unit 240 can be disposed on the fourth branch line 274, but is not limited thereto. The voltage adjustment unit 240 can also be integrated in the data driving unit, which can be determined according to specific situations. That is to say, the data driving unit can directly output the data voltage V+ or the data voltage V- according to needs, or the data driving unit outputs the data voltage V, and then lowers or raises it through the voltage adjustment unit 240 on the fourth branch line 274 to obtain the data voltage V+ or the data voltage V-.

[0065] The input control unit 250 is connected to the polarity partition detection unit 230. The high-level signal and the low-level signal output by the polarity partition detection unit 230 control the operation of the input control unit 250 to form a normal polarity mode and a polarity symmetric mode. In the normal polarity mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are opposite, and the input control unit 250 controls the selection unit to operate, so that the first selection unit 210 and the second selection unit 220 output the data voltage V. In the polarity symmetric mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are the same, and the input control unit 250 controls the selection unit to operate, so that the first branch line 271 and the fourth branch line 274 are in a group, and the second branch line 272 and the third branch line 273 are in a group, and the data voltage is output alternately line by line.

[0066] The data driving unit can be encapsulated in a chip. The selection unit, the polarity partition detection unit 230, the voltage adjustment unit 240, and the input control unit 250 can be encapsulated in a chip, or the entire driving module 200 can be encapsulated in a chip, and the specific encapsulation method can be determined according to specific situations.

[0067] See Figure 2As shown, the display panel 100 includes a plurality of sub-pixels 110 arranged in an array, and each column of sub-pixels 110 is arranged between two data lines. The sub-pixels 110 in odd rows are connected to the data line on their left side, and the sub-pixels 110 in even rows are connected to the data line on their right side. Conversely, the sub-pixels 110 in odd rows can be connected to the data line on their right side, and the sub-pixels 110 in even rows can be connected to the data line on their left side.

[0068] The display panel 100 can be divided into a plurality of display areas. The plurality of display areas include adjacent first display area 101 and second display area 102. The number of data lines in the first display area 101 and the second display area 102 is equal. The first display area 101 includes data line 1, data line 2,..., data line n - 1, data line n arranged in sequence from left to right, and the second display area 102 includes data line n + 1, data line n + 2, etc. arranged in sequence from left to right, where n is an integer greater than 1.

[0069] In the normal polarity mode, the polarities of the data voltages of the data lines of the entire display panel 100 alternate between positive and negative, that is, "-+-+". In the polarity symmetric mode, the polarities of adjacent display areas are symmetric. The polarity of the data voltage of the data lines in the left first display area 101 is "+-+-", and the polarity of the data voltage of the data lines in the right second display area 102 is "-+-+". When the display panel 100 is switched to the polarity symmetric mode, that is, the polarities of adjacent display areas are symmetric, coupling can be cancelled, thereby improving or eliminating lateral crosstalk.

[0070] However, since the polarities of adjacent display areas are symmetric, there is always a situation where all pixels in a column at the junction are either all positive or all negative, and this will not change. The overall color of this column is light, and color deviation will occur in the area where this column is located, affecting the display quality of the display panel 100. For example, if the pixel column at the junction is composed of red (R) sub-pixels 110, the area where this column is located will be biased towards cyan or light blue.

[0071] In this embodiment, when the driving module 200 is used to drive the display panel 100, the first branch line 271 and the second branch line 272 are both connected to the first data line (for example, data line n), and the third branch line 273 and the fourth branch line 274 are both connected to the second data line (for example, data line n + 1).

[0072] In the normal polarity mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are opposite. The polarity partition detection unit 230 outputs a low-level signal to the input control unit 250, and the input control unit 250 controls the selection unit to work, so that both the first selection unit 210 and the second selection unit 220 output the data voltage V. In the polarity symmetric mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are the same. The polarity partition detection unit 230 outputs a high-level signal to the input control unit 250, and the input control unit 250 controls the selection unit to work, so that the first branch line 271 and the fourth branch line 274 are in a group, and the second branch line 272 and the third branch line 273 are in a group, and the data voltage is output alternately line by line.

[0073] For example, when scanning the first line, since at least the voltage adjustment unit 240 is provided on the fourth branch line 274, the fourth branch line 274 and the data line n + 1 output the data voltage V-, and the brightness of the green (G) sub-pixel 110 controlled by the data line n + 1 is reduced, and the first branch line 271 and the data line n output the data voltage V; when scanning the second line, the second branch line 272, the data line n, the fourth branch line 274 and the data line n + 1 output the data voltage V, and so on.

[0074] The human eye sensory contribution values of the red, green, and blue sub-pixels 110 are different. The human eye sensory contribution value of the red sub-pixel 110 is about 30%, the human eye sensory contribution value of the green sub-pixel 110 is about 60%, and the human eye sensory contribution value of the blue sub-pixel 110 is about 10%. The human eye sensory contribution value of the green sub-pixel 110 is significantly higher than that of the blue sub-pixel 110. Therefore, by setting the voltage adjustment unit 240 on the fourth branch line 274 to reduce the brightness of the green sub-pixel 110, the color deviation can be significantly improved.

[0075] In this embodiment, the driving module 200 includes a data driving unit, a selection unit, a polarity partition detection unit 230, a voltage adjustment unit 240, and an input control unit 250. The first signal line 261 and the second signal line 262 are both connected to the data driving unit. The polarity partition detection unit 230 is connected to the first signal line 261 and the second signal line 262. The selection unit includes a first selection unit 210 and a second selection unit 220. The first selection unit 210 is connected to the first signal line 261 through a first branch line 271 and a second branch line 272. The second selection unit 220 is connected to the second signal line 262 through a third branch line 273 and a fourth branch line 274. At least one voltage adjustment unit 240 is disposed on the fourth branch line 274. The input control unit 250 is connected to the polarity partition detection unit 230. In the polarity symmetric mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are the same. The polarity partition detection unit 230 controls the selection unit to operate through the input control unit 250, so that the first branch line 271 and the fourth branch line 274 are in a group, and the second branch line 272 and the third branch line 273 are in a group, and the data voltage is output row by row alternately. Since the data voltage V- output by the fourth branch line 274 and the data line n + 1 is lowered, the brightness of the green sub-pixel 110 controlled by the data line n + 1 is reduced, so that the color deviation can be improved or eliminated, and the display quality of the display panel 100 can be improved.

[0076] In some embodiments, the polarity partition detection unit 230 includes an exclusive OR gate circuit and an exclusive NOR gate circuit. When the polarity partition detection unit 230 is an exclusive OR gate circuit, if the data voltage polarities of the first signal line 261 and the second signal line 262 are the same, the exclusive OR gate circuit outputs a low level signal; if the data voltage polarities of the first signal line 261 and the second signal line 262 are different, the exclusive OR gate circuit outputs a high level signal.

[0077] When the polarity partition detection unit 230 is an exclusive NOR gate circuit, if the data voltage polarities of the first signal line 261 and the second signal line 262 are the same, the exclusive NOR gate circuit outputs a high level signal; if the data voltage polarities of the first signal line 261 and the second signal line 262 are different, the exclusive NOR gate circuit outputs a low level signal. In the following, the case where the polarity partition detection unit 230 is an exclusive NOR gate circuit is taken as an example for description. When the polarity partition detection unit 230 is an exclusive OR gate circuit, the control principle is the same, so it will not be described again.

[0078] The polarity partition detection unit 230 includes an exclusive OR gate circuit or an exclusive NOR gate circuit. By comparing the data voltage polarities of the first signal line 261 and the second signal line 262 through the exclusive OR gate circuit or the exclusive NOR gate circuit, it is judged whether the driving module 200 is in the normal polarity mode or the polarity partition mode. The structure of the polarity partition detection unit 230 is simple, and the manufacturing cost of the driving module 200 can be reduced.

[0079] In some embodiments, the voltage adjustment unit 240 is disposed on the fourth branch line 274 and is configured to lower the data voltage on the fourth branch line 274.

[0080] The voltage adjustment unit 240 is disposed on the fourth branch line 274. Compared with the solution in which the voltage adjustment unit 240 is integrated in the data driving unit, the complexity of the data driving unit can be reduced, and the manufacturing cost of the driving module 200 can be reduced.

[0081] In some embodiments, the voltage adjustment unit 240 is further disposed on the second branch line 272 and is configured to lower the data voltage on the second branch line 272.

[0082] When scanning the first row, since the voltage adjustment unit 240 is disposed on the fourth branch line 274, the fourth branch line 274 and the data line n+1 output the data voltage V-, and the brightness of the green (G) sub-pixel 110 controlled by the data line n+1 is reduced; when scanning the second row, since the voltage adjustment unit 240 is disposed on the second branch line 272, the second branch line 272 and the data line n output the data voltage V-, and the brightness of the blue (B) sub-pixel 110 controlled by the data line n is reduced, as Figure 3 shown.

[0083] The brightness of the blue sub-pixel 110 and the green sub-pixel 110 on both sides of the pixel column at the junction is reduced, which can further improve or eliminate color deviation and improve the display quality of the display panel 100.

[0084] In some embodiments, the first selection unit 210 includes a first transistor 211 and a second transistor 212. The first end of the first transistor 211 is connected to the first branch line 271, and the second end of the first transistor 211 is used to connect to the first data line. The first end of the second transistor 212 is connected to the second branch line 272, and the second end of the second transistor 212 is used to connect to the first data line. One of the first transistor 211 and the second transistor 212 is a P-channel transistor and the other is an N-channel transistor. For example, the first transistor 211 is an N-channel transistor and the second transistor 212 is a P-channel transistor.

[0085] The second selection unit 220 includes a third transistor 221 and a fourth transistor 222. A first end of the third transistor 221 is connected to the third branch line 273, and a second end of the third transistor 221 is for connecting to the second data line. A first end of the fourth transistor 222 is connected to the fourth branch line 274, and a second end of the fourth transistor 222 is for connecting to the second data line. One of the third transistor 221 and the fourth transistor 222 is a P-channel transistor and the other is an N-channel transistor, and the channel types of the first transistor 211 and the third transistor 221 are different. For example, the third transistor 221 is a P-channel transistor and the fourth transistor 222 is an N-channel transistor.

[0086] Both the first selection unit 210 and the second selection unit 220 are composed of two transistors with different channel types. The structure of the selection unit is simple, which can reduce the manufacturing cost of the driving module 200.

[0087] In some embodiments, the input control unit 250 includes a signal generator 251, a fifth transistor 252, a sixth transistor 253, and a seventh transistor 254. The signal generator 251 is configured to output a high-level signal and a low-level signal that alternate row by row. The signal generator 251 is connected to the frame start signal line, and the switching frequency of the high-level signal and the low-level signal of the signal generator 251 matches the refresh rate of the display panel 100, and the durations of the high-level signal and the low-level signal are both the time for scanning one row.

[0088] A first end of the fifth transistor 252 is connected to the signal generator 251, a second end of the fifth transistor 252 is connected to the control ends of the first transistor 211, the second transistor 212, the third transistor 221, and the fourth transistor 222, and a control end of the fifth transistor 252 is connected to the polarity partition detection unit 230. The fifth transistor 252 can be an N-channel transistor.

[0089] A first end of the sixth transistor 253 is connected to the first power supply 281, the first power supply 281 outputs a high-level signal, a second end of the sixth transistor 253 is connected to the control ends of the first transistor 211 and the second transistor 212, and a control end of the sixth transistor 253 is connected to the polarity partition detection unit 230. The sixth transistor 253 is a P-channel transistor.

[0090] A first end of the seventh transistor 254 is connected to the second power supply 282, the second power supply 282 outputs a low-level signal, a second end of the seventh transistor 254 is connected to the control ends of the third transistor 221 and the fourth transistor 222, and a control end of the seventh transistor 254 is connected to the polarity partition detection unit 230. The seventh transistor 254 is a P-channel transistor.

[0091] In the normal polarity mode, the data voltage of the first signal line 261 and the data voltage of the second signal line 262 have different polarities, the polarity partition detection unit 230 outputs a low-level signal, and the fifth transistor 252 is turned off; the sixth transistor 253 is turned on, and the high-level signal output by the first power supply 281 controls the first transistor 211 to turn on and controls the second transistor 212 to turn off, and the first branch line 271 outputs the data voltage V; the seventh transistor 254 is turned on, and the low-level signal output by the second power supply 282 controls the third transistor 221 to turn on and controls the fourth transistor 222 to turn off, and the third branch line 273 outputs the data voltage V.

[0092] In polarity symmetry mode, the data voltage on the first signal line 261 and the data voltage on the second signal line 262 have the same polarity. The polarity partition detection unit 230 outputs a high-level signal, and the sixth and seventh transistors 253 and 254 are both off. The fifth transistor 252 is on. Because the signal generator 251 alternately outputs high-level and low-level signals on a row-by-row basis, the first transistor 211 and the fourth transistor 222 form a group, and the second transistor 212 and the third transistor 221 form a group, and they are alternately turned on and off on a row-by-row basis. The first branch line 271 and the fourth branch line 274 form a group, and the second branch line 272 and the third branch line 273 form a group, and they alternately output data voltages on a row-by-row basis. For example, when scanning the first row, the first branch line 271 outputs a data voltage V, and the fourth branch line 274 outputs a data voltage V-. When scanning the second row, the second branch line 272 outputs a data voltage V-, and the third branch line 273 outputs a data voltage V.

[0093] It should be noted that the fifth transistor 252 can be an N-channel transistor, and the sixth transistor 253 and the seventh transistor 254 can be P-channel transistors, but is not limited to this. When the polarity partition detection unit 230 is an XOR gate circuit, the fifth transistor 252 can also be a P-channel transistor, and the sixth transistor 253 and the seventh transistor 254 can also be N-channel transistors.

[0094] In some embodiments, the voltage adjustment unit 240 is further disposed on the second branch line 272 for increasing the data voltage on the second branch line 272 .

[0095] The voltage adjustment unit 240 on the second branch line 272 can either reduce or increase the brightness of the blue sub-pixel 110. The driving module 200 can selectively reduce or increase the brightness of the blue sub-pixel 110 according to the color deviation of the display panel 100, thereby increasing the color deviation adjustment range.

[0096] Example 2

[0097] The difference between the second embodiment and the first embodiment is that the driving module 200 further includes a third selection unit 291 and a fourth selection unit 292 .

[0098] See Figure 4 As shown, the third selection unit 291 is connected to the third signal line 263 through the fifth branch line 275 and the sixth branch line 276, and is used to control one of the fifth branch line 275 and the sixth branch line 276 to output a data voltage to the data line n - 1. A voltage adjustment unit 240 is provided on the sixth branch line 276. The structure of the third selection unit 291 is the same as that of the second selection unit 220, and the connection manner between the third selection unit 291 and the input control unit 250 is the same as the connection manner between the second selection unit 220 and the input control unit 250.

[0099] The fourth selection unit 292 is connected to the fourth signal line 264 through the seventh branch line 277 and the eighth branch line 278, and is used to control one of the seventh branch line 277 and the eighth branch line 278 to output a data voltage to the data line n + 2. A voltage adjustment unit 240 is provided on the eighth branch line 278. The structure of the fourth selection unit 292 is the same as that of the first selection unit 210, and the connection manner between the fourth selection unit 292 and the input control unit 250 is the same as the connection manner between the second selection unit 220 and the input control unit 250.

[0100] In the normal polarity mode, the fifth branch line 275 and the seventh branch line 277 output the data voltage V; in the polarity symmetric mode, when scanning the first row, the sixth branch line 276 outputs the data voltage V -, and the seventh branch line 277 outputs the data voltage V; when scanning the second row, the fifth branch line 275 outputs the data voltage V, and the eighth branch line 278 outputs the data voltage V -, as Figure 5 shown. That is to say, the brightness of the blue sub - pixel 110 controlled by the data line n - 1 is reduced, and the brightness of the green sub - pixel 110 controlled by the data line n + 2 is reduced.

[0101] The brightness of all the sub - pixels 110 in one pixel column on each side of the pixel column at the junction (red pixel column) is reduced, which can further improve or eliminate color deviation and improve the display quality of the display panel 100.

[0102] It should be noted that the brightness of the sub - pixels 110 on the right side of the data line n - 1 and the left side of the data line n + 2 can be selectively reduced through the third selection unit 291 and the fourth selection unit 292, but it is not limited to this. In the polarity symmetric mode, the brightness of all the sub - pixels 110 controlled by the data line n - 1 and the data line n + 2 can also be reduced, which can be determined according to the specific situation.

[0103] Embodiment III

[0104] The main difference between Embodiment III and Embodiment I is that the structures of the first selection unit 210 and the second selection unit 220 are different.

[0105] See Figure 6 As shown, the first selection unit 210 further includes an eighth transistor 213 and a ninth transistor 214. The first end of the eighth transistor 213 is connected to the first signal line 261, and the second end of the eighth transistor 213 is connected to the first branch line 271 and the second branch line 272. The first end of the ninth transistor 214 is connected to the first signal line 261, and the second end of the ninth transistor 214 is connected to the first data line. A voltage adjustment unit 240 is provided on the first branch line 271, and the voltage adjustment unit 240 on the second branch line 272 is used to lower the data voltage, and the voltage adjustment unit 240 on the first branch line 271 is used to increase the data voltage.

[0106] The second selection unit 220 further includes a tenth transistor 223 and an eleventh transistor 224. The first end of the tenth transistor 223 is connected to the second signal line 262, and the second end of the tenth transistor 223 is connected to the third branch line 273 and the fourth branch line 274. The first end of the eleventh transistor 224 is connected to the second signal line 262, and the second end of the eleventh transistor 224 is connected to the second data line. A voltage adjustment unit 240 is provided on the third branch line 273, and the voltage adjustment unit 240 on the fourth branch line 274 is used to lower the data voltage, and the voltage adjustment unit 240 on the third branch line 273 is used to increase the data voltage.

[0107] Among them, the eighth transistor 213 and the tenth transistor 223 are N-channel transistors, and the ninth transistor 214 and the eleventh transistor 224 are P-channel transistors. When the polarity partition detection unit 230 is an exclusive-OR gate circuit, the eighth transistor 213 and the tenth transistor 223 can be P-channel transistors, and the ninth transistor 214 and the eleventh transistor 224 are N-channel transistors.

[0108] The first selection unit 210 and the second selection unit 220 include four transistors and can perform two selections. The first selection can be used to select whether to adjust the data voltage, and the second selection can be used to select to lower the data voltage or increase the data voltage.

[0109] It should be noted that the driving module 200 can adopt the combination of Embodiment 2 and Embodiment 3, that is, the first selection unit 210 and the second selection unit 220 adopt the four-transistor solution of Embodiment 3, and the third selection unit 291 and the fourth selection unit 292 adopt the two-transistor solution of Embodiment 1.

[0110] In some embodiments, the input control unit 250 includes a signal generator 251, a fifth transistor 252, a sixth transistor 253, and a seventh transistor 254.

[0111] The signal generator 251 is used to output high-level signals and low-level signals that alternate line by line. The signal generator 251 is connected to the frame start signal line. The switching frequency of the high-level signals and low-level signals of the signal generator 251 matches the refresh rate of the display panel 100. The duration of both the high-level signals and the low-level signals is the time for scanning one line.

[0112] The first terminal of the fifth transistor 252 is connected to the signal generator 251. The second terminal of the fifth transistor 252 is connected to the control terminals of the first transistor 211, the second transistor 212, the third transistor 221, and the fourth transistor 222. The control terminal of the fifth transistor 252 is connected to the polarity partition detection unit 230. The fifth transistor 252 can be an N-channel transistor.

[0113] The first terminal of the sixth transistor 253 is connected to the first power supply 281. The first power supply 281 outputs a high-level signal. The second terminal of the sixth transistor 253 is connected to the control terminals of the eighth transistor 213, the ninth transistor 214, the tenth transistor 223, and the eleventh transistor 224. The control terminal of the sixth transistor 253 is connected to the polarity partition detection unit 230. The sixth transistor 253 is a P-channel transistor.

[0114] The first terminal of the seventh transistor 254 is connected to the second power supply 282. The second power supply 282 outputs a low-level signal. The second terminal of the seventh transistor 254 is connected to the control terminals of the eighth transistor 213, the ninth transistor 214, the tenth transistor 223, and the eleventh transistor 224. The control terminal of the seventh transistor 254 is connected to the polarity partition detection unit 230. The seventh transistor 254 is a P-channel transistor.

[0115] In the normal polarity mode, the data voltages of the first signal line 261 and the second signal line 262 have different polarities. The polarity partition detection unit 230 outputs a low-level signal. The fifth transistor 252 and the seventh transistor 254 are turned off. The sixth transistor 253 is turned on. The high-level signal output by the first power supply 281 controls the ninth transistor 214 and the eleventh transistor 224 to be turned on, and controls the eighth transistor 213 and the tenth transistor 223 to be turned off. The ninth transistor 214 and the eleventh transistor 224 output the data voltage V.

[0116] In the polarity symmetric mode, the data voltages of the first signal line 261 and the second signal line 262 have the same polarity. The polarity partition detection unit 230 outputs a high-level signal, the sixth transistor 253 is turned off, and the fifth transistor 252 and the seventh transistor 254 are turned on. Since the signal generator 251 alternately outputs high-level signals and low-level signals line by line, the first transistor 211 and the fourth transistor 222 form a group, and the second transistor 212 and the third transistor 221 form a group, which are alternately turned on and off line by line. The first branch line 271 and the fourth branch line 274 form a group, and the second branch line 272 and the third branch line 273 form a group, which alternately output data voltages line by line. For example, when scanning the first row, the first branch line 271 outputs a data voltage V+, and the brightness of the red sub-pixel 110 increases. The fourth branch line 274 outputs a data voltage V-, and the brightness of the green sub-pixel 110 decreases. When scanning the second row, the second branch line 272 outputs a data voltage V-, and the brightness of the blue sub-pixel 110 decreases. The third branch line 273 outputs a data voltage V+, and the brightness of the red sub-pixel 110 increases, as Figure 7 shown.

[0117] In the polarity symmetric mode, there is always a situation where all pixels in a column at the junction are either all positive or all negative, and this will not change. The overall color of the red pixel column is relatively light. Increasing the data voltage of the red pixel column can further improve or eliminate color deviation and improve the display quality of the display panel 100.

[0118] It should be noted that the fifth transistor 252 and the seventh transistor 254 can be N-channel transistors, and the sixth transistor 253 can be a P-channel transistor, but it is not limited to this. When the polarity partition detection unit 230 is an exclusive OR gate circuit, the fifth transistor 252 and the seventh transistor 254 can also be P-channel transistors, and the sixth transistor 253 can also be an N-channel transistor.

[0119] The eighth transistor 213 and the ninth transistor 214 are controlled by the first power supply 281. Which one of the eighth transistor 213 and the ninth transistor 214 is an N-channel transistor can be set according to whether the first power supply 281 outputs a high-level signal or a low-level signal. The tenth transistor 223 and the eleventh transistor 224 are controlled by the second power supply 282. Which one of the tenth transistor 223 and the eleventh transistor 224 is an N-channel transistor can be set according to whether the second power supply 282 outputs a high-level signal or a low-level signal.

[0120] In addition, the eighth transistor 213 and the ninth transistor 214 are controlled by the first power supply 281, and the tenth transistor 223 and the eleventh transistor 224 are controlled by the second power supply 282. However, this is not limited thereto. The eighth transistor 213, the ninth transistor 214, the tenth transistor 223, and the eleventh transistor 224 may also be controlled by the polarity partition detection unit 230, depending on the specific situation.

[0121] Embodiment 4

[0122] This application provides a display device. As shown in Figure 8 the figure, the display device includes a driving module 200 and a display panel 100. The display panel 100 is connected to the driving module 200, and the driving module 200 includes the driving module 200 disclosed in Embodiments 1 to 3.

[0123] The display device includes a driving module 200, which includes a data driving unit, a selection unit, a polarity partition detection unit 230, a voltage adjustment unit 240, and an input control unit 250. The first signal line 261 and the second signal line 262 are both connected to the data driving unit. The polarity partition detection unit 230 is connected to the first signal line 261 and the second signal line 262. The selection unit includes a first selection unit 210 and a second selection unit 220. The first selection unit 210 is connected to the first signal line 261 through the first branch line 271 and the second branch line 272. The second selection unit 220 is connected to the second signal line 262 through the third branch line 273 and the fourth branch line 274. At least one voltage adjustment unit 240 is disposed on the fourth branch line 274. The input control unit 250 is connected to the polarity partition detection unit 230. In the polarity symmetric mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are the same. The polarity partition detection unit 230 controls the selection unit to operate through the input control unit 250, so that the first branch line 271 and the fourth branch line 274 form a group, and the second branch line 272 and the third branch line 273 form a group, and the data voltage is output alternately line by line. Since the data voltage V- output after being lowered is output from the fourth branch line 274 and the data line n + 1, the brightness of the green sub-pixel 110 controlled by the data line n + 1 is reduced, and the color deviation can be improved or eliminated, and the display quality of the display panel 100 can be improved.

Claims

1. A driving module, comprising a data driving unit, characterized in that, The driving module further includes: A polarity partition detection unit connected to the first signal line and the second signal line, both the first signal line and the second signal line being connected to the data driving unit; A selection unit including a first selection unit and a second selection unit. The first selection unit is connected to the first signal line through a first branch line and a second branch line, and is used to control one of the first branch line and the second branch line to output a data voltage. The second selection unit is connected to the second signal line through a third branch line and a fourth branch line, and is used to control one of the third branch line and the fourth branch line to output a data voltage; A voltage adjustment unit, at least one of the voltage adjustment units being disposed on the fourth branch line or in the data driving unit; An input control unit connected to the polarity partition detection unit. In the normal polarity mode, the data voltage polarities of the first signal line and the second signal line are opposite, and the input control unit controls the selection unit to work so that the first selection unit and the second selection unit output data voltages. In the polarity symmetric mode, the data voltage polarities of the first signal line and the second signal line are the same, and the input control unit controls the selection unit to work so that the first branch line and the fourth branch line form a group, and the second branch line and the third branch line form a group, and the data voltages are output alternately line by line.

2. The drive module according to claim 1, wherein The first selection unit includes a first transistor and a second transistor. The first end of the first transistor is connected to the first branch line, the second end of the first transistor is used to connect to a first data line, the first end of the second transistor is connected to the second branch line, the second end of the second transistor is used to connect to the first data line, and one of the first transistor and the second transistor is a P-channel transistor and the other is an N-channel transistor; The second selection unit includes a third transistor and a fourth transistor. The first end of the third transistor is connected to the third branch line, the second end of the third transistor is used to connect to a second data line, the first end of the fourth transistor is connected to the fourth branch line, the second end of the fourth transistor is used to connect to the second data line, and one of the third transistor and the fourth transistor is a P-channel transistor and the other is an N-channel transistor, and the channel types of the first transistor and the third transistor are different.

3. The drive module according to claim 2, characterized in that, The input control unit includes a signal generator, a fifth transistor, a sixth transistor, and a seventh transistor. The signal generator is connected to a frame start signal line, and the signal generator is used to output a high-level signal and a low-level signal that alternate line by line; The first end of the fifth transistor is connected to the signal generator, the second end of the fifth transistor is connected to the control ends of the first transistor, the second transistor, the third transistor, and the fourth transistor, and the control end of the fifth transistor is connected to the polarity partition detection unit; A first end of the sixth transistor is connected to a first power supply, the first power supply outputs the high-level signal, a second end of the sixth transistor is connected to control ends of the first transistor and the second transistor, and a control end of the sixth transistor is connected to the polarity partition detection unit; A first end of the seventh transistor is connected to a second power supply, the second power supply outputs the low-level signal, a second end of the seventh transistor is connected to control ends of the third transistor and the fourth transistor, and a control end of the seventh transistor is connected to the polarity partition detection unit; Wherein, the fifth transistor is an N-channel transistor, the sixth transistor and the seventh transistor are P-channel transistors, or the fifth transistor is a P-channel transistor, and the sixth transistor and the seventh transistor are N-channel transistors.

4. The drive module according to claim 3, characterized in that, The voltage adjustment unit is arranged on the fourth branch line and is used for lowering the data voltage on the fourth branch line.

5. The drive module according to claim 4, wherein The voltage adjustment unit is further arranged on the second branch line and is used for lowering the data voltage on the second branch line.

6. The drive module according to claim 4, wherein The voltage adjustment unit is further arranged on the second branch line and is used for raising the data voltage on the second branch line.

7. The drive module according to claim 2, wherein The first selection unit further includes an eighth transistor and a ninth transistor. A first end of the eighth transistor is connected to the first signal line, a second end of the eighth transistor is connected to the first branch line and the second branch line, a first end of the ninth transistor is connected to the first signal line, a second end of the ninth transistor is connected to the first data line, the voltage adjustment unit is arranged on the first branch line, the voltage adjustment unit on the second branch line is used for lowering the data voltage, and the voltage adjustment unit on the first branch line is used for raising the data voltage; The second selection unit further includes a tenth transistor and an eleventh transistor. A first end of the tenth transistor is connected to the second signal line, a second end of the tenth transistor is connected to the third branch line and the fourth branch line, a first end of the eleventh transistor is connected to the second signal line, a second end of the eleventh transistor is connected to the second data line, the voltage adjustment unit is arranged on the third branch line, the voltage adjustment unit on the fourth branch line is used for lowering the data voltage, and the voltage adjustment unit on the third branch line is used for raising the data voltage; Wherein, the eighth transistor and the tenth transistor are N-channel transistors, the ninth transistor and the eleventh transistor are P-channel transistors, or the eighth transistor and the tenth transistor are P-channel transistors, and the ninth transistor and the eleventh transistor are N-channel transistors.

8. The drive module according to claim 7, wherein The input control unit includes a signal generator, a fifth transistor, a sixth transistor and a seventh transistor. The signal generator is connected to the frame start signal line, and the signal generator is used for outputting high-level signals and low-level signals that alternate line by line; The first end of the fifth transistor is connected to the signal generator, the second end of the fifth transistor is connected to the control ends of the first transistor, the second transistor, the third transistor, and the fourth transistor, and the control end of the fifth transistor is connected to the polarity partition detection unit; The first end of the sixth transistor is connected to a first power supply that outputs the high-level signal, the second end of the sixth transistor is connected to the control ends of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor, and the control end of the sixth transistor is connected to the polarity partition detection unit; The first end of the seventh transistor is connected to a second power supply that outputs the low-level signal, the second end of the seventh transistor is connected to the control ends of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor, and the control end of the seventh transistor is connected to the polarity partition detection unit; Wherein, the fifth transistor and the seventh transistor are N-channel transistors, the sixth transistor is a P-channel transistor, or the fifth transistor and the seventh transistor are P-channel transistors, and the sixth transistor is an N-channel transistor.

9. The drive module according to claim 1, wherein, The polarity partition detection unit includes an exclusive-OR gate circuit or an exclusive-NOR gate circuit.

10. A display device, characterized in that, Comprising: The driving module according to any one of claims 1 to 9; A display panel, connected to the driving module.

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