A high-precision anti-interference circuit structure

Abstract

The present invention relates to the field of battery power supply technology, and more specifically to a high-precision anti-interference circuit structure. In the present invention, by configuring a capacitor circuit, a first control circuit, a second control circuit, and a follower circuit, it is possible to fix the output control signal to a high-level signal after the input signal is on the rising edge and greater than a first flip threshold voltage, and to fix the output control signal to a low-level signal after the input signal is on the falling edge and less than the first flip threshold voltage. That is, noise on the rising edge of the input signal will not be recognized as multiple rising edges, and noise on the falling edge will not be recognized as multiple falling edges, thereby improving the anti-interference capability, control accuracy, and reliability of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of battery power supply, and in particular to a high-precision anti-interference circuit structure. Background Art

[0002] Prior art battery charging circuits typically include an integrated circuit control chip, a power circuit, and a battery load. The integrated circuit control chip controls the power circuit to charge the battery load. When the battery load is charging, changes in the battery load generate high-frequency noise. This high-frequency noise may couple to the chip pins through parasitic capacitance or PCB traces, thereby interfering with the control signals within the chip. This can cause a single rising or falling edge of the control signal to be recognized as multiple rising or falling edges, resulting in control signal distortion, reduced accuracy, and reduced reliability of the battery charging circuit. Summary of the Invention

[0003] In view of this, the present invention provides a high-precision anti-interference circuit structure to solve the technical problem that the control signal in the battery charging circuit is easily interfered with, resulting in control signal disorder.

[0004] The technical solutions provided by the present invention are as follows:

[0005] A first aspect of the present invention provides a high-precision anti-interference circuit structure, comprising: a follower circuit, a first end of which receives an input signal, a second end of which is connected to a first end of a first control circuit and a first end of a capacitor circuit, a third end of which is connected to a first end of a second control circuit and a second end of the capacitor circuit, a fourth end of which is connected to the second end of the first control circuit, a fifth end of which is connected to the second end of the second control circuit, and the fourth end is used to output a control signal; a first control circuit, a third end of which is connected to a third end of the capacitor circuit and a third end of the second control circuit; a capacitor circuit, a fourth end of which is connected to an external power supply, and a fifth end of which is grounded;

[0006] When the input signal is at a rising edge and is greater than a first flip threshold voltage, the control signal output by the follower circuit does not follow the change of the input signal and always outputs a high-level control signal. When the capacitor circuit discharges to a second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit follows the change of the input signal, and the capacitor circuit enters a charging state.

[0007] When the input signal is at a falling edge and is less than the first flip threshold voltage, the control signal output by the follower circuit does not follow the change of the input signal and always outputs a low-level control signal. When the capacitor circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit follows the change of the input signal, and the capacitor circuit enters a charging state.

[0008] The first flip threshold voltage is the voltage at which a component in the follower circuit undergoes voltage flipping, and the second flip threshold voltage is the voltage at which a component in the first control circuit and the second control circuit undergoes voltage flipping.

[0009] In an optional embodiment, when the input signal is on a rising edge and is greater than a first flip threshold voltage, the follower circuit outputs a high-level control signal at the fourth end and a low-level signal at the fifth end according to the input signal and the low-level signal output by the second control circuit at the previous moment; the second end of the first control circuit receives the high-level control signal and outputs a high-level signal at the first end according to the high-level signal generated after the capacitor circuit is charged at the previous moment and the state of the first control circuit at the previous moment; the second end of the second control circuit receives the low-level signal output by the fifth end of the follower circuit and outputs a low-level signal at the first end according to the state of the second control circuit at the previous moment; under the control of the high-level signal output by the first control circuit and the low-level signal output by the second control circuit, the follower circuit outputs a high-level control signal;

[0010] When the input signal is on a falling edge and is less than the first flip threshold voltage, the follower circuit outputs a low-level control signal at the fourth end and a high-level signal at the fifth end according to the input signal and the low-level signal output by the first control circuit at the previous moment; the second end of the second control circuit receives the high-level signal output by the fifth end of the follower circuit, and outputs a high-level signal at the first end according to the high-level signal generated after the capacitor circuit is charged at the previous moment and the state of the second control circuit at the previous moment. Under the control of the high-level signal output by the second control circuit, the follower circuit outputs a low-level control signal.

[0011] In an optional embodiment, when the input signal is on a rising edge and is greater than a first flip threshold voltage, the capacitor circuit enters a discharge state according to a high-level signal output by the first end of the first control circuit, and outputs a low-level signal when discharged to a second flip threshold voltage; the third end of the first control circuit receives the low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end; the third end of the second control circuit receives the low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end; based on the low-level signal output by the first end of the first control circuit and the low-level signal output by the first end of the second control circuit, the control signal output by the follower circuit follows the input signal, and at the same time, the capacitor circuit enters a charging state;

[0012] After the capacitor circuit is charged to a high level, the first end of the first control circuit and the first end of the second control circuit output a low level signal. Based on the low level signal output by the first end of the first control circuit and the first end of the second control circuit, the control signal output by the follower circuit follows the input signal change. At the same time, the capacitor circuit maintains the high level state after charging.

[0013] In an optional embodiment, when the input signal is at a falling edge and is less than a first flip threshold voltage, the capacitor circuit enters a discharge state according to a high-level signal output by the first end of the second control circuit, and outputs a low-level signal when discharged to the second flip threshold voltage. The third end of the second control circuit receives the low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end; the third end of the first control circuit receives the low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end. Based on the low-level signal output by the first end of the first control circuit and the low-level signal output by the first end of the second control circuit, the control signal output by the follower circuit follows the input signal change, and at the same time, the capacitor circuit enters a charging state;

[0014] After the capacitor circuit is charged to a high level, the first end of the second control circuit and the first end of the first control circuit output a low level signal. Based on the low level signal output by the first end of the first control circuit and the first end of the second control circuit, the control signal output by the follower circuit follows the input signal change. At the same time, the capacitor circuit maintains the high level state after charging.

[0015] In an optional embodiment, when the circuit is just powered on and the input signal is a low-level signal, the first control circuit and the second control circuit respectively output low-level signals at the first end according to the capacitor circuit in the initial state, and the capacitor circuit enters a charging state according to the low-level signals output by the first control circuit and the second control circuit; the follower circuit outputs a low-level control signal at the fourth end according to the input signal and the low-level signal output by the first control circuit.

[0016] In an optional embodiment, when the circuit is just powered on and the input signal is a high-level signal, the first control circuit and the second control circuit respectively output low-level signals at the first end according to the initial state of the capacitor circuit, and the capacitor circuit enters a charging state according to the low-level signals output by the first control circuit and the second control circuit; the follower circuit outputs a high-level control signal at the fourth end according to the input signal and the low-level signal output by the second control circuit.

[0017] In an optional embodiment, the follower circuit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and a second NAND gate; the input end of the first inverter receives an input signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the third inverter, the input end of the third inverter is connected to the first end of the first control circuit and the first end of the capacitor circuit, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the fourth inverter, the input end of the fourth inverter is connected to the first end of the second control circuit and the second end of the capacitor circuit, the output end of the second NAND gate is connected to the input end of the second inverter and the second end of the second control circuit, the output end of the second inverter is connected to the second end of the first control circuit, and outputs a control signal.

[0018] In an optional embodiment, the first control circuit includes: a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate; the first input end of the third NAND gate is connected to the output end of the eighth NAND gate and the third input end of the sixth NAND gate, the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, the first input end of the fifth NAND gate, and the first input end of the sixth NAND gate, the output end of the third NAND gate is connected to the first input end of the fourth NAND gate, the second input end of the fourth NAND gate is connected to the second input end of the sixth NAND gate and the fourth end of the follower circuit, the third input end of the fourth NAND gate is connected to the second input end of the eighth NAND gate, the third input end of the seventh NAND gate, the third end of the capacitor circuit, and the third end of the second control circuit, the second input end of the fifth NAND gate is connected to the output end of the seventh NAND gate, the output end of the fifth NAND gate is connected to the first input end of the seventh NAND gate, the second end of the follower circuit, and the first end of the capacitor circuit, and the output end of the sixth NAND gate is connected to the second input end of the seventh NAND gate and the first input end of the eighth NAND gate.

[0019] In an optional embodiment, the second control circuit includes: a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, and a fourteenth NAND gate; the first input end of the ninth NAND gate is connected to the output end of the fourteenth NAND gate and the third input end of the twelfth NAND gate, the second input end of the ninth NAND gate is connected to the output end of the tenth NAND gate, the first input end of the eleventh NAND gate, and the first input end of the twelfth NAND gate, the output end of the ninth NAND gate is connected to the first input end of the tenth NAND gate, the second input end of the tenth NAND gate is connected to the twelfth NAND gate The second input terminal of the NAND gate and the fifth terminal of the follower circuit, the third input terminal of the tenth NAND gate is connected to the second input terminal of the fourteenth NAND gate, the third input terminal of the thirteenth NAND gate, the third terminal of the capacitor circuit and the third terminal of the first control circuit, the second input terminal of the eleventh NAND gate is connected to the output terminal of the thirteenth NAND gate, the output terminal of the eleventh NAND gate is connected to the first input terminal of the thirteenth NAND gate, the third terminal of the follower circuit and the second terminal of the capacitor circuit, and the output terminal of the twelfth NAND gate is connected to the second input terminal of the thirteenth NAND gate and the first input terminal of the fourteenth NAND gate.

[0020] In an optional embodiment, the capacitor circuit includes: a first OR gate, a first capacitor, a first switch tube, a second switch tube, a third switch tube and a first current source; the first input end of the first OR gate is connected to the first end of the first control circuit and the second end of the follower circuit, the second input end of the first OR gate is connected to the first end of the second control circuit and the third end of the follower circuit, the output end of the first OR gate is connected to the first end of the first switch tube, the second end of the first switch tube is connected to one end of the first current source and an external power supply, the third end of the first switch tube is connected to one end of the first capacitor, the first end of the second switch tube, the third end of the first control circuit and the third end of the second control circuit, the other end of the first capacitor is connected to the second end of the second switch tube, the first end of the third switch tube and grounded, and the third end of the second switch tube is connected to the second end, the third end and the other end of the first current source.

[0021] In an optional implementation, the time T0 for the third terminal of the capacitor circuit to discharge to the second flip threshold voltage is expressed by the following formula:

[0022] max[T1,T3] <T0<min[T1+T2,T3+T4]

[0023] In the formula, T1 represents the time when the input signal rises from the first flip threshold voltage to the external power supply voltage on the rising edge, T2 represents the sum of the time when the input signal is in a high-level signal and the time when the input signal drops from the external power supply voltage to the first flip threshold voltage on the falling edge, T3 represents the time when the input signal drops from the first flip threshold voltage to the ground voltage on the falling edge; T4 represents the sum of the time when the input signal is in a low-level signal and the time when the input signal rises from the ground voltage to the first flip threshold voltage on the rising edge. The voltage of the high-level signal is equal to the external power supply voltage, and the voltage of the low-level signal is equal to the ground voltage.

[0024] A second aspect of the present invention provides a battery-powered circuit, comprising: an integrated circuit control chip, a power circuit, and a battery load. The integrated circuit control chip comprises the first aspect of the present invention and the high-precision anti-interference circuit structure of any one of the first aspects. The integrated circuit control chip controls the power circuit to power the battery load according to a control signal output by a follower circuit.

[0025] The technical solution of the present invention has the following advantages:

[0026] In the present invention, by configuring the capacitor circuit, the first control circuit, the second control circuit, and the follower circuit, the output control signal is fixed to a high-level signal when the input signal is on a rising edge and greater than a first flip threshold voltage, and the output control signal is fixed to a low-level signal when the input signal is on a falling edge and less than the first flip threshold voltage. That is, noise on the rising edge of the input signal is not recognized as multiple rising edges, and noise on the falling edge is not recognized as multiple falling edges, thereby improving the circuit's anti-interference capability, control accuracy, and reliability.

[0027] In the present invention, a high-precision anti-interference circuit structure is provided in the integrated circuit control chip, so that the control signal inside the integrated circuit control chip will not be interfered with by changes in battery load, thereby improving the accuracy and reliability of the battery charging circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 1 is a structural block diagram of a high-precision anti-interference circuit structure in an embodiment of the present invention;

[0030] Figure 2 1 is a schematic diagram of a high-precision anti-interference circuit structure according to an embodiment of the present invention;

[0031] Figure 3 Schematic diagram of the waveforms of the input signal and output control signal of the high-precision anti-interference circuit structure in an embodiment of the present invention;

[0032] Figure 4 4 is a structural block diagram of a battery power supply circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0036] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] The embodiment of the present invention provides a high-precision anti-interference circuit structure, such as Figure 1As shown, it includes: a follower circuit 10, a first end of which receives an input signal IN, a second end connected to the first end of the first control circuit 20 and the first end of the capacitor circuit 40, a third end connected to the first end of the second control circuit 30 and the second end of the capacitor circuit 40, a fourth end connected to the second end of the first control circuit 20, a fifth end connected to the second end of the second control circuit 30, and the fourth end is used to output a control signal OUT; the first control circuit 20, a third end of which is connected to the third end of the capacitor circuit 40 and the third end of the second control circuit 30; the capacitor circuit 40, a fourth end of which is connected to the external power supply VCC, and a fifth end of which is grounded GND.

[0038] When the input signal is at a rising edge and is greater than the first flip threshold voltage, the control signal output by the follower circuit does not follow the input signal change and always outputs a high-level control signal. When the capacitor circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit follows the input signal change, and the capacitor circuit enters a charging state.

[0039] When the input signal is at a falling edge and is less than the first flip threshold voltage, the control signal output by the follower circuit does not follow the input signal change and always outputs a low-level control signal. When the capacitor circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit follows the input signal change, and the capacitor circuit enters a charging state.

[0040] The first flip threshold voltage is the voltage at which a component in the follower circuit undergoes voltage flipping, and the second flip threshold voltage is the voltage at which a component in the first control circuit and the second control circuit undergoes voltage flipping.

[0041] Among them, when the circuit is just powered on, that is, when the external power supply connected to the capacitor circuit is just connected, the capacitor circuit has not been charged yet and the capacitor circuit is in an initial state. At this time, the terminal voltage of the third end of the capacitor circuit connected to the first control circuit and the second control circuit is a low-level signal, then the first control circuit and the second control circuit output low-level signals at the first end respectively according to the capacitor circuit in the initial state, and the low-level signals output by the first control circuit and the second control circuit are then input into the capacitor circuit through the first end and the second end of the capacitor circuit, thereby causing the capacitor circuit to enter a charging state.

[0042] In an optional embodiment, when the circuit is powered on and the input signal is at a low level, based on the low level signal output by the first control circuit, after the low level input signal is input to the follower circuit, the fourth end of the follower circuit outputs a low level control signal, and the fifth end of the follower circuit outputs a high level signal.

[0043] When the input signal switches from a low level to a high level (i.e., the input signal is on a rising edge and is greater than a first flip threshold voltage), the follower circuit outputs a high-level control signal at the fourth end and a low-level signal at the fifth end according to the input signal and the low-level signal output by the second control circuit at the previous moment (i.e., when the input signal is at a low level); the second end of the first control circuit receives the high-level control signal and outputs a high-level signal at the first end according to the high-level signal generated after the capacitor circuit is charged at the previous moment and the state of the first control circuit at the previous moment (i.e., the state when the input signal is at a low level); the second end of the second control circuit receives the low-level signal output by the fifth end of the follower circuit and outputs a low-level signal at the first end according to the state of the second control circuit at the previous moment; under the control of the high-level signal output by the first control circuit and the low-level signal output by the second control circuit, the follower circuit outputs a high-level control signal.

[0044] When the input signal switches to a high level, the capacitor circuit enters a discharge state according to the high level signal output by the first end of the first control circuit, and outputs a low level signal when discharged to the second flip threshold voltage; the third end of the first control circuit receives the low level signal generated after the capacitor circuit is discharged, and outputs a low level signal at the first end; the third end of the second control circuit receives the low level signal generated after the capacitor circuit is discharged, and outputs a low level signal at the first end, based on the low level signal output by the first end of the first control circuit and the low level signal output by the first end of the second control circuit, the control signal output by the follower circuit follows the change of the input signal, and at the same time, the capacitor circuit enters a charging state;

[0045] After the capacitor circuit is charged to a high level, the first end of the first control circuit and the first end of the second control circuit output a low level signal. Based on the low level signal output by the first end of the first control circuit and the first end of the second control circuit, the control signal output by the follower circuit follows the input signal change. At the same time, the capacitor circuit maintains the high level state after charging.

[0046] In an optional embodiment, when the circuit is powered on and the input signal is at a high level, based on the low level signal output by the second control circuit, after the high level input signal is input to the follower circuit, the fourth terminal of the follower circuit outputs a high level control signal. The fifth terminal of the follower circuit outputs a low level signal.

[0047] When the input signal switches from a high level to a low level (i.e., the input signal is on a falling edge and is less than the first flip threshold voltage), the follower circuit outputs a low-level control signal at the fourth end and a high-level signal at the fifth end based on the input signal and the low-level signal output by the first control circuit at the previous moment (i.e., when the input signal is at a high level); the second end of the second control circuit receives the high-level signal output by the fifth end of the follower circuit, and outputs a high-level signal at the first end based on the high-level signal generated after the capacitor circuit is charged at the previous moment and the state of the second control circuit at the previous moment (i.e., the state when the input signal is at a high level). Under the control of the high-level signal output by the second control circuit, the follower circuit outputs a low-level control signal.

[0048] When the input signal switches to a low level, the capacitor circuit enters a discharge state according to the high level signal output by the first end of the second control circuit, and outputs a low level signal when discharged to the second flip threshold voltage. The third end of the second control circuit receives the low level signal generated after the capacitor circuit is discharged, and outputs a low level signal at the first end; the third end of the first control circuit receives the low level signal generated after the capacitor circuit is discharged, and outputs a low level signal at the first end. Based on the low level signal output by the first end of the first control circuit and the low level signal output by the first end of the second control circuit, the control signal output by the follower circuit follows the change of the input signal, and at the same time, the capacitor circuit enters a charging state;

[0049] After the capacitor circuit is charged to a high level, the first end of the second control circuit and the first end of the first control circuit output a low level signal. Based on the low level signal output by the first end of the first control circuit and the first end of the second control circuit, the control signal output by the follower circuit follows the input signal change. At the same time, the capacitor circuit maintains the high level state after charging.

[0050] It should be noted that, among the above-mentioned signals, the low-level signal can be a ground signal, i.e., a zero-level signal, and the high-level signal can be an external power supply voltage signal. The control signal output by the fourth terminal of the follower circuit can be used as the output signal of the high-precision anti-interference circuit structure, i.e., the circuit structure outputs a control signal to control other structures. In addition, when this circuit structure is not set, the related art may directly use the input signal (as a control signal) to control other structures. However, due to the presence of interference signals, the input signal may be affected. Therefore, the present invention provides this circuit structure, which can obtain an undisturbed output signal by adjusting the input signal, and then the undisturbed output signal can be used to control other structures.

[0051] Under normal circumstances, due to the large gap between high-level signals and low-level signals, when the input signal is in a low-level signal or a high-level signal, even if there is an interference signal from the outside, the interference signal input into the circuit structure will not cause the input signal to change from a high level to a low level or from a low level to a high level. Therefore, the output signal of the circuit structure will not usually be affected. However, in the process of the input signal switching from a low-level signal to a high-level signal (i.e., the input signal is on the rising edge), or in the process of the input signal switching from a high-level signal to a low-level signal (i.e., the input signal is on the falling edge), the interference signal may affect the input signal. Therefore, through the configuration of the above-mentioned capacitor circuit, the first control circuit, the second control circuit, and the follower circuit, it is possible to make the output control signal fixed to a high-level signal after the input signal is on the rising edge and greater than the first flip threshold voltage, and to fix the output control signal to a low-level signal after the input signal is on the falling edge and less than the first flip threshold voltage. Thus, the output control signal is not affected by the interference signal.

[0052] In the present invention, by configuring the capacitor circuit, the first control circuit, the second control circuit, and the follower circuit, the output control signal is fixed to a high-level signal when the input signal is on a rising edge and greater than a first flip threshold voltage, and the output control signal is fixed to a low-level signal when the input signal is on a falling edge and less than the first flip threshold voltage. That is, noise on the rising edge of the input signal is not recognized as multiple rising edges, and noise on the falling edge is not recognized as multiple falling edges, thereby improving the circuit's anti-interference capability, control accuracy, and reliability.

[0053] In an optional embodiment, as Figure 2 As shown, the follower circuit includes: a first inverter N1, a second inverter N2, a third inverter N3, a fourth inverter N4, a first NAND gate A1, and a second NAND gate A2; the input end of the first inverter N1 receives an input signal, the output end of the first inverter N1 is connected to the first input end of the first NAND gate A1, the second input end of the first NAND gate A1 is connected to the output end of the third inverter N3, the input end of the third inverter N3 is connected to the first end of the first control circuit and the first end of the capacitor circuit, the output end of the first NAND gate A1 is connected to the first input end of the second NAND gate A2, the second input end of the second NAND gate A2 is connected to the output end of the fourth inverter N4, the input end of the fourth inverter N4 is connected to the first end of the second control circuit and the second end of the capacitor circuit, the output end of the second NAND gate A2 is connected to the input end of the second inverter N2 and the second end of the second control circuit, the output end of the second inverter N2 is connected to the second end of the first control circuit, and outputs the control signal.

[0054] The first control circuit includes: a third NAND gate A3, a fourth NAND gate A4, a fifth NAND gate A5, a sixth NAND gate A6, a seventh NAND gate A7, and an eighth NAND gate A8; a first input end of the third NAND gate A3 is connected to the output end of the eighth NAND gate A8 and the third input end of the sixth NAND gate A6, a second input end of the third NAND gate A3 is connected to the output end of the fourth NAND gate A4, the first input end of the fifth NAND gate A5, and the first input end of the sixth NAND gate A6, an output end of the third NAND gate A3 is connected to the first input end of the fourth NAND gate A4, a second input end of the fourth NAND gate A4 is connected to the sixth NAND gate A6. The second input terminal of the NOT gate A6 and the fourth terminal of the follower circuit, the third input terminal of the fourth NAND gate A4 is connected to the second input terminal of the eighth NAND gate A8, the third input terminal of the seventh NAND gate A7, the third terminal of the capacitor circuit and the third terminal of the second control circuit, the second input terminal of the fifth NAND gate A5 is connected to the output terminal of the seventh NAND gate A7, the output terminal of the fifth NAND gate A5 is connected to the first input terminal of the seventh NAND gate A7, the second terminal of the follower circuit and the first terminal of the capacitor circuit, and the output terminal of the sixth NAND gate A6 is connected to the second input terminal of the seventh NAND gate A7 and the first input terminal of the eighth NAND gate A8.

[0055] The second control circuit includes: a ninth NAND gate A9, a tenth NAND gate A10, an eleventh NAND gate A11, a twelfth NAND gate A12, a thirteenth NAND gate A13, and a fourteenth NAND gate A14; a first input end of the ninth NAND gate A9 is connected to the output end of the fourteenth NAND gate A14 and the third input end of the twelfth NAND gate A12, a second input end of the ninth NAND gate A9 is connected to the output end of the tenth NAND gate A10, the first input end of the eleventh NAND gate A11, and the first input end of the twelfth NAND gate A12, an output end of the ninth NAND gate A9 is connected to the first input end of the tenth NAND gate A10, a second input end of the tenth NAND gate A10 is connected to the twelfth NAND gate A12 The second input terminal of the NAND gate A12 and the fifth terminal of the follower circuit, the third input terminal of the tenth NAND gate A10 is connected to the second input terminal of the fourteenth NAND gate A14, the third input terminal of the thirteenth NAND gate A13, the third terminal of the capacitor circuit and the third terminal of the first control circuit, the second input terminal of the eleventh NAND gate A11 is connected to the output terminal of the thirteenth NAND gate A13, the output terminal of the eleventh NAND gate A11 is connected to the first input terminal of the thirteenth NAND gate A13, the third terminal of the follower circuit and the second terminal of the capacitor circuit, and the output terminal of the twelfth NAND gate A12 is connected to the second input terminal of the thirteenth NAND gate A13 and the first input terminal of the fourteenth NAND gate A14.

[0056] The capacitor circuit includes: a first OR gate F1, a first capacitor C1, a first switch tube M1, a second switch tube M2, a third switch tube M3 and a first current source B1; the first input end of the first OR gate F1 is connected to the first end of the first control circuit and the second end of the follower circuit, the second input end of the first OR gate F1 is connected to the first end of the second control circuit and the third end of the follower circuit, the output end of the first OR gate F1 is connected to the first end of the first switch tube M1, the second end of the first switch tube M1 is connected to one end of the first current source B1 and an external power supply, the third end of the first switch tube M1 is connected to one end of the first capacitor C1, the first end of the second switch tube M2, the third end of the first control circuit and the third end of the second control circuit, the other end of the first capacitor C1 is connected to the second end of the second switch tube M2, the first end of the third switch tube M3 and grounded, and the third end of the second switch tube M2 is connected to the second end and the third end of the third switch tube M3 and the other end of the first current source B1.

[0057] Based on the specific structures of the above-mentioned follower circuit, the first control circuit, the second control circuit and the capacitor circuit, the working principle of the high-precision anti-interference circuit structure is as follows:

[0058] When the circuit is first powered on, the terminal voltage of the first capacitor C1 is 0. That is, at this time, one input terminal of the fourth NAND gate A4, the seventh NAND gate A7, and the eighth NAND gate A8 is at a low level. Therefore, the fourth NAND gate A4 and the seventh NAND gate A7 both output a high level to the fifth NAND gate A5, and the fifth NAND gate A5 outputs a low level to the first OR gate F1. At the same time, one input terminal of the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14 is at a low level. Therefore, the tenth NAND gate A10 and the thirteenth NAND gate A13 both output a high level to the eleventh NAND gate A11, and the eleventh NAND gate A11 outputs a low level to the first OR gate F1. Therefore, at this time, the first OR gate F1 outputs a low level to the first switch tube M1, turning on the first switch tube M1, and the terminal voltage of the first capacitor C1 is pulled to a high level.

[0059] Therefore, after the circuit is powered on, the third inverter N3 outputs a high level to the first NAND gate A1, the fourth inverter N4 outputs a high level to the second NAND gate A2, and the first capacitor C1 outputs a high level to the third input terminal of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the third input terminal of the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14.

[0060] At the same time, the first current source B1 pulls up the control terminal voltage of the second switch tube M2 and the third switch tube M3, and the second switch tube M2 and the third switch tube M3 are turned on. At this time, the width-to-length ratio of the second switch tube M2 and the third switch tube M3 is designed to be M:1, and the current generated in the first current source B1 is recorded as I1. Therefore, it can be obtained that the current flowing through the second switch tube M2 is .

[0061] (1) When the input signal IN is low, the first inverter N1 outputs a high level, the first NAND gate A1 outputs a low level, the second NAND gate A2 outputs a high level, and the second inverter N2 outputs a low level. That is, at this time, the control signal OUT is also low. The low level signal is input to the fourth NAND gate A4 and the sixth NAND gate A6. The fourth NAND gate A4 and the sixth NAND gate A6 output a high level. At this time, both input terminals of the eighth NAND gate A8 input a high level. Therefore, the eighth NAND gate A8 outputs a low level to the third NAND gate A3, and the third NAND gate A3 outputs a high level to the first input terminal of the fourth NAND gate A4. At the same time, the high-level signal output by the second NAND gate A2 is input to the second control circuit, and when power is just turned on, the fourteenth NAND gate A14 and the tenth NAND gate A10 both output high-level signals to the ninth NAND gate A9, the ninth NAND gate A9 outputs a low-level signal to the tenth NAND gate A10, the tenth NAND gate 10 outputs a high-level signal to the eleventh NAND gate A11, and the fourteenth NAND gate A14 outputs a high-level signal to the twelfth NAND gate A12, so that the three input terminals of the twelfth NAND gate A12 all input high-level signals, therefore, the twelfth NAND gate A12 outputs a low-level signal, the thirteenth NAND gate A13 outputs a high-level signal, and the eleventh NAND gate A11 outputs a low-level signal based on the two high-level signals, that is, the first end of the second control circuit keeps outputting a low-level signal when the input signal is a low-level signal.

[0062] When the input signal IN switches from a low level to a high level, that is, when the rising edge voltage of the input signal IN rises to the first flip threshold voltage V1 of the first inverter N1, the first inverter N1 outputs a low level, and the first NAND gate A1 outputs a high level, that is, both input terminals of the second NAND gate A2 are high levels. Therefore, the second NAND gate A2 outputs a low level, and the output terminal of the second inverter N2 switches from a low level to a high level. Therefore, at this time, the control signal OUT switches from a low level to a high level, that is, at this time, the second input terminals of the fourth NAND gate A4 and the sixth NAND gate A6 input a high level. Therefore, the three input terminals of the fourth NAND gate A4 all input a high level, so the fourth NAND gate A4 outputs a low level, and the low level signal is input to the sixth NAND gate A6 and the fifth NAND gate A6. The NAND gate A5, the sixth NAND gate A6 and the fifth NAND gate A5 all output high levels. Therefore, at this time, the first OR gate F1 outputs a high level and the third inverter N3 outputs a low level. At the same time, the low level output by the second NAND gate A2 is input into the tenth NAND gate A10 and the twelfth NAND gate A12. The tenth NAND gate A10 and the twelfth NAND gate A12 output high levels. Since the output end of the eleventh NAND gate A11 was previously in a low level state, at this time, the thirteenth NAND gate A13 outputs a high level, the eleventh NAND gate A11 still outputs a low level, and the fourth inverter N4 still outputs a high level.

[0063] From the above analysis, it can be seen that when the input signal IN switches from a low level to a high level, the third inverter N3 outputs a low level. At this time, no matter what kind of interference the input signal IN is subjected to, the first NAND gate A1 always outputs a high level to the second NAND gate A2. Since the fourth inverter N4 outputs a high level to the second NAND gate A2, the second NAND gate A2 always outputs a low level, and the second inverter N2 always outputs a high level, that is, the control signal OUT is always a high level. That is, at this time, the change of the input signal IN will not affect the control signal OUT; at the same time, since the first OR gate F1 outputs a high level, the first switch tube M1 is turned off, and the first capacitor C1 is discharged through the second switch tube M2, and the discharge current is equal to , when the first capacitor C1 is discharged to a terminal voltage lower than the second inversion threshold voltage V2 of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13 and the fourteenth NAND gate A14, the fourth NAND gate A4 and the seventh NAND gate A7 both output a high level to the fifth NAND gate A5, the fifth NAND gate A5 outputs a low level to the first OR gate F1 and the third inverter N3, the output terminal of the third inverter N3 switches from a low level to a high level, the output signal of the first NAND gate A1 is determined by the input signal IN, that is, at this time, the control signal OUT changes with the input signal IN, and since the input voltage of the eighth NAND gate A8 is lower than the second inversion threshold voltage V2, the eighth NAND gate A8 outputs a high level. Therefore, at this time, both input terminals of the third NAND gate A3 are high levels, and the The third NAND gate A3 outputs a low level. At the same time, the three input terminals of the sixth NAND gate A6 are all high levels. Therefore, the sixth NAND gate A6 outputs a low level. At the same time, the tenth NAND gate A10 and the thirteenth NAND gate A13 both output a high level to the eleventh NAND gate A11. Since the output terminal of the eleventh NAND gate A11 was previously in a low level state, the thirteenth NAND gate A13 outputs a high level. The eleventh NAND gate A11 still outputs a low level to the first OR gate F1. Therefore, at this time, the first OR gate F1 outputs a low level to the first switch tube M1, turning on the first switch tube M1, and the terminal voltage of the first capacitor C1 is instantly pulled to a high level. That is, at this time, the input terminals of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14 are switched to a high level state again.

[0064] At this time, according to the above analysis, it can be seen that the eleventh NAND gate A11 still outputs a low level, which will not be described here. At the same time, since the output terminal of the third NAND gate A3 was previously in a low level state, when the third input terminal of the fourth NAND gate A4 is switched back to a high level state, the fourth NAND gate A4 still outputs a high level, and since the output terminal of the sixth NAND gate A6 was previously in a low level state, the eighth NAND gate A8 still outputs a high level to the sixth NAND gate A6. That is, at this time, the three input terminals of the sixth NAND gate A6 are all high levels, so the sixth NAND gate A6 is high. Gate A6 outputs a low level to the seventh NAND gate A7, and the seventh NAND gate A7 outputs a high level to the fifth NAND gate A5. Therefore, both input terminals of the fifth NAND gate A5 are high. The fifth NAND gate A5 still outputs a low level to the first OR gate F1 and the third inverter N3. Therefore, the output terminal of the third inverter N3 remains high, and the control signal OUT changes with the input signal IN. At the same time, the first OR gate F1 outputs a low level, the first switch M1 is always in the on state, and the terminal voltage of the first capacitor C1 is always high.

[0065] (2) When the input signal IN is high, the first inverter N1 outputs a low level, and the first NAND gate A1 outputs a high level. From the above analysis, it can be seen that the fourth inverter N4 outputs a high level to the second NAND gate A2. Therefore, the second NAND gate A2 outputs a low level. The low level signal is input to the tenth NAND gate A10 and the twelfth NAND gate A12. The tenth NAND gate A10 and the twelfth NAND gate A12 output a high level. At this time, both input terminals of the fourteenth NAND gate A14 input a high level. Therefore, the fourteenth NAND gate A14 outputs a low level to the ninth NAND gate A9, and the ninth NAND gate A9 outputs a high level to the first input terminal of the tenth NAND gate A10. At the same time, the control signal OUT is a high-level signal and is input to the first control circuit. When power is just turned on, the eighth NAND gate A8 and the fourth NAND gate A4 both output high-level signals to the third NAND gate A3, the third NAND gate A3 outputs a low-level signal to the fourth NAND gate A4, the fourth NAND gate A4 outputs a high-level signal to the fifth NAND gate A5, and the eighth NAND gate A8 outputs a high-level signal to the sixth NAND gate A6. As a result, the three input terminals of the sixth NAND gate A6 all input high-level signals. Therefore, the sixth NAND gate A6 outputs a low-level signal, the seventh NAND gate A7 outputs a high-level signal, and the fifth NAND gate A5 outputs a low-level signal based on the two high-level signals. That is, the first end of the first control circuit keeps outputting a low-level signal when the input signal is a high-level signal.

[0066] When the input signal IN switches from a high level to a low level, that is, when the falling edge voltage of the input signal IN drops to the first flip threshold voltage V1 of the first inverter N1, the first inverter N1 outputs a high level. From the above analysis, it can be seen that the third inverter N3 outputs a high level to the first NAND gate A1. Therefore, the first NAND gate A1 outputs a low level to the second NAND gate A2. The second NAND gate A2 outputs a high level. The output end of the second inverter N2 switches from a high level to a low level. Therefore, at this time, the control signal OUT switches from a high level to a low level. The low level is input to the fourth NAND gate A4 and the sixth NAND gate A6. The fourth NAND gate A4 and the sixth NAND gate A6 output a high level. Since the output end of the fifth NAND gate A5 was previously in a low level state, at this time, The seventh NAND gate A7 outputs a high level, the fifth NAND gate A5 still outputs a low level, and the third inverter N3 still outputs a high level. At the same time, the second input terminals of the tenth NAND gate A10 and the twelfth NAND gate A12 input a high level. Therefore, the three input terminals of the tenth NAND gate A10 all input a high level. Therefore, the tenth NAND gate A10 outputs a low level, and this low level signal is input to the eleventh NAND gate A11 and the twelfth NAND gate A12. The eleventh NAND gate A11 and the twelfth NAND gate A12 both output a high level. Therefore, at this time, the first OR gate F1 outputs a high level, and the fourth inverter N4 outputs a low level.

[0067] From the above analysis, it can be seen that when the input signal IN switches from a high level to a low level, the fourth inverter N4 outputs a low level. At this time, no matter what kind of interference the input signal IN is subjected to, the second NAND gate A2 outputs a high level to the second inverter N2. The second inverter N2 always outputs a low level, that is, the control signal OUT is always a low level. That is, at this time, the change of the input signal IN will not affect the control signal OUT. At the same time, since the first OR gate F1 outputs a high level, the first switch tube M1 is turned off, and the first capacitor C1 is discharged through the second switch tube M2. The discharge current is equal to When the first capacitor C1 is discharged to a terminal voltage lower than the second inversion threshold voltage V2 of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13 and the fourteenth NAND gate A14, the tenth NAND gate A10 and the thirteenth NAND gate A13 both output a high level to the eleventh NAND gate A11, and the eleventh NAND gate A11 outputs a low level to the first OR gate F1 and the fourth inverter N4. The output terminal of the fourth inverter N4 switches from a low level to a high level, and the output signal of the second NAND gate A2 is determined by the input signal IN. That is, at this time, the control signal OUT changes with the input signal IN. Moreover, since the input voltage of the fourteenth NAND gate A14 is lower than the second inversion threshold voltage V2, the fourteenth NAND gate A14 outputs a high level. Therefore, at this time, the two input terminals of the ninth NAND gate A9 are switched to high level. The input terminals of the ninth NAND gate A9 are all high, and the third NAND gate A12 outputs a low. At the same time, the three input terminals of the twelfth NAND gate A12 are all high, so the twelfth NAND gate A12 outputs a low. At the same time, the fourth NAND gate A4 and the seventh NAND gate A7 both output a high level to the fifth NAND gate A5. Since the output terminal of the fifth NAND gate A5 was previously in a low level state, the seventh NAND gate A7 outputs a high level, and the fifth NAND gate A5 still outputs a low level to the first OR gate F1. Therefore, at this time, the first OR gate F1 outputs a low level to the first switch tube M1, turning on the first switch tube M1, and the terminal voltage of the first capacitor C1 is instantly pulled to a high level. That is, at this time, the input terminals of the fourth NAND gate A4, the seventh NAND gate A7, the eighth NAND gate A8, the tenth NAND gate A10, the thirteenth NAND gate A13, and the fourteenth NAND gate A14 are switched to a high level state again.

[0068] At this time, according to the above analysis, the fifth NAND gate A5 still outputs a low level, which will not be described in detail here. At the same time, since the output terminal of the ninth NAND gate A9 was previously in a low level state, when the third input terminal of the tenth NAND gate A10 is switched back to a high level state, the tenth NAND gate A10 still outputs a high level, and since the output terminal of the twelfth NAND gate A12 was previously in a low level state, the fourteenth NAND gate A14 still outputs a high level to the twelfth NAND gate A12. That is, at this time, the three input terminals of the twelfth NAND gate A12 are all high levels, so the twelfth NAND gate A14 is still high. A12 outputs a low level to the thirteenth NAND gate A13, and the thirteenth NAND gate A13 outputs a high level to the eleventh NAND gate A11. Therefore, both input terminals of the eleventh NAND gate A11 are high levels. The eleventh NAND gate A11 still outputs a low level to the first OR gate F1 and the fourth inverter N4. Therefore, the output terminal of the fourth inverter N4 remains high, and the control signal OUT changes with the input signal IN. At the same time, the first OR gate F1 outputs a low level, the first switch tube M1 is always in the on state, and the terminal voltage of the first capacitor C1 is always high.

[0069] According to the above circuit principle analysis, we can get Figure 3 The waveform diagram of the input signal IN and the control signal OUT shown in FIG. Figure 3 As shown, when the rising edge voltage of the input signal IN rises to the first flip threshold voltage V1, the control signal OUT switches from a low level to a high level. When the falling edge voltage of the input signal IN drops to the first flip threshold voltage V1, the control signal OUT switches from a high level to a low level, ensuring that the noise on the rising edge of the input signal IN will not be recognized as multiple rising edges, and the noise on the falling edge will not be recognized as multiple falling edges, thereby improving the anti-interference ability, control accuracy and reliability of the circuit.

[0070] In an optional embodiment, the time T0 for the voltage at the third terminal of the capacitor circuit to discharge from the external power supply voltage to the voltage at which the components in the first control circuit and the second control circuit undergo voltage reversal (i.e., the second reversal threshold voltage V2) is expressed by the following formula:

[0071] max[T1,T3] <T0<min[T1+T2,T3+T4]

[0072] Wherein, T1 represents the time when the input signal rises from the first flip threshold voltage to the external power supply voltage on the rising edge, T2 represents the sum of the time when the input signal is a high-level signal and the time when the input signal drops from the external power supply voltage to the first flip threshold voltage on the falling edge, T3 represents the time when the input signal drops from the first flip threshold voltage to the ground voltage on the falling edge; T4 represents the sum of the time when the input signal is a low-level signal and the time when the input signal rises from the ground voltage to the first flip threshold voltage on the rising edge.

[0073] Specifically, when the input signal IN switches from a low level to a high level, the third inverter N3 outputs a low level. At this time, no matter what kind of interference the input signal IN is subjected to, the second NAND gate A2 always outputs a low level, and the second inverter N2 always outputs a high level, that is, the control signal OUT is always a high level. That is, at this time, the change of the input signal IN will not affect the control signal OUT, until the first capacitor C1 is discharged to a voltage at its terminal lower than the second flip threshold voltage V2, the output end of the third inverter N3 switches from a low level to a high level, and the output signal of the first NAND gate A1 is determined by the input signal IN, that is, at this time , the control signal OUT changes with the input signal IN; therefore, during the time T0 from the time the first capacitor C1 discharges from the external power supply voltage VCC to the time the terminal voltage of the first capacitor C1 is lower than the second flip threshold voltage V2, the change of the input signal IN will not affect the control signal OUT. At this time, the time T0 is designed to be greater than the time T1 from the time the voltage of the input signal IN rises from V1 to VCC on the rising edge, and less than the time T1 from the time the voltage of the input signal IN rises from V1 to VCC on the rising edge + the time T2 from the time the voltage of the input signal IN is at a high level of the external power supply voltage VCC to the time it falls from VCC to V1 on the falling edge.

[0074] Similarly, when the input signal IN switches from a high level to a low level, the fourth inverter N4 outputs a low level. At this time, no matter what kind of interference the input signal IN is subjected to, the second NAND gate A2 outputs a high level to the second inverter N2. The second inverter N2 always outputs a low level, that is, the control signal OUT is always a low level. That is, at this time, the change of the input signal IN will not affect the control signal OUT. Until the first capacitor C1 is discharged to a voltage at its terminal lower than the second flip threshold voltage V2, the output terminal of the fourth inverter N4 switches from a low level to a high level, and the output signal of the second NAND gate A2 is determined by the input signal IN. That is, at this time, the control signal OUT follows the change of the input signal IN; therefore, during the time T0 from the discharge of the first capacitor C1 from the external power supply voltage VCC to the time when the terminal voltage of the first capacitor C1 is lower than the second flip threshold voltage V2, the change of the input signal IN will not affect the control signal OUT. At this time, the time T0 is designed to be greater than the time T3 from the voltage of the input signal IN falling from V1 to 0 on the falling edge, and less than the time T3 from the voltage of the input signal IN falling from V1 to 0 on the falling edge + the time T4 from the voltage of the input signal IN being at the low level ground voltage GND to rising from 0 to V1 on the rising edge.

[0075] Therefore, based on the above two analyses, the time T0 from when the first capacitor C1 discharges from the external power supply voltage VCC to when its terminal voltage is lower than the second flip threshold voltage V2 is designed to be greater than max[T1, T3] and less than min[T1+T2, T3+T4]. At this time, by selecting the appropriate capacitance value of the first capacitor C1, the size of the current I1, and the size of the coefficient M, T0 is within the design range.

[0076] In the present invention, when the rising edge voltage of the input signal IN rises to the first flip threshold voltage V1, the control signal OUT is switched from a low level to a high level. When the falling edge voltage of the input signal IN drops to the first flip threshold voltage V1, the control signal OUT is switched from a high level to a low level, ensuring that the noise on the rising edge of the input signal IN will not be identified as multiple rising edges, and the noise on the falling edge will not be identified as multiple falling edges, thereby improving the anti-interference ability, control accuracy and reliability of the circuit; at the same time, by selecting a suitable capacitance value of the first capacitor C1, the size of the current I1 and the size of the coefficient M, it can be applied to control circuits of any cycle time and duty cycle, thereby improving the application range of the high-precision anti-interference circuit structure.

[0077] The present invention also provides a battery powered circuit, such as Figure 4 As shown, it includes: an integrated circuit control chip, a power circuit and a battery load. The integrated circuit control chip includes the high-precision anti-interference circuit structure of the above embodiment. The integrated circuit control chip controls the power circuit to power the battery load according to the control signal output by the follower circuit.

[0078] In the present invention, by providing the above-mentioned high-precision anti-interference circuit structure in the integrated circuit control chip, the control signal inside the integrated circuit control chip will not be interfered with by changes in battery load, thereby improving the accuracy and reliability of the battery charging circuit.

[0079] Although exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions, and modifications to these embodiments without departing from the spirit of the present invention and the scope of protection defined by the appended claims. Such modifications and variations fall within the scope defined by the appended claims. For other examples, those skilled in the art will readily appreciate that the order of the process steps may be varied while remaining within the scope of protection of the present invention.

[0080] Furthermore, the scope of application of the present invention is not limited to the processes, mechanisms, manufactures, compositions of matter, means, methods, and steps of the specific embodiments described in the specification. From the disclosure of the present invention, a person of ordinary skill in the art will readily understand that any currently existing or later developed processes, mechanisms, manufactures, compositions of matter, means, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be applied in accordance with the present invention. Therefore, the claims appended hereto are intended to include within their scope such processes, mechanisms, manufactures, compositions of matter, means, methods, or steps.

Claims

1. A high-precision anti-interference circuit structure, characterized in that: include: a follower circuit, wherein a first end receives an input signal, a second end is connected to a first end of the first control circuit and a first end of the capacitor circuit, a third end is connected to a first end of the second control circuit and a second end of the capacitor circuit, a fourth end is connected to a second end of the first control circuit, a fifth end is connected to a second end of the second control circuit, and the fourth end is used to output a control signal; a first control circuit, a third end of which is connected to the third end of the capacitor circuit and the third end of the second control circuit; a capacitor circuit, a fourth terminal of which is connected to an external power supply, and a fifth terminal of which is grounded; When the input signal is at a rising edge and is greater than a first flip threshold voltage, the control signal output by the follower circuit does not follow the change of the input signal and always outputs a high-level control signal. When the capacitor circuit discharges to a second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit follows the change of the input signal, and the capacitor circuit enters a charging state. When the input signal is at a falling edge and is less than the first flip threshold voltage, the control signal output by the follower circuit does not follow the change of the input signal and always outputs a low-level control signal. When the capacitor circuit discharges to the second flip threshold voltage and generates a low-level signal, the control signal output by the follower circuit follows the change of the input signal, and the capacitor circuit enters a charging state. The first flip threshold voltage is the voltage at which the components in the follower circuit undergo voltage flipping, and the second flip threshold voltage is the voltage at which the components in the first control circuit and the second control circuit undergo voltage flipping; When the input signal is on a rising edge and is greater than a first flip threshold voltage, the follower circuit outputs a high-level control signal at the fourth end and a low-level signal at the fifth end according to the input signal and the low-level signal output by the second control circuit at the previous moment; the second end of the first control circuit receives the high-level control signal, and outputs a high-level signal at the first end according to the high-level signal generated after the capacitor circuit is charged at the previous moment and the state of the first control circuit at the previous moment; the second end of the second control circuit receives the low-level signal output by the fifth end of the follower circuit, and outputs a low-level signal at the first end according to the state of the second control circuit at the previous moment; under the control of the high-level signal output by the first control circuit and the low-level signal output by the second control circuit, the follower circuit outputs a high-level control signal; When the input signal is on a falling edge and is less than the first flip threshold voltage, the follower circuit outputs a low-level control signal at the fourth end and outputs a high-level signal at the fifth end according to the input signal and the low-level signal output by the first control circuit at the previous moment; the second end of the second control circuit receives the high-level signal output by the fifth end of the follower circuit, and outputs a high-level signal at the first end according to the high-level signal generated after the capacitor circuit is charged at the previous moment and the state of the second control circuit at the previous moment. Under the control of the high-level signal output by the second control circuit, the follower circuit outputs a low-level control signal.

2. The high-precision anti-interference circuit structure according to claim 1, characterized in that: When the input signal is at a rising edge and is greater than a first flip threshold voltage, the capacitor circuit enters a discharge state according to a high-level signal output by the first end of the first control circuit, and outputs a low-level signal when discharged to a second flip threshold voltage; the third end of the first control circuit receives a low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end; the third end of the second control circuit receives a low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end, based on the low-level signal output by the first end of the first control circuit and the low-level signal output by the first end of the second control circuit, the control signal output by the follower circuit follows the change of the input signal, and at the same time, the capacitor circuit enters a charging state; After the capacitor circuit is charged to a high level, the first end of the first control circuit and the first end of the second control circuit output a low level signal. Based on the low level signal output by the first end of the first control circuit and the first end of the second control circuit, the control signal output by the follower circuit follows the input signal change. At the same time, the capacitor circuit maintains a high level state after charging.

3. The high-precision anti-interference circuit structure according to claim 1, characterized in that: When the input signal is at a falling edge and is less than a first flip threshold voltage, the capacitor circuit enters a discharge state according to a high-level signal output by the first end of the second control circuit, and outputs a low-level signal when discharged to a second flip threshold voltage. The third end of the second control circuit receives the low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end; the third end of the first control circuit receives the low-level signal generated after the capacitor circuit is discharged, and outputs a low-level signal at the first end. Based on the low-level signal output by the first end of the first control circuit and the low-level signal output by the first end of the second control circuit, the control signal output by the follower circuit changes with the input signal, and at the same time, the capacitor circuit enters a charging state; After the capacitor circuit is charged to a high level, the first end of the second control circuit and the first end of the first control circuit output a low level signal. Based on the low level signal output by the first end of the first control circuit and the first end of the second control circuit, the control signal output by the follower circuit follows the input signal change. At the same time, the capacitor circuit maintains a high level state after charging.

4. The high-precision anti-interference circuit structure according to claim 1, characterized in that: When the circuit is just powered on and the input signal is a low-level signal, the first control circuit and the second control circuit respectively output low-level signals at the first end according to the capacitor circuit in the initial state, and the capacitor circuit enters a charging state according to the low-level signals output by the first control circuit and the second control circuit; the follower circuit outputs a low-level control signal at the fourth end according to the input signal and the low-level signal output by the first control circuit.

5. The high-precision anti-interference circuit structure according to claim 1, characterized in that: When the circuit is just powered on and the input signal is a high-level signal, the first control circuit and the second control circuit respectively output low-level signals at the first end according to the capacitor circuit in the initial state, and the capacitor circuit enters a charging state according to the low-level signals output by the first control circuit and the second control circuit; the follower circuit outputs a high-level control signal at the fourth end according to the input signal and the low-level signal output by the second control circuit.

6. The high-precision anti-interference circuit structure according to claim 1, characterized in that: The follower circuit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and a second NAND gate; The input end of the first inverter receives an input signal, the output end of the first inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the third inverter, the input end of the third inverter is connected to the first end of the first control circuit and the first end of the capacitor circuit, the output end of the first NAND gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the output end of the fourth inverter, the input end of the fourth inverter is connected to the first end of the second control circuit and the second end of the capacitor circuit, the output end of the second NAND gate is connected to the input end of the second inverter and the second end of the second control circuit, the output end of the second inverter is connected to the second end of the first control circuit, and outputs a control signal.

7. The high-precision anti-interference circuit structure according to claim 1, characterized in that: The first control circuit includes: a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate; The first input end of the third NAND gate is connected to the output end of the eighth NAND gate and the third input end of the sixth NAND gate, the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, the first input end of the fifth NAND gate and the first input end of the sixth NAND gate, the output end of the third NAND gate is connected to the first input end of the fourth NAND gate, the second input end of the fourth NAND gate is connected to the second input end of the sixth NAND gate and the fourth end of the follower circuit, the third input end of the fourth NAND gate is connected to the second input end of the eighth NAND gate, the third input end of the seventh NAND gate, the third end of the capacitor circuit and the third end of the second control circuit, the second input end of the fifth NAND gate is connected to the output end of the seventh NAND gate, the output end of the fifth NAND gate is connected to the first input end of the seventh NAND gate, the second end of the follower circuit and the first end of the capacitor circuit, and the output end of the sixth NAND gate is connected to the second input end of the seventh NAND gate and the first input end of the eighth NAND gate.

8. The high-precision anti-interference circuit structure according to claim 1, characterized in that: The second control circuit includes: a ninth NAND gate, a tenth NAND gate, an eleventh NAND gate, a twelfth NAND gate, a thirteenth NAND gate, and a fourteenth NAND gate; The first input end of the ninth NAND gate is connected to the output end of the fourteenth NAND gate and the third input end of the twelfth NAND gate, the second input end of the ninth NAND gate is connected to the output end of the tenth NAND gate, the first input end of the eleventh NAND gate and the first input end of the twelfth NAND gate, the output end of the ninth NAND gate is connected to the first input end of the tenth NAND gate, the second input end of the tenth NAND gate is connected to the second input end of the twelfth NAND gate and the fifth end of the follower circuit, the third input end of the tenth NAND gate is connected to the second input end of the fourteenth NAND gate, the third input end of the thirteenth NAND gate, the third end of the capacitor circuit and the third end of the first control circuit, the second input end of the eleventh NAND gate is connected to the output end of the thirteenth NAND gate, the output end of the eleventh NAND gate is connected to the first input end of the thirteenth NAND gate, the third end of the follower circuit and the second end of the capacitor circuit, and the output end of the twelfth NAND gate is connected to the second input end of the thirteenth NAND gate and the first input end of the fourteenth NAND gate.

9. The high-precision anti-interference circuit structure according to claim 1, characterized in that: The capacitor circuit includes: a first OR gate, a first capacitor, a first switch tube, a second switch tube, a third switch tube and a first current source; The first input end of the first OR gate is connected to the first end of the first control circuit and the second end of the follower circuit, the second input end of the first OR gate is connected to the first end of the second control circuit and the third end of the follower circuit, the output end of the first OR gate is connected to the first end of the first switch tube, the second end of the first switch tube is connected to one end of the first current source and an external power supply, the third end of the first switch tube is connected to one end of the first capacitor, the first end of the second switch tube, the third end of the first control circuit and the third end of the second control circuit, the other end of the first capacitor is connected to the second end of the second switch tube, the first end of the third switch tube and grounded, and the third end of the second switch tube is connected to the second end, the third end and the other end of the first current source of the third switch tube.

10. The high-precision anti-interference circuit structure according to claim 1, characterized in that: The time T0 for the capacitor circuit to discharge to the second flip threshold voltage is expressed by the following formula: max[T1,T3] <T0<min[T1+T2,T3+T4] In the formula, T1 represents the time when the input signal rises from the first flip threshold voltage to the external power supply voltage on the rising edge, T2 represents the sum of the time when the input signal is a high-level signal and the time when the input signal drops from the external power supply voltage to the first flip threshold voltage on the falling edge, T3 represents the time when the input signal drops from the first flip threshold voltage to the ground voltage on the falling edge; T4 represents the sum of the time when the input signal is a low-level signal and the time when the input signal rises from the ground voltage to the first flip threshold voltage on the rising edge, the voltage of the high-level signal is equal to the external power supply voltage, and the voltage of the low-level signal is equal to the ground voltage.

11. A battery powered circuit, characterized in that: include: An integrated circuit control chip, a power circuit and a battery load, wherein the integrated circuit control chip includes the high-precision anti-interference circuit structure described in any one of claims 1 to 10, and the integrated circuit control chip controls the power circuit to power the battery load according to the control signal output by the follower circuit.

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