Power supply circuit, power supply method thereof, and power supply chip

Abstract

The present invention discloses a power supply circuit and a power supply method thereof, and a power supply chip, belonging to the technical field of power supply chips. The power supply circuit includes a logic subcircuit, a driving subcircuit, and a driving energy storage capacitor. The driving subcircuit is used to supply power to the driving energy storage capacitor and the logic subcircuit; the first voltage terminal and the second voltage terminal of the driving subcircuit are respectively connected to the two ends of the driving energy storage capacitor, and the driving subcircuit is configured to detect the voltage difference between the two ends of the driving energy storage capacitor and control the charging state of the driving energy storage capacitor; the current input terminal of the logic subcircuit is connected to the third voltage terminal so that the logic subcircuit and the driving subcircuit are connected in series, and the output control terminal is connected to the control terminal of the logic subcircuit to establish a voltage across the driving energy storage capacitor. The driving subcircuit supplies power to the logic subcircuit and charges the driving energy storage capacitor of the driving subcircuit at the same time. The two circuits use the same current, saving the chip's own power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of power chips, and in particular to a power circuit and a power supply method thereof, and a power chip. Background Art

[0002] Switching power supply chips are mainly used to convert power, such as boosting, bucking, or stepping up and down. The internal power tubes generally use power transistors or power MOS tubes. For step-down switching power supplies, the MOS tubes integrated inside the chip are divided into PMOS and NMOS power tubes, corresponding to two different drive circuits. There are many technical solutions to improve the conversion efficiency of power supply chips, and reducing the power consumption of the chip itself is the current mainstream technical solution.

[0003] Among them, the inherent power consumption inside the power chip is mainly generated by the internal logic circuit and power tube drive circuit of the chip (the switching loss and conduction loss of the power tube are not considered here, because these two losses can be solved by increasing the switching speed of the MOS tube in the chip and reducing the conduction internal resistance of the MOS tube). Since the internal logic circuit of the chip draws power from the power supply, and the drive circuit draws power from the power supply separately, the power supply circuits of the two modules are independent and do not affect each other. However, the problem is that the power consumption of the chip is relatively large. When the chip is working, the internal logic and drive circuits are in working state, so the loss generated is basically fixed, and the chip's inherent power consumption is relatively large.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a power supply circuit and a power supply method thereof, and a power supply chip, so as to solve the problem of high inherent power consumption of the power supply chip.

[0006] To solve the above technical problems, the present invention provides a power supply circuit, comprising a logic sub-circuit, a driving sub-circuit, and a driving energy storage capacitor, wherein the driving sub-circuit is used to supply power to the driving energy storage capacitor and the logic sub-circuit;

[0007] The driving sub-circuit has an output control terminal, a first voltage terminal, a second voltage terminal and a third voltage terminal, wherein the first voltage terminal and the second voltage terminal are respectively connected to the two ends of the driving energy storage capacitor, and the driving sub-circuit is configured to detect the voltage difference between the two ends of the driving energy storage capacitor and control the charging state of the driving energy storage capacitor;

[0008] The current input terminal of the logic subcircuit is connected to the third voltage terminal so that the logic subcircuit and the drive subcircuit are connected in series, and the output control terminal is connected to the control terminal of the logic subcircuit to establish the voltage across the drive energy storage capacitor.

[0009] Preferably, when the power tube operates normally, the driving sub-circuit provides the required current to the logic sub-circuit.

[0010] Preferably, the driving sub-circuit includes a clamping module, the output control terminal, the first voltage terminal, the second voltage terminal, and the third voltage terminal are all subordinate to the clamping module, the clamping module includes a voltage detection component and a current control component, the output terminal of the voltage detection component and the input terminal of the current control component are connected in common and connected as the output control terminal;

[0011] The voltage detection component is used to detect the voltage difference between the two ends of the driving energy storage capacitor and output a corresponding level signal;

[0012] The current control component is used to provide corresponding current to the driving energy storage capacitor and the logic sub-circuit according to the output of the voltage detection component, and when the power tube is working normally, the driving sub-circuit provides the required current to the logic sub-circuit.

[0013] Preferably, the voltage detection component includes a second comparator, a third switching element, a third constant current source, a fourth constant current source and a first resistor, the first input end of the second comparator is connected to the two ends of the driving energy storage capacitor through two resistors, the second input end of the second comparator is connected to the second end of the first resistor, the input end of the third constant current source, and the input end of the fourth constant current source, the first end of the first resistor is connected to the first end of the driving energy storage capacitor, the output end of the fourth constant current source is connected to the input end of the third switching element, the control end of the third switching element is connected to the output end of the second comparator, and the output end of the third switching element and the output end of the third constant current source are both grounded;

[0014] The second comparator is used to output a second level signal from the output control end to the logic sub-circuit when the voltage difference across the driving energy storage capacitor reaches a second preset value, so that the power tube operates normally, the power supply circuit operates normally, and the driving sub-circuit continues to reduce the charging current of the driving energy storage capacitor to reduce the voltage difference across the driving energy storage capacitor to the first preset value.

[0015] Preferably, the current control component includes a first current output unit and a second current output unit, and the output ends of the first current output unit and the second current output unit are connected together as the third voltage end to be connected to the current input end of the logic sub-circuit. The first current output unit is used to provide a compensation current for the logic sub-circuit when the power tube is in a frequency reduction state, and the second current output unit is used to provide a charging current for the logic sub-circuit when the power tube is working normally.

[0016] Preferably, the second current output unit is further used to stop or reduce the output of the first current output unit when the power tube is working normally; the first current output unit is further used to stop or reduce the output of the second current output unit when the power tube is in a frequency reduction state.

[0017] Preferably, the logic sub-circuit includes a momentary latch unit and a first comparator, the input end of the momentary latch unit is connected to the output control end, and the output end is connected to the second input end of the first comparator, for receiving the control signal provided by the output control end and controlling the power tube through the first comparator.

[0018] Preferably, the instantaneous latch unit adopts the structure of RS latch and timer, which is used to pull down the level signal of the second input terminal for a predetermined time to turn off the power tube and enable the driving sub-circuit to charge the driving energy storage capacitor.

[0019] A method for obtaining power from a power supply circuit, comprising the power supply circuit as described above, and obtaining power by the following method:

[0020] providing the required current to the logic sub-circuit through the driver sub-circuit;

[0021] The driving sub-circuit is used to detect the voltage difference between the two ends of the driving energy storage capacitor, and when the voltage difference between the two ends of the driving energy storage capacitor reaches a second preset value:

[0022] The driving sub-circuit outputs a second level signal to the logic sub-circuit, the power tube operates normally, the power supply circuit operates normally, the charging current of the driving energy storage capacitor is reduced, and the voltage difference across the driving energy storage capacitor is reduced, so that the voltage difference across the driving energy storage capacitor is reduced to a first preset value.

[0023] A power chip includes the power circuit as described above.

[0024] In the power supply circuit provided by the present invention, a series power supply mode is adopted for the logic sub-circuit and the driving sub-circuit, that is, the driving energy storage capacitor of the driving sub-circuit is charged while the logic sub-circuit is powered. The two circuits use the same current, and the driving sub-circuit also switches the current according to the voltage of the driving energy storage capacitor, thereby saving the chip's own power consumption.

[0025] In the power supply circuit power supply method provided by the present invention, the inherent power consumption of the chip is reduced by using a driving sub-circuit to synchronously supply power to the driving energy storage capacitor and the logic sub-circuit, and the voltage across the driving energy storage capacitor is monitored. Based on this, the corresponding current is set to charge the driving energy storage capacitor. The driving sub-circuit provides the required current according to the working state of the power supply circuit, further reducing power consumption, and constructing a set of dynamic power supply control and output optimization systems, thereby reducing chip power consumption and ensuring that the chip can stably control the switching of the internal power supply circuit and the normal operation of the logic in any state, ensuring normal chip function and long-term reliability. The power supply circuit power supply method provided by the present invention and the power supply circuit provided by the present invention belong to the same inventive concept. Therefore, the power supply circuit power supply method provided by the present invention has at least all the advantages of the power supply circuit provided by the present invention, which will not be repeated here.

[0026] The power chip provided by the present invention and the power circuit provided by the present invention belong to the same inventive concept. Therefore, the power chip provided by the present invention has at least all the advantages of the power circuit provided by the present invention, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0028] Figure 1 This is a schematic diagram of the internal structure of an existing power chip;

[0029] Figure 2 This is a schematic diagram of the internal structure of a power chip according to an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of a current control component in a clamping module according to an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a voltage detection component in a clamping module according to an embodiment of the present invention;

[0032] Figure 5 FIG. 1 is a schematic diagram of a transient latch unit according to an embodiment of the present invention.

[0033] Attached photos

[0034] 100. Existing power chip; 200. Power chip.

[0035] 1. Existing logic sub-circuit; 2. Existing driving sub-circuit; 3. Existing power tube; 4. Logic sub-circuit; 5. Driving sub-circuit; 6. Power tube.

[0036] 101. Existing startup and voltage regulation module; 102. Existing logic function module; 1021. Existing error amplifier; 1022. Existing compensation unit; 1023. Existing comparator; 1024. Existing oscillator; 1025. Existing overcurrent protection unit; 1026. Existing latch; 1027. Existing overtemperature protection unit; 103. Existing clamping module; 104. Existing drive module.

[0037] 201. Start-up and voltage regulation module; 202. Logic function module; 2021. Error amplifier; 2022. Compensation unit; 2023. First comparator; 2024. Oscillator; 2025. Overcurrent protection unit; 2026. Latch; 2027. Overtemperature protection unit; 2028. Instantaneous latch unit; 203. Clamping module; 2031. First voltage terminal; 2032. Second voltage terminal; 2033. First current output unit; 2034. Second current output unit; 2035. Second comparator; 2036. Third voltage terminal; 204. Driving module; 2041. First driving terminal; 2042. Second driving terminal; 2043. Third driving terminal; 2044. Fourth driving terminal. DETAILED DESCRIPTION

[0038] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0039] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium; they can be internal communication between two elements or an interactive relationship between two elements. In addition, as used in the present invention, "one element is arranged on another element" generally only means that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element, and it should not be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] The core idea of ​​the present invention is to provide a power supply circuit, a power supply method thereof, and a power supply chip. By adopting a series power supply mode for the logic sub-circuit and the driving sub-circuit, that is, supplying power to the logic sub-circuit while charging the driving energy storage capacitor of the driving sub-circuit, the two circuits use the same current, and the driving sub-circuit will also switch the current according to the voltage of the driving energy storage capacitor, thereby saving the chip's own power consumption.

[0041] The following description is given with reference to the accompanying drawings.

[0042] Research has found that the drain-source voltage of MOS transistors is relatively high, but the gate-source voltage is generally within 20V. For high-voltage power chips, dedicated MOS transistor driver circuits are required to quickly turn the power transistors inside the chip on or off. The CISS capacitance (the input capacitance of the MOS transistor, also known as parasitic capacitance) or COSS capacitance (the output capacitance of the MOS transistor, also known as parasitic capacitance) of the power MOS transistor is relatively large. If the power MOS transistor needs to be turned on or off quickly, the gate-source of the MOS transistor must be charged (to charge the parasitic capacitance) at the moment of turn-on. The current peak is in the hundreds of milliamperes (mA). After the power transistor is turned on, only a tiny current is required to keep the device on. When turning off the power transistor, the gate-source of the MOS transistor needs to be short-circuited. This can instantly discharge the charge in the gate-source parasitic capacitance and quickly turn off the power transistor.

[0043] Existing solutions all draw power from the power supply for the chip's internal logic subcircuits, while the driver module draws power independently from the power supply. These two modules operate independently, without affecting each other. However, this results in high chip power consumption, especially as the input voltage increases. This inherently high power consumption causes the chip to heat up significantly when exposed to high input voltage, preventing it from stably outputting high power.

[0044] For example Figure 1 The conventional power supply chip 100 shown in the figure has its existing logic sub-circuit 1 and existing driver sub-circuit 2 independently powered, which can be referred to as parallel power supply. The existing logic sub-circuit 1 includes an existing startup and voltage regulation module 101 and an existing logic function module 102. The existing logic function module 102 includes an existing error amplifier 1021, an existing compensation unit 1022, an existing comparator 1023, an existing oscillator 1024, an existing overcurrent protection unit 1025, an existing latch 1026, an existing overtemperature protection unit 1027, and the like. The existing driver sub-circuit 2 is defined as an existing power transistor driver module, including an existing clamping module 103 and an existing driver module 104. The specific functions of the above units and modules can be understood based on their names.

[0045] The existing power supply chip 100 also includes an existing power tube 3, a VIN port, a VC port, a SW port, a GND port, and an FB port. Among them, the VC port and the VIN port are used to connect to the drive energy storage capacitor CC, the SW port is used to output voltage, the FB port is used to obtain feedback voltage, and the GND port is used for grounding. The VIN port is also used to obtain input power. It can be seen from the block diagram that the two modules are powered independently. The total current consumed by the chip during operation is IQ1+IQ2. The current consumed is relatively large. For a high-voltage power management chip, the power consumption generated by this current is too large, and the heat is serious. The chip cannot output high power.

[0046] Further research revealed that a series power supply mode could be used to address the high current consumption issue. This mode simultaneously powers the logic circuit and charges the driver module's energy storage capacitor, allowing both modules to use the same current, thus reducing the chip's power consumption. However, due to significant differences in power supply mode from conventional circuits, the existing circuit design architecture could not guarantee stable and reliable chip operation, necessitating the addition of an auxiliary judgment module to enhance chip reliability.

[0047] Based on this, the present invention determines the voltage difference across the drive energy storage capacitor CC and controls the power supply from the third voltage terminal (i.e., node C) to the internal logic sub-circuit of the chip by outputting a control terminal (i.e., VON) signal, as well as the charging of the drive energy storage capacitor CC, thereby achieving a more precise and controllable series power supply mode. This prevents significant changes in the voltage of the clamping module driving the energy storage capacitor due to changes in the chip's operating state during operation.

[0048] For details, please refer to Figure 2-Figure 5 , which is a schematic diagram of an embodiment of the present invention. Figure 2 As shown, a power supply circuit includes a logic sub-circuit 4, a driving sub-circuit 5, and a driving energy storage capacitor CC, wherein the driving sub-circuit 5 is used to supply power to the driving energy storage capacitor CC and the logic sub-circuit 4;

[0049] The driving sub-circuit 5 has an output control terminal VON, a first voltage terminal 2031, a second voltage terminal 2032 and a third voltage terminal 2036. The first voltage terminal 2031 and the second voltage terminal 2032 are respectively connected to the two ends of the driving energy storage capacitor CC. The driving sub-circuit 5 is configured to detect the voltage difference between the two ends of the driving energy storage capacitor CC and control the charging state of the driving energy storage capacitor CC.

[0050] The current input terminal of the logic sub-circuit 4 is connected to the third voltage terminal 2036, so that the logic sub-circuit 4 and the driving sub-circuit 5 are connected in series, and the output control terminal VON is connected to the control terminal of the logic sub-circuit 4 to establish the voltage across the driving energy storage capacitor CC.

[0051] like Figure 2As shown, power is supplied by connecting the logic sub-circuit 4 and the driving sub-circuit 5 in series. It is understandable that the series power supply mode is quite different from the conventional circuit. The original circuit design architecture cannot guarantee that the chip can work stably and reliably. It is necessary to further add an auxiliary judgment module to increase the reliability of the chip. For example, at the moment the chip is powered on, the voltage of the internal logic sub-circuit 4 is established quickly, but the driving energy storage capacitor CC of the driving sub-circuit 5 needs to store a certain amount of energy first to ensure the subsequent rapid and normal opening or closing of the power tube 6. If the energy stored in the driving energy storage capacitor CC is abnormal (too high or too low), the power tube 6 cannot be opened or closed normally. If it starts working at this time, it may cause the chip to fail. Therefore, in order to improve the reliability of the series power supply circuit, the driving sub-circuit 5 supplies power to the logic sub-circuit 4 while also monitoring the voltage difference across the driving energy storage capacitor CC, for example Figure 2 and Figure 3 Since the VIN voltage remains essentially unchanged after power-on, the VON signal is output by determining the voltage at point VC to control the power supply state of the third voltage terminal 2036 to the chip's internal logic sub-circuit 4. Furthermore, the VON signal is used to control the charging state of the VIN terminal of the drive energy storage capacitor CC by the driver sub-circuit 5. This establishes the voltage across the drive energy storage capacitor CC during the initial power-on phase, achieving a more precise and controllable series power supply mode. This prevents significant fluctuations in the voltage of the energy storage capacitor CC driven by the VC clamp circuit due to changes in the chip's operating state (the VC clamp circuit drives the energy storage capacitor CC to power the driver module 204, allowing the driver module 204 to provide a transient high current to the gate-source of the MOS transistor, thereby quickly turning on the power transistor 6), which could prevent the normal on / off control of the power transistor 6.

[0052] like Figure 2 The control terminal and input terminal of the power tube 6 are both connected to the output terminal of the driving sub-circuit 5. Specifically, the control terminal and input terminal of the power tube 6 are connected to the driving module 204, and are connected to the output terminal of the logic sub-circuit 4 through the driving module 204. The first voltage terminal 2031 and the second voltage terminal 2032 correspond to VIN and VC respectively, the third voltage terminal 2036 corresponds to the C node, and the output control terminal corresponds to VON. The two expressions have the same meaning.

[0053] In one embodiment, when the power tube 6 is operating normally, the driver sub-circuit 5 provides the required current to the logic sub-circuit 4. The switching frequency corresponding to the switching power supply is several hundred kHz. To reduce the switching loss of the power tube, the power tube turn-on time within the chip is in the nanosecond range. However, the power tube has parasitic capacitance, so a dedicated MOS tube driver circuit is required to control the power tube 6 within the chip. This circuit transiently provides a current of several hundred mA to the gate-source of the power tube to quickly turn on the MOS tube. Since the MOS tube is a voltage-controlled device, once the power tube 6 is turned on, it consumes substantially no drive current during the subsequent several microseconds of continuous operation. The energy consumed by the MOS tube each time it is turned on can be considered fixed; the more times it is turned on per unit time, the greater the energy consumption. During normal operation, the chip's switching frequency is the highest, i.e., the highest energy consumption. Under conditions such as light load or short circuit, the chip will reduce its operating frequency, i.e., operate in a reduced-frequency state. When the power tube 6 is operating normally, that is, when the power chip is operating normally, there is no need to continue to use transient currents of hundreds of mA. Only a small current can be used to keep the device turned on. When the power chip is operating in a reduced-frequency state, in order to prevent continuous charging from causing the voltage of the driving energy storage capacitor CC to be too high, thereby damaging the power tube, the charging current of the driving energy storage capacitor CC is reduced, and the voltage difference across the driving energy storage capacitor CC is reduced. The driving sub-circuit 5 can provide current based on the current operating state of the power tube 6, that is, provide current based on the voltage difference across the driving energy storage capacitor CC, thereby reducing the inherent power consumption of the entire power supply circuit.

[0054] Specifically, the driving sub-circuit 5 includes a clamping module 203. The output control terminal VON, the first voltage terminal 2031, the second voltage terminal 2032, and the third voltage terminal 2036 are all subordinate to the clamping module 203. The clamping module 203 includes a voltage detection component and a current control component. The output terminal of the voltage detection component and the input terminal of the current control component are connected in common and connected as the output control terminal.

[0055] The voltage detection component is used to detect the voltage difference between the two ends of the driving energy storage capacitor CC and output a corresponding level signal;

[0056] The current control component is used to provide corresponding current to the driving energy storage capacitor CC and the logic sub-circuit 4 respectively according to the output of the voltage detection component, and when the power tube is working normally, the driving sub-circuit 5 provides the required current to the logic sub-circuit 4.

[0057] It can be understood that the logic sub-circuit 4 and the driving sub-circuit 5 are connected in series through the clamping module 203. The voltage detection component in the clamping module 203 detects the voltage across the driving energy storage capacitor CC, and outputs a corresponding level signal to the output control terminal VON and the current control component according to the voltage of the driving energy storage capacitor CC. The current control component can control the internally powered constant current source to charge the driving energy storage capacitor CC according to the level signal. The output control terminal VON is also externally connected to the logic sub-circuit 4, and is used to delay the start-up of the power tube 6 at the initial power-on stage, and is used to charge the driving energy storage capacitor CC, establish the voltage across the driving energy storage capacitor CC, and make the driving energy storage capacitor CC store a certain amount of energy, thereby achieving the purpose of quickly turning on and off the power tube 6.

[0058] The driver sub-circuit 5 further includes a driver module 204. A first driver terminal 2041 of the driver module 204 is connected to the output terminal of the latch 2026 in the logic sub-circuit 4, a second driver terminal 2042 is connected to the second voltage terminal 2032, i.e., VC, and a third driver terminal 2043 and a fourth driver terminal 2044 are respectively connected to the source and gate of the power tube 6. The source is also connected to VIN. Therefore, by connecting to the logic sub-circuit 4 through the output control terminal VON, the power tube 6 can be delayed in the early stage of power-on, and the drive energy storage capacitor CC can be charged through the driver module 204 to establish a voltage across the drive energy storage capacitor CC.

[0059] like Figure 4 As shown, the voltage detection component includes a second comparator 2035, a third switching element Q3, a third constant current source IS3, a fourth constant current source IS4 and a first resistor R1. The first input end of the second comparator 2035 is connected to the two ends of the driving energy storage capacitor CC through two resistors, the second input end of the second comparator 2035 is connected to the second end of the first resistor R1, the input end of the third constant current source IS3, and the input end of the fourth constant current source IS4. The first end of the first resistor R1 is connected to the first end of the driving energy storage capacitor CC. The output end of the fourth constant current source IS4 is connected to the input end of the third switching element Q3, the control end of the third switching element Q3 is connected to the output end of the second comparator 2035, and the output end of the third switching element Q3 and the output end of the third constant current source IS3 are both grounded.

[0060] The second comparator 2035 is configured to, when the voltage difference across the drive energy storage capacitor CC reaches a second preset value, output a second level signal from the output control terminal VON to the logic sub-circuit 4, causing the power transistor 6 to operate normally, thereby enabling the power supply circuit to operate normally. The second comparator 2035 also reduces the charging current of the drive energy storage capacitor CC to reduce the voltage difference across the drive energy storage capacitor CC to the first preset value. Otherwise, the second comparator 2035 outputs a first level signal to continue charging the drive energy storage capacitor CC, thereby increasing the voltage difference across the drive energy storage capacitor CC. For example, since the voltage at the VIN terminal of the drive energy storage capacitor CC remains substantially unchanged, the voltage difference across the drive capacitor CC can be changed by charging the VC terminal.

[0061] It should be noted that after the voltage difference across the energy storage capacitor CC reaches the second preset value, when the voltage difference across the energy storage capacitor CC is reduced to the first preset value by charging, the output control terminal VON is correspondingly switched to output the first level signal, the power tube 6 switches normally, and the entire chip operates normally. The non-inverting input terminal of the second comparator 2035 is connected to the A node, and the A node is respectively connected to the second resistor R2 and the third resistor R3. The other ends of the second resistor R2 and the third resistor R3 are respectively connected to the two ends of the energy storage capacitor CC, that is, VIN and VC of the energy storage capacitor CC. The inverting input terminal of the second comparator 2035 is used to provide a reference value for comparison with the non-inverting input terminal, which is provided by the third constant current source IS3 and the fourth constant current source IS4, the first resistor R1, and the third switch element Q3. The first resistor R1 and the third constant current source IS4 are connected to the first resistor R1 and the third constant current source IS4. 3, node B is further connected to a fourth constant current source IS4, the other end of the fourth constant current source IS4 is further connected to the input end of the third switching element Q3, and the control end of the third switching element Q3 is connected to the output control end VON. The third switching element Q3 and the third constant current source IS3 are added to change the voltage value of the node B. When the output control end VON is high, the third switching element Q3 is turned on to lower the voltage value of the node B, thereby increasing the hysteresis window and avoiding VON oscillation. The output end of the second comparator 2035 is the output control end VON.

[0062] In one embodiment, the third switching element Q3 is an NPN transistor, the first level signal and the second level signal are relatively high level signals and low level signals, and after VON is triggered low, regardless of the state of the output control terminal VON signal, the logic sub-circuit 4 no longer controls the output, and the power tube 6 and the entire chip work normally.

[0063] Specifically, the current control component includes a first current output unit 2033 and a second current output unit 2034. The output ends of the first current output unit 2033 and the second current output unit 2034 are connected together as the third voltage end 2036 to be connected to the current input end of the logic sub-circuit 4. The first current output unit 2033 is used to provide a compensation current for the logic sub-circuit 4 when the power tube 6 is in a frequency reduction state. The second current output unit 2034 is used to provide a charging current for the logic sub-circuit 4 when the power tube 6 is working normally.

[0064] It can be understood that the second current output unit 2034 is also used to stop or reduce the output of the first current output unit 2033 when the power tube 6 is working normally; the first current output unit 2033 is also used to stop or reduce the output of the second current output unit 2034 when the power tube 6 is in a frequency reduction state.

[0065] The first current output unit 2033 outputs the compensation current I1, and the second current output unit 2034 outputs the charging current I2. electricity The current I2 is used for common power supply or individual power supply under the control of the signal provided by the output control terminal VON.

[0066] Based on the current I1 output by the first current output unit 2033 of the power supply, the current I2 output by the second current output unit 2034, and the output control terminal VON signal provided by the voltage detection component, it can be known that the circuit working state changes in the following situations: First, when the chip is working normally with load, the switching frequency is fixed. At this time, the amount of charge generated by the current I2 supplying power to the logic sub-circuit 4 per unit time is consistent with the amount of charge generated by the current I3 that turns on the MOS tube discharge to the driving module 204. Since the charge amounts of charging and discharging are basically the same, the voltage VC will not change, and the current I1 can be turned off, leaving only I2. Second, when the chip is started with load or enters discontinuous mode, no-load, or short-circuited, it operates in a reduced frequency state, with a frequency of 1 / 4-1 / 5 of the normal operating frequency. After the frequency is reduced, the charge generated by the discharge current I3 is less than the charge generated by the charging current I2. When the charging charge is greater than the discharging charge, the voltage across the drive energy storage capacitor CC will continue to increase. To prevent excessive voltage and damage to the power transistor 6 (the gate-source voltage difference of the power transistor is generally controlled within 20V), when the voltage reaches a second preset value, it is necessary to reduce the current I2 or even shut down I2. In this case, VON outputs a low level, and I1 begins to power the logic sub-circuit 4. This reduces the charge on the drive energy storage capacitor CC, and the voltage difference across the capacitor gradually decreases and remains within the normal range. Third, when the chip operates in light-load mode, the switching frequency will be lower. After I2 operates for a period of time, the capacitor voltage will reach the first preset value. At this time, the chip control logic can refer to the second case to ensure normal operation of the entire chip.

[0067] like Figure 3As shown, the first current output unit 2033 includes a first switching element Q1, a first constant current source IS1, a first voltage regulator DZ1, and a first diode D1. The input end of the first switching element Q1 is connected to the input end of the first constant current source IS1, the control end is connected to the output end of the first constant current source IS1, the output end is connected to the first diode D1, the input end of the first voltage regulator DZ1 is connected to the output end of the first constant current source IS1, and the output end is grounded; the second current output unit 2034 includes a second switching element Q2, a second constant current source IS2, a second voltage regulator DZ2, and a second diode D2. The input end of the second constant current source IS2 is connected to the input end of the first constant current source IS1. The two terminals are connected in common and serve as a first voltage terminal 2031, namely, VIN, connected to one end of the driving energy storage capacitor CC. The output terminal of the second constant current source IS2 is connected to the control terminal of the second switching element Q2 and the input terminal of the second voltage-stabilizing diode DZ2. The input terminal of the second switching element Q2 serves as a second voltage terminal 2032, namely, VC, connected to the other end of the driving energy storage capacitor CC. The output terminal of the second voltage-stabilizing diode DZ2 is grounded, the output terminal of the second switching element Q2 is connected to the input terminal of the second diode D2, and the output terminals of the first diode D1 and the second diode D2 are connected to the C node, namely, the third voltage terminal 2036, and are connected to the startup and voltage regulation module 201 of the logic sub-circuit 4 through the C node.

[0068] The current control component further includes a switching element Q0, a first capacitor C1, and a fourth switching element Q4. The input end of the switching element Q0 is connected to the control end of the first current output unit 2033 to control the first current output unit 2033. More preferably, the input end of the switching element Q0 is connected to the control end of the first switching element Q1, and the control end of the switching element Q0 is connected to the second comparator 2035 of the voltage detection component as the output control end VON. The output end of the switching element Q0 is grounded. The first end of the first capacitor C1, the fourth switching element The input end of Q4 is connected to the third voltage end 2036, that is, the C node. The control end of the fourth switch element Q4 is connected to the first voltage end 2031, that is, VIN. The output end of the fourth switch element Q4 and the second end of the first capacitor C1 are both grounded to prevent the third voltage end 2036 from oscillating. The second driving end 2042 and the third driving end 2043 of the driving module 204 are respectively connected to the two ends of the driving energy storage capacitor CC, and the third driving end 2043 is also connected to the source of the power tube 6. The fourth driving end 2044 is connected to the gate of the power tube 6.

[0069] The switch element Q0 , the first switch element Q1 , and the second switch element Q2 are all NPN transistors, and the fourth switch element Q4 is a PNP transistor.

[0070] As described above, during the initial power-up phase, to ensure that the drive energy storage capacitor CC of the VC clamp module 203 can be charged, I1 is disabled, leaving only I2 operational. Since the logic sub-circuit 4 can operate as long as there is current, and the drive energy storage capacitor CC requires time to charge, if the VC capacitor voltage has not yet built up and is too low, turning on the power transistor 6 at this time will cause the gate-source voltage of the power transistor 6 to be too low, preventing the power transistor 6 from fully turning on, resulting in significant MOS transistor losses and, in severe cases, thermal breakdown of the power transistor 6. To address this issue, the output control terminal VON of the clamp module 203 can output a corresponding level signal to control the logic sub-circuit 4, thereby disabling the power transistor 6 for a predetermined period of time during the initial power-up phase.

[0071] At the initial stage of power-on, the working state of the power tube 6 is controlled, the power tube 6 is turned off, and the output control terminal VON outputs a first level signal, that is, a high level. When I2 charges the driving energy storage capacitor CC to the second preset value, since it is the first time to power on, only I2 charges the driving energy storage capacitor CC, and the power tube 6 does not work, so I3 is 0. When the voltage of the driving energy storage capacitor CC is charged to the second preset value, a second level signal, that is, a low level, is output to allow the chip to start normal operation, that is, the power tube 6 turns on the normal switch. Since this second preset value is somewhat large, I1 is turned on and I1 is used to power the logic sub-circuit 4 synchronously. When the VC voltage returns to the first preset value, I2 is restored to power supply alone and I1 is turned off. In the entire working logic, I1 briefly participates in the power supply, and basically relies entirely on I2 for power supply, so that power consumption can be reduced. At this time, the module output control terminal VON signal is switched to the second level signal, and the control of the power tube 6 is also released.

[0072] In order to solve the problem that the power tube 6 may be thermally broken down at the initial stage of power-on, the present invention introduces a transient latch unit 2028, such as Figure 2 As shown, the logic sub-circuit 4 includes a transient latch unit 2028 and a first comparator 2023. The input terminal of the transient latch unit 2028 is connected to the output control terminal VON, and the output terminal is connected to the second input terminal of the first comparator 2023. The transient latch unit 2028 is configured to receive a control signal provided by the output control terminal VON and control the power transistor 6 via the first comparator 2023. The transient latch unit 2028 is configured to shut down the power transistor 6 at the initial power-on stage to charge the drive energy storage capacitor CC to ensure energy stored at both ends. The second input terminal is the inverting input terminal of the first comparator 2023, i.e., the VE node. The transient latch unit 2028 can pull down VE for a period of time based on the level signal of the output control terminal VON, thereby shutting down the power transistor 6 to charge both ends of the drive energy storage capacitor CC.

[0073] At the beginning of power-on, VE is pulled low in advance by the instantaneous latch unit 2028 (the VE signal is used to control the working state of the power tube. When the VE signal is pulled low, the power tube 6 inside the chip will not turn on and is in the off state) and locked for a preset time (this time is relatively short). When I2 charges the driving energy storage capacitor CC to the second preset value, (since it is the first time to power on, only I2 charges the driving energy storage capacitor CC, and the power tube 6 does not work, so I3 is 0), when the voltage is charged to the second preset value, a signal will be output to allow the chip to start normal operation, that is, the power tube 6 turns on the normal switch. Since the second preset value is a bit large, I1 will be turned on and I1 will be used to power the logic sub-circuit 4 simultaneously. When the VC voltage returns to the first preset value, I2 will resume power supply alone and I1 will be turned off. In the entire working logic, I1 briefly participates in the power supply, and basically relies entirely on I2 for power supply, so power consumption can be reduced. At this time, the module outputs a low-level signal VON.

[0074] Better, such as Figure 5 As shown, the instantaneous latch unit 2028 adopts the structure of RS latch and timer, which is used to pull down the level signal of the second input terminal VE for a predetermined time to turn off the power tube 6 and enable the driving sub-circuit 5 to charge the driving energy storage capacitor CC.

[0075] Therefore, after the instantaneous latch unit 2028 detects that the VON signal is low, the Q point outputs a high-level signal and no longer controls the VE signal, and the chip resumes normal operation. When this module uses the RS latch, as long as VON is triggered low, the Q point always outputs a high-level signal regardless of the VON signal state (because the S terminal is only high for a short time and is low the rest of the time, the Q point can be continuously high).

[0076] Specifically, the logic sub-circuit 4 also includes a startup and voltage regulation module 201, which receives current from the second voltage terminal 2032, namely VC, and provides current to the logic function module 202. The logic function module 202 includes an error amplifier 2021, a compensation unit 2022, an oscillator 2024, an overcurrent protection unit 2025, a latch 2026 and an overtemperature protection unit 2027. The above modules and devices have the same connection control method as the existing solution and are not repeated here.

[0077] like Figure 5As shown, the instantaneous latch unit 2028 includes the fifth switch element Q5 to the eighteenth switch element Q18, the fifth constant current source IS5, the fourth resistor R4 to the sixth resistor R6 and the capacitor C0. The fifth switch element Q5 to the eleventh switch element Q11 are PNP transistors, and the rest are NPN transistors. The tenth switch element Q10 and the capacitor C0 constitute a timer. The inputs of the fifth switch element Q5, the seventh switch element Q7, the eighth switch element Q8, the ninth switch element Q9, the tenth switch element Q10 and the eleventh switch element Q11 are The input terminal of the sixth switching element Q6 is connected to the control terminal of the fifth switching element Q5, the control terminal of the sixth switching element Q6 is connected to the input terminal of the fifth constant current source IS5 and the output terminal of the fifth switching element Q5, the output terminal of the sixth switching element Q6 is grounded, the output terminal of the fifth constant current source IS5 is grounded, the input terminal of the twelfth switching element Q12 is connected to the output terminal of the seventh switching element Q7, the control terminal of the twelfth switching element Q12 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to VON, and the output terminal of the twelfth switching element Q12 is connected to the output terminal of the seventh switching element Q7. The input terminal of the twelfth switching element Q12 is also connected to the control terminal of the thirteenth switching element Q13. The input terminal of the thirteenth switching element Q13, the input terminal of the fourteenth switching element Q14, and the control terminal of the fifteenth switching element Q15 are connected to the output terminal of the eighth switching element Q8. The control terminal of the fourteenth switching element Q14 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5, one end of the sixth resistor R6, the input terminal of the fifteenth switching element Q15, and the input terminal of the sixteenth switching element Q16 are connected to the input terminal of the ninth switching element Q9. The output terminal of the tenth switching element Q10 is connected to one end of the capacitor C0, and a current IC5 flows through the capacitor C0. The other end of the capacitor C0 is connected to the control terminal of the sixteenth switching element Q16. The control terminal of the seventeenth switching element Q17 is connected to the other end of the sixth resistor R6. The input terminal of the seventeenth switching element Q17 is connected to the output terminal of the eleventh switching element Q11 and the control terminal of the eighteenth switching element Q18. The input terminal of the eighteenth switching element Q18 is VE. The output terminals of the twelfth switching element Q12 to the eighteenth switching element Q18 are all grounded.

[0078] like Figure 5As shown, the specific circuit mainly consists of an RS latch and a timer. When the chip starts up, VC has not yet been successfully established, VON is high, and the R terminal is low. At this time, the S terminal utilizes the charging effect of capacitor C0. The S terminal is high, and the RS output Q is low, so VE is low, thereby achieving the purpose of pulling VE down. When the capacitor is fully charged and the S terminal is low, waiting for VC to charge and VON to be low, the R terminal is high, and the Q signal is high, releasing the pull-down of the VE signal. Since S is low, R does not change its level after this, and Q remains high, without affecting the VE voltage. This completes the delay function, achieving soft start and preventing the power tube 6 from operating in an abnormal state. This delay function mainly relies on the charge and discharge characteristics of the capacitor. Initially, the voltage across capacitor C0 is zero, and capacitor C0 is charged. At this time, the S terminal is high, and the sixteenth switch element Q16 is turned on. When capacitor C0 is fully charged, the sixteenth switch element Q16 is turned off, and the delay time is t1. The delay time and the capacitance value, the charging current is equal to IC5; the delay time t1 = C0 * V0 / IC5. Where C0 is the capacitance, V0 is 0.7V in the present invention.

[0079] Through the coordinated design of the clamping module 203 and the instantaneous latch unit 2028, a dynamic power supply control and output optimization system is constructed to reduce the chip power consumption and ensure that the chip can stably control the internal power supply circuit switching and logic operation in any state, ensuring the long-term reliability of the chip function.

[0080] Based on the same technical concept, the present invention also provides a method for obtaining power from a power supply circuit, including the power supply circuit as described above, and obtaining power using the following method:

[0081] Providing the required current to the logic sub-circuit 4 through the driving sub-circuit 5;

[0082] The driving sub-circuit 5 is used to detect the voltage difference between the two ends of the driving energy storage capacitor CC. When the voltage difference between the two ends of the driving energy storage capacitor CC reaches a second preset value:

[0083] The driving sub-circuit 5 outputs a second level signal to the logic sub-circuit 4, and the power tube 6 operates normally, so that the power supply circuit operates normally, the charging current of the driving energy storage capacitor CC is reduced, and the voltage difference across the driving energy storage capacitor CC is reduced, so that the voltage difference across the driving energy storage capacitor CC is reduced to a first preset value.

[0084] In which, when the voltage difference across the driving energy storage capacitor CC does not reach the second preset value, the driving sub-circuit 5 outputs a first level signal to the logic sub-circuit 4, the power tube 6 is turned off, and the driving sub-circuit 5 continues to charge the two ends of the driving energy storage capacitor CC to establish the voltage across the driving energy storage capacitor CC; and in the process of the voltage difference across the driving energy storage capacitor CC decreasing to the first preset value, after the logic sub-circuit 4 is triggered by the second level signal, regardless of the state of the output control terminal VON signal, the power tube 6 and the power supply circuit operate normally.

[0085] By connecting the logic sub-circuit 4 and the driving sub-circuit 5 in series, the driving sub-circuit 5 is used to synchronously power the driving energy storage capacitor CC and the logic sub-circuit 4, thereby reducing the inherent power consumption of the chip, and monitoring the voltage across the driving energy storage capacitor CC. Based on this, the corresponding current is set to charge the driving energy storage capacitor CC. The current provided inside the driving sub-circuit 5 is variable, and the required current IQ3 is provided according to the working state of the power supply circuit, further reducing power consumption. For example, when the power supply circuit is operating normally, the required current is less than the turn-on current, that is, the turn-on current is used to turn on the power tube 6 when power is turned on, and the voltage of the driving energy storage capacitor CC changes. The driving sub-circuit 5 can change the current accordingly based on the change in the voltage of the driving energy storage capacitor CC, thereby providing a smaller current.

[0086] As described above, the internal structure of the clamp module 203, the compensation current I1 output by the first current output unit 2033 in the current control component, and the charging current I2 output by the second current output unit 2034 are used to provide power together or independently under the control of the signal provided by the output control terminal VON. I2 is provided during normal chip operation, while I1 can also be introduced in other situations, such as during power-up.

[0087] Figure 3 and Figure 4The circuit structure of clamping module 203 shows that due to the operating characteristics of the DCDC circuit, the MOS transistor is in a periodic switching state during normal operation. Therefore, the charge on the energy storage capacitor CC is also periodically discharged. I2 is the charging current driving the energy storage capacitor CC (this current is a continuous current), and I3 is the discharging current driving the energy storage capacitor CC (this current is a switching current). I3 charges the CISS of the power transistor PMOS in parallel, causing the PMOS power transistor 6 to turn on quickly (the amount of charge consumed by power transistor 6 each time it is turned on can be considered fixed; the more times it is turned on per unit time, the greater the total charge consumed). The charging and discharging charges of I3 and I2 per unit time are the same, ensuring that I2 is always providing power while I1 is always off. As mentioned above, the I2 current is not completely constant. When the chip operates in discontinuous mode, is unloaded, or is short-circuited, the chip frequency is reduced, and the switching loss current of its PMOS power transistor 6 decreases. That is, the amount of charge discharged by I3 decreases. At this time, after the VC voltage difference reaches the second preset value, VON outputs a low level, and I1 also powers the logic sub-circuit 4. By adjusting the parameters, it can be achieved that when I2 and I1 are powered simultaneously, the current required by the logic sub-circuit 4 is mainly provided by I1, and the I2 current can be very small. By reducing the I2 current value charging the energy storage capacitor CC, the voltage of the energy storage capacitor CC is ensured to not continue to increase (after the CC voltage exceeds 20V, turning on the power transistor 6 will damage the power transistor 6).

[0088] like Figure 4 To accurately detect the VC voltage state, the voltage detection component utilizes a highly sensitive comparator COMP, a preset constant current source, and a resistor to set the reference voltage of the second comparator 2035. The VC voltage is then compared with the set reference voltage. When the voltage on the lower plate of the driving energy storage capacitor CC is detected to be lower than the set internal reference value, it indicates that the driving energy storage capacitor CC has been sufficiently charged. VON outputs a low level, and I1 begins to power the logic sub-circuit 4. Reasonable settings ensure that I2 approaches zero, preventing the voltage difference on the driving energy storage capacitor CC from further increasing. During normal operation, reasonable settings ensure that the charging charge of I2 and the discharging charge of I3 per unit time are equal. In this way, the main power consumption of the power supply chip remains I2. After the chip is operating normally, I1 is turned off. The state of switching the power supply terminal of I1 only occurs during low-frequency operation such as startup, short-circuit protection, and light load. In addition, a fourth switching element Q4 and a first capacitor C1 are added to provide stable power supply for the startup and voltage stabilization module 201 and ensure that the charge on the first capacitor C1 is discharged when the chip is shut down, ensuring that the startup and voltage stabilization module 201 shuts down quickly. The first diode D1 and the second diode D2 are added to clamp the voltage at point C and ensure stability at point C. The third switch element Q3 and the third constant current source IS3 are added to change the voltage value at point B. When VON is high, the third switch element Q3 is turned on to change the reference value at point B, thereby increasing the hysteresis window and preventing VON oscillation.

[0089] Based on the same technical concept, the present invention also provides a power chip, including the power circuit as described above.

[0090] In existing power supply chips, the logic power supply circuit and the power tube drive circuit are powered separately, resulting in relatively high power consumption of the chip itself, affecting the output power under high-voltage conditions. To reduce power consumption, the present invention uses a series power supply mode to reuse one current path, eliminating the need to power the logic sub-circuit separately. Due to changes in the power supply state, multiple detection modes and power supply modes are provided to solve possible abnormalities that may occur in the chip under different working modes.

[0091] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A power supply circuit, characterized in that: It includes a logic sub-circuit, a driving sub-circuit, and a driving energy storage capacitor, wherein the driving sub-circuit is used to supply power to the driving energy storage capacitor and the logic sub-circuit; The driving sub-circuit has an output control terminal, a first voltage terminal, a second voltage terminal and a third voltage terminal, wherein the first voltage terminal and the second voltage terminal are respectively connected to the two ends of the driving energy storage capacitor, and the driving sub-circuit is configured to detect the voltage difference between the two ends of the driving energy storage capacitor and control the charging state of the driving energy storage capacitor; The current input terminal of the logic sub-circuit is connected to the third voltage terminal, so that the logic sub-circuit and the driving sub-circuit are connected in series, and the output control terminal is connected to the control terminal of the logic sub-circuit to establish the voltage across the driving energy storage capacitor; when the power tube is working normally, the driving sub-circuit provides the required current to the logic sub-circuit; The driving sub-circuit includes a clamping module, the clamping module includes a voltage detection component, the voltage detection component includes a second comparator, a third switching element, a third constant current source, a fourth constant current source and a first resistor, the first input end of the second comparator is respectively connected to the two ends of the driving energy storage capacitor through two resistors, the second input end of the second comparator is connected to the second end of the first resistor, the input end of the third constant current source, and the input end of the fourth constant current source, the first end of the first resistor is connected to the first voltage end of the driving energy storage capacitor, the output end of the fourth constant current source is connected to the input end of the third switching element, the control end of the third switching element is connected to the output end of the second comparator, and the output end of the third switching element and the output end of the third constant current source are both grounded; The second comparator is used to output a second level signal from the output control end to the logic sub-circuit when the voltage difference across the driving energy storage capacitor reaches a second preset value, so that the power tube operates normally, the power supply circuit operates normally, and the charging current of the driving energy storage capacitor is reduced to reduce the voltage difference across the driving energy storage capacitor to the first preset value.

2. The power supply circuit according to claim 1, wherein: The output control terminal, the first voltage terminal, the second voltage terminal and the third voltage terminal are all subordinate to the clamping module, and the clamping module includes a current control component. The output terminal of the voltage detection component and the input terminal of the current control component are connected in common and connected as the output control terminal; The voltage detection component is used to detect the voltage difference between the two ends of the driving energy storage capacitor and output a corresponding level signal; The current control component is used to provide corresponding current to the driving energy storage capacitor and the logic sub-circuit according to the output of the voltage detection component, and when the power tube is working normally, the driving sub-circuit provides the required current to the logic sub-circuit.

3. The power supply circuit according to claim 2, wherein: The current control component includes a first current output unit and a second current output unit. The output ends of the first current output unit and the second current output unit are connected together as the third voltage end to be connected to the current input end of the logic sub-circuit. The first current output unit is used to provide a compensation current for the logic sub-circuit when the power tube is in a frequency reduction state. The second current output unit is used to provide a charging current for the logic sub-circuit when the power tube is operating normally.

4. The power supply circuit according to claim 3, wherein: The second current output unit is further used to stop or reduce the output of the first current output unit when the power tube is working normally; the first current output unit is further used to stop or reduce the output of the second current output unit when the power tube is in a frequency reduction state.

5. The power supply circuit according to claim 1, wherein: The logic sub-circuit includes a transient latch unit and a first comparator. The input end of the transient latch unit is connected to the output control end, and the output end is connected to the second input end of the first comparator. The logic sub-circuit is used to receive the control signal provided by the output control end and control the power tube through the first comparator.

6. The power supply circuit according to claim 5, characterized in that: The instantaneous latch unit adopts the structure of RS latch and timer, and is used to pull down the level signal of the second input terminal for a predetermined time to turn off the power tube, so that the driving sub-circuit charges the driving energy storage capacitor.

7. A method for obtaining power from a power supply circuit, characterized in that: The power supply circuit according to any one of claims 1 to 6 is provided with power by the following method: providing the required current to the logic sub-circuit through the driver sub-circuit; The driving sub-circuit is used to detect the voltage difference between the two ends of the driving energy storage capacitor, and when the voltage difference between the two ends of the driving energy storage capacitor reaches a second preset value: The driving sub-circuit outputs a second level signal to the logic sub-circuit, the power tube operates normally, the power supply circuit operates normally, the charging current of the driving energy storage capacitor is reduced, and the voltage difference across the driving energy storage capacitor is reduced, so that the voltage difference across the driving energy storage capacitor is reduced to a first preset value.

8. A power chip, characterized in that: The method comprises the power supply circuit according to any one of claims 1 to 6.

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