Efficient Hadamard decoding method and device suitable for high-speed parallel processing, storage medium and electronic equipment

Abstract

The invention provides an efficient Hadamard decoding method and device suitable for high-speed parallel processing, a storage medium and electronic equipment, and relates to the technical field of decoding, and the method comprises the steps: calculating an inner product of all Hadamard code words and a channel input LLR value through an FHT algorithm; according to the symmetry characteristic of a Hadamard matrix, bits needing to be decoded are grouped in pairs, a plurality of bit groups are obtained, and each bit group comprises a first bit and a second bit; and performing internal interleaving processing on each bit group, and calculating the maximum posterior probability value of the first bit and the second bit in each bit group according to the interleaving condition and the inner product to complete decoding. According to the technical scheme, the same decoding result is obtained under the condition that comparison is reduced, and hardware resource consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of decoding technologies, and more particularly, to an efficient Hadamard decoding method, apparatus, storage medium, and electronic device suitable for high-speed parallel processing. Background Art

[0002] Hadamard coding is a class of classical codes with extremely low code rates. When combined with other types of codes such as LDPC codes or Turbo codes, it can achieve excellent extremely low code rate code constructions. However, to achieve throughput improvement, high-speed parallel processing is generally required. Therefore, Hadamard coding is widely used in parallel in these constructions, consuming a large amount of logic resources.

[0003] The maximum a posteriori probability decoding of Hadamard codewords is the theoretically optimal decoding method in terms of performance.

[0004] Let the channel input LLR value be Then the maximum a posteriori probability value of each bit in the maximum a posteriori probability decoding is: ; In actual implementation, the max-log-MAP criterion is used to calculate the maximum a posteriori probability value, that is: ; Where represents the number of columns of the Hadamard matrix, represents the number of rows of the Hadamard matrix, represents the j-th column vector of the Hadamard matrix, represents the channel input LLR value.

[0005] To calculate the result of the above formula, it is first necessary to use the FHT algorithm to calculate the inner product of all Hadamard codewords and the channel input LLR values, and then use the DFHT calculation to compare and find the maximum value to obtain the posterior probability value.

[0006] In this process, due to high-speed parallel processing, resources cannot be reused and only pipelining operations can be performed. Therefore, when calculating the posterior probability values of the information bits and the last bit, the decoder with the DFHT design process needs to perform 96 comparisons, which greatly reduces the resource utilization rate. Summary of the Invention

[0007] Embodiments of the present application provide an efficient Hadamard decoding method, apparatus, storage medium, and electronic device suitable for high-speed parallel processing, so as to reduce the consumption of hardware resources in the efficient Hadamard decoding process of high-speed parallel processing.

[0008] Other features and advantages of the present application will become apparent from the following detailed description, or will be learned in part from the practice of the present application.

[0009] According to a first aspect of an embodiment of the present application, an efficient Hadamard decoding method applicable to high-speed parallel processing is provided, including: Calculating the inner product of all Hadamard codewords and the channel input LLR values through the FHT algorithm; There are symbols with the same number, pairing the bits corresponding to two rows with symbols with the opposite number to obtain a plurality of bit groups, where the bit groups include a first bit and a second bit, denotes the order of the Hadamard matrix;

[0010] In some embodiments of the present application, based on the foregoing solution, the calculation formula of the inner product is as follows: ; (1) where, denotes the inner product, denotes the th column in the Hadamard matrix, denotes the channel input LLR value, denotes the order of the Hadamard matrix.

[0011] In some embodiments of the present application, based on the foregoing solution, according to the symmetric property of the Hadamard matrix, pairing the bits to be decoded in pairs to obtain a plurality of bit groups, including: There are symbols with the same number, pairing the bits corresponding to two rows with symbols with the opposite number to obtain a plurality of bit groups, where

[0012] denotes the order of the Hadamard matrix. Interleaving the first bit and the second bit in each bit group with each other.

[0013] In some embodiments of the present application, based on the foregoing solution, calculating the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation includes: For any group of bit groups after internal interleaving, first perform level comparison calculations based on the inner product to obtain the maximum a posteriori probability value of the first bit in the bit group; then flip the level comparison result and perform the level comparison calculation to obtain the maximum a posteriori probability value of the second bit, where is a positive integer greater than or equal to 1.

[0014] In some embodiments of the present application, based on the foregoing solution, the calculation formula for the maximum a posteriori probability of the first bit is as follows: ; (2) where represents the coded information bit, represents the channel input LLR value, represents the number of bits.

[0015] According to the second aspect of the embodiments of the present application, an efficient Hadamard decoding device suitable for high-speed parallel processing is provided, including: A first calculation unit for calculating the inner product of all Hadamard codewords and the channel input LLR value through the FHT algorithm; A classification unit for pairing the bits corresponding to two rows in the Hadamard matrix where there are symbols with the same number and symbols with the opposite number pairwise to obtain a plurality of bit groups, where the bit group includes a first bit and a second bit, represents the order of the Hadamard matrix; A processing unit for performing internal interleaving processing on each bit group; A second calculation unit for calculating the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation and the inner product to complete decoding.

[0016] According to the third aspect of the embodiments of the present application, a computer-readable storage medium is provided, where computer instructions are stored in the storage medium, and when the computer instructions run on the computer, the computer is caused to execute the method described in the first aspect.

[0017] According to the fourth aspect of the embodiments of the present application, an electronic device is provided, including: a memory and a processor; The memory is used for storing computer instructions; The processor is used for calling the computer instructions stored in the memory, so that the electronic device executes the method described in the first aspect.

[0018] In the technical solution of the present application, first, the FHT calculation is performed on the channel input LLR values. Then, according to the symmetric property of the Hadamard matrix, the bits to be decoded are grouped in pairs and corresponding interleaving is performed, so that the comparison results of the two bits in each group can be utilized mutually, obtaining the same decoding result with fewer comparisons and reducing the consumption of hardware resources.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings: Figure 1 shows a schematic flowchart of an efficient Hadamard decoding method applicable to high-speed parallel processing according to an embodiment of the present application; Figure 2 shows a schematic logic diagram of an efficient Hadamard decoding method applicable to high-speed parallel processing according to an embodiment of the present application; Figure 3 shows a schematic diagram of the comparison calculation of the i-th bit before interleaving according to an embodiment of the present application; Figure 4 shows a schematic diagram of the comparison calculation of the k-th bit after interleaving according to an embodiment of the present application; Figure 5 shows a block diagram of an efficient Hadamard decoding device applicable to high-speed parallel processing according to an embodiment of the present application; Figure 6 shows a block diagram of an electronic device according to an embodiment of the present application; Figure 7 shows a schematic structural diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] Now, the exemplary embodiments will be described more comprehensively with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present application will be more comprehensive and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art.

[0022] In addition, the described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0023] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0024] The flowcharts shown in the drawings are only illustrative and not necessarily include all the contents and operations / steps, nor are they necessarily executed in the described order. For example, some operations / steps may be decomposed, while some operations / steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0025] It should be noted that the term "a plurality" mentioned herein refers to two or more.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that the objects so used can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described.

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0028] Hereinafter, some embodiments of the present application will be described in detail with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0029] See Figure 1, showing a schematic flow diagram of an efficient Hadamard decoding method applicable to high-speed parallel processing according to an embodiment of the present application.

[0030] As Figure 1 shown, an efficient Hadamard decoding method applicable to high-speed parallel processing is presented, specifically including steps S100 to S300.

[0031] To facilitate understanding of the technical solution of the present application, the Hadamard codewords are described below.

[0032] Hadamard codewords are constructed from all columns of a -order Hadamard matrix , where , = [+1], ; Let , and each column is a Hadmard codeword, that is . Then among them is the encoded information bit.

[0033] Referring to Figure 1 , step S100, calculate the inner product of all Hadamard codewords and the channel input LLR values through the FHT algorithm.

[0034] It can be understood that this step is the same as the inner product calculation process in the maximum a posteriori probability decoding method.

[0035] In some feasible embodiments, based on the foregoing solution, the calculation formula of the inner product is as follows: ; where represents the inner product, represents the th column in the Hadamard matrix, represents the channel input LLR value, represents the order of the Hadamard matrix.

[0036] Continuing to refer to Figure 1 , step S200, according to the symmetry characteristic of the Hadamard matrix, group the bits to be decoded in pairs to obtain multiple bit groups, where the bit group includes a first bit and a second bit.

[0037] In some feasible embodiments, based on the foregoing solution, step S200 includes: There are symbols with the same number in the Hadamard matrix, The bits corresponding to two rows with opposite numbers of symbols are paired in pairs to obtain a plurality of bit groups, where represents the order of the Hadamard matrix.

[0038] For example, in the Hadamard matrix, the i-th row and the k-th row have symbols with the same number, symbols with opposite numbers, then the i-th bit and the k-th bit are paired in pairs to form a bit group.

[0039] Continue to refer to Figure 1 , step S300, perform internal interleaving processing on each bit group, and calculate the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation and the inner product to complete decoding.

[0040] In some feasible embodiments, based on the foregoing solution, the performing internal interleaving processing on each bit group includes: Interleave the first bit and the second bit in each bit group with each other.

[0041] In some feasible embodiments, based on the foregoing solution, the calculating the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation includes: For any internally interleaved bit group, first perform level comparison calculations according to the inner product to obtain the maximum a posteriori probability value of the first bit in the bit group; then flip the level comparison result and then perform the level comparison calculations to obtain the maximum a posteriori probability value of the second bit, where is a positive integer greater than or equal to 1.

[0042] It can be understood that in this embodiment, the size of is determined by the number of comparison levels required to calculate the maximum a posteriori probability value of the first bit.

[0043] It can be understood that by repeating this step, the maximum a posteriori probability values of the bits in all bit groups can be obtained, and thus decoding can be realized.

[0044] Exemplarily, referring to Figure 2 , a logical schematic diagram of this method is shown.

[0045] Such as Figure 2As shown, this method first obtains all inner product values through FHT, then classifies and pairs the bits to be decoded. Each bit group undergoes different interleaving processes, changing the comparison order. At this time, pairwise comparison of the maximum and minimum values is performed in sequence, with one processing clock for one parallel comparison. The maximum a posteriori probability value of the first bit is obtained through r-level comparison. At the same time, due to the symmetry of the interleaving relationship design, the result of the (r - 1)-level comparison can be directly flipped and then the r-level comparison is performed to obtain the maximum a posteriori probability value of the second bit.

[0046] In some feasible embodiments, based on the foregoing solution, the calculation formula for the maximum a posteriori probability of the first bit is as follows: ; Wherein, represents the coded information bit, represents the channel input LLR value, represents the number of bits.

[0047] Next, the principle of this method is described.

[0048] The calculation of the maximum a posteriori probability value is performed using the max-log-MAP criterion, that is ; For the calculation of the maximum a posteriori probability of the i-th bit, first find all vectors that satisfy , and the corresponding vectors . Due to the symmetry of the Hadamard coding, there are such vectors in total. Then, arrange the corresponding inner product values of these vectors accordingly, which constitutes the positive group of the i-th bit.

[0049] ; At this time, due to the symmetry of the Hadamard coding, the negative group formed by the vectors that satisfy and the corresponding inner product values, and each value of it is exactly the opposite of the positive group. Therefore, the maximum value of the negative group corresponds to the minimum value of the positive group.

[0050] In summary, calculating the maximum a posteriori probability of the i-th bit can be changed to: ; At this time, only the maximum and minimum values of need to be found, and r-level pairwise comparisons are required. Here, a 16-code-length Hadamard example with r = 4 is used, such as Figure 3As shown, for a 16 - code - length Hadamard with r = 4, calculating the maximum a posteriori probability of one bit requires 22 comparisons.

[0051] Since in , that is, in the positive group of each bit, the sign of depends on the sign of . Due to the row - column symmetry of the Hadamard matrix, for the numbers in the i - th row, and for any numbers in the k - th row, there are numbers with the same sign and

[0052] numbers with opposite signs. Therefore, the maximum a posteriori probabilities for the i - th bit and the k - th bit can be paired for calculation, that is, by interleaving and rearranging , the interleaved data is obtained: ; where represents the set of inner - product values of the column vectors of the Hadamard matrix with +1 in all the rows and the LLR values, represents the set of inner - product values of the column vectors of the Hadamard matrix with +1 in the k - th row and the LLR values, represents the interleaved inner - product value.

[0053] Taking the Hadamard of 16 - code - length with r = 4 as an example, after 22 comparisons in the normal way, the result is obtained, while the comparison method of Figure 4 is as shown.

[0054] As shown in the figure, the comparisons with the same result as are marked in green, and the opposite comparison results are marked in red. Therefore, to obtain and , only the third - level comparison result of needs to be recorded. In the fourth - level comparison, the result after flipping the first third - level comparison result in the upper half and the second third - level comparison result in the lower half is compared, that is, is obtained; similarly, the result after flipping the first third - level comparison result in the lower half and the second third - level comparison result in the upper half is compared, that is, is obtained.

[0055] In summary, obtaining the maximum a posteriori probability values of the i-th bit and the k-th bit only requires 22 + 2 = 24 comparisons. In the Hadamard example with a code length of 16 and r = 4, a total of 72 comparisons are required for calculating the posterior probability of 6 bits including the information bits and the last bit. Compared with 96 times in the prior art, the resource utilization efficiency is improved by 33%, and this improvement will be even greater as the code length increases.

[0056] Experiments show that in the Hadamard example with a code length of 16 and r = 4, the present invention reduces the resource overhead by 33% compared with the prior art, which is of great significance for high-speed parallel processors.

[0057] The following introduces the device embodiments of the present application, which can be used to execute an efficient Hadamard decoding method applicable to high-speed parallel processing in the above embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application above.

[0058] Refer to Figure 5 As shown, an efficient Hadamard decoding device 500 applicable to high-speed parallel processing according to an embodiment of the present application includes: A first calculation unit 501, configured to calculate the inner product of all Hadamard codewords and the channel input LLR values through the FHT algorithm; A classification unit 502, configured to pair the bits corresponding to two rows in the Hadamard matrix where there are the same number of symbols and the opposite number of symbols pairwise to obtain a plurality of bit groups, where the bit groups include a first bit and a second bit, indicating the order of the Hadamard matrix; A processing unit 503, configured to perform internal interleaving processing on each bit group; A second calculation unit 504, configured to calculate the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation and the inner product to complete decoding.

[0059] As Figure 6 shown, an embodiment of the present application further provides an electronic device 600, including a memory 610, a processor 620, and a computer program 611 stored in the memory 610 and executable on the processor. When the processor 620 executes the computer program 611, the steps of the above-mentioned efficient Hadamard decoding method applicable to high-speed parallel processing are implemented.

[0060] Since the electronic device introduced in this embodiment is the device adopted by an efficient Hadamard decoding device suitable for high-speed parallel processing in the embodiments of the present application, based on the method introduced in the embodiments of the present application, those skilled in the art can understand the specific implementation manners and various variations of the electronic device in this embodiment. Therefore, the specific implementation of how this electronic device implements the method in the embodiments of the present application will not be described in detail here. As long as the device adopted by those skilled in the art to implement the method in the embodiments of the present application belongs to the scope protected by the present application.

[0061] In the specific implementation process, when the computer program 611 is executed by the processor, it can implement any implementation manner in the corresponding embodiment of the first aspect.

[0062] Figure 7 The structural schematic diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application is shown.

[0063] It should be noted that Figure 7 The computer system 700 of the electronic device shown is only an example and should not bring any limitation to the functions and usage scope of the embodiments of the present application.

[0064] As Figure 7 shown, the computer system 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 702 or the program loaded from the storage section 708 into the random access memory (RAM) 703, such as executing the method described in the above embodiments. In the RAM 703, various programs and data required for system operation are also stored. The CPU 701, ROM 702, and RAM 703 are connected to each other through a bus 704. The input / output (I / O) interface 705 is also connected to the bus 704.

[0065] The following components are connected to the I / O interface 705: an input section 706 including a keyboard, a mouse, etc.; an output section 707 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as required. A removable medium 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the drive 710 as required so that a computer program read therefrom is installed into the storage section 708 as required.

[0066] Specifically, according to an embodiment of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, an embodiment of the present application includes a computer program product including a computer program carried on a computer-readable medium, the computer program including program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 709, and / or installed from the removable medium 711. When the computer program is executed by a central processing unit (CPU) 701, various functions defined in the system of the present application are executed.

[0067] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present application, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which the computer-readable program code is carried. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and this computer-readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0068] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. Among them, each block in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0069] The units involved in the embodiments described in this application can be implemented in software or in hardware, and the described units can also be provided in a processor. In some cases, the names of these units do not constitute a limitation on the units themselves.

[0070] As another aspect, the present application also provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes an efficient Hadamard decoding method applicable to high-speed parallel processing described in the above embodiments.

[0071] As another aspect, the present application also provides a computer-readable medium. The computer-readable medium can be included in the electronic device described in the above embodiments; or it can exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more programs. When the above one or more programs are executed by an electronic device, the electronic device implements an efficient Hadamard decoding method applicable to high-speed parallel processing described in the above embodiments.

[0072] It should be noted that although several modules or units of a device for action execution are mentioned in the above detailed description, such a division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of the two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0073] Through the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented in software or in the form of software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (such as a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiments of the present application.

[0074] Other embodiments of the present application will be readily contemplated by those skilled in the art after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An efficient Hadamard decoding method applicable to high-speed parallel processing, characterized in that, Including: Calculating the inner product of all Hadamard codewords and the channel input LLR values through the FHT algorithm; According to the symmetry property of the Hadamard matrix, pairwise grouping the bits to be decoded to obtain multiple bit groups, where each bit group includes a first bit and a second bit; Performing internal interleaving processing on each bit group, and calculating the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation and the inner product to complete decoding.

2. The method according to claim 1, wherein The calculation formula of the inner product is as follows: ；（1） Among them, represents the inner product, represents the th column in the Hadamard matrix, represents the channel input LLR value, represents the order of the Hadamard matrix.

3. The method according to claim 1, characterized in that, The pairwise grouping of the bits to be decoded according to the symmetry property of the Hadamard matrix to obtain multiple bit groups includes: For two rows in a Hadamard matrix with numbers having the same sign and numbers having opposite signs, pair up the corresponding bits to obtain multiple bit groups, where represents the order of the Hadamard matrix.

4. The method according to claim 1, wherein The performing internal interleaving processing on each bit group includes: Interleaving the first bit and the second bit in each bit group with each other.

5. The method according to claim 4, wherein The calculating the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation includes: For any group of bit groups after internal interleaving, first perform level comparison calculations according to the inner product to obtain the maximum a posteriori probability value of the first bit in the bit group; then flip the level comparison result and then perform level comparison calculations to obtain the maximum a posteriori probability value of the second bit, where is a positive integer greater than or equal to 1.

6. The method according to claim 5, wherein The calculation formula of the maximum a posteriori probability of the first bit is as follows: ；（2） Among them, represents the coded information bits, represents the channel input LLR value, represents the number of bits.

7. An efficient Hadamard decoding device applicable to high-speed parallel processing, characterized in that, Including: A first calculation unit for calculating the inner product of all Hadamard codewords and the channel input LLR values through the FHT algorithm; A classification unit is used to pair up the bits corresponding to two rows in a Hadamard matrix where there are the same number of symbols and the same number of symbols with opposite signs in two rows to obtain multiple bit groups. Among them, the bit group includes a first bit and a second bit, represents the order of the Hadamard matrix; A processing unit for performing internal interleaving processing on each bit group; A second calculation unit for calculating the maximum a posteriori probability values of the first bit and the second bit in each bit group according to the interleaving situation and the inner product to complete decoding.

8. A computer-readable storage medium, characterized in that, Computer instructions are stored in the storage medium, and when the computer instructions are run on a computer, the computer is caused to execute the method according to any one of claims 1-6.

9. An electronic device, characterized in that, Including: A memory and a processor; The memory for storing computer instructions; The processor for calling the computer instructions stored in the memory, causing the electronic device to execute the method according to any one of claims 1-6.

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