An efficient Hadamard decoding method, device, storage medium and electronic device suitable for high-speed parallel processing

Abstract

The present application provides an efficient Hadamard decoding method, device, storage medium, and electronic device suitable for high-speed parallel processing, relating to the field of decoding technology. The method comprises: calculating the inner product of all Hadamard codewords and channel input LLR values ​​using an FHT algorithm; grouping the bits to be decoded in pairs according to the symmetry characteristics of the Hadamard matrix to obtain multiple bit groups, wherein the bit groups include a first bit and a second bit; performing internal interleaving processing on each bit group, and calculating the maximum a posteriori probability value of the first bit and the second bit in each bit group based on the interleaving situation and the inner product to complete the decoding. The technical solution of the present application obtains the same decoding result while reducing comparisons, thereby reducing hardware resource consumption.

Description

Technical Field

[0001] The present application relates to the field of decoding technology, and in particular to an efficient Hadamard decoding method, device, storage medium, and electronic device suitable for high-speed parallel processing. Background Art

[0002] Hadamard coding is a classic type of code that constructs very low bit rates. Combining it with other types of codes, such as LDPC codes or Turbo codes, can create excellent very low bit rate coding structures. However, to achieve increased throughput, high-speed parallel processing is generally required. Therefore, Hadamard coding is used extensively in parallel in these constructions, consuming significant logic resources.

[0003] The maximum a posteriori probability decoding of Hadamard codewords is the decoding method with the best performance in theory.

[0004] Assume that the channel input LLR value is , then the maximum a posteriori probability value of each bit of maximum a posteriori probability decoding is:

[0005] ;

[0006] In actual implementation, the max-log-MAP criterion is used to calculate the maximum a posteriori probability value, that is:

[0007] ;

[0008] in, represents the number of columns of the Hadamard matrix, represents the number of rows of the Hadamard matrix, represents the j-th column vector of the Hadamard matrix, Indicates the channel input LLR value.

[0009] To calculate the result of the above formula, we first need to use the FHT algorithm to calculate the inner product of all Hadamard codewords and the channel input LLR values, and then use the DFHT calculation to compare and find the maximum value to obtain the posterior probability value.

[0010] In this process, due to high-speed parallel processing, resources cannot be reused and can only be pipelined. Therefore, when calculating the information bit and the posterior probability value of the last bit, the decoder of the DFHT design process needs to spend 96 comparisons, which greatly reduces resource utilization. Summary of the Invention

[0011] The embodiments of the present application provide an efficient Hadamard decoding method, apparatus, storage medium, and electronic device suitable for high-speed parallel processing, so as to reduce hardware resource consumption during the efficient Hadamard decoding process of high-speed parallel processing.

[0012] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0013] According to a first aspect of an embodiment of the present application, there is provided an efficient Hadamard decoding method suitable for high-speed parallel processing, comprising:

[0014] Calculate the inner product of all Hadamard codewords and channel input LLR values ​​through the FHT algorithm;

[0015] The Hadamard matrix exists The numbers have the same sign, The bits corresponding to the two rows with opposite number signs are paired in pairs to obtain multiple bit groups, wherein the bit groups include the first bit and the second bit. represents the order of the Hadamard matrix;

[0016] Internal interleaving is performed on each bit group, and the maximum a posteriori probability value of the first bit and the second bit in each bit group is calculated based on the interleaving situation and the inner product to complete the decoding.

[0017] In some embodiments of the present application, based on the above scheme, the calculation formula of the inner product is as follows:

[0018] ; (1)

[0019] in, represents the inner product, Indicates the first List, Indicates the channel input LLR value, Represents the order of the Hadamard matrix.

[0020] In some embodiments of the present application, based on the aforementioned solution, the bits to be decoded are grouped in pairs according to the symmetric property of the Hadamard matrix to obtain multiple bit groups, including:

[0021] The Hadamard matrix exists The numbers have the same sign, The bits corresponding to the two rows with opposite numbers are paired up to obtain multiple bit groups, where: Represents the order of the Hadamard matrix.

[0022] In some embodiments of the present application, based on the aforementioned solution, performing internal interleaving on each bit group includes:

[0023] The first bit and the second bit in each bit group are interleaved with each other.

[0024] In some embodiments of the present application, based on the aforementioned solution, calculating the maximum a posteriori probability value of the first bit and the second bit in each bit group according to the interleaving situation includes:

[0025] For any group of bits after internal interleaving, first perform the inner product The maximum posterior probability value of the first bit in the bit group is calculated by level comparison; then the The first comparison result is flipped before the second The maximum posterior probability value of the second bit is obtained by level comparison calculation, where is a positive integer greater than or equal to 1.

[0026] In some embodiments of the present application, based on the aforementioned solution, the maximum a posteriori probability of the first bit is calculated as follows:

[0027] ; (2)

[0028] in, represents the coded information bits, Indicates the channel input LLR value, Indicates the number of bits.

[0029] According to a second aspect of an embodiment of the present application, there is provided an efficient Hadamard decoding device suitable for high-speed parallel processing, comprising:

[0030] A first calculation unit is used to calculate the inner product of all Hadamard code words and channel input LLR values ​​through an FHT algorithm;

[0031] Classification unit, used to convert the Hadamard matrix into The numbers have the same sign, The bits corresponding to the two rows with opposite number signs are paired in pairs to obtain multiple bit groups, wherein the bit groups include the first bit and the second bit. represents the order of the Hadamard matrix;

[0032] a processing unit, configured to perform internal interleaving processing on each bit group;

[0033] The second calculation unit is used to calculate the maximum a posteriori probability value of the first bit and the second bit in each bit group according to the interleaving situation and the inner product to complete decoding.

[0034] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein the storage medium stores computer instructions. When the computer instructions are executed on a computer, the computer executes the method according to the first aspect.

[0035] According to a fourth aspect of the embodiments of the present application, there is provided an electronic device, including: a memory and a processor;

[0036] The memory is used to store computer instructions;

[0037] The processor is configured to call the computer instructions stored in the memory so that the electronic device executes the method according to the first aspect.

[0038] The technical solution of the present application first performs FHT calculation on the channel input LLR value, and then groups the bits to be decoded into groups of two based on the symmetry characteristics of the Hadamard matrix and interleaves them accordingly, so that the comparison results of the two bits in each group can be used for each other, obtaining the same decoding result while reducing comparisons and reducing hardware resource consumption.

[0039] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0041] Figure 1 A flow chart of an efficient Hadamard decoding method suitable for high-speed parallel processing according to an embodiment of the present application is shown;

[0042] Figure 2 A logic diagram of an efficient Hadamard decoding method suitable for high-speed parallel processing according to an embodiment of the present application is shown;

[0043] Figure 3 FIG2 shows a schematic diagram of comparison calculation of the i-th bit before interleaving according to an embodiment of the present application;

[0044] Figure 4 1 shows a schematic diagram of comparison calculation of the k-th bit after interleaving according to an embodiment of the present application;

[0045] Figure 5 A block diagram of an efficient Hadamard decoding device suitable for high-speed parallel processing according to an embodiment of the present application is shown;

[0046] Figure 6 A block diagram of an electronic device according to an embodiment of the present application is shown;

[0047] Figure 7 A schematic diagram of the structure of a computer system suitable for implementing an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0049] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0050] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0051] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0052] It should be noted that the “plurality” mentioned in this article refers to two or more.

[0053] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described.

[0054] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0055] The following will describe some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0056] See also Figure 1 , shows a flow chart of an efficient Hadamard decoding method suitable for high-speed parallel processing according to an embodiment of the present application.

[0057] like Figure 1 As shown, an efficient Hadamard decoding method suitable for high-speed parallel processing is presented, which specifically includes steps S100 to S300.

[0058] To facilitate understanding of the technical solution of this application, Hadamard codewords are explained below.

[0059] The Hadamard codeword is composed of a Hadamard matrix of order All columns are constructed, where , =[+1],

[0060] ;

[0061] set up , each column is a Hadmard code word, that is . Then is the coded information bit.

[0062] refer to Figure 1 , step S100, calculating the inner product of all Hadamard codewords and channel input LLR values ​​through the FHT algorithm.

[0063] It can be understood that this step is the same as the inner product calculation process in the maximum a posteriori probability decoding method.

[0064] In some feasible embodiments, based on the above solution, the calculation formula of the inner product is as follows:

[0065] ;

[0066] in, represents the inner product, Indicates the first List, Indicates the channel input LLR value, Represents the order of the Hadamard matrix.

[0067] Continue to refer Figure 1 In step S200 , the bits to be decoded are grouped in pairs according to the symmetric property of the Hadamard matrix to obtain a plurality of bit groups, wherein the bit groups include a first bit and a second bit.

[0068] In some feasible embodiments, based on the above solution, step S200 includes:

[0069] The Hadamard matrix exists The numbers have the same sign, The bits corresponding to the two rows with opposite numbers are paired up to obtain multiple bit groups, where: Represents the order of the Hadamard matrix.

[0070] For example, in a Hadamard matrix, the i-th and k-th rows exist The numbers have the same sign, If the numbers have opposite signs, the i-th bit and the k-th bit are paired into a bit group.

[0071] Continue to refer Figure 1 In step S300, internal interleaving is performed on each bit group, and the maximum a posteriori probability value of the first bit and the second bit in each bit group is calculated according to the interleaving situation and the inner product to complete decoding.

[0072] In some feasible embodiments, based on the above solution, performing internal interleaving on each bit group includes:

[0073] The first bit and the second bit in each bit group are interleaved with each other.

[0074] In some feasible embodiments, based on the above solution, calculating the maximum a posteriori probability value of the first bit and the second bit in each bit group according to the interleaving situation includes:

[0075] For any group of bits after internal interleaving, first perform the inner product The maximum posterior probability value of the first bit in the bit group is calculated by level comparison; then the The first comparison result is flipped before the second The maximum posterior probability value of the second bit is obtained by level comparison calculation, where is a positive integer greater than or equal to 1.

[0076] It can be understood that, in this embodiment, The size of is determined by the number of comparisons required to calculate the maximum a posteriori probability value of the first bit.

[0077] It can be understood that by repeating this step, the maximum a posteriori probability value of the bits in all bit groups can be obtained, thereby achieving decoding.

[0078] For example, see Figure 2 , which shows a logical diagram of the method.

[0079] like Figure 2 As shown, this method first obtains all inner product values ​​through FHT, then classifies and pairs the bits to be decoded, and performs different interleaving processing on each bit group, so that the comparison order changes. At this time, the maximum and minimum values ​​are compared pairwise, and a parallel comparison is performed for one processing clock. The maximum a posteriori probability value of the first bit is obtained through r-level comparison. At the same time, due to the symmetry of the interleaving relationship design, the result of the comparison at the r-1 level can be directly flipped and then the r-level comparison can be performed to obtain the maximum a posteriori probability value of the second bit.

[0080] In some feasible embodiments, based on the above solution, the maximum a posteriori probability of the first bit is calculated as follows:

[0081] ;

[0082] in, represents the coded information bits, Indicates the channel input LLR value, Indicates the number of bits.

[0083] Next, the principle of this method is explained.

[0084] The maximum posterior probability value is calculated using the max-log-MAP criterion, that is,

[0085] ;

[0086] For the maximum a posteriori probability calculation of the i-th bit, first find all the Vector , and the corresponding vector , due to the symmetry of Hadamard coding, such a vector A total of Then the inner product values ​​corresponding to these vectors are Arranged accordingly, they constitute the positive group of the i-th bit .

[0087] ;

[0088] At this time, due to the symmetry of Hadamard coding, The negative grouping of the vector and the corresponding inner product value , each of its values ​​is exactly the opposite of the positive group, so the maximum value of the negative group corresponds to the minimum value of the positive group.

[0089] In summary, calculating the maximum a posteriori probability of the i-th bit can be transformed into:

[0090] ;

[0091] At this time, only the To find the maximum and minimum values, we need to compare them pairwise at r levels. Here we take the Hadamard example with a length of 16 codes and r=4, as shown in the following example: Figure 3 As shown, the Hadamard code with a length of 16 and r=4 requires 22 comparisons to complete the maximum a posteriori probability calculation of one bit.

[0092] because middle , that is, in each bit positive group, The sign of The symbol of , due to the symmetry of the Hadamard matrix, so for the i-th row Number , any k-th row Number , so that the two rows have The numbers have the same sign, and The numbers have opposite signs.

[0093] Therefore, the maximum posterior probability of the i-th bit and the k-th bit can be calculated as a pair, that is, by interleaving and rearranging and , get the interleaved data:

[0094] ;

[0095] in, Indicates that all The set of inner product values ​​of the Hadamard matrix column vector with line +1 and the LLR value, Represents the set of inner product values ​​of all Hadamard matrix column vectors with +1 in the kth row and LLR values, Represents the inner product value after interleaving.

[0096] Taking the 16-code Hadamard example with r=4, The result is obtained after 22 comparisons in the normal way, and The comparison method is as follows Figure 4 shown.

[0097] As shown in the figure, The comparisons with the same results are marked in green, and the opposite comparisons are marked in red. Therefore, to obtain and , just record In the fourth level comparison, the first three-level comparison result of the upper half and the second three-level comparison result of the lower half are reversed and compared to obtain Similarly, compare the first three-level comparison result of the lower half with the second three-level comparison result of the upper half after flipping, and we get .

[0098] In summary, obtaining the maximum a posteriori probability values ​​for the i-th bit and the k-th bit requires only 22 + 2 = 24 comparisons. In the Hadamard example with a 16-code length of r = 4, a total of 72 comparisons are required to calculate the a posteriori probability of the information bit and the last bit, a total of 6 bits. Compared with 96 comparisons in the existing technology, this improves resource utilization efficiency by 33%. This improvement will be further increased as the code length increases.

[0099] Experiments show that in a 16-code Hadamard example with r=4, the present invention reduces resource overhead by 33% compared to the prior art, which is of great significance for high-speed parallel processors.

[0100] The following describes an apparatus embodiment of the present application, which can be used to perform an efficient Hadamard decoding method suitable for high-speed parallel processing in the above-mentioned embodiments of the present application. For details not disclosed in the apparatus embodiment of the present application, please refer to the above-mentioned method embodiment of the present application.

[0101] Reference Figure 5 As shown, according to one embodiment of the present application, an efficient Hadamard decoding device 500 suitable for high-speed parallel processing includes:

[0102] The first calculation unit 501 is configured to calculate the inner product of all Hadamard codewords and channel input LLR values ​​using an FHT algorithm;

[0103] Classification unit 502, used to classify the The numbers have the same sign, The bits corresponding to the two rows with opposite number signs are paired in pairs to obtain multiple bit groups, wherein the bit groups include the first bit and the second bit. represents the order of the Hadamard matrix;

[0104] a processing unit 503, configured to perform internal interleaving processing on each bit group;

[0105] The second calculation unit 504 is configured to calculate the maximum a posteriori probability value of the first bit and the second bit in each bit group according to the interleaving condition and the inner product to complete decoding.

[0106] like Figure 6 As shown, an embodiment of the present application also provides an electronic device 600, including a memory 610, a processor 620, and a computer program 611 stored on the memory 610 and executable on the processor. When the processor 620 executes the computer program 611, the steps of the above-mentioned efficient Hadamard decoding method suitable for high-speed parallel processing are implemented.

[0107] Since the electronic device introduced in this embodiment is a device used to implement an efficient Hadamard decoding device suitable for high-speed parallel processing in the embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application will not be introduced in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application falls within the scope of protection to be protected by this application.

[0108] During the specific implementation process, when the computer program 611 is executed by the processor, any implementation method of the embodiments corresponding to the first aspect can be implemented.

[0109] Figure 7 A schematic diagram of the structure of a computer system suitable for implementing an electronic device according to an embodiment of the present application is shown.

[0110] It should be noted that Figure 7 The computer system 700 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0111] like Figure 7As shown, computer system 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes, such as the methods described in the above embodiments, based on programs stored in read-only memory (ROM) 702 or programs loaded from storage 708 into random access memory (RAM) 703. RAM 703 also stores various programs and data required for system operation. CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to bus 704.

[0112] The following components are connected to the I / O interface 705: an input section 706 including a keyboard, mouse, and the like; an output section 707 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and speakers; a storage section 708 including devices such as a hard disk; and a communication section 709 including a network interface card such as a LAN (Local Area Network) card or a modem. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 710 as needed, so that computer programs read from the media can be installed in the storage section 708 as needed.

[0113] In particular, according to embodiments of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for executing the methods illustrated in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via the communication section 709 and / or installed from removable media 711. When executed by the central processing unit (CPU) 701, the computer program performs the various functions defined in the system of the present application.

[0114] It should be noted that the computer-readable medium described in the embodiments of this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal transmitted in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0115] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. Among them, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, and the above-mentioned module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0116] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. In some cases, the names of these units do not constitute limitations on the units themselves.

[0117] As another aspect, the present application further provides a computer program product or computer program, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform an efficient Hadamard decoding method suitable for high-speed parallel processing as described in the above embodiment.

[0118] As another aspect, the present application further provides a computer-readable medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not be incorporated into the electronic device. The computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device implements the efficient Hadamard decoding method suitable for high-speed parallel processing described in the above embodiments.

[0119] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiment of the application, the features and functions of two or more modules or units described above can be concretized in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0120] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiments of the present application.

[0121] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in this application. It should be understood that this application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of this application is limited only by the appended claims.

Claims

1. An efficient Hadamard decoding method suitable for high-speed parallel processing, characterized in that: include: Calculate the inner product of all Hadamard codewords and channel input LLR values ​​through the FHT algorithm; According to the symmetric property of the Hadamard matrix, the bits to be decoded are grouped in pairs to obtain a plurality of bit groups, wherein the bit groups include a first bit and a second bit; Perform internal interleaving on each bit group, and calculate the maximum a posteriori probability value of the first bit and the second bit in each bit group based on the interleaving situation and the inner product to complete the decoding; The internal interleaving process for each bit group includes: Interleaving the first bit and the second bit in each bit group with each other; The calculating the maximum a posteriori probability value of the first bit and the second bit in each bit group according to the interleaving situation includes: For any group of bits after internal interleaving, first perform the inner product The maximum posterior probability value of the first bit in the bit group is calculated by level comparison; then the The first comparison result is flipped before the second The maximum posterior probability value of the second bit is obtained by level comparison calculation, where represents the order of the Hadamard matrix, is a positive integer greater than or equal to 1.

2. The method according to claim 1, characterized in that The inner product is calculated as follows: ；（1） in, represents the inner product, Indicates the first List, Indicates the channel input LLR value, Represents the order of the Hadamard matrix.

3. The method according to claim 1, characterized in that According to the symmetric property of the Hadamard matrix, the bits to be decoded are grouped in pairs to obtain multiple bit groups, including: The Hadamard matrix exists The numbers have the same sign, The bits corresponding to the two rows with opposite numbers are paired up to obtain multiple bit groups, where: Represents the order of the Hadamard matrix.

4. The method according to claim 1, wherein The maximum a posteriori probability of the first bit is calculated as follows: ；（2） in, represents the coded information bits, Indicates the channel input LLR value, Indicates the number of bits.

5. An efficient Hadamard decoding device suitable for high-speed parallel processing, applied to the method according to any one of claims 1 to 4, characterized in that: include: A first calculation unit is used to calculate the inner product of all Hadamard code words and channel input LLR values ​​through an FHT algorithm; Classification unit, used to convert the Hadamard matrix into The numbers have the same sign, The bits corresponding to the two rows with opposite number signs are paired in pairs to obtain multiple bit groups, wherein the bit groups include the first bit and the second bit. represents the order of the Hadamard matrix; a processing unit, configured to perform internal interleaving processing on each bit group; The second calculation unit is used to calculate the maximum a posteriori probability value of the first bit and the second bit in each bit group according to the interleaving situation and the inner product to complete decoding.

6. A computer-readable storage medium, characterized in that The storage medium stores computer instructions, which, when executed on a computer, enable the computer to execute the method according to any one of claims 1 to 4.

7. An electronic device, characterized in that: include: memory and processor; The memory is used to store computer instructions; The processor is configured to call the computer instructions stored in the memory so that the electronic device executes the method according to any one of claims 1 to 4.

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