Circuit board and semiconductor package having same

Abstract

A circuit board according to an embodiment includes a build-up structure including a plurality of insulating layers stacked in a vertical direction; the protection layer is arranged on the lamination structure; and a plurality of insulating members disposed on the protective layer and spaced apart from each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10 - 2024 - 0000322, filed on January 2, 2024, the entire contents of which are incorporated herein by reference. Technical field

[0003] Embodiments relate to a circuit board, and more particularly, to a circuit board having improved electrical reliability and a semiconductor package including the circuit board. Background art

[0004] As the performance of electrical / electronic products has advanced, technologies for arranging a larger number of semiconductor devices on a semiconductor package substrate of a limited size have been proposed and studied. However, since general semiconductor packages are based on mounting a single semiconductor device, there are limitations in obtaining desired performance.

[0005] Therefore, recently, a semiconductor package has been provided in which multiple substrates are used to arrange multiple semiconductor devices. Such a semiconductor package has a structure in which multiple semiconductor devices are connected to each other on the substrate in horizontal and / or vertical directions. Accordingly, the semiconductor package has the advantages of effectively using the mounting area of semiconductor devices and being able to perform high - speed signal transmission through short signal transmission paths between semiconductor devices.

[0006] In addition, according to the trend of high integration, semiconductor packages applied to products providing the Internet of Things (IoT), autonomous driving vehicles, and high - performance servers are increasing in terms of the number and / or size of semiconductor devices. In addition, as the functional parts of semiconductor devices are divided, the concept of semiconductor packages is expanding to semiconductor dice.

[0007] Meanwhile, the number and / or type of semiconductor devices and / or semiconductor dice mounted on a circuit board are being diversified, and thus, semiconductor devices and / or semiconductor dice are mounted on the circuit board in various ways. For example, semiconductor devices having relatively fine electrodes can be mounted on a circuit board using connection members such as microspheres, and semiconductor devices having relatively large electrodes can be mounted on a circuit board using connection members such as solder paste.

[0008] At this time, when installing a semiconductor device using a connection member such as solder paste, a reflow process may be performed after applying the solder paste to pads provided on a circuit board. At this time, the solder paste is provided with a flux, and the above-mentioned flux may flow around the pads during the reflow process. The above-mentioned flux flow may contaminate the surface of the circuit board or cause an electrical short problem of pads that are electrically connected to each other and arranged adjacent to each other. Therefore, a de-fluxing process for removing the above-mentioned flux is performed after the reflow process.

[0009] At this time, the thickness of recent semiconductor packages is decreasing. As a result, the distance in the vertical direction between pads provided on a circuit board and terminals of a semiconductor device may also decrease. If the distance in the above-mentioned vertical direction decreases, the solution of the de-fluxing process may not sufficiently penetrate into the space between the circuit board and the semiconductor device, which may cause electrical and / or mechanical reliability problems because the flux is not completely removed.

[0010] At this time, the above-mentioned problem can be solved by increasing the vertical distance between the pads and the terminals of the semiconductor device to allow the solution of the de-fluxing process to sufficiently penetrate. However, semiconductor devices using microspheres can be installed on a circuit board together with semiconductor devices using the above-mentioned solder paste. In addition, when increasing the distance in the vertical direction between the pads and the terminals of the semiconductor device to improve the permeability of the above-mentioned de-fluxing solution, the size of the microspheres (for example, the width in the horizontal direction and the thickness in the vertical direction) may increase. Therefore, the pitch of the pads provided on the circuit board may also increase. In this case, due to the increase in the area of the circuit board, it may be difficult to miniaturize the semiconductor package, or it may be difficult to place all the pads connected to the electrodes of the semiconductor device in a limited space.

[0011] Therefore, a method is needed that can achieve a fine pitch of pads provided on a circuit board and increase the distance in the vertical direction between the pads and the semiconductor device to a certain level or greater when setting a coupling member such as solder paste. Summary of the Invention

[0012] Technical Problem

[0013] Embodiments provide a circuit board having a new structure and a semiconductor package including the circuit board.

[0014] In addition, embodiments provide a circuit board and a semiconductor package including the circuit board that can ensure a space for the penetration of a de-fluxing solution.

[0015] In addition, embodiments provide a circuit board and a semiconductor package including the circuit board that can prevent the residue of flux escaping from an adhesive member.

[0016] In addition, an embodiment provides a circuit board and a semiconductor package including the circuit board, and the circuit board can increase the distance from a semiconductor device in a vertical direction while achieving a fine pitch of pads.

[0017] Furthermore, an embodiment provides a circuit board and a semiconductor package including the circuit board, and the circuit board has a structure that can improve the injection characteristics of a molding member.

[0018] The technical problems to be solved by the proposed embodiments are not limited to the above technical problems, and those skilled in the art of the embodiments proposed below can clearly understand other technical problems not mentioned.

[0019] Technical Solutions

[0020] A circuit board according to an embodiment includes a build-up structure including a plurality of insulating layers stacked in a vertical direction; a protective layer provided on the build-up structure; and a plurality of insulating members provided on the protective layer and spaced apart from each other.

[0021] In addition, the material of the plurality of insulating members is the same as the material of the protective layer.

[0022] In addition, the thickness of each of the plurality of insulating members in the vertical direction is greater than the thickness of the protective layer in the vertical direction.

[0023] In addition, the thickness of each of the plurality of insulating members in the vertical direction is between 1.2 times and 5 times the thickness of the protective layer in the vertical direction.

[0024] In addition, the build-up structure includes a pad portion provided on its upper surface, and the plurality of insulating members are spaced apart from each other in a peripheral region of the pad portion on the protective layer.

[0025] Furthermore, the protective layer has a through hole exposing the pad portion from the protective layer, and the plurality of insulating members are spaced apart from each other in a region surrounding the through hole.

[0026] In addition, each of the plurality of insulating members is not aligned with the through hole of the protective layer in the vertical direction.

[0027] In addition, each of the plurality of insulating members is spaced apart from the through hole of the protective layer by a predetermined distance in the horizontal direction.

[0028] Furthermore, the distance is greater than the thickness of the protective layer in the vertical direction.

[0029] In addition, the distance is less than the thickness of each of the plurality of insulating members in the vertical direction.

[0030] In addition, the pad portion includes a plurality of pads, and among them, the area of the upper surface of at least one of the plurality of pads is larger than the area of the upper surface of each of the plurality of insulating members.

[0031] Meanwhile, a semiconductor package according to an embodiment includes: a stacked insulating layer including a plurality of insulating layers stacked in the vertical direction; a pad portion disposed on the upper surface of the stacked insulating layer; a protective layer disposed on the stacked insulating layer and having a through hole overlapping the pad portion in the vertical direction, and a plurality of insulating members disposed on the protective layer and spaced apart from each other in the horizontal direction around the through hole.

[0032] In addition, the thickness of the plurality of insulating members is greater than the thickness of the protective layer.

[0033] Furthermore, the plurality of insulating members are integrally formed with the protective layer.

[0034] In addition, the material of the plurality of insulating members is the same as the material of the protective layer.

[0035] In addition, each of the plurality of insulating members includes an upper surface, among which the pad portion includes a plurality of pads, among which each of the plurality of pads includes an upper surface, and among which the area of the upper surface of at least one of the plurality of insulating members is smaller than the area of the upper surface of at least one of the plurality of pads.

[0036] Furthermore, the semiconductor package further includes a semiconductor device disposed on the plurality of insulating members.

[0037] In addition, the semiconductor device includes a plurality of electrodes, and among them, the plurality of electrodes include overlapping electrodes overlapping the insulating members in the vertical direction and non-overlapping electrodes not overlapping the insulating members in the vertical direction.

[0038] Furthermore, the semiconductor package further includes a conductive adhesive disposed between the semiconductor device and the pad portion, wherein the conductive adhesive overlaps the insulating members in the horizontal direction.

[0039] Furthermore, the conductive adhesive has at least a part extending between the overlapping electrodes of the semiconductor device and the insulating members.

[0040] Advantageous Effects

[0041] The circuit board according to an embodiment may include a stacked structure including a plurality of insulating layers stacked in a vertical direction, a protective layer disposed on the stacked structure, and a plurality of insulating members disposed on the protective layer and spaced apart from each other. That is, the embodiment may place the insulating members in a partial region on the protective layer and use the above insulating members to increase the distance in the vertical direction between the upper surface of the stacked structure and the lower surface of the semiconductor device. Therefore, the embodiment allows sufficient space for the flux removal solution to penetrate.

[0042] That is, the insulating members may be used to maintain a vertical spacing distance between the upper surface of the stacked structure and the lower surface of the semiconductor device at a predetermined distance. The insulating members allow the flux removal solution to easily penetrate into the space between the upper surface of the stacked structure and the lower surface of the semiconductor device, thereby preventing flux from remaining on the stacked structure. In addition, the insulating members allow a molding member (to be described later) to easily flow into the space between the upper surface of the stacked structure and the lower surface of the semiconductor device, whereby the semiconductor device can be stably molded with the molding member. Therefore, the embodiment can stably protect the semiconductor device from external substances such as moisture and can make the semiconductor device operate more stably.

[0043] In addition, the vertical thickness of the protective layer may be smaller than the vertical thickness of the insulating members, which can solve the problem of circuit board bending that occurs when the stress acting on the insulating members increases. Furthermore, the embodiment can prevent the width and thickness of the bonding member from increasing in the region using the bonding method with microspheres. In addition, the embodiment can improve circuit integration by using microspheres to refine the pitch of the pads in the bonding region. The embodiment thereby ensures sufficient space for the flux removal solution to penetrate, thus solving the problems of electrical short circuits and / or surface contamination that may occur due to residual flux.

[0044] The insulating members may be placed around the pad portions on the protective layer. For example, the insulating members may include a first insulating member to a fourth insulating member spaced apart from each other. Therefore, this ensures space for the solution to penetrate through different regions for flux removal. In addition, this can solve the problems of electrical short circuits and / or surface contamination that may occur due to residual flux.

[0045] In addition, embodiments may allow a plurality of insulating members to be disposed in regions between each of a plurality of pads, and may allow a semiconductor device to be more stably placed on a circuit board. For example, if the insulating members are only placed in specific regions, there may be a problem that the semiconductor device is mounted on the circuit board at an angle, which may reduce the electrical and / or mechanical reliability of the circuit board and the semiconductor package. Accordingly, embodiments allow the first through fourth insulating members to be disposed between each pad such that the semiconductor device disposed on the circuit board can be stably supported. Accordingly, the flatness of the semiconductor device can be improved, and the semiconductor device can be more stably mounted. Accordingly, embodiments can enable the semiconductor device to operate more stably. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1A is a perspective view schematically showing a circuit board according to an embodiment.

[0047] Figure 1B is a cross-sectional view taken along the Figure 1A A-A' direction of the circuit board according to the first embodiment.

[0048] Figure 1C is a cross-sectional view taken along the Figure 1A B-B' direction of the circuit board according to the first embodiment.

[0049] Figure 1D is a cross-sectional view taken along the Figure 1A A-A' direction of the circuit board according to the second embodiment.

[0050] Figure 2A (a) of is a perspective view showing a two-phase MLCC.

[0051] Figure 2A of (b) is a plan view showing the two-phase MLCC after being mounted on a circuit board.

[0052] Figure 2B of (a) is a perspective view showing a three-phase MLCC.

[0053] Figure 2B of (b) is a plan view showing the three-phase MLCC after being mounted on a circuit board.

[0054] Figure 3A is a top view of the region (R1) in Figure 1B before the protective layer and the insulating member are provided.

[0055] Figure 3B is a plan view of the protective layer provided with Figure 3A the through holes in.

[0056] Figure 3C is provided inFigure 3B Top view of the insulating member on the protective layer in

[0057] Figure 4A is a perspective view schematically showing a semiconductor package according to a first embodiment.

[0058] Figure 4B is mounted on Figure 3C Top view of the semiconductor device on the circuit board in

[0059] Figure 4C is a sectional view taken along the Figure 4B A-A' direction in

[0060] Figure 4D is a sectional view taken along the Figure 4B B-B' direction in

[0061] Figure 4E is a sectional view taken along the Figure 4B C-C' direction in

[0062] Figure 4F is a sectional view taken along the Figure 4B D-D' direction in

[0063] Figure 5 is a sectional view showing a semiconductor package according to a second embodiment.

[0064] Figure 6 is a sectional view showing a semiconductor package according to a third embodiment.

[0065] Figure 7 is a sectional view showing a semiconductor package according to a fourth embodiment. Detailed Description of the Invention

[0066] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0067] However, the spirit and scope of the present invention are not limited to a part of the described embodiments, and can be implemented in various other forms. Within the spirit and scope of the present invention, one or more elements of the embodiments can be selectively combined and replaced.

[0068] In addition, unless otherwise clearly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention can be interpreted as having the same meaning as commonly understood by those of ordinary skill in the art to which the present invention pertains, and terms such as those defined in a common dictionary can be interpreted as having a meaning consistent with their meaning in the context of the relevant field. Furthermore, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention.

[0069] In this specification, the singular forms may also include the plural forms unless specifically stated in a phrase, and may include at least one of all combinations that can be combined among A, B, and C when described as "at least one (or more) of A, B, and C". In addition, when describing elements of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

[0070] These terms are only used to distinguish an element from other elements, and these terms are not limited to the nature, order, or sequence of the elements. Additionally, when an element is described as "connected", "coupled", or "contacted" to another element, it may include not only when the element is directly "connected", "coupled", or "contacted" to other elements, but also when the element is "connected", "coupled", or "contacted" by another element between the element and other elements.

[0071] In addition, when described as "on (above)" or "under (below)" each element, "on (above)" or "under (below)" may include not only when two elements are directly connected to each other, but also when one or more other elements are formed or provided between the two elements. Furthermore, when expressed as "on (above)" or "under (below)", it may include not only the upper direction based on one element, but also the lower direction.

[0072] It should be understood that the terms "comprising", "including", or "having" specify the presence of the described features, integers, steps, operations, elements, components, and / or groups thereof disclosed in this specification, but do not exclude the possibility of the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0073] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention pertains. Terms defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology. Unless explicitly defined in this application, they should not be interpreted in an idealized or overly formal sense.

[0074] Hereinafter, embodiments will be described in detail with reference to the drawings. However, the same or corresponding components will be assigned the same reference numerals regardless of the reference numerals, and their repeated description will be omitted.

[0075] Before describing the embodiments, an electronic device (not shown) to which the semiconductor package of the embodiments is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet PC, a laptop computer, a netbook, a TV, a video game, a smart watch, an automobile, etc. However, the embodiments are not limited thereto, and may be any other electronic device that processes data other than these.

[0076] The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. In addition, the semiconductor package includes a circuit board, a semiconductor chip, a bonding part that electrically connects the semiconductor device and the circuit board, a resin part that fills the space between the semiconductor device and the circuit board, and a molding part that completely surrounds the semiconductor device.

[0077] The semiconductor device may include an active device and / or a passive device, and may have various functions. The active device may be a semiconductor chip in the form of an integrated circuit (IC), in which hundreds to millions of devices are integrated in one chip. The semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application specific IC (ASIC), etc., or a chipset including a specific combination of those listed so far. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc. In addition, the passive device may be a resistor, a capacitor, an inductor, etc., and is not limited to a semiconductor material, and may be, for example, a multilayer ceramic capacitor (MLCC)

[0078] The product group to which the semiconductor package of the embodiments is applied may be any one of a CSP (chip scale package), an FC-CSP (flip chip-chip scale package), an FC-BGA (flip chip ball grid array), a POP (package on package), and a SIP (system in package), but is not limited thereto.

[0079] Figure 1A is a perspective view schematically showing a circuit board according to an embodiment. Figure 1B is along the first embodiment Figure 1A A cross-sectional view of the circuit board taken along the A-A' direction. Figure 1C is along the first embodiment Figure 1ACross-sectional view taken along the B-B' direction of the circuit board. Figure 1D is a cross-sectional view taken along the A-A' direction of the circuit board according to the second embodiment Figure 1A Cross-sectional view taken along the A-A' direction of the circuit board. Figure 2A (a) of is a perspective view showing a two-phase MLCC. Figure 2A (b) of is a plan view showing the two-phase MLCC after being mounted on the circuit board. Figure 2B (a) of is a perspective view showing a three-phase MLCC. Figure 2B (b) of is a plan view showing the three-phase MLCC after being mounted on the circuit board. Figure 3A is the top view of the area (R1) in before the protective layer and the insulating member are provided Figure 1B Top view of the area (R1) in. Figure 3B is provided with Figure 3A Plan view of the protective layer with vias in. Figure 3C is provided on Figure 3B Top view of the insulating member on the protective layer in. Figure 4A is a perspective view schematically showing a semiconductor package according to the first embodiment. Figure 4B is the top view of the semiconductor device mounted on the circuit board in Figure 3C Top view of the semiconductor device mounted on the circuit board in. Figure 4C is taken along Figure 4B Cross-sectional view taken along the A-A' direction in. Figure 4D is taken along Figure 4B Cross-sectional view taken along the B-B' direction in. Figure 4E is taken along Figure 4B Cross-sectional view taken along the C-C' direction in. Figure 4F is taken along Figure 4B Cross-sectional view taken along the D-D' direction in. Figure 5 is a cross-sectional view showing a semiconductor package according to the second embodiment. Figure 6 is a cross-sectional view showing a semiconductor package according to the third embodiment. Figure 7 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0080] Hereinafter, the circuit board according to the embodiment and the semiconductor package including the circuit board will be described in detail with reference to Figures 1A to 7 Detailed description of the circuit board according to the embodiment and the semiconductor package including the circuit board.

[0081] Refer to Figure 1A and 1B and 1C, the circuit board 10 according to the first embodiment may include a stacked structure 100, protective layers 140 and 150 provided on one surface and / or the other surface of the stacked structure 100, and an insulating member 160 provided on one surface of the protective layer 140.

[0082] Here, the meaning of being provided on one surface and another surface is not only understood as a configuration in which one surface is in direct contact with another surface, but it should also be understood that different configurations exist between one surface of the stacked structure 100 and the first protective layer 140 and between another surface of the stacked structure 100 and the second protective layer 150.

[0083] The stacked structure 100 includes a stacked insulating layer 110, a wiring layer 120, and a via electrode 130.

[0084] The stacked insulating layer 110 may have a structure in which a plurality of insulating layers are stacked in a vertical direction. The stacked insulating layer 110 may include a first insulating layer 111 closest to the first protective layer 140 in the vertical direction, a second insulating layer 112 farther from the first protective layer 140 than the first insulating layer 111 in the vertical direction, a third insulating layer 113 farther from the first protective layer 140 than the second insulating layer 112 in the vertical direction, and a fourth insulating layer 114 farther from the first protective layer 140 than the third insulating layer 113 in the vertical direction. In this case, the first insulating layer 111 may refer to the uppermost insulating layer provided on the uppermost side of the stacked insulating layer 110 having a structure in which a plurality of layers are stacked, and the fourth insulating layer 114 may refer to the lowermost insulating layer provided on the lowermost side of the stacked insulating layer 110 having a structure in which a plurality of layers are stacked. However, the embodiments are not limited thereto, and the stacked insulating layer 110 may further include a fifth insulating layer (not shown) provided between the fourth insulating layer 114 and the second protective layer 150, and a sixth insulating layer (not shown) provided between the fifth insulating layer (not shown) and the second protective layer 150.

[0085] The first to fourth insulating layers 111, 112, 113, and 114 are provided to be isolated in the vertical direction between the first to fifth wiring layers 121, 122, 123, 124, and 125, which will be described later. For example, the first to fourth insulating layers 111, 112, 113, and 114 may be made of a thermosetting insulating material containing inorganic fillers in a resin or ABF (Ajinomoto Build-up Film) of Ajinomoto. However, the embodiments are not limited thereto, and a photocurable insulating material (photoimageable dielectric, PID) may be used to form a fine pattern.

[0086] At least one of the first to fourth insulating layers 111, 112, 113, and 114 may have an insulating material different from that of at least another insulating layer. Exemplarily, at least one of the first to fourth insulating layers 111, 112, 113, and 114 may include a reinforcing member 114R. In one embodiment, the reinforcing member 114R may refer to fiberglass. In another embodiment, the reinforcing member 114R may refer to GCP (glass core primer). The reinforcing member 114R may be disposed in at least one of the first to fourth insulating layers 111, 112, 113, and 114 to increase the rigidity of the circuit board 10. The reinforcing member 114R prevents the circuit board 10 from being significantly bent in a specific direction, thereby improving the positional alignment of the wiring layer 120 and the via electrode 130. In addition, this may improve the electrical and / or mechanical reliability of the circuit board 10 and the semiconductor package. Additionally, the reinforcing member 114R may increase the rigidity of the circuit board 10, thereby improving the process characteristics during the process of mounting a semiconductor device on the circuit board 10 and increasing the product yield. Therefore, the reinforcing member 114R enables a semiconductor device to be stably mounted on the circuit board 10 and allows the semiconductor device to operate stably. Thus, the operational reliability can be improved by ensuring that electronic products such as servers to which the semiconductor package is applied operate stably. As Figure 1B shown in 1C or, the reinforcing member 114R may be disposed in the fourth insulating layer 114. That is, the circuit board 10 may be manufactured with a carrier member (not shown) disposed, and the fourth insulating layer 114 may be the layer farthest from the carrier member. At this time, when the reinforcing member 114R is disposed in the fourth insulating layer 114, the circuit board 10 can be further prevented from being bent in a specific direction during the process of removing the carrier member. However, the embodiment is not limited thereto, and the reinforcing member 114R may be disposed in an insulating layer other than the fourth insulating layer 114. Exemplarily, the reinforcing members 114R may be alternately arranged in the first to fourth insulating layers 111, 112, 113, and 114 in the vertical direction, whereby the rigidity of the circuit board 10 can be further increased.

[0087] The wiring layer 120 may include a first wiring layer 121 closest to the first protective layer 140 in the vertical direction, a second wiring layer 122 farther from the first protective layer 140 than the first wiring layer 121, a third wiring layer 123 farther from the first protective layer 140 than the second wiring layer 122, a fourth wiring layer 124 farther from the first protective layer 140 than the third wiring layer 121, and a fifth wiring layer 125 farther from the first protective layer 140 than the fourth wiring layer 124. The wiring layer 120 may have, for example, an embedded trace substrate (ETS) structure to implement a fine pattern. Specifically, the wiring layer disposed on the uppermost or lowermost side among the first to fifth wiring layers 121, 122, 123, 124, and 125 may be embedded in the stacked insulating layer 110. Here, being embedded means that at least a part of the side surface of the wiring layer having the ETS structure is covered by the stacked insulating layer 110. The first wiring layer 121 may be embedded in the first insulating layer 121. The first wiring layer 121 is the wiring layer closest to the semiconductor device disposed on the circuit board 10. At this time, when the first wiring layer 121 is manufactured by the ETS method, the pads and traces constituting the first wiring layer 121 can be stably protected by the insulating layer, so that the circuit integration of the first wiring layer 121 can be miniaturized and improved. Therefore, the semiconductor device disposed on the circuit board 10 can be more easily electrically connected, and the semiconductor device can operate more stably.

[0088] According to an embodiment having an ETS structure, a recessed portion may be provided on the upper surface of the first insulating layer 111 toward the lower surface of the first stacked insulating layer 110, and the first wiring layer 121 may be provided in the recessed portion of the first insulating layer 111. In addition, the second wiring layer 122 may be provided in the recessed portion provided on the upper surface of the second insulating layer 112, the third wiring layer 123 may be provided in the recessed portion provided on the upper surface of the third insulating layer 113, the fourth wiring layer 124 may be provided in the recessed portion provided on the upper surface of the fourth insulating layer 114, and the fifth wiring layer 125 may protrude below the lower surface of the fourth insulating layer 114. Therefore, as described above, the circuit integration can be improved by miniaturizing the first to fifth wiring layers 121, 122, 123, 124, and 125. Therefore, this embodiment can protect the first to fifth wiring layers 121, 122, 123, 124, and 125 from contaminants such as external moisture and improve the reliability of the semiconductor package.

[0089] The first to fifth wiring layers 121, 122, 123, 124, and 125 may include traces for respectively transmitting signals and / or power, and pads for connecting the traces of each of the first to fifth wiring layers 121, 122, 123, 124, and 125 to other components. Exemplarily, refer to Figure 1BOr 1C, the first wiring layer 121 and the second wiring layer 122 are connected to the first through electrode 131. At this time, in order to connect the trace of the first through electrode 131 and the second wiring layer 122, the second wiring layer 122 may include a pad connected to the first through electrode 131. Figure 1B and 1C Only the pads of the first wiring layer 121 are shown, but the first wiring layer 121 may further include traces connecting a plurality of pads.

[0090] The first to fifth wiring layers 121, 122, 123, 124, and 125 can be used for electrically connecting semiconductor devices provided on the circuit board 10. Each of the first to fifth wiring layers 121, 122, 123, 124, and 125 can be freely designed considering impedance.

[0091] The first wiring layer 121 may include a plurality of pads 121a, 121b, 121c, and 121d. The plurality of pads 121a, 121b, 121c, and 121d of the first wiring layer 121 may refer to electrodes connected to the terminals of semiconductor devices mounted on the circuit board 10. That is, Figure 1B and 1C A partial region R1 among the entire region of the circuit board 10 may be shown, and the first wiring layer 121 may further include additional pads connected to other semiconductor devices in regions other than the region R1. At this time, the plurality of pads 121a, 121b, 121c, and 121d may refer to the portion of the first wiring layer 121 that overlaps with the through holes 141 (to be described later) of the first protective layer 140 in the vertical direction. Therefore, at least two of the plurality of pads 121a, 121b, 121c, and 121d may represent regions that overlap with the through holes 141 (to be described later) of the first protective layer 140 in the vertical direction in an integrated pad.

[0092] In addition, through electrodes 130 may be provided in the stacked insulating layer 110 to connect each of the first to fifth wiring layers 121, 122, 123, 124, and 125. The through electrodes 130 may include first to fourth through electrodes 131, 132, 133, and 134. Exemplarily, the first through electrode 131 is provided between the first wiring layer 121 and the second wiring layer 122, the second through electrode 132 is provided between the second wiring layer 122 and the third wiring layer 123, the third through electrode 133 is provided between the third wiring layer 123 and the fourth wiring layer 124, and the fourth through electrode 134 is provided between the fourth wiring layer 124 and the fifth wiring layer 125. The first to fifth wiring layers 121, 122, 123, 124, and 125 are electrically connected to each other through the first to fourth through electrodes 131, 132, 133, and 134.

[0093] The first through fourth vias 131, 132, 133, and 134 can be formed simultaneously during the process of arranging the second through fifth wiring layers 122, 123, 124, and 125. As an example, during the process of forming the second wiring layer 122 under the first wiring layer 121, vias are formed in the first insulating layer 111 to expose a part of the first wiring layer 121. Thus, the second wiring layer 122 can be formed together with the first via 131 filling the vias in the first insulating layer 111. Therefore, the first via 131 can be divided into protrusions of the second wiring layer 122. Similarly, each of the second through fourth vias 132, 133, and 134 can be divided into protrusions of each of the third through fifth wiring layers 123, 234, and 125, and connected to another wiring layer provided above each wiring layer.

[0094] In addition, the first through fifth wiring layers 121, 122, 123, 124, and 125 are sequentially stacked on the lower surface of the first protective layer 140 in the vertical direction. Therefore, the inclination directions of each of the first through fourth vias 131, 132, 133, and 134 can be the same. Exemplarily, each of the first through fourth vias 131, 132, 133, and 134 provided in the stacked structure 100 can have an inclination that increases in width toward the second protective layer 150.

[0095] The protective layers 140 and 150 can include the first protective layer 140 provided on the upper surface of the stacked structure 100 and / or the second protective layer 150 provided on the lower surface of the stacked structure 100. The first protective layer 140 can protect the upper surface of the first wiring layer 121 and / or the first insulating layer 111 from external moisture or contaminants. In addition, when a semiconductor device is disposed on the circuit board 10 using a material such as solder, the first protective layer 140 is used to prevent a short circuit between solders due to low wettability with the solder. The first protective layer 140 can be made of a photocurable insulating material, and for example, a solder resist can be used. However, the embodiments are not limited thereto, and the first protective layer 140 can include a thermosetting insulating material as the same insulating material as the stacked insulating layer 110. The first protective layer 140 can be made of the same insulating material as the first insulating layer 111. For example, the first protective layer 140 can be provided as an Ajinomoto build-up film (ABF).

[0096] The first protective layer 140 may have a through hole 141. The through hole 141 may pass through the first protective layer 140 from the upper surface of the first protective layer 140 toward the lower surface of the first protective layer 140. For example, the first protective layer 140 may include a through hole 141 that exposes at least a part of the upper surface of the stacked structure 100. The stacked structure 100 may provide a space in which at least one semiconductor device is placed, and the first protective layer 140 may include a through hole 141 that overlaps the above space of the stacked structure 100 in the vertical direction. For example, the protective layer 140 may include a through hole 141 that overlaps the plurality of pads 121a, 121b, 121c, and 121d of the first wiring layer 121 in the vertical direction.

[0097] The insulating member 160 may be locally disposed on the first protective layer 140, and the first protective layer 140 is disposed on one surface of the stacked structure 100. For example, the insulating member 160 may be an insulating patch disposed on the first protective layer 140, and a plurality of insulating members 160 may be disposed on the first protective layer 140 and spaced apart from each other. The insulating member 160 may be disposed around the through hole 141 of the first protective layer 140. The insulating member 160 may not overlap or be misaligned with the through hole 141 of the first protective layer 140 in the vertical direction. The insulating member 160 may be disposed at a position spaced apart from the inner wall of the through hole 141 forming the first protective layer 140 in the horizontal direction toward the outer surface of the stacked structure 100. For example, the plurality of insulating members 160 are spaced apart from each other in the peripheral region of the pad portion 501 on the first protective layer 140.

[0098] The structure of the above-described circuit board 10 is merely an example for explaining the present invention, and the technical concept of the present invention is not limited to the stacked structure of the embodiments.

[0099] For example, according to Figure 1B and 1C the embodiment of, the circuit board may be a coreless board without a core layer. For example, the circuit board of the first embodiment may be a circuit board manufactured by the ETS (Embedded Trace Substrate) method. Therefore, the first to fourth insulating layers 111, 112, 113, and 114 may have a structure in which they are stacked in the vertical direction from top to bottom in sequence.

[0100] Alternatively, according to Figure 1D the embodiment of, the circuit board may be a core board including a core layer. For example, the circuit board of the second embodiment may be a circuit board manufactured by the SAP method or the MSAP method. In this case, as Figure 1C shown in, the circuit board may include a core layer 110a, a first stacked layer UB disposed on one surface of the core layer 110a, and a second stacked layer LB disposed on the other surface of the core layer 110a.

[0101] The core layer 110a is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing member 110aR such as glass fiber, and is used to improve the rigidity of the circuit board. As the number of terminals of semiconductor devices provided on recent circuit boards increases, the wiring becomes more complex. Therefore, the thicknesses of the first laminated insulating layer 110b and the second laminated insulating layer 110c tend to increase. Thus, the core layer 110a of this embodiment can have a thickness of 120 μm to 1200 μm to improve the overall rigidity of the circuit board and prevent excessive signal loss. A via can be formed through one side and the other side of the core layer 110a. The via in the core layer 110a can be formed using a mechanical drilling process or a CO2 laser. When a via is formed in the core layer 110a using mechanical drilling, the inclined surface of the inner wall of the via can be perpendicular to one surface and / or the other surface of the core layer 110a. Additionally, when a via is formed in the core layer 110a using a CO2 laser, the inner wall of the via can have a plurality of recesses and / or protrusions alternately stacked in the vertical direction. Here, the recess can refer to a region recessed in a direction away from the horizontal center of the via provided in the core layer 110a, and the protrusion can refer to a region protruding and / or bulging toward the horizontal center of the via provided in the core layer 110a. Additionally, the recesses and protrusions can be alternately provided on the inner wall of the via forming the core layer 110a. Here, alternately provided means that the protrusions are provided between a plurality of recesses, and the recesses are provided between a plurality of protrusions. In the case of forming a via using a mechanical drilling process, the path for transmitting an electrical signal is shortened, which may be advantageous for electrical characteristics, but the process cost may increase. Additionally, when recesses and protrusions are formed on the inner wall of the via using a CO2 laser, the thickness of the core via electrode 130-1 provided on the inner wall of the via can be increased in a subsequent process, which has the advantages of reducing impedance and reducing process cost. Therefore, according to the application field of the semiconductor package, the processing method of the via provided in the core layer 110a can be freely and selectively used.

[0102] The core via click 130-1 can be disposed within the via of the core layer 110a. The core via electrode 130-1 is used to electrically connect the first build-up layer UB and the second build-up layer LB. Therefore, preferably, the core via electrode 130-1 densely fills the via to achieve functions such as resistance or heat dissipation. However, as described above, when the thickness of the core layer 110a becomes thick, it may be difficult for the core via electrode 130-1 to densely fill the via. For example, if the via provided in the thick core layer 110a is to be filled by the plating process as described above, voids may occur inside the core via electrode 130-1. The voids expand due to the heat generated during the operation of the semiconductor package, which reduces the mechanical reliability of the circuit board. Therefore, the core via electrode 130-1 having a predetermined thickness is disposed on the inner wall of the via of the core layer 110a. The thickness of the core via electrode 130-1 does not mean the thickness in the vertical direction, which is the direction in which the first build-up layer UB, the core layer 110a, and the second build-up layer LB are stacked. That is, the thickness of the core via electrode 130-1 means the thickness in the horizontal direction perpendicular to the vertical direction. The thickness of the core via electrode 130-1 can be arranged to have a thickness of 5 μm to 20 μm to prevent voltage drop that occurs as the thickness of the core layer 110a increases and to prevent the generation of voids. It is difficult to densely fill the inside of the core via electrode 130-1 with metal by a process such as plating, resulting in empty spaces. The empty spaces may be a problem that makes it difficult to uniformly place the first build-up layer UB when stacking the first build-up layer UB.

[0103] Therefore, the filling member 110aF can be disposed inside the core via electrode 130-1, thereby ensuring the flatness of the core layer 110a. As an example, the filling member 110aF can be disposed in the via of the core layer 110a, the core via electrode 130-1 surrounds the side surface of the filling member 110aF, and can be disposed between the inner wall of the via and the outer surface of the filling member 110aF.

[0104] The upper surface of the filling member 110aF can be in the same plane as the upper surface of the core layer 110a, or can be disposed to be closer to the first build-up layer UB than the upper surface of the core layer 110a in the vertical direction. The lower surface of the filling member 110aF can be in the same plane as the lower surface of the core layer 110a, or can be disposed to be closer to the second build-up layer LB than the lower surface of the core layer 110a in the vertical direction. This can be freely designed to solve the flatness when stacking the first build-up layer UB and the second build-up layer LB.

[0105] The first stacked layer UB is disposed on one surface of the core layer 110a. The first stacked layer UB includes a plurality of insulating layers 110b, a plurality of circuit layers 120-1, a plurality of through electrodes 130-2, a first protective layer 140a, and an insulating member 160a. The second stacked layer LB is disposed on the other surface of the core layer 110a. The second stacked layer LB includes a plurality of insulating layers 110c, a plurality of circuit layers 120-2, a plurality of through electrodes 130-3, and a second protective layer 150a. The circuit layers 120-1 and 120-2, the through electrodes 130-2 and 130-3, the insulating member 160a, and the protective layers 140a and 150a in each of the insulating layers 110b of the first stacked layer UB and the insulating layers 110c of the second stacked layer LB can correspond to the stacked insulating layer 110, the wiring layer 120, the through electrode 130, and the protective layers 140 and 150 described in the first embodiment, and their detailed descriptions are omitted. Hereinafter, based on Figure 1B and 1C The detailed structure of the present application will be described with reference to the coreless substrate shown.

[0106] The circuit board 10 can provide a space for mounting semiconductor devices. At this time, the type of semiconductor device mounted on the circuit board 10 can vary, and the method of mounting the semiconductor device on the circuit board 10 can also vary according to the type of semiconductor device. For example, in the case of a semiconductor device having relatively large terminals or low-density terminals, a bonding method using an adhesive member such as general solder paste can be used.

[0107] The bonding method using solder paste can include the process of applying an adhesive member (such as solder paste having a flux inside) on the pads 121a, 121b, 121c, and 121d, and a reflow process of placing the semiconductor device on the adhesive member. At this time, when the reflow process is performed, the flux provided in the adhesive member can flow, and the flowing flux may contact other adjacent pads and cause an electrical short circuit problem. Contact with the upper surface of the stacked insulating layer may cause contamination of the circuit board surface. Therefore, after performing the reflow process, a defluxing process can be performed to remove the above-mentioned flux. The defluxing process can be performed by removing the above-mentioned flux by infiltrating a solution for defluxing into the space between the circuit board and the semiconductor device. At this time, in the defluxing process, the flux can be completely removed or can remain on the stacked structure 100, depending on whether there is sufficient space for the above-mentioned solution to infiltrate.

[0108] At this time, the size of the space into which the solution for the defluxing process can infiltrate can be determined by the horizontal distance between the terminals provided in the semiconductor device and the vertical distance between the semiconductor device and the stacked structure 100. At this time, the vertical distance between the semiconductor device and the stacked structure 100 can be determined by the vertical thickness of the first protective layer 140 provided on the stacked structure 100.

[0109] However, as the circuit board and / or semiconductor package become lighter, thinner, and shorter, correspondingly, the vertical thickness of the first protective layer 140 tends to become thinner. Therefore, there are limitations to increasing the vertical distance between the semiconductor device and the stacked structure 100. In addition, semiconductor devices using bonding methods other than solder paste can be mounted on the circuit board. For example, in the case where the terminal density of the semiconductor device is relatively high, thermocompression bonding (TC bonding) can be used to reduce the amount of solder used, or a bonding method using an adhesive member internally equipped with conductive balls can be used. At this time, when using the TC bonding method or the bonding method using an adhesive member equipped with conductive balls, the horizontal width and vertical thickness of the adhesive member increase as the vertical thickness of the first protective layer 140 increases. Therefore, the pitch between the pads 121a, 121b, 121c, and 121d can be increased. At this time, recently, the functions provided by semiconductor devices have increased, and as the performance of semiconductor devices improves, the number of I / O terminals provided in the semiconductor device has also increased. Therefore, the width and / or pitch of the I / O terminals provided in the semiconductor device become smaller. When the size of the adhesive member increases as the vertical thickness of the first protective layer 140 increases, during the process of connecting the I / O terminals of the semiconductor device, an electrical short circuit may occur when multiple coupling members come into contact with each other. For this reason, due to the limitation of the vertical thickness of the first protective layer 140, there are limitations to increasing the vertical distance between the semiconductor device and the stacked structure 100.

[0110] In addition, the horizontal distance between the terminals provided in the semiconductor device can be determined by the number and / or density of the terminals provided in the semiconductor device. At this time, the number of terminals provided in the semiconductor device can vary according to the type of semiconductor device. At this time, the horizontal distance between adjacent terminals can decrease as the number of terminals provided in the semiconductor device increases, which may make it difficult to ensure sufficient space for the solution for the desoldering process to penetrate.

[0111] Recently, there has been a trend to place capacitors adjacent to semiconductor devices to improve the power drop characteristics when transmitting power to the semiconductor devices. At this time, when the capacitor is set as a discrete device such as a chip, there is a problem of increased inductance. For example, if the capacitor is an MLCC, in order to reduce the equivalent inductance, the two-terminal capacitor can be increased to a four-terminal capacitor, which can reduce the inductance and improve the power transmission characteristics delivered to the semiconductor chip.

[0112] Reference Figure 2A , existing MLCCs can be equipped with two terminals. Figure 2A The (a) of is a perspective view showing a two-phase MLCC, Figure 2AFigure (b) is a plan view after a two-phase MLCC is mounted on a circuit board. The MLCC includes a device body 200, a first terminal 210 provided on a first surface of the device body 200, and a second terminal 220 provided on a second surface of the device body 200 opposite to the first surface. In this case, since the MLCC can have only two terminals 210 and 220, the horizontal distance between the two terminals 210 and 220 can be greater than the distance when the MLCC has a larger number of terminals. Therefore, when the MLCC is mounted on the circuit board 10, since sufficient space for solution penetration can be ensured corresponding to the horizontal distance between the two terminals 210 and 220, the flux can be completely removed.

[0113] Reference Figure 2B , the MLCC can be equipped with four terminals. Figure 2B Figure (a) is a perspective view showing a three-phase MLCC, Figure 2B Figure (b) is a plan view after a three-phase MLCC is mounted on a circuit board. The MLCC includes a device body 230, a first terminal 240 provided on a first surface of the device body 230, a second terminal 250 provided on a second surface of the device body 230 opposite to the first surface, a third terminal 260 provided on a third surface between the first surface and the second surface of the device body 230, and a fourth terminal 270 can be provided on a fourth surface of the device body 230 opposite to the third surface. In this case, the MLCC has four terminals 240, 250, 260, and 270. Therefore, the horizontal distance between the four terminals 240, 250, 260, and 270 can be smaller than the horizontal distance in the case of only two terminals 210 and 220. Therefore, when the MLCC is mounted on the circuit board 10, since the horizontal distance between the four terminals 240, 250, 260, and 270 is relatively small, it may be difficult to ensure sufficient space for solution penetration. As a result, the flux is not completely removed, which may cause an electrical short circuit problem or contamination of the circuit board surface, or cause voids during subsequent processes (such as underfill or molding). This may reduce the reliability of the semiconductor package.

[0114] For this purpose, the embodiment allows an insulating member 160 to be placed in a local area on the first protective layer 140, and allows the use of the above-mentioned insulating member 160 to increase the vertical distance between the upper surface of the stacked structure 100 and the lower surface of the semiconductor device. Thereby, the embodiment ensures sufficient space for the solution used for flux removal to penetrate.

[0115] That is, the insulating member 160 can be used to ensure that the vertical spacing distance between the upper surface of the stacked structure 100 and the lower surface of the semiconductor device is a predetermined distance or more. The insulating member 160 allows the de-soldering solution to easily penetrate into the space between the upper surface of the stacked structure 100 and the lower surface of the semiconductor device, thereby preventing solder from remaining on the stacked structure 100. In addition, the insulating member 160 can be used to allow the molding member, which will be described later, to easily flow into the space between the upper surface of the stacked structure 100 and the lower surface of the semiconductor device. For ease of explanation, the insulating member 160 is separated into a layer different from the first protective layer 140 in Figures 1A to 7 and the insulating member 160 is not limited thereto and may refer to the protrusions of the first protective layer 140. For example, the first protective layer 140 and the insulating member 160 may be integrally formed. Thus, the insulating member 160 may be protrusions arranged to be spaced apart from each other in the horizontal direction on the upper surface of the first protective layer 140. As another example, the first protective layer 140 and the insulating member 160 may be separate layers. At this time, the first protective layer 140 and the insulating member 160 may be made of the same insulating material, and for example, a solder resist may be used.

[0116] At this time, the vertical thickness H1 of the first protective layer 140 may be different from the vertical thickness H2 of the insulating member 160. Preferably, the vertical thickness H1 of the first protective layer 140 may be less than the vertical thickness H2 of the insulating member 160.

[0117] If the vertical thickness H1 of the first protective layer 140 is greater than the vertical thickness H2 of the insulating member 160, the stress caused by the thermal cycle generated by the first protective layer 140 may increase, which may cause the circuit board to bend significantly in a specific direction. In addition, if the vertical thickness H1 of the first protective layer 140 is greater than the vertical thickness H2 of the insulating member 160, the width and thickness of the bonding member may increase in the region where the bonding method using microspheres described above is used, which may make it difficult to refine the pitch of the pads. In addition, when the thickness H2 of the insulating member 160 is less than the thickness H1 of the first protective layer 140, it may be difficult to ensure sufficient space for the solution for de-soldering to penetrate, which may cause an electrical short circuit problem and / or a surface contamination problem due to residual solder.

[0118] For example, the vertical thickness H2 of the insulating member 160 may be in the range of 1.2 to 5 times the vertical thickness H1 of the first protective layer 140. If the vertical thickness H2 of the insulating member 160 is less than 1.2 times the vertical thickness H1 of the first protective layer 140, the effects achieved by arranging the insulating member 160 may be minimal, and electrical short - circuit problems and / or surface contamination problems may occur due to residual flux. If the vertical thickness H2 of the insulating member 160 is greater than 5 times the vertical thickness H1 of the first protective layer 140, the vertical distance between the stacked structure and the semiconductor device may increase excessively, and the volume of the adhesive member used to mount the semiconductor device may increase. As a result, due to the increase in the volume of the adhesive member, cracks may occur in the adhesive member even under a small impact, leading to electrical reliability problems between the semiconductor device and the stacked structure, or electrical short - circuit problems may occur, where multiple adjacent adhesive members come into contact with each other due to the spread of the adhesive member in the horizontal direction.

[0119] In addition, the area of the upper surface of the insulating member 160 may be different from the area of the upper surfaces of the pads 121a, 121b, 121c, and 121d. For example, a plurality of insulating members 160 are provided, and the area of the upper surface of each of the plurality of insulating members 160 may be smaller than the area of the upper surfaces of the pads 121a, 121b, 121c, and 121d. Thus, the embodiment can minimize the area where the insulating member 160 is placed, minimize the transfer of stress acting on the insulating member 160 due to thermal cycling to the pads 121a, 121b, 121c, and 121d, and minimize the occurrence of cracks in the coupling members provided on the pads 121a, 121b, 121c, and 121d.

[0120] That is, when a semiconductor device is mounted on a circuit board using solder, the first protective layer 140 is arranged to have a predetermined thickness to have a predetermined pitch. In addition, in order to facilitate the penetration of the solution for de - fluxing when mounting an MLCC, the insulating member 160 may be placed thicker than the first protective layer 140 to improve the Z - height.

[0121] In addition, as described above, for ease of explanation, the insulating member 160 and the first protective layer 140 are described as different layers. However, the embodiments are not limited thereto, and the insulating member 160 may be a protrusion from which the first protective layer 140 protrudes. That is, the insulating member 160 may be made of the same material as the first protective layer 140 to reduce the difference in the coefficient of thermal expansion from the first protective layer 140, and may be made of a material different from the first protective layer 140 to facilitate improving the above-described Z height. Specifically, the first protective layer 140 shown in the present specification may be made of a solder resist material, and the insulating member 160 may also be made of a solder resist material. In addition, the first protective layer 140 is made of a solder resist material, and the insulating member 160 may be a thermosetting insulating material containing inorganic fillers in a resin, and for example, ABF (Ajinomoto Build-up Film) of Ajinomoto may be used. However, the embodiments are not limited thereto, and a photo-curable insulating material (photo-imageable dielectric, PID) may be used to form a fine pattern. Preferably, in order to reduce the difference in the coefficient of thermal expansion between the first protective layer 140 and the insulating member 160, the first protective layer 140 and the insulating member 160 are preferably made of the same material, and for example, may be made of a solder resist. However, the insulating member 160 may be made of a material different from the first protective layer 140 to more stably ensure the Z height.

[0122] Hereinafter, the arrangement structures of the pads 121a, 121b, 121c, and 121d, the first protective layer 140, and the insulating member 160 of the stacked structure 100 of the embodiments will be described in more detail. At this time, the circuit board of the embodiments may provide a space for mounting a semiconductor device, and for example, may provide a space for mounting a three-phase MLCC having four terminals. Hereinafter, the arrangement structures of the pads 121a, 121b, 121c, and 121d, the first protective layer 140, and the insulating member 160 of the stacked structure 100 in the space for mounting the three-phase MLCC will be described. However, the embodiments are not limited thereto, and the structures of the pads 121a, 121b, 121c, 121d, the first protective layer 140, and the insulating member 160 of the stacked structure 100 described later may also be implemented in a space provided with passive devices and / or active devices other than MLCCs.

[0123] Refer to Figure 3A , a wiring layer 320 may be provided on the upper surface of the stacked insulating layer 310. The wiring layer 320 may represent a wiring layer among the wiring layers provided on the upper surface of the stacked insulating layer 310 that serves as a pad for connecting to a terminal of a semiconductor device.

[0124] The wiring layer 320 may include a first wiring pattern 321, a second wiring pattern 322, and a third wiring pattern 323. The second wiring pattern 322 and the third wiring pattern 323 may be arranged to be spaced apart from each other in a first horizontal direction on the upper surface of the stacked insulating layer 310. Additionally, the first wiring pattern 321 may be disposed to surround the second wiring pattern 322 and the third wiring pattern 323 at a position spaced apart from the second wiring pattern 322 and the third wiring pattern 323.

[0125] Reference Figure 3B , a protective layer 330 may be disposed on the stacked insulating layer 310. The protective layer 330 may have a through hole 331 that penetrates from the upper surface of the protective layer 330 to the lower surface of the protective layer 330. At least a part of the through hole 331 may overlap with the upper surface of the wiring layer 320 in the vertical direction, and another part may overlap with the upper surface of the stacked insulating layer 310 in the vertical direction in an area where the wiring layer 320 is not provided. Additionally, each of the first wiring pattern 321, the second wiring pattern 322, and the third wiring pattern 323 may be provided with pads that overlap with the through hole 331 of the protective layer 330 in the vertical direction.

[0126] For example, the first wiring pattern 321 may overlap with the through hole 331 at different positions in the vertical direction. For example, the first wiring pattern 321 may include a first pad 321-1 that overlaps with the through hole 331 in the vertical direction on a first side of the through hole 331. Additionally, the first wiring pattern 321 may include a second pad 321-2 that overlaps with the through hole 331 in the vertical direction on a second side of the through hole 331. The first pad 321-1 and the second pad 321-2 are parts of the first wiring pattern 321, and thus, the first pad 321-1 and the second pad 321-2 may be connected to each other.

[0127] Additionally, the second wiring pattern 322 may include a third pad 322-1 that overlaps with the through hole 331 in a direction perpendicular to the through hole 331 on a third side of the through hole 331. Additionally, the third wiring pattern 323 may include a fourth pad 323-1 that overlaps with the through hole 331 in the vertical direction on a fourth side of the through hole 331.

[0128] That is, a part of the through hole 331 of the protective layer 330 may overlap with the wiring layer 320 in the vertical direction, and the area of the wiring layer 320 that overlaps with the through hole 331 in the vertical direction may be used as pads 321-1, 321-2, 322-1, and 323-1 that are connected to terminals of the semiconductor device.

[0129] In addition, at least a part of the through hole 331 of the protective layer 330 may not overlap or be misaligned with the wiring layer 320 in the vertical direction. That is, at least a part of the upper surface of the stacked insulating layer 310 may overlap with the through hole of the protective layer 330 in the vertical direction, but not overlap (or be offset) with the wiring layer 320 in the vertical direction. For example, a through hole 331 provided in the protective layer 330 may expose the upper surface of the stacked insulating layer 310 provided between the pads 321-1, 321-2, 322-1, and 323-1 from the protective layer 330, and at the same time expose the pads 321-1, 321-2, 322-1, and 323-1, respectively. However, the embodiment is not limited thereto. As another example, the through holes of the protective layer 330 may include a plurality of hole portions spaced apart from each other in the horizontal direction, and each of the plurality of hole portions may overlap with each of the pads 321-1, 321-2, 322-1, and 323-1 in the vertical direction. Hereinafter, an embodiment will be described in which one through hole 331 overlaps with the pads 321-1, 321-2, 322-1, and 323-1 in the vertical direction and also overlaps with the upper surface of the stacked insulating layer 310 between the pads 321-1, 321-2, 322-1, and 323-1 in the vertical direction.

[0130] Exemplarily, the region between the first pad 321-1 and the second pad 321-2 and / or the region between the third pad 322-1 and the fourth pad 323-1 may overlap with the through hole 331 of the protective layer 330 in the vertical direction. Accordingly, the vertical distance between the circuit board and the semiconductor device in the region between the pads 321-1, 321-2, 322-1, and 323-1 may be the vertical distance between the upper surface of the stacked insulating layer 310 and the upper surface of the semiconductor device. Therefore, this embodiment can increase the vertical distance between the circuit board and the semiconductor device in the region between the pads 321-1, 321-2, 322-1, and 323-1, allow the solution for removing the solder flux to more easily penetrate into the above region, and allow the solder flux to be more completely removed. Therefore, this embodiment can solve the electrical reliability problems that may occur due to incomplete removal of the solder flux. In addition, this embodiment can solve the surface contamination problems that may occur due to residual solder flux. Therefore, this embodiment can improve the electrical reliability of the circuit board and enable the semiconductor device placed on the circuit board to be placed more stably. In addition, this embodiment can enable the semiconductor device to operate more stably, such as products of servers applying semiconductor packages can operate more stably.

[0131] Reference Figure 3C, the insulating members 341, 342, 343, and 344 can be disposed on the protective layer 330. The insulating members 341, 342, 343, and 344 can protrude a certain height on the protective layer 330. The insulating members 341, 342, 343, and 344 can be disposed in a region that vertically overlaps with the semiconductor device mounted on the circuit board. For example, the insulating members 341, 342, 343, and 344 can include a region that vertically overlaps with the semiconductor device disposed on the circuit board. The overlapping region increases the vertical distance between the semiconductor device and the pad, thereby ensuring sufficient space for the solution for desoldering to penetrate.

[0132] The insulating members 341, 342, 343, and 344 can be disposed around the pads 321-1, 321-2, 322-1, and 323-1. Exemplarily, the first insulating member 341 can be disposed between the first pad 321-1 and the third pad 322-1, the second insulating member 342 can be disposed between the first pad 321-1 and the fourth pad 323-1, the third insulating member 343 can be disposed between the second pad 321-2 and the fourth pad 323-1, and the fourth insulating member 344 can be disposed between the second pad 321-2 and the third pad 322-1. The first to fourth insulating members 341, 342, 343, and 344 are arranged at different positions and spaced apart from each other. Therefore, the solution for desoldering can easily penetrate into the space between each insulating member. In addition, the first to fourth insulating members 341, 342, 343, and 344 are disposed between each pad 321-1, 321-2, 322-1, and 323-1, so that the semiconductor device can be more stably placed on the circuit board 10. For example, if the insulating members 341, 342, 343, and 344 are only disposed in a specific region, there may be a problem that the semiconductor device is mounted on the circuit board 10 at an angle, which may deteriorate the electrical and / or mechanical reliability of the circuit board and the semiconductor package. Therefore, this embodiment allows the first to fourth insulating members 341, 342, 343, and 344 to be disposed between the respective pads 321-1, 321-2, 322-1, and 323-1. Therefore, the semiconductor device disposed on the circuit board 10 can be stably supported, and thereby, the flatness of the semiconductor device can be improved, so that the semiconductor device can be more stably mounted. Therefore, this embodiment can make the semiconductor device work more stably.

[0133] In addition, insulating members 341, 342, 343, and 344 may be provided around the through hole 331 provided in the protective layer 330. At this time, the insulating members 341, 342, 343, and 344 may not overlap or be misaligned with the through hole 331 provided in the protective layer 330 in the vertical direction. If the insulating members 341, 342, 343, and 344 overlap the through hole 331 in the vertical direction, since at least a part of the pads 321-1, 321-2, 322-1, and 323-1 overlaps the insulating members 341, 342, 343, and 344 in the vertical direction, the process characteristics during the process of mounting the semiconductor device may deteriorate, or the process characteristics during the process of applying the adhesive member may deteriorate. As a result, the areas of the pads 321-1, 321-2, 322-1, and 323-1 may decrease, and the contact resistance between the semiconductor device and the circuit board may increase.

[0134] The insulating members 341, 342, 343, and 344 may be provided at positions spaced apart from the inner wall of the through hole 331 of the protective layer 330 at regular intervals in the horizontal direction. For example, the inner wall of the through hole 331 may include a first inner wall 331-1 extending in a first horizontal direction on the stacked insulating layer 310, and the insulating members 341, 342, 343, and 344 may be spaced apart from the first inner wall 331-1 by a first distance W1 in the horizontal direction. Exemplarily, the insulating members 341, 342, 343, and 344 may be spaced apart from the periphery of the upper end of the first inner wall 331-1 by a first distance W1 in the horizontal direction.

[0135] In addition, the inner wall of the through hole 331 may include a second inner wall 331-2 extending in a second horizontal direction on the stacked insulating layer 310, and the insulating members 341, 342, 343, and 344 may be spaced apart from the second inner wall 331-2 by a second distance W2 in the second horizontal direction. The insulating members 341, 342, 343, and 344 may be spaced apart from the upper periphery of the second inner wall 331-2 by a second distance W2 in the second horizontal direction. The first distance W1 and the second distance W2 may be the same as or different from each other.

[0136] The first distance W1 and the second distance W2 may be greater than the vertical thickness of the protective layer 330. In addition, if the first distance W1 and the second distance W2 are less than the vertical thickness of the protective layer 330, at least a part of the insulating members 341, 342, 343, and 344 may cover the through hole of the protective layer 330 due to process errors during the process of forming the insulating members 341, 342, 343, and 344. Therefore, the electrical reliability and / or the mechanical reliability may be reduced.

[0137] The first distance W1 and the second distance W2 may be less than the vertical thickness of the insulating members 341, 342, 343, and 344. If the first distance W1 and the second distance W2 are greater than the vertical thickness of the insulating members 341, 342, 343, and 344, the area of the overlapping region in the vertical direction between the insulating members 341, 342, 343, and 344 and the semiconductor device may decrease. In addition, there may be a problem that at least some of the insulating members 341, 342, 343, and 344 do not overlap with the semiconductor device in the vertical direction. Further, if the first distance W1 and the second distance W2 are greater than the vertical thickness of the insulating members 341, 342, 343, and 344, the semiconductor device may not be stably placed on the circuit board, and as a result, mechanical reliability and / or electrical reliability problems may occur.

[0138] Reference Figure 4A and 4B , the semiconductor package of this embodiment may include a circuit board and a semiconductor device 440 disposed on the circuit board.

[0139] The circuit board may include a stacked structure 400, a first protective layer 410, and a second protective layer 420, and a plurality of insulating members 430 spaced apart from each other may be disposed on the first protective layer 410. For example, the plurality of insulating members 430 are spaced apart from each other in the peripheral region of the pad portion on the first protective layer 410.

[0140] In addition, the stacked structure 400 may include a stacked insulating layer 401 and a plurality of pads 402, 403, 404, and 405. Further, the first protective layer 410 is disposed on the stacked insulating layer 401 and may include vias 411 overlapping the plurality of pads 402, 403, 404, and 405 in the vertical direction.

[0141] The semiconductor device 440 may be placed on the stacked structure 400. The semiconductor device 440 may include a device body 441 and first to fourth terminals 441, 443, 444, and 445. Each of the first to fourth terminals 441, 443, 444, and 445 may be electrically connected to the pads 402, 403, 404, and 405 and the bonding member 450.

[0142] The semiconductor device 440 may also include regions OR1, OR2, OR3, and OR4 overlapping the insulating members 431, 432, 433, and 434 in the vertical direction. Here, the semiconductor device 440 includes active devices such as a CPU, a memory, a GPU, and an FPGA. In addition, the semiconductor device 440 should be interpreted to mean not only those made of a semiconductor material such as silicon (Si), but also capacitors and electronic devices such as MLCCs.

[0143] Exemplarily, the semiconductor device 440 may include a first overlapping region OR1 that overlaps with the first insulating member 431 in the vertical direction, a second overlapping region OR2 that overlaps with the second insulating member 432 in the vertical direction, a third overlapping region OR3 that overlaps with the third insulating member 433 in the vertical direction, and a fourth overlapping region OR4 that overlaps with the fourth insulating member 434 in the vertical direction. Additionally, the first to fourth overlapping regions OR1, OR2, OR3, and OR4 may also be located in the corner regions of the semiconductor device 440. The first to fourth overlapping regions OR1, OR2, OR3, and OR4 are located in the corner regions of the semiconductor device 440, thereby minimizing the stress transmitted to the semiconductor device 440 caused by the thermal cycling of the insulating members 431, 432, 433, and 434. Thereby, the semiconductor device 440 can be placed more stably on the circuit board.

[0144] Additionally, the planar area of each of the first to fourth overlapping regions OR1, OR2, OR3, and OR4 may satisfy the range of 2% to 7% of the planar area of the semiconductor device 440. If the planar area of each of the first to fourth overlapping regions OR1, OR2, OR3, and OR4 is less than 2% of the planar area of the semiconductor device 440, the semiconductor device 440 may not be stably supported by the insulating members 431, 432, 433, and 434. As a result, the semiconductor device 440 may be mounted on the circuit board in an inclined state. If the planar area of each of the first to fourth overlapping regions OR1, OR2, OR3, and OR4 exceeds 7% of the planar area of the semiconductor device 440, the effect of expanding the space for the flux-removing solution may be insignificant, and the resulting improvement in flux removal may be insignificant.

[0145] That is, the semiconductor device 440 includes a plurality of terminals, and the plurality of terminals may include an overlapping region that overlaps with the insulating members 431, 432, 433, and 434 in the vertical direction and a non-overlapping region that is not aligned with the insulating member 160 in the vertical direction. Additionally, the overlapping region may include a part of the lower surface of the first terminal 442 of the semiconductor device 440 and a part of the lower surface of the second terminal 443. Additionally, the non-overlapping region may include the remaining part of the lower surface of the first terminal 442 of the semiconductor device, the remaining part of the lower surface of the second terminal 443, the entire area of the lower surface of the third terminal 444, and the entire area of the lower surface of the fourth terminal 445.

[0146] In addition, each of the above non-overlapping regions may overlap with the pads in the vertical direction and may contact the adhesive member 445. Further, each of the above overlapping regions may be placed in direct contact with the insulating members 431, 432, 433, and 434, or may be spaced apart from the insulating members 431, 432, 433, and 434 in the vertical direction, with the adhesive member 445 therebetween.

[0147] Reference Figures 4C to 4F , the first pad 402, the second pad 403, the third pad 404, and the fourth pad 405 may be provided on the upper surface of the stacked insulating layer 401. Further, a protective layer 410 having vias overlapping with the first pad 402, the second pad 403, the third pad 404, and the fourth pad 405 in the vertical direction may be provided on the upper surface of the stacked insulating layer 401.

[0148] An adhesive member 450 may be provided on the first pad 402, the second pad 403, the third pad 404, and the fourth pad 405. Further, a semiconductor device 440 may be provided on the adhesive member 450. The semiconductor device 440 may include a device body 441, a first terminal 442 connected to the first pad 402, a second terminal 443 connected to the second pad 403, a third terminal 444 connected to the third pad 404, and a fourth terminal 445 connected to the fourth pad 405. At this time, each of the first terminal 442, the second terminal 443, the third terminal 444, and the fourth terminal 445 of the semiconductor device 440 may include a region vertically overlapping with each of the first pad 402, the second pad 403, the third pad 404, and the fourth pad 405, and this region may include a region not in contact with the circuit board. Exemplarily, the region of each of the first terminal 442, the second terminal 443, the third terminal 444, and the fourth terminal 445 of the semiconductor device 440 that overlaps with the first pad 402, the second pad 403, the third pad 404, and the fourth pad 405 in the vertical direction may be spaced apart from the upper surface of the protective layer 410 of the circuit board by a first vertical distance H2 without contacting the insulating members 431, 432, 433, 434. The first vertical distance H2 may correspond to the thickness of the insulating members 431, 432, 433, and 434 provided on the protective layer 410. Thus, this embodiment can increase the vertical distance between the semiconductor device 440 and the circuit board by the first vertical distance H2 corresponding to the thickness of the insulating members 431, 432, 433, and 434. Therefore, sufficient space can be ensured for the solution for de-soldering to penetrate, thereby improving the void problem that occurs during subsequent processes (such as underfilling and / or molding). Therefore, the electrical reliability and / or mechanical reliability of the circuit board and the semiconductor package can be further improved.

[0149] In addition, the semiconductor device 440 may include regions that overlap with the insulating members 431, 432, 433, and 434 in the vertical direction. Moreover, the overlapping regions OR1, OR1, OR3, and OR4 of the semiconductor device 440 that overlap with the insulating members 431, 432, 433, and 434 in the vertical direction may be set to be in direct contact with the insulating members 431, 432, 433, and 434. Thus, the semiconductor device 440 can be supported by the insulating members 431, 432, 433, and 434 and be more stably placed on the circuit board. However, the embodiment is not limited thereto.

[0150] Exemplarily, the overlapping regions OR1, OR2, OR3, and OR4 of the semiconductor device 440 may be spaced apart from the insulating members 431, 432, 433, and 434 in the vertical direction by adjusting the volume of the adhesive member 450. In this case, the adhesive member 450 may be disposed between the insulating members 431, 432, 433, and 434 and the overlapping regions OR1, OR2, OR3, and OR4 of the semiconductor device 440. In this case, this embodiment can further increase the contact area between the adhesive member 450 and the semiconductor device 440, thereby allowing the semiconductor device 440 to be more stably placed on the circuit board.

[0151] Reference Figure 4B , when a MLCC having four terminals is placed on the circuit board, the terminals of the MLCC may have regions that overlap with the insulating members 431, 432, 433, and 434 in the vertical direction and regions that do not overlap with the insulating members 431, 432, 433, and 434 in the vertical direction. Specifically, the first terminal 442 and the second terminal 443 vertically overlap with the insulating members 431, 432, 433, and 434, and the third terminal 444 and the fourth terminal 445 do not vertically overlap with the insulating members 431, 432, 433, and 434. Therefore, it is possible to facilitate the penetration of the solution for desoldering into the spaces between the third terminal 444 and the first terminal 442 and the second terminal 443 and between the fourth terminal 445 and the first terminal 442 and the second terminal 443, and enable the stable mounting of the MLCC.

[0152] Reference Figure 5 , the semiconductor package according to the second embodiment may include a stacked structure 500, a first semiconductor device 540, and a second semiconductor device 560.

[0153] The first semiconductor device 540 and the second semiconductor device 560 can be mounted on the stacked structure 500 using different bonding methods. Exemplarily, the first semiconductor device 540 can be mounted on the stacked structure 500 using solder paste through the first bonding member 530. In this case, the first pad portion 501 can be provided on the upper surface of the stacked structure 500, and the first bonding member 530 can be provided on the first pad portion 501. Additionally, a protective layer 510 having vias overlapping the first pad portion 501 in the vertical direction is provided on the stacked structure 500, and an insulating member 520 can be provided around the vias of the protective layer 510 and / or around the first pad portion 501. Thus, the first semiconductor device 540 can be mounted on the first pad portion 501 while being supported by the insulating member 520 through the first bonding member 450.

[0154] Additionally, the second semiconductor device 560 can be mounted on the stacked structure 500 using TC bonding and / or microspheres through the second bonding member 550. In this case, the second pad portion 502 can be further provided on the stacked structure 500, and the second bonding member 560 can be provided on the second pad portion 502.

[0155] At this time, the second semiconductor device 560 may not overlap or be misaligned with the insulating member 520 in the vertical direction. For example, the insulating member 520 may not be provided around the area where the second semiconductor device 560 is mounted and / or around the second pad portion 502. Thus, this embodiment can reduce the size of the second bonding member 550, and thereby, the pitch of the second pad portion 502 can be refined.

[0156] Additionally, the semiconductor package may further include a molding member 570. The molding member 570 can be provided to surround the first semiconductor device 540 and the second semiconductor device 550.

[0157] Reference Figure 6 , the semiconductor package can include a stacked structure 600. Additionally, a first semiconductor device 640, a second semiconductor device 670, and a third semiconductor device 675 can be mounted on the stacked structure 600.

[0158] The first semiconductor device 640 may be mounted on the stacked structure 600 using a bonding method different from that of the second semiconductor device 670 and the third semiconductor device 680. Exemplarily, the first semiconductor device 640 may be mounted on the stacked structure 600 using solder paste through the first bonding member 630. In this case, the first pad portion 601 may be provided on the upper surface of the stacked structure 600, and the first bonding member 630 may be provided on the first pad portion 601. Additionally, a protective layer 610 having vias overlapping the first pad portion 601 in the vertical direction is provided on the stacked structure 600, and an insulating member 620 may be provided around the vias of the protective layer 610 and / or around the first pad portion 601. Accordingly, the first semiconductor device 640 may be mounted on the first pad portion 601 while being supported by the insulating member 620 through the first bonding member 650.

[0159] Additionally, the second semiconductor device 670 and the third semiconductor device 675 may be mounted on the stacked structure 600 using TC bonding and / or microspheres through the second bonding member 650. In this case, the second pad portion 602 and the third pad portion 603 may be further provided on the stacked structure 600, and the second bonding member 560 may be provided on the second pad portion 602 and the third pad portion 603.

[0160] At this time, the second semiconductor device 670 and the third semiconductor device 675 may not overlap or be misaligned with the insulating member 620 in the vertical direction. Exemplarily, the insulating member 620 may not be provided around the regions where the second semiconductor device 670 and the third semiconductor device 675 are mounted and / or around the second pad portion 602 and the third pad portion 603. Accordingly, this embodiment may reduce the size of the second bonding member 650, and thereby, the pitch between the second pad portion 602 and the third pad portion 603 may be refined.

[0161] Additionally, the circuit board may further include a connection member 680 embedded in the stacked structure 600. Recently, the number of signals that semiconductor devices must process has increased, and thus, the size of semiconductor devices tends to become larger. However, increasing the area of semiconductor devices causes a problem of reduced yield of semiconductor devices. Therefore, small chips may be placed on the circuit board by dividing the size or functional portions of the semiconductor device patterns, and a connection member 680 having a function of electrically connecting them may be embedded in the circuit board. However, the connection member 680 is not limited thereto, and semiconductor devices may be connected to memories or other semiconductor devices.

[0162] The connection member 680 may be disposed in an insulating layer adjacent to the protective layer 610 in the stacked structure 600. In this case, the signal transmission distance between the second semiconductor device 670 and the third semiconductor device 675 and the connection member 680 can be reduced, and thus, it is beneficial to prevent signal loss. That is, the connection member 680 is electrically connected to a plurality of semiconductor devices disposed on the circuit board, and thus, it can be beneficial to reduce signal transmission loss by reducing the signal transmission distance when adjacent to the plurality of semiconductor devices.

[0163] In addition, the third coupling member 690 is disposed on the lower surfaces of the second pad portion 602 and the third pad portion 603. The third coupling member 690 may be solder, but is not limited thereto. The connection member 680 includes a pad portion, and the pad portion of the connection member 680 is electrically connected to the second pad portion 602 and the third pad portion 603 through the third coupling member 690.

[0164] The connection member 680 may be used to electrically connect the second semiconductor device 670 and the third semiconductor device 675. In this case, the connection member 680 may be a bridge die. Exemplarily, the connection member 680 partially overlaps the second semiconductor device 670 and the third semiconductor device 675 in the vertical direction. In addition, the connection member 680 electrically connects some terminals of the second semiconductor device 670 and the third semiconductor device 675 to each other. The connection member 680 may be made of a material such as silicon or a semiconductor device, or may be made of an organic material such as a photosensitive resin or a thermosetting resin. Small chip units separated by function and / or pitch or a plurality of semiconductor devices having different functions (e.g., CPU and GPU, GPU and HBM, etc.) may be mounted on the circuit board, and the connection member 680 may be used to electrically connect them horizontally.

[0165] The connection member 680 may be an organic bridge, which can smoothly supply power from bottom to top and minimize the loss of the supplied power. At this time, in the case of an inorganic bridge including a silicon substrate, power can be supplied through TSV (Through-Silicon Via), but there are problems of an increase in the process cost of TSV processing and a decrease in product yield. Therefore, preferably, the connection member 680 of this embodiment is an organic bridge.

[0166] According to Figure 7 an embodiment of, the above circuit board may be used as an interposer 700 disposed between a semiconductor package substrate and a semiconductor device of a semiconductor package.

[0167] That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and the thickness of the circuit board increases accordingly. However, as the thickness increases, problems such as a decrease in the yield of the circuit board may occur. Therefore, the circuit board can be divided into an interposer 700 and a semiconductor package board 720. The above circuit board can be used not only as the semiconductor package board 720 but also as the interposer 700.

[0168] The semiconductor package substrate 720 is disposed on the lower surface of the interposer 700. The semiconductor package substrate 720 can electrically connect the main board of the electronic device and the interposer 700.

[0169] At this time, the fourth coupling member 710 can be disposed between the interposer 700 and the semiconductor package substrate 720, through which the interposer 700 and the semiconductor package substrate 720 can be electrically coupled.

[0170] On the other hand, when the circuit board having the above characteristics of the present invention is used in IT devices or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the characteristics of the present invention performs a semiconductor package function, it can be used to safely protect the semiconductor chip from external moisture or contaminants, or alternatively, problems such as leakage current between terminals, electrical short circuits, and electrical open circuits of the terminals supplied to the semiconductor chip can be solved. In addition, when responsible for the signal transmission function, the noise problem can be solved. Thus, the circuit board having the above characteristics of the present invention can maintain the stable functions of IT devices or household appliances, so that the entire product and the circuit board applying the present invention can achieve functional unity or technical interlock with each other.

[0171] When the circuit board having the above characteristics of the present invention is used in transportation devices such as vehicles, problems such as signal distortion transmitted to the transportation device can be solved, or alternatively, by safely protecting the semiconductor chip that controls the transportation device from the outside and solving problems such as leakage current or electrical short circuits or electrical open circuits between the terminals supplied to the semiconductor chip, the safety of the transportation device can be further improved. Therefore, the transportation device and the circuit board applying the present invention can achieve functional integrity or technical interlock with each other. In addition, when the circuit board having the above characteristics of the present invention is used in transportation devices such as vehicles, high-current signals required by the vehicle can be transmitted at high speed, thereby improving the safety of the transportation device. In addition, even in the event of an accident occurring in various driving environments of the transportation device, the circuit board and the semiconductor package including the circuit board can operate normally, thereby safely protecting the driver.

[0172] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but not limited to one embodiment. In addition, those of ordinary skill in the art to which the embodiments pertain can even combine or modify the features, structures, effects, etc. shown in each embodiment relative to other embodiments. Therefore, it should be understood that the content related to such combinations and such modifications is included within the scope of the embodiments.

[0173] The above description has focused on the embodiments, but it is merely illustrative and does not limit the embodiments. Those skilled in the art to which the embodiments pertain can understand that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. Additionally, it should be understood that the differences related to these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: A stacked structure including a plurality of insulating layers stacked in a vertical direction; A protective layer disposed on the stacked structure; And A plurality of insulating members disposed on the protective layer and spaced apart from each other.

2. The circuit board according to claim 1, wherein The plurality of insulating members are made of the same material as the protective layer.

3. The circuit board according to claim 2, wherein, Each of the plurality of insulating members has a thickness in the vertical direction greater than the thickness of the protective layer in the vertical direction.

4. The circuit board according to claim 3, wherein, The thickness of each of the plurality of insulating members in the vertical direction is between 1.2 times and 5 times the thickness of the protective layer in the vertical direction.

5. The circuit board according to claim 1, wherein, The stacked structure includes a pad portion disposed on its upper surface, and Wherein, the plurality of insulating members are spaced apart from each other in a peripheral region of the pad portion on the protective layer.

6. The circuit board according to claim 5, wherein, The protective layer has a through hole exposing the pad portion from the protective layer, and Wherein, the plurality of insulating members are spaced apart from each other in a region around the through hole.

7. The circuit board according to claim 6, wherein, Each of the plurality of insulating members is not aligned with the through hole of the protective layer in the vertical direction.

8. The circuit board according to claim 7, wherein, Each of the plurality of insulating members is spaced apart from the through hole of the protective layer by a predetermined distance in the horizontal direction.

9. The circuit board according to claim 8, wherein, The distance is greater than the thickness of the protective layer in the vertical direction.

10. The circuit board according to claim 8, wherein, The distance is less than the thickness of each of the plurality of insulating members in the vertical direction.

11. The circuit board according to claim 5, wherein, The pad portion includes a plurality of pads, and Wherein, the area of the upper surface of at least one of the plurality of pads is greater than the area of the upper surface of each of the plurality of insulating members.

12. A semiconductor package, comprising: A stacked insulating layer including a plurality of insulating layers stacked in a vertical direction; A protective layer disposed on the stacked insulating layer; And A plurality of insulating members disposed on the protective layer and spaced apart from each other.

13. The semiconductor package according to claim 12, wherein, The thickness of the plurality of insulating members is greater than the thickness of the protective layer.

14. The semiconductor package according to claim 13, wherein, The plurality of insulating members are integrally formed with the protective layer.

15. The semiconductor package according to claim 13, wherein, The plurality of insulating members are made of the same material as the protective layer.

16. The semiconductor package according to claim 13, further comprising a pad portion disposed on the upper surface of the stacked insulating layer, and Among them, The plurality of insulating members are spaced apart from each other in a peripheral region of the pad portion on the protective layer.

17. The semiconductor package according to claim 16, wherein, Each of the plurality of insulating members includes an upper surface, Wherein, the pad portion includes a plurality of pads, Wherein, each of the plurality of pads includes an upper surface, and Wherein, the area of the upper surface of at least one of the plurality of insulating members is less than the area of the upper surface of at least one of the plurality of pads.

18. The circuit board according to claim 16, wherein, The protective layer has a through hole overlapping with the pad portion in the vertical direction, and The plurality of insulating members are spaced apart from each other in the horizontal direction around the through hole.

19. The semiconductor package according to claim 12, further comprising: A semiconductor device disposed on the plurality of insulating members.

20. The semiconductor package according to claim 19, wherein, The semiconductor device includes a plurality of electrodes, and wherein the plurality of electrodes include overlapping electrodes that overlap the insulating member in a vertical direction and non-overlapping electrodes that do not overlap the insulating member in a vertical direction.

21. The semiconductor package according to claim 20, further comprising: a conductive adhesive disposed between the semiconductor device and the pad portion, wherein the conductive adhesive overlaps the insulating member in a horizontal direction.

22. The semiconductor package according to claim 21, wherein, The conductive adhesive has at least a portion that extends between the overlapping electrodes of the semiconductor device and the insulating member.

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