Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a manufacturing method thereof and electronic equipment, and the manufacturing method comprises the steps: providing a substrate, forming a laminated structure on the substrate, and enabling the laminated structure to comprise first dielectric layers and second dielectric layers which are alternately arranged; forming a first groove, wherein the first groove vertically penetrates through the laminated structure; etching the first dielectric layer to form a groove, wherein the groove is recessed from the first groove to a direction far away from the first groove along a direction parallel to the substrate; forming a pseudo gate structure, wherein the pseudo gate structure fills the first trench and the groove; forming isolation grooves which extend along the first direction and are arranged at intervals along the second direction; etching to remove part of the pseudo gate structure, and reserving the pseudo gate structure covering the groove wall of the groove; forming a semiconductor layer, a gate dielectric layer and a word line in the first trench and the groove in sequence; and etching to remove a part of the pseudo gate structure and a part of the semiconductor layer in the groove to prevent the residual semiconductor layer in the groove from forming a parasitic device.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, making any minor difference in the process production likely to affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, the industry has proposed various semiconductor structure designs and process optimizations to meet the requirements of current products. Summary of the Invention

[0004] This application provides a semiconductor structure, a manufacturing method thereof, and an electronic device.

[0005] In a first aspect, this application provides a manufacturing method of a semiconductor structure, including the following steps: Provide a substrate, and form a stacked structure on the substrate, where the stacked structure includes a first dielectric layer and a second dielectric layer alternately arranged in a direction away from the substrate; Form a first trench, where the first trench penetrates the stacked structure in a direction perpendicular to the substrate; Etch the first dielectric layer based on the first trench to form a groove; Form a dummy gate structure, where the dummy gate structure fills the first trench and the groove; Form isolation trenches, where the isolation trenches extend in a first direction and are arranged at intervals in a second direction, the first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction; Etch and remove part of the dummy gate structure, and retain the dummy gate structure covering the sidewalls of the groove; Form a semiconductor layer, a gate dielectric layer, and a word line in sequence in the first trench and the groove; Etch and remove part of the dummy gate structure and part of the semiconductor layer in the groove.

[0006] Optionally, forming a dummy gate structure includes: Form a protective layer, where the protective layer covers the sidewalls of the first trench and the sidewalls of the groove; Form a dummy gate layer, where the dummy gate layer covers the protective layer and fills the first trench and the groove.

[0007] Optionally, etching and removing part of the dummy gate structure includes: Etch away the dummy gate layer in the first trench, exposing the protective layer covering the sidewalls of the first trench; Etch away the protective layer covering the sidewalls of the first trench; Etch away the dummy gate layer in the groove.

[0008] Optionally, the protective layer has a high etch selectivity with respect to the first dielectric layer and the second dielectric layer.

[0009] Optionally, forming a dummy gate structure includes: Deposit a first material to fill the first trench and the groove to form the dummy gate structure, the first material having a high etch selectivity with respect to the first dielectric layer and the second dielectric layer.

[0010] Optionally, after forming the isolation trench, the following steps are further included: Etch away the second dielectric layer to form an active material layer at the position where the second dielectric layer is removed; Etch away the active material layer on both sides of the dummy gate structure along the second direction to form an active layer. Along the first direction, the active layer includes a first segment and a second segment independently disposed on both sides of the dummy gate structure, and along the second direction, the size of the active layer is smaller than the size of the first dielectric layer.

[0011] Optionally, before forming the active material layer, further included: forming a diffusion barrier layer, the diffusion barrier layer covering the exposed surface of the dummy gate structure and the exposed surface of the first dielectric layer; After forming the active layer, etch away the diffusion barrier layer on both sides of the dummy gate structure along the second direction.

[0012] Optionally, before etching away part of the dummy gate structure, further included: Form a first barrier layer, the first barrier layer covering the exposed surface of the active layer; Form a first isolation layer, the first isolation layer covering the first barrier layer and filling the isolation trench.

[0013] Optionally, after forming the semiconductor layer, the gate dielectric layer, and the word line, etch away the first isolation layer in the isolation trench to expose the dummy gate structure in the groove.

[0014] Optionally, the dummy gate structure has a high etch selectivity with respect to the first isolation layer.

[0015] In a second aspect, the present application provides a semiconductor structure, including: A substrate; At least one layer of memory cell layer disposed on the substrate, the memory cell layer including at least one memory cell; the memory cell including at least one transistor, the transistor including: A gate and a gate dielectric layer connected to each other, and a semiconductor channel disposed on a side of the gate dielectric layer away from the gate; the semiconductor channel includes a bottom close to the substrate, a top away from the substrate, and a middle portion connecting the bottom and the top, and a dimension of the middle portion in a direction parallel to the substrate is smaller than dimensions of the bottom and the top in the direction parallel to the substrate.

[0016] Optionally, further including: A word line perpendicular to the substrate: A plurality of the gates serve as a part of the word line, and in a direction perpendicular to the substrate, two adjacent gates are connected by a connecting portion, and a dimension of the connecting portion in a direction parallel to the substrate is larger than a dimension of the gate in the direction parallel to the substrate.

[0017] Optionally, further including: An active layer, the active layer including a first segment and a second segment separated and disposed along a first direction parallel to the substrate, the first segment and the second segment are respectively connected to the semiconductor channel, and a protective layer is provided between the first segment and the top, and between the first segment and the bottom.

[0018] Optionally, the bottom and the top of the semiconductor channel extend in a direction away from the word line, the bottom, the top and the middle portion form a groove-like structure, one end of the first segment close to the word line extends into the groove-like structure, and one end of the second segment close to the word line extends into the groove-like structure.

[0019] Optionally, further including: A first dielectric layer is provided between two adjacent layers of the memory cell layers in a direction perpendicular to the substrate, and the protective layer has a high etching selectivity with respect to the first dielectric layer.

[0020] Optionally, further including: A second isolation layer provided between two adjacent layers of the memory cell layers, the second isolation layer being located between the first dielectric layer and the connecting portion.

[0021] Optionally, further including: The material of the second isolation layer is different from the material of the first dielectric layer, and the material of the second isolation layer includes at least one of silicon nitride or silicon oxynitride.

[0022] Optionally, further including: A diffusion barrier layer is disposed on the top surface of the active layer away from the substrate, the bottom surface close to the substrate, and the side surface of the active layer close to the semiconductor channel.

[0023] Optionally, at the gate, the gate dielectric layer, the semiconductor channel, the diffusion barrier layer, and the active layer are sequentially disposed in a direction away from the gate.

[0024] In a third aspect, the present application provides an electronic device including the semiconductor structure as described in the second aspect.

[0025] The semiconductor structure, its manufacturing method, and the electronic device of the present application have the following beneficial effects: In the manufacturing method of the semiconductor structure of the present application, after forming the first trench by optimizing the process flow, a groove extending in a direction parallel to the substrate is formed on the sidewall of the first trench, and the isolation trench is formed to expose a part of the dummy gate structure in the groove. During the process of etching and removing the dummy gate structure, the dummy gate structure covering the sidewall of the groove is retained. In this way, after forming the semiconductor layer, the gate dielectric layer, and the word line, the semiconductor layer in the groove can be etched and removed based on the isolation trench, avoiding the formation of parasitic devices due to the residual semiconductor layer in the groove, and improving the performance of the semiconductor structure.

[0026] In the semiconductor structure of the present application, the dimensions of the bottom and top of the semiconductor layer are larger than those of the middle part, facilitating the disconnection of the semiconductor layer from both sides and removing the parasitic channel; Along the direction perpendicular to the substrate, there is no remaining conductive film layer between adjacent transistors, and there is no trouble of parasitic channels, improving the electrical performance and yield rate of the semiconductor structure, and being beneficial to the multi-layer stacking and miniaturization of the semiconductor structure. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is a process flow chart of the manufacturing method of the semiconductor structure provided in some embodiments.

[0029] Figure 2 It is a top view of the stacked structure in some embodiments.

[0030] Figure 3 It is along Figure 2 A cross-sectional view perpendicular to the substrate along the line A-A in

[0031] Figure 4For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 3 A-A line in

[0032] Figure 5 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 3 A-A line in

[0033] Figure 6 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 3 A-A line in

[0034] Figure 7 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 3 A-A line in

[0035] Figure 8 For some embodiments, it is a cross-sectional view parallel to the substrate along the Figure 7 B-B line in

[0036] Figure 9 For some embodiments, it is a cross-sectional view parallel to the substrate along the Figure 7 C-C line in

[0037] Figure 10 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 3 A-A line in

[0038] Figure 11 For some embodiments, it is a cross-sectional view parallel to the substrate along the Figure 7 B-B line in

[0039] Figure 12 For some embodiments, it is a cross-sectional view parallel to the substrate along the Figure 7 C-C line in

[0040] Figure 13 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 12 D-D line in

[0041] Figure 14 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 12 D-D line in

[0042] Figure 15 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the Figure 12 E-E line in

[0043] Figure 16 A cross-sectional view parallel to the substrate along the C-C line after forming the active material layer in some embodiments. Figure 7 in the middle.

[0044] Figure 17 A cross-sectional view perpendicular to the substrate along the D-D line after forming the active material layer in some embodiments. Figure 12 in the middle.

[0045] Figure 18 A cross-sectional view parallel to the substrate along the C-C line after forming the active layer in some embodiments. Figure 7 in the middle.

[0046] Figure 19 A cross-sectional view perpendicular to the substrate along the D-D line after forming the active layer in some embodiments. Figure 12 in the middle.

[0047] Figure 20 A cross-sectional view perpendicular to the substrate along the E-E line after forming the active layer in some embodiments. Figure 12 in the middle.

[0048] Figure 21 A cross-sectional view perpendicular to the substrate along the D-D line after forming the first barrier layer in some embodiments. Figure 12 in the middle.

[0049] Figure 22 A cross-sectional view perpendicular to the substrate along the D-D line after forming the first isolation layer in some embodiments. Figure 12 in the middle.

[0050] Figure 23 A cross-sectional view perpendicular to the substrate along the D-D line after forming the first isolation layer in some embodiments. Figure 12 in the middle.

[0051] Figure 24 A cross-sectional view perpendicular to the substrate along the D-D line after removing the dummy gate layer in the first trench in some embodiments. Figure 12 in the middle.

[0052] Figure 25 A cross-sectional view perpendicular to the substrate along the E-E line after removing the dummy gate layer in the first trench in some embodiments. Figure 12 in the middle.

[0053] Figure 26 A cross-sectional view perpendicular to the substrate along the D-D line after removing the protective layer in the first trench in some embodiments. Figure 12 in the middle.

[0054] Figure 27 A cross-sectional view perpendicular to the substrate along the D-D line after removing the protective layer in the first trench in some embodiments.Figure 12 Cross-sectional view perpendicular to the substrate along line E-E.

[0055] Figure 28 For some embodiments, after removing the dummy gate layer in the groove, along Figure 12 Cross-sectional view perpendicular to the substrate along line D-D.

[0056] Figure 29 For some embodiments, after removing part of the dummy gate structure, along Figure 12 Cross-sectional view perpendicular to the substrate along line D-D.

[0057] Figure 30 For some embodiments, after removing part of the dummy gate structure, along Figure 12 Cross-sectional view perpendicular to the substrate along line E-E.

[0058] Figure 31 For some embodiments, after forming the semiconductor layer, the gate dielectric layer, and the word line, along Figure 7 Cross-sectional view parallel to the substrate along line B-B.

[0059] Figure 32 For some embodiments, after forming the semiconductor layer, the gate dielectric layer, and the word line, along Figure 7 Cross-sectional view parallel to the substrate along line C-C.

[0060] Figure 33 For some embodiments, after forming the semiconductor layer, the gate dielectric layer, and the word line, along Figure 12 Cross-sectional view perpendicular to the substrate along line D-D.

[0061] Figure 34 For some embodiments, after removing the first isolation layer in the isolation trench, along Figure 12 Cross-sectional view perpendicular to the substrate along line D-D.

[0062] Figure 35 For some embodiments, after removing the first isolation layer in the isolation trench, along Figure 12 Cross-sectional view perpendicular to the substrate along line E-E.

[0063] Figure 36 For some embodiments, after removing the dummy gate structure in the groove, along Figure 7 Cross-sectional view parallel to the substrate along line B-B.

[0064] Figure 37 For some embodiments, after removing the dummy gate structure in the groove, along Figure 12 Cross-sectional view perpendicular to the substrate along line D-D.

[0065] Figure 38 For some embodiments, after removing the dummy gate structure in the groove, along Figure 12Cross-sectional view perpendicular to the substrate along the E-E line.

[0066] Figure 39 For some embodiments, it is a cross-sectional view parallel to the substrate along the B-B line after removing the semiconductor layer in the groove. Figure 7 Cross-sectional view parallel to the substrate along the B-B line.

[0067] Figure 40 For some embodiments, it is a cross-sectional view parallel to the substrate along the B-B line after removing the semiconductor layer in the groove. Figure 12 Cross-sectional view perpendicular to the substrate along the D-D line.

[0068] Figure 41 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the E-E line after removing the semiconductor layer in the groove. Figure 12 Cross-sectional view perpendicular to the substrate along the E-E line.

[0069] Figure 42 For some embodiments, it is a cross-sectional view parallel to the substrate along the B-B line of the provided semiconductor structure. Figure 7 Cross-sectional view parallel to the substrate along the B-B line.

[0070] Figure 43 For some embodiments, it is a cross-sectional view parallel to the substrate along the B-B line of the provided semiconductor structure. Figure 7 Cross-sectional view parallel to the substrate along the C-C line.

[0071] Figure 44 For some embodiments, it is a cross-sectional view parallel to the substrate along the C-C line of the provided semiconductor structure. Figure 12 Cross-sectional view perpendicular to the substrate along the D-D line.

[0072] Figure 45 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the E-E line of the provided semiconductor structure. Figure 12 Cross-sectional view perpendicular to the substrate along the E-E line.

[0073] Figure 46 For some embodiments, it is a cross-sectional view perpendicular to the substrate along the D-D line of the provided semiconductor structure. Figure 12 Cross-sectional view perpendicular to the substrate along the D-D line.

[0074] Explanation of reference numerals: 100, substrate; 101, oxide layer; 121, isolation trench; 131, connection part; 140, channel trench; 141, first trench; 142, groove; 200, stacked structure; 210, first dielectric layer; 220, second dielectric layer; 230, diffusion barrier layer; 240, active material layer; 250, active layer; 250a, first segment; 250b, second segment; 260, first barrier layer; 310, first isolation layer; 320, second isolation layer; 400, dummy gate structure; 410, protection layer; 420, dummy gate layer; 500, semiconductor channel; 500a, bottom; 500b, top; 500c, middle part; 510, semiconductor layer; Z1, storage cell area; Z2, bit line area; BL, bit line; WL, word line; GM, gate dielectric layer; SU, storage cell; MCT, transistor; G1, gate; S / D1, first source / drain; S / D2, second source / drain; D1, first direction; D2, second direction; D3, third direction. Detailed implementation

[0075] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0077] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part; for example, the first doping type can be referred to as the second doping type, and similarly, the second doping type can be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.

[0078] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the attached figures is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. Additionally, the device can also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0079] As used herein, the singular forms of "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0080] This application provides a semiconductor structure, a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor structure optimizes the process flow. After forming a first trench, a groove extending in a direction parallel to the substrate is formed on the sidewall of the first trench. An isolation trench is formed to expose a part of the dummy gate structure in the groove. During the process of etching and removing the dummy gate structure, the dummy gate structure covering the sidewall of the groove is retained. Thus, after forming the semiconductor layer, the gate dielectric layer, and the word line, the semiconductor layer in the groove can be etched and removed based on the isolation trench, avoiding the formation of parasitic devices due to the residual semiconductor layer in the groove, and improving the performance of the semiconductor structure.

[0081] In some exemplary embodiments of the present disclosure, a manufacturing method of a semiconductor structure is provided, as Figure 1 shown, Figure 1The flowchart of the manufacturing method of a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown. In this embodiment, the semiconductor structure is not limited. Hereinafter, a dynamic random access memory (DRAM) will be taken as an example for introduction, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other types of memories, such as a static random-access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FRAM), and a magnetic random-access memory (MRAM).

[0082] Figure 1 The flowchart of the manufacturing method of a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown, Figures 2 - 46 which is a schematic diagram of each stage of the manufacturing method of the semiconductor structure. Hereinafter, in conjunction with Figures 2 - 46 the manufacturing method of the semiconductor structure of this embodiment will be introduced. As Figure 1 shown, a manufacturing method of a semiconductor structure according to this embodiment includes the following steps: Step S110: Provide a substrate, and form a stacked structure on the substrate. The stacked structure includes a first dielectric layer and a second dielectric layer alternately arranged in a direction away from the substrate.

[0083] Step S120: Form a first trench, and the first trench penetrates the stacked structure in a direction perpendicular to the substrate.

[0084] Step S130: Etch the first dielectric layer based on the first trench to form a groove.

[0085] Step S140: Form a dummy gate structure, and the dummy gate structure fills the first trench and the groove.

[0086] Step S150: Form isolation trenches, which extend in a first direction and are arranged at intervals in a second direction. Both the first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect.

[0087] Step S160: Etch and remove part of the dummy gate structure, and retain the dummy gate structure covering the sidewalls of the groove.

[0088] Step S170: Sequentially form a semiconductor layer, a gate dielectric layer, and a word line in the first trench and the groove.

[0089] Step S180: Etch and remove part of the dummy gate structure and part of the semiconductor layer in the groove.

[0090] In step S110, as Figure 2 shown in the cross-sectional view of the A-A plane (refer to A-A in Figure 3 ) after the stacked structure 200 is formed on the substrate 100, Figure 3 and the top view of the stacked structure 200 is shown. Refer to Figure 2 and Figure 3 . As shown, the substrate 100 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate can be a layered substrate including, such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. The substrate 100 can be a single-layer structure or a multi-layer structure.

[0091] In this embodiment, an oxide layer 101 is formed on the top surface of the substrate 100. The oxide layer 101 is used to protect the substrate 100 from being contaminated when exposed to the process environment and ensure that the substrate 100 has good conductivity.

[0092] The stacked structure 200 can be formed on the substrate 100 by the following implementation manners: Refer to Figure 2 and Figure 3 . As shown, any one of the deposition processes of chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering can be selected to alternately deposit the first dielectric layer 210 and the second dielectric layer 220, and repeat the cycle several times to form the stacked structure 200.

[0093] The first dielectric layer 210 and the second dielectric layer 220 of the stacked structure 200 can be alternately stacked in 2 to 1024 layers or more. For example, the first dielectric layer 210 and the second dielectric layer 220 can be alternately stacked in 48 layers, 64 layers, 128 layers, 256 layers, or 512 layers, etc. Among them, the material of the first dielectric layer 210 includes silicon oxide, and the material of the second dielectric layer 220 includes silicon nitride.

[0094] Refer to Figure 3 . As shown, according to the semiconductor structure to be formed, the stacked structure 200 is laid out, and a storage cell region Z1 and a bit line region Z2 are defined on the stacked structure 200. The storage cell region Z1 and the bit line region Z2 are arranged along the first direction D1, and the first direction D1 is parallel to the top surface of the substrate 100.

[0095] In step S120, as Figure 4 shown, referring to Figure 2 , Figure 3 , a first mask layer (the first mask layer) is formed on the top surface of the stacked structure 200. The first mask layer defines a pattern of the first trench 141. The stacked structure 200 is etched according to the first mask layer, and the exposed first dielectric layer 210 and second dielectric layer 220 are etched away layer by layer to form a first trench 141 that penetrates the stacked structure 200 in the third direction D3 perpendicular to the substrate 100.

[0096] In this embodiment, a plurality of first trenches 141 may be formed in the storage unit region Z1 of the stacked structure 200. The plurality of first trenches 141 are arranged at intervals in the storage unit region Z1 along the second direction D2. The second direction D2 is parallel to the top surface of the substrate 100, and the second direction D2 intersects the first direction D1.

[0097] It should be noted that the first trench 141 may penetrate the oxide layer 101 to expose a part of the top surface of the substrate 100; or, as shown in this embodiment, the first trench 141 may only penetrate the stacked structure 200 and the first trench 141 does not penetrate the oxide layer 101. Since the thickness of the oxide layer 101 is very thin, the oxide layer 101 is easily broken down, so the oxide layer 101 does not affect the electrical connection between the word line WL formed in the subsequent steps and the substrate 100.

[0098] In step S130, as Figure 5 shown, referring to Figure 4 , a wet etching process may be used to etch away a part of the first dielectric layer 210 exposed on the sidewalls of the first trench 141 to form a groove 142. The groove 142 is connected to the first trench 141, and the groove 142 is recessed from the first trench 141 in a direction away from the first trench 141 along a direction parallel to the substrate 100.

[0099] For example, an etching solution may be injected into the first trench 141. The etching solution has a high etching selectivity with respect to the second dielectric layer 220. The removal amount of the first dielectric layer 210 can be precisely controlled by controlling the etching time, so as to precisely control the size of the groove 142 in the direction parallel to the substrate 100.

[0100] The first trench 141 and the groove 142 connected thereto together form a channel trench 140. Along a plane parallel to the substrate 100, the size of the channel trench 140 provided in the first dielectric layer 210 is larger than the size of the channel trench 140 provided in the second dielectric layer 220.

[0101] In step S140, in this embodiment, forming a dummy gate structure includes the following steps: Step S141: Forming a protective layer that covers the sidewalls of the first trench and the sidewalls of the groove.

[0102] As shown in Figure 6 and referring to Figure 5 , a protective layer 410 can be formed by atomic layer deposition process. The protective layer 410 covers the sidewalls of the first trench 141 and the sidewalls of the recess 142. The protective layer 410 has a high etch selectivity with respect to the first dielectric layer 210 and the second dielectric layer 220. The material of the protective layer 410 can include silicon oxide.

[0103] It can be understood that although the materials of the protective layer 410 and the first dielectric layer 210 both include silicon oxide, during the formation of the protective layer 410, a high etch selectivity between the protective layer 410 and the first dielectric layer 210 can be achieved by adjusting the deposition process conditions and process parameters.

[0104] Step S142: Form a dummy gate layer that covers the protective layer and fills the first trench and the recess.

[0105] As shown in Figure 7 , Figure 8 , Figure 9 and referring to Figure 5 , Figure 6 , any one of chemical vapor deposition process, atomic layer deposition process or sputtering can be selected to deposit the dummy gate layer 420. The dummy gate layer 420 covers the protective layer 410 and fills the first trench 141 and the recess 142. The material of the dummy gate layer 420 can include at least one of single-crystalline silicon and polycrystalline silicon. In this embodiment, the dummy gate layer 420 and the protective layer 410 together form a dummy gate structure 400.

[0106] Referring to Figure 8 , Figure 9 , along the plane parallel to the substrate 100, the size of the dummy gate structure 400 formed in the first dielectric layer 210 is larger than the size of the dummy gate structure 400 formed in the second dielectric layer 220.

[0107] In some other embodiments, to form the dummy gate structure 400, the following implementation can be adopted: As shown in Figure 10 and referring to Figure 5 , deposit a first material to fill the first trench 141 and the recess 142 to form the dummy gate structure 400. The first material has a high etch selectivity with respect to the first dielectric layer 210 and the second dielectric layer 220. Exemplarily, the first material can be selected from one of spin-on carbon material and alumina. In this embodiment, only one deposition process is required to form the dummy gate structure 400, which saves the process steps and the process time.

[0108] In step S150, as shown in Figure 11 , Figure 12 , Figure 13 and referring to Figure 8, Figure 9 , Figure 10 , a second mask layer (not shown in the figure) is formed on the top surface of the stacked structure 200, and the second mask layer defines a pattern of the isolation trench 121.

[0109] Etch the stacked structure 200 according to the second mask layer to form the isolation trench 121 in the memory cell region Z1 (refer to Figure 3 ). The isolation trench 121 extends along the first direction D1 and is arranged at intervals along the second direction D2. Both the first direction D1 and the second direction D2 are parallel to the substrate 100, and the first direction D1 and the second direction D2 intersect.

[0110] For example, the included angle between the first direction D1 and the second direction D2 can be 30°, 45°, 60°, 90°, 120° or 150°. In some embodiments, the included angle between the first direction D1 and the second direction D2 is 90°, and the first direction D1 and the second direction D2 are perpendicularly intersecting.

[0111] As Figure 11 , Figure 12 , Figure 13 shown, refer to Figure 8 , Figure 9 , Figure 10 , the isolation trench 121 divides the stacked structure 200 in the memory cell region Z1 into strip-shaped structures (not labeled in the figure) that extend along the first direction D1 and are arranged at intervals along the second direction D2.

[0112] A dummy gate structure 400 is correspondingly disposed in each strip-shaped structure, and a part of the sidewall of the dummy gate structure 400 located in the groove 142 is exposed in the isolation trench 121. In other words, each isolation trench 121 exposes a part of the sidewalls of the dummy gate structures 400 located on both sides of it along the second direction D2.

[0113] After step S150 and before step S160, the following steps are also performed: Step S10: Etch and remove the second dielectric layer, and form an active material layer at the position where the second dielectric layer is removed.

[0114] First, etch and remove all of the second dielectric layer 220 based on the isolation trench 121. As Figure 14 , Figure 15 shown, refer to Figure 10 , Figure 13 , etchant can be injected into the isolation trench 121, and the etchant has a high etching selectivity with respect to the first dielectric layer 210 and the dummy gate structure 400. For example, phosphoric acid solution can be injected into the isolation trench 121, and all of the second dielectric layer 220 is dissolved and removed by the phosphoric acid solution. Refer to Figure 3, all the second dielectric layers 220 in the storage cell region Z1 and all the second dielectric layers 220 in the bit line region Z2 are removed, exposing the sidewalls of the dummy gate structure 400 that were originally covered by the second dielectric layer 220, and the first dielectric layer 210 is supported by the dummy gate structure 400.

[0115] Then, a diffusion barrier layer 230 is formed, and the diffusion barrier layer 230 covers the exposed surface of the dummy gate structure 400 and the exposed surface of the first dielectric layer 210. As Figure 16 , Figure 17 shown, any one of the atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process (Physical Vapor Deposition, PVD) can be selected to deposit and form the diffusion barrier layer 230, and the diffusion barrier layer 230 covers the exposed surface of the dummy gate structure 400 and the surface of the first dielectric layer 210.

[0116] The material of the diffusion barrier layer 230 can be selected from metal titanium or titanium compounds, metal tantalum or tantalum compounds, metal platinum or platinum compounds. In this embodiment, the material of the diffusion barrier layer 230 includes titanium nitride.

[0117] Next, as Figure 16 , Figure 17 shown, any one of the atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process can be selected to deposit and form the active material layer 240, and the active material layer 240 covers the diffusion barrier layer 230 and fills the position where the second dielectric layer 220 was originally provided. The material of the active material layer 240 can include at least one of metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al). In this embodiment, the material of the active material layer 240 includes metal tungsten.

[0118] Next, the diffusion barrier layer 230 located on both sides of the dummy gate structure 400 along the second direction D2 is etched and removed. A dry process can be used to etch and remove the active material layer 240 in the isolation trench 121, and then, a wet process is used to etch and remove the diffusion barrier layer 230 in the isolation trench 121 to cut the active material layer 240 into multiple layers arranged at intervals along the third direction D3, and the multiple active material layers 240 are independently provided.

[0119] In this embodiment, the active material layer 240 in the bit line region Z2 is formed into a bit line BL, and the bit line BL extends along the second direction D2 and is arranged at intervals along the third direction D3.

[0120] Step S20: Etch and remove the active material layers on both sides of the dummy gate structure along the second direction to form an active layer. Along the first direction, the active layer includes a first segment and a second segment independently disposed on both sides of the dummy gate structure, and along the second direction, the size of the active layer is smaller than that of the first dielectric layer.

[0121] As Figure 18 , Figure 19 , Figure 20 shown, referring to Figure 16 , Figure 17 , based on the isolation trench 121, etch the active material layer 240. Use an anisotropic etching process to etch the active material layer 240 along the second direction D2, remove part of the active material layer 240, and cut off the active material layer 240 along the first direction D1 to form an active layer 250. The active layer 250 includes a first segment 250a and a second segment 250b oppositely disposed on both sides of the dummy gate structure 400. And along the second direction D2, the size of the active layer 250 is smaller than that of the first dielectric layer 210. The two sides of the active layer 250 are recessed relative to the first dielectric layer 210, and the active layer 250 exposes a part of the diffusion barrier layer 230 covering the dummy gate structure 400.

[0122] Next, as Figure 18 , Figure 19 , Figure 20 shown, after forming the active layer 250, etch and remove the diffusion barrier layer 230 exposed by the active layer 250. For example, a wet process can be used to etch and remove the exposed diffusion barrier layer 230, and only the diffusion barrier layer 230 located between the active layer 250 and the dummy gate structure 400 is retained, thereby preventing the metal material in the active layer 250 from diffusing into other devices and avoiding contamination of other devices.

[0123] Step S30: Form a first barrier layer, and the first barrier layer covers the exposed surface of the active layer.

[0124] In some embodiments, as Figure 21 shown, the first barrier layer 260 can be deposited by atomic layer deposition or chemical vapor deposition. The first barrier layer 260 covers the exposed surface of the active layer 250, the exposed surface of the first dielectric layer 210, and the exposed surface of the dummy gate structure 400. The material of the first dielectric layer 210 may include at least one of silicon nitride or silicon oxynitride.

[0125] As Figure 21 shown, the first barrier layer 260 covers the exposed surface of the active layer 250, preventing the active layer 250 from being exposed to the process space and oxidized in subsequent processes, avoiding deterioration of the electrical performance of the active layer 250, and thus improving the electrical performance of the semiconductor structure.

[0126] Step S40: Form a first isolation layer that covers the first barrier layer and fills the isolation trenches.

[0127] As Figure 22 shown, referring to Figure 21 , the first isolation layer 310 can be formed by a spin coating process or a deposition process. The pseudo-gate structure 400 has a high etch selectivity with respect to the first isolation layer 310. In this embodiment, the material of the first isolation layer 310 can include spin-on carbon or silicon oxide.

[0128] In some other embodiments, referring to Figure 23 shown, the first barrier layer 260 may not be formed, and the active layer 250 is nitrided so that a part of the material on the exposed surface of the active layer 250 is nitrided, a nitride layer is formed on the exposed surface of the active layer 250, and then the first isolation layer 310 is formed by a spin coating process or a deposition process. The first isolation layer 310 covers the active layer 240 and fills the isolation trench 121. In the subsequent embodiments, the solution without forming the first barrier layer 260 is described.

[0129] In step S160, in this embodiment, part of the pseudo-gate structure 400 is etched away to expose the first trench 141 and part of the recess 142, including: Step S161: Etch away the pseudo-gate layer in the first trench to expose the protective layer covering the sidewalls of the first trench.

[0130] As Figure 24 , Figure 25 shown, referring to Figure 20 , Figure 23 , a third mask layer (not shown in the figure) is formed on the top surface of the stacked structure 200. The third mask layer exposes the top surface of the pseudo-gate layer 420. The pseudo-gate layer 420 is etched according to the third mask layer, and the pseudo-gate layer 420 in the first trench 141 (referring to Figure 5 ) is etched away along the third direction D3 by an anisotropic etching process to expose the protective layer 410 covering the sidewalls of the first trench 141.

[0131] Step S162: Etch away the protective layer covering the sidewalls of the first trench.

[0132] As Figure 26 , Figure 27 shown, referring to Figure 24 , Figure 25 , the protective layer 410 covering the sidewalls of the first trench 141 is etched by a wet process to expose the diffusion barrier layer 230 that was etched and retained in the previous step.

[0133] Step S163: Etch away the pseudo-gate layer in the recess.

[0134] AsFigure 28 , Figure 30 As shown in reference Figure 26 , Figure 27 , all of the dummy gate layer 420 in the groove 142 is etched away by a wet process, exposing the protective layer 410 covering the sidewalls of the groove 142.

[0135] In some embodiments, to etch away part of the dummy gate structure 400 to expose the first trench 141 and part of the groove 142, the following implementation can be adopted: As Figure 29 shown in reference Figure 11 , first, all of the dummy gate structure 400 in the first trench 141 is etched away.

[0136] Then, based on the first trench 141, the dummy gate structure 400 in the groove 142 is etched. An anisotropic etching process of the dummy gate structure 400 in the groove 142 can be carried out using plasma, etching away part of the dummy gate structure 400 along the direction parallel to the substrate 100. By controlling the energy and direction of the plasma, part of the dummy gate structure 400 in the groove 142 is etched away, and the dummy gate structure 400 covering the groove wall of the groove 142 is retained.

[0137] In step S170, first, as Figure 31 , Figure 32 , Figure 33 , Figure 34 shown in reference Figure 28 , Figure 30 , an atomic layer deposition process can be used to deposit and form a semiconductor layer 510, and the semiconductor layer 510 covers the groove walls of the first trench 141 (refer to Figure 5 ) and the dummy gate structure 400 (refer to Figure 5 ) in the groove 142 (refer to Figure 28 or Figure 29 , Figure 30 ). The material of the semiconductor layer 510 can include Indium Gallium Zinc Oxide (IGZO).

[0138] The material of the semiconductor layer 510 may include indium gallium zinc oxide. For example, the material of the semiconductor layer 510 may include at least one of the following materials: tin oxide zinc (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tungsten oxide doped (IWO), zinc oxide (ZnOx), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), indium zinc oxide (InSnOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO).

[0139] Then, as Figure 31 , Figure 32 , Figure 33 shown, the gate dielectric layer GM is deposited and formed by an atomic layer deposition process, and the gate dielectric layer GM covers the semiconductor layer 510. Among them, the material of the gate dielectric layer GM may include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanate (SrTiO3), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), strontium silicate (SrSiO); alternatively, the material of the gate dielectric layer GM may include at least one of hafnium silicon oxynitride (HfSiON), zirconium silicon oxynitride (ZrSiON), strontium silicon oxynitride (SrSiON). In some embodiments, the material of the gate dielectric layer GM includes aluminum oxide, and the thickness of the gate dielectric layer GM is 10 nm.

[0140] Next, as Figure 31 , Figure 32 , Figure 33 shown, the word line WL is deposited and formed by an atomic layer deposition process or a chemical vapor deposition process, and the word line WL covers the gate dielectric layer GM and fills the unfilled areas in the first trench 141 and the groove 142. The material of the word line WL may be selected from at least one of indium tin oxide doped (Indium Tin Oxide, ITO), aluminum doped zinc oxide (AZO), indium doped zinc oxide thin film (IZO).

[0141] During the process of depositing and forming the word line WL, some materials may be deposited on the top surface of the structure. After the materials of the word line WL fill the unfilled areas in the first trench 141 and the recess 142, a Chemical Mechanical Planarization (CMP) process is used to grind and remove the materials of the word line WL deposited on the top surface of the structure.

[0142] In this embodiment, after forming the semiconductor layer 510, the gate dielectric layer GM, and the word line WL, the following steps are further performed: Step S1701: Etch and remove the first isolation layer in the isolation trench to expose the dummy gate structure in the recess.

[0143] As Figure 34 、 Figure 35 shown, referring to 31, Figure 32 、 Figure 33 , a fourth mask layer (not shown in the figure) is formed on the top surface of the structure, and the fourth mask layer exposes the top surface of the first isolation layer 310 located in the isolation trench 121. Based on the fourth mask layer, the first isolation layer 310 can be etched using a dry process, a wet process, or a combination of the dry process and the wet process to etch and remove the first isolation layer 310 in the isolation trench 121, exposing a part of the dummy gate structure 400 in the recess 142.

[0144] Referring to Figure 33 、 Figure 34 , along the second direction D2, the first isolation layer 310 in the recessed areas on both sides of the active layer 250 relative to the first dielectric layer 210 is etched and retained, and the etched and retained first isolation layer 310 is used to protect the active layer 250 and the semiconductor layer 510 connected to the active layer 250.

[0145] In step S180, as Figure 36 、 Figure 37 、 Figure 38 shown, referring to Figure 31 、 Figure 34 、 Figure 35 , based on the isolation trench 121, a wet process is used to etch and remove part of the dummy gate structure 400, exposing the semiconductor layer 510 in the recess 142. For example, an etchant can be injected into the isolation trench 121. The dummy gate structure 400 has a high etching selectivity relative to the first isolation layer 310. The dummy gate structure 400 connected to the first dielectric layer 210 is etched and removed, while avoiding damage to the first isolation layer 310 by the etchant, and further avoiding etching damage to the active layer 250 and the semiconductor layer 510 connected to the active layer 250.

[0146] Then, as Figure 39 、 Figure 40 、 Figure 41As shown, the exposed semiconductor layer 510 is removed by wet etching, and the exposed gate dielectric layer GM is exposed. The remaining semiconductor layer 510 is etched to form semiconductor channels 500 arranged at intervals along the third direction D3.

[0147] In this embodiment, after removing the semiconductor layer 510 in the groove 142, the following steps are further performed: As Figure 42 、 Figure 43 、 Figure 44 、 Figure 45 、 Figure 46 shown, an oxide is deposited in an oxygen atmosphere to form a second isolation layer 320. The second isolation layer 320 covers the gate dielectric layer GM in the groove 142, fills the unfilled area in the groove 142, and isolates the trench 121. The material of the second isolation layer may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0148] Then, a chemical mechanical polishing process is used to polish the top surface of the second isolation layer 320 into a flat surface to facilitate subsequent other process treatments on the semiconductor structure.

[0149] In the manufacturing method of the semiconductor structure of this embodiment, by optimizing the process, after forming the first trench, the sidewalls of the first trench are directly etched to form a groove extending in a direction parallel to the substrate, so that the size of the pseudo-gate structure formed in the groove is larger than the size of the pseudo-gate structure formed in the first trench. Then, an isolation trench is formed to expose a part of the pseudo-gate structure located in the groove, thereby realizing the removal of the semiconductor layer in the groove by etching the isolation trench, avoiding the formation of parasitic devices due to the remaining semiconductor layer between adjacent active layers, improving the performance of the semiconductor structure, and being beneficial to the multi-layer stacking and miniaturization of the three-dimensional semiconductor structure.

[0150] In the manufacturing method of the semiconductor structure of this embodiment, by optimizing the process, the complexity and challenge of the process are reduced, the process steps are streamlined, the process steps of small-size repeated light exposure-etching are reduced, and the process cost and process time are saved.

[0151] In some embodiments, a semiconductor structure is provided, such as Figure 42 、 Figure 43 、 Figure 44 、 Figure 45 、 Figure 46As shown, the semiconductor structure includes a substrate 100 and a multi-layer memory cell layer disposed in a direction perpendicular to the substrate 100 (the third direction D3); the memory cell layer includes multiple rows and multiple columns of memory cells SU, the row direction is the first direction D1, the column direction is the second direction D2, both the first direction D1 and the second direction D2 are parallel to the substrate 100, and the first direction D1 and the second direction D2 intersect; the memory cell SU includes at least one transistor MCT, the transistor MCT includes a gate G1 and a gate dielectric layer GM connected to each other, and a semiconductor channel 500 disposed on a side of the gate dielectric layer GM away from the gate G1; the semiconductor channel 500 includes a bottom 500a close to the substrate, a top 500b away from the substrate 100, and an intermediate portion 500c connecting the bottom 500a and the top 500b, and the size of the intermediate portion 500c in the direction parallel to the substrate 100 is smaller than the sizes of the bottom 500a and the top 500b in the direction parallel to the substrate 100.

[0152] The included angle between the first direction D1 and the second direction D2 can be 30°, 45°, 60°, 90°, 120° or 150°. In some embodiments, the included angle between the first direction D1 and the second direction D2 is 90°, and the first direction D1 and the second direction D2 intersect perpendicularly.

[0153] The semiconductor structure of this embodiment is fabricated by the fabrication process of the above embodiment. By etching the first dielectric layer based on the first trench to form a groove, the groove is recessed from the first trench in a direction parallel to the substrate, and the semiconductor structure of this embodiment can be formed. The sizes of the bottom 500a and the top 500b of the semiconductor channel 500 are larger than the size of the intermediate portion 500c, which is convenient for disconnecting the semiconductor layer from both sides to form the semiconductor channel 500.

[0154] In the semiconductor structure of this embodiment, along the direction perpendicular to the substrate 100, there is no remaining conductive film layer between adjacent transistors MCT, and there is no trouble of parasitic devices, which improves the electrical performance and yield rate of the semiconductor structure, and is beneficial to the multi-layer stacking and miniaturization of the semiconductor structure.

[0155] In some embodiments, as Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 shown, the semiconductor structure further includes a word line WL in a direction perpendicular to the substrate 100 (the third direction D3): multiple gates G1 serve as part of the word line WL. Along the direction perpendicular to the substrate 100 (the third direction D3), two adjacent gates G1 are connected by a connecting portion 131, and the size of the connecting portion 131 in the direction parallel to the substrate 100 is larger than the size of the gate G1 in the direction parallel to the substrate 100.

[0156] The size of the connection part 131 of the word line WL is larger than the size of the gate G1, so that the sizes of the bottom 500a and the top 500b of the semiconductor channel 500 are larger, facilitating the formation of the semiconductor channel 500 by disconnecting the semiconductor layer from both sides during the fabrication process of the semiconductor structure.

[0157] In some embodiments, such as Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 as shown, the semiconductor structure further includes an active layer 250, the active layer 250 includes a first segment 250a and a second segment 250b that are separately arranged along a first direction D1 parallel to the substrate 100, the first segment 250a and the second segment 250b are respectively connected to the semiconductor channel 500, and there is a protective layer 410 between the first segment 250a and the top 500b, and between the first segment 250a and the bottom 500a.

[0158] Along the direction perpendicular to the substrate 100, the remaining dummy gate structure 400 is disposed between the bottom 500a of the semiconductor channel 500 and the connection part 131 below it, and between the top 500b of the semiconductor channel 500 and the connection part 131 above it. The remaining dummy gate structure 400 can enhance the isolation performance between adjacent two layers of memory cells SU.

[0159] In some embodiments, such as Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 as shown, the bottom 500a and the top 500b of the semiconductor channel 500 extend away from the word line WL. Along the direction parallel to the substrate 100, the bottom 500a, the top 500b and the middle part 500c form a groove-like structure, and one end of the first segment 250a close to the word line WL extends into the groove-like structure, and one end of the second segment 250b close to the word line WL extends into the groove-like structure.

[0160] Each transistor MCT further includes a first source / drain S / D1 and a second source / drain S / D2 connected to the semiconductor channel 500. The first source / drain S / D1 is disposed in the partial structure where the first segment 250a is connected to the semiconductor channel 500, and the second source / drain S / D2 is disposed in the partial structure where the second segment 250b is connected to the semiconductor channel 500.

[0161] The middle part 500c of the semiconductor channel 500 surrounds and covers the circumferential surface of the gate G1.

[0162] The bottom 500a, top 500b, and middle part 500c of the semiconductor channel 500 enclose a trough-like structure. The first source / drain S / D1 and the second source / drain S / D2 are oppositely arranged in the trough-like structure along the first direction D1 and are respectively in contact connection with the semiconductor channel 500. In this way, the contact area between the first source / drain S / D1, the second source / drain S / D2, and the semiconductor channel 500 is increased, the gate control ability of the transistor MCT is increased, and the short-channel effect is effectively suppressed.

[0163] In the trough-like structure formed by the semiconductor channel 500, the area other than the areas where the first source / drain S / D1 and the second source / drain S / D2 are arranged is filled with the first dielectric layer 210. That is, referring to Figure 44 、 Figure 46 shown, along the second direction D2, the first dielectric layer 210 is connected to the semiconductor channel 500.

[0164] In some embodiments, as Figure 42 、 Figure 43 、 Figure 44 、 Figure 45 、 Figure 46 shown, the semiconductor structure further includes a first dielectric layer 210 between adjacent two memory cell layers along the direction perpendicular to the substrate 100 (the third direction D3), and the protective layer 410 has a high etching selectivity ratio relative to the first dielectric layer 210.

[0165] Among them, the protective layer 410 prevents the wet solution from damaging the dummy gate layer during the etching of the second dielectric layer and avoids affecting the length of the gate G1 of the transistor.

[0166] In some embodiments, as Figure 42 、 Figure 43 、 Figure 44 、 Figure 45 、 Figure 46 shown, the semiconductor structure further includes a second isolation layer 320 disposed between adjacent two memory cell layers. The second isolation layer 320 is located between the first dielectric layer 210 and the connection portion 131. The second isolation layer 320 can further enhance the isolation effect between adjacent two memory cells SU.

[0167] In some embodiments, as Figure 42 、 Figure 43 、 Figure 44 、 Figure 45 、 Figure 46 shown, the material of the second isolation layer 320 is different from the material of the first dielectric layer 210, and the material of the second isolation layer 320 includes at least one of silicon nitride or silicon oxynitride. There are two materials of isolation layers between adjacent two memory cells SU, which enhances the isolation effect between the two memory cells SU.

[0168] In some embodiments, such as Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 as shown, the semiconductor structure further includes a diffusion barrier layer 230 disposed on the top surface of the active layer 250 away from the substrate, the bottom surface close to the substrate 100, and the side surface of the active layer 250 on the side close to the semiconductor channel 500.

[0169] In some embodiments, such as Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 as shown, at the gate G1, the gate dielectric layer GM, the semiconductor channel 500, the diffusion barrier layer 230, and the active layer 250 are sequentially disposed in a direction away from the gate G1.

[0170] In some embodiments, such as 42, Figure 43 , Figure 45 , Figure 46 as shown, the semiconductor structure further includes a first barrier layer 260 disposed on the sidewalls of the active layer 250 oppositely arranged along the second direction D2. Along the second direction D2, the first barrier layer 260 is further disposed between the first dielectric layer 210 and the semiconductor channel 500.

[0171] In some embodiments, an electronic device is provided, and the electronic device includes the semiconductor structure in the above embodiments. The electronic device can be a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0172] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification. The above-described embodiments only represent several implementation manners of the present application, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, It includes the following steps: Provide a substrate, and form a stacked structure on the substrate, the stacked structure including a first dielectric layer and a second dielectric layer alternately arranged in a direction away from the substrate; Form a first trench, the first trench penetrating the stacked structure in a direction perpendicular to the substrate; Etch the first dielectric layer based on the first trench to form a groove; Form a dummy gate structure, the dummy gate structure filling the first trench and the groove; Form isolation trenches, the isolation trenches extending in a first direction and arranged at intervals in a second direction, both the first direction and the second direction being parallel to the substrate, and the first direction and the second direction intersecting; Etch and remove part of the dummy gate structure, and retain the dummy gate structure covering the sidewalls of the groove; Successively form a semiconductor layer, a gate dielectric layer, and a word line in the first trench and the groove; Etch and remove part of the dummy gate structure and part of the semiconductor layer in the groove.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Forming a dummy gate structure includes: Form a protective layer, the protective layer covering the sidewalls of the first trench and the sidewalls of the groove; Form a dummy gate layer, the dummy gate layer covering the protective layer and filling the first trench and the groove.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein Etching and removing part of the dummy gate structure includes: Etch and remove the dummy gate layer in the first trench to expose the protective layer covering the sidewalls of the first trench; Etch and remove the protective layer covering the sidewalls of the first trench; Etch and remove the dummy gate layer in the groove.

4. The method for manufacturing a semiconductor structure according to claim 2, wherein, The protective layer has a high etching selectivity with respect to the first dielectric layer and the second dielectric layer.

5. The manufacturing method of the semiconductor structure according to claim 1, wherein Forming a dummy gate structure includes: Deposit a first material to fill the first trench and the groove to form the dummy gate structure, the first material having a high etching selectivity with respect to the first dielectric layer and the second dielectric layer.

6. The method for fabricating a semiconductor structure according to claim 1, wherein After forming the isolation trenches, the following steps are further included: Etch and remove the second dielectric layer, and form an active material layer at the position where the second dielectric layer is removed; Etch and remove the active material layer on both sides of the dummy gate structure along the second direction to form an active layer. Along the first direction, the active layer includes a first segment and a second segment independently arranged on both sides of the dummy gate structure, and along the second direction, the size of the active layer is smaller than the size of the first dielectric layer.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, Before forming the active material layer, further include: forming a diffusion barrier layer, the diffusion barrier layer covering the exposed surfaces of the dummy gate structure and the exposed surface of the first dielectric layer; After forming the active layer, etch and remove the diffusion barrier layer located on both sides of the dummy gate structure along the second direction.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein, Before etching and removing part of the dummy gate structure, further include: Form a first barrier layer, the first barrier layer covering the exposed surface of the active layer; Form a first isolation layer, the first isolation layer covering the first barrier layer and filling the isolation trenches.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, After forming the semiconductor layer, the gate dielectric layer, and the word line, etch and remove the first isolation layer in the isolation trenches to expose the dummy gate structure in the groove.

10. The manufacturing method of the semiconductor structure according to claim 8, characterized in that, The dummy gate structure has a high etching selectivity with respect to the first isolation layer.

11. A semiconductor structure, characterized in that, It includes: A substrate; At least one memory cell layer disposed on the substrate, the memory cell layer including at least one memory cell; The memory cell includes at least one transistor, and the transistor includes: A gate and a gate dielectric layer connected to each other, and a semiconductor channel disposed on a side of the gate dielectric layer away from the gate; The semiconductor channel includes a bottom close to the substrate, a top away from the substrate, and a middle portion connecting the bottom and the top, and a dimension of the middle portion in a direction parallel to the substrate is smaller than dimensions of the bottom and the top in the direction parallel to the substrate.

12. The semiconductor structure according to claim 11, wherein, Further included are: Word lines perpendicular to the substrate: A plurality of the gates serve as a part of the word lines, and along a direction perpendicular to the substrate, two adjacent ones of the gates are connected by a connection portion, and a dimension of the connection portion in a direction parallel to the substrate is larger than a dimension of the gate in the direction parallel to the substrate.

13. The semiconductor structure according to claim 12, wherein Further included are: An active layer, the active layer including a first segment and a second segment separated and disposed along a first direction parallel to the substrate, the first segment and the second segment being respectively connected to the semiconductor channel, and a protective layer is provided between the first segment and the top, and between the first segment and the bottom.

14. The semiconductor structure according to claim 13, wherein The bottom and the top of the semiconductor channel extend in a direction away from the word line, and the bottom, the top and the middle portion form a groove-like structure, and an end of the first segment close to the word line extends into the groove-like structure, and an end of the second segment close to the word line extends into the groove-like structure.

15. The semiconductor structure according to claim 13, wherein Further included are: Along a direction perpendicular to the substrate, a first dielectric layer is provided between two adjacent memory cell layers, and the protective layer has a high etching selectivity with respect to the first dielectric layer.

16. The semiconductor structure according to claim 15, wherein Further included are: A second isolation layer disposed between two adjacent memory cell layers, and the second isolation layer is located between the first dielectric layer and the connection portion.

17. The semiconductor structure according to claim 16, wherein, Further included are: The material of the second isolation layer is different from the material of the first dielectric layer, and the material of the second isolation layer includes at least one of silicon nitride or silicon oxynitride.

18. The semiconductor structure according to claim 13, wherein, Further included are: A diffusion barrier layer is disposed on a top surface of the active layer away from the substrate, a bottom surface close to the substrate, and a side surface of the active layer close to the semiconductor channel.

19. The semiconductor structure according to claim 18, wherein, At the gate, the gate dielectric layer, the semiconductor channel, the diffusion barrier layer and the active layer are sequentially disposed in a direction away from the gate.

20. An electronic device, characterized in that, Including the semiconductor structure according to any one of claims 11-19.

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