Magnetoresistive random access memory device

Abstract

There is provided a magnetoresistive random access memory (MRAM) device including: a cell region on a substrate; a core peripheral region on the substrate and adjacent to the cell region in a horizontal direction; a first interlayer insulating layer in the cell region and the core peripheral region; a second interlayer insulating layer on the first interlayer insulating layer; a first interconnection line in the first interlayer insulating layer, in which the first interconnection line is in the cell region and the core peripheral region; a second interconnect line in the second interlayer insulating layer, in which the second interconnect line is in the core peripheral region and connected to the first interconnect line; a lower electrode contact on the first interconnect line in the cell region; and a magnetic tunnel junction structure on the lower electrode contact portion, in which the lower electrode contact portion and the second interconnect line overlap each other in a horizontal direction.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0001668, filed with the Korean Intellectual Property Office on January 4, 2024, the entire disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a magnetoresistive memory device, that is, a magnetoresistive random access memory (MRAM) device. Background art

[0004] As electronic devices become faster and / or consume less power, there is an increasing demand for higher speed and / or lower operating voltage of semiconductor devices in electronic devices. To meet these demands, MRAM devices have been proposed as semiconductor devices. MRAM devices have received much attention as next - generation semiconductor devices because they have characteristics such as high - speed operation and / or non - volatility.

[0005] Generally, an MRAM device may include a magnetic tunnel junction. The magnetic tunnel junction may include two magnetic materials and an insulating layer sandwiched therebetween. The resistance value of the magnetic tunnel junction may vary according to the magnetization directions of the two magnetic materials. For example, when the magnetization directions of the two magnetic materials are anti - parallel to each other, the magnetic tunnel junction may have a large resistance value, while when the magnetization directions of the two magnetic materials are parallel to each other, the magnetic tunnel junction may have a small resistance value. The difference in resistance values can be used to write / read data.

[0006] With the development of the electronics industry, there are increasing demands for high integration and low power consumption of MRAM devices. Therefore, a large amount of research has been conducted to meet these demands. Summary of the invention

[0007] Provided is a magnetoresistive random access memory (MRAM) device having improved performance and reliability.

[0008] Also provided is an MRAM device having a simplified manufacturing process.

[0009] The present disclosure is not limited to the above problems, and those skilled in the art can clearly understand other problems not mentioned from the following description.

[0010] According to one aspect of the present disclosure, a magnetoresistive random access memory (MRAM) device includes: a cell region on a substrate; a core peripheral region on the substrate and adjacent to the cell region in a horizontal direction; a first interlayer insulating layer in the cell region and the core peripheral region; a second interlayer insulating layer on the first interlayer insulating layer; a first interconnect in the first interlayer insulating layer, wherein the first interconnect is in the cell region and the core peripheral region; a second interconnect in the second interlayer insulating layer, wherein the second interconnect is in the core peripheral region and connected to the first interconnect; a lower electrode contact on the first interconnect in the cell region; and a magnetic tunnel junction structure on the lower electrode contact, wherein the lower electrode contact and the second interconnect overlap each other in the horizontal direction.

[0011] According to one aspect of the present disclosure, a magnetoresistive random access memory (MRAM) device includes: a cell region on a substrate; a core peripheral region on the substrate and adjacent to the cell region in a horizontal direction; a cell transistor in the cell region; a core peripheral transistor in the peripheral region; a cell interconnect in the cell region, wherein the cell interconnect is connected to the cell transistor; a core peripheral interconnect in the core peripheral region, wherein the core peripheral interconnect is connected to the core peripheral transistor; a lower electrode contact connected to the cell interconnect; and a magnetic tunnel junction structure on the lower electrode contact, wherein an upper surface of each of the cell interconnect and the core peripheral interconnect is at a vertical height that is the same as or lower than a vertical height of a lower surface of the magnetic tunnel junction structure, and wherein a vertical height of at least a portion of the core peripheral interconnect overlaps a vertical height of the lower electrode contact in the horizontal direction.

[0012] According to one aspect of the present disclosure, a magnetoresistive random access memory (MRAM) device includes: a cell region on a substrate; a core peripheral region on the substrate and adjacent to the cell region in a horizontal direction; a cell transistor in the cell region; a core peripheral transistor in the core peripheral region; a cell interlayer insulating layer on the cell transistor; a core peripheral interlayer insulating layer on the core peripheral transistor; a plurality of cell interconnect lines connected to the cell transistor; a plurality of core peripheral interconnect lines connected to the core peripheral transistor; a lower electrode contact on the uppermost cell interconnect line among the plurality of cell interconnect lines; an information storage structure on the lower electrode contact, the information storage structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode, wherein the lower electrode, the magnetic tunnel junction structure, and the upper electrode are stacked in sequence; and a bit line on the information storage structure, wherein the plurality of cell interconnect lines pass through the cell interlayer insulating layer at a vertical height that is the same as or lower than the vertical height of the lower surface of the magnetic tunnel junction structure, wherein the plurality of core peripheral interconnect lines pass through the core peripheral interlayer insulating layer at a vertical height that is the same as or lower than the vertical height of the lower surface of the magnetic tunnel junction structure, and wherein the lower electrode contact overlaps with the uppermost core peripheral interconnect line among the plurality of core peripheral interconnect lines in a horizontal direction. Description of the Drawings

[0013] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a circuit diagram of a unit memory cell of a magnetoresistive random access memory (MRAM) device according to one or more embodiments;

[0015] Figure 2 is a cross-sectional view showing an MRAM device according to one or more embodiments;

[0016] Figure 3 is a cross-sectional view showing an information storage structure of an MRAM device according to one or more embodiments;

[0017] Figure 4A and Figure 4B is a cross-sectional view showing an example of an information storage structure of an MRAM device according to one or more embodiments;

[0018] Figure 5 is Figure 2 an enlarged cross-sectional view of regions EX1 and EX2 of

[0019] Figure 6 、 Figure 7 and Figure 8is a cross-sectional view showing an MRAM device according to one or more embodiments;

[0020] Figure 9 is a cross-sectional view showing an MRAM device according to one or more embodiments; and

[0021] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 and Figure 18 is a cross-sectional view showing a method of manufacturing an MRAM device according to one or more embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals throughout the specification refer to the same elements.

[0023] As used herein, a plurality of "units", "modules", "elements", and "blocks" may be implemented as a single component, or a single "unit", "module", "element", and "block" may include a plurality of components.

[0024] It should be understood that when an element is referred to as being "connected" or connected to another element, it can be directly or indirectly connected to the other element.

[0025] Moreover, when a component "includes" or "contains" an element, unless otherwise specifically described to the contrary, the component may also include other elements without excluding other elements.

[0026] Throughout the description, when an element is "on" another element, this includes not only the case where the element is in contact with the other element, but also the case where there is another element between the two elements.

[0027] Here, the expressions "at least one of a, b, or c" and "at least one of a, b, and c" mean "only a", "only b", "only c", "a and b", "both a and c", "both b and c", and "all of a, b, and c".

[0028] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, the present disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0029] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

[0030] For any method or process described herein, identification codes may be used for convenience of description, but are not intended to illustrate the order of each step or operation. Each step or operation may be implemented in an order different from the order shown, unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the context of the present disclosure clearly dictates otherwise.

[0031] Figure 1 is a circuit diagram of a unit memory cell MC of a magnetoresistive random access memory (MRAM) device according to one or more embodiments.

[0032] Referring to Figure 1 , the unit memory cell MC may include a memory element ME and a selection element SE. The memory element ME may be electrically connected in series to the selection element SE. The memory element ME may be connected between the bit line BL and the selection element SE. The selection element SE may be connected between the memory element ME and the source line SL and may be controlled by the word line WL. The selection element SE may include, for example, a bipolar transistor or a metal oxide semiconductor (MOS) field effect transistor.

[0033] The memory element ME may include a magnetic tunnel junction MTJ, which includes magnetic layers ML1 and ML2 separated from each other and a tunnel barrier TBL between the magnetic layers ML1 and ML2. One of the magnetic layers ML1 and ML2 may be a reference layer, whose magnetization direction is fixed in one direction independently of an external magnetic field in a normal use environment. The other of the magnetic layers ML1 and ML2 may be a free layer, whose magnetization direction varies between two stable magnetization directions due to an external magnetic field or current. When the magnetization directions of the reference layer and the free layer are antiparallel to each other, the resistance of the magnetic tunnel junction MTJ may be much larger than when the magnetization directions of the reference layer and the free layer are parallel to each other. That is, the resistance of the magnetic tunnel junction MTJ may be adjusted by changing the magnetization direction of the free layer. Accordingly, the memory element ME may store data in the unit memory cell MC by using the resistance difference according to the magnetization directions of the reference layer and the free layer.

[0034] Figure 2 is a cross-sectional view showing an MRAM device according to one or more embodiments. Figure 3 is a cross-sectional view showing an information storage structure 180 of an MRAM device 100 according to one or more embodiments. Figure 4A and Figure 4B is a cross-sectional view showing an example of the information storage structure 180 of the MRAM device 100 according to one or more embodiments. Figure 5 is showing Figure 2 an enlarged cross-sectional view of regions EX1 and EX2 of

[0035] Referring toFigure 2 In Figure 2 , the MRAM device 100 may include a substrate 110, which includes a cell region CR and a core / periphery region (also referred to as a core-periphery region) C / PR. In the substrate 110, the cell region CR and the core / periphery region C / PR may be arranged along a first horizontal direction (X direction) (i.e., offset relative to each other).

[0036] The substrate 110 may include a semiconductor element (such as Si or Ge), or a compound semiconductor element, such as SiC, GaAs, InAs, or InP. The substrate 110 may include a semiconductor substrate, at least one insulating layer formed on the semiconductor substrate, and / or a structure including at least one conductive region. The conductive region may include, for example, a well doped with impurities or a structure doped with impurities. A device isolation layer 111 that defines a plurality of active regions AC may be formed in the substrate 110. The device isolation layer 111 may include an oxide layer, a nitride layer, or a combination thereof. In one or more example embodiments, the device isolation layer 111 may have various structures, such as a shallow trench isolation (STI) structure.

[0037] An interlayer insulating layer 120, a lower conductive region 121, a first etch stop layer 131, a first interlayer insulating layer 132, a second etch stop layer 141, and a second interlayer insulating layer 142 may be disposed on the cell region CR and the core / periphery region C / PR of the substrate 110.

[0038] The interlayer insulating layer 120 may include an insulating layer including an oxide layer, a silicon nitride layer, or a combination thereof. The lower conductive region 121 may pass through the interlayer insulating layer 120 and be connected to the plurality of active regions AC of the substrate 110. The lower conductive region 121 may include various conductive regions, such as an interconnect layer, a contact plug, and a transistor. The lower conductive region 121 may include polysilicon, metal, conductive metal nitride, metal silicide, or a combination thereof.

[0039] The first etch stop layer 131 and the first interlayer insulating layer 132 may be disposed on the interlayer insulating layer 120. The first etch stop layer 131 may include a nitride, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or silicon oxycarbonitride (SiOCN). The first interlayer insulating layer 132 may include an insulating layer including an oxide layer, a silicon nitride layer, or a combination thereof.

[0040] A first interconnect structure 150 passing through the first etch stop layer 131 and the first interlayer insulating layer 132 may be disposed in the cell region CR and the core / periphery region C / PR. The first interconnect structure 150 may include a first interconnect via 151 and a first interconnect line 152. The first interconnect structure 150 may include at least one of metal and conductive metal nitride. For example, the first interconnect structure 150 may include copper.

[0041] The second etch stop layer 141 covering the first interlayer insulating layer 132 and the second interlayer insulating layer 142 may be disposed in the cell region CR and the core / periphery region C / PR. The second etch stop layer 141 may include a nitride such as SiN, SiON, SiCN, or SiOCN. The second interlayer insulating layer 142 may include an insulating layer including an oxide layer, a silicon nitride layer, or a combination thereof.

[0042] The lower electrode contact portion 170 may be disposed in the cell region CR. The lower electrode contact portion 170 may pass through the second etch stop layer 141 and the second interlayer insulating layer 142 and be connected to the first interconnect structure 150.

[0043] The second interconnect structure 160 passing through the second etch stop layer 141 and the second interlayer insulating layer 142 may be disposed in the core / periphery region C / PR. The second interconnect structure 160 may include a second interconnect via 161 and a second interconnect line 162. The second interconnect structure 160 may include at least one of a metal and a conductive metal nitride. For example, the second interconnect structure 160 may include copper.

[0044] In the core / periphery region C / PR, the upper etch stop layer 143 may be disposed on the second interlayer insulating layer 142. The upper etch stop layer 143 may include a nitride such as SiN, SiON, SiCN, or SiOCN. The upper etch stop layer 143 may cover the second interconnect structure 160 passing through the second etch stop layer 141 and the second interlayer insulating layer 142.

[0045] Next, refer to Figure 5 Describe the first interconnect structure 150, the second interconnect structure 160, and the lower electrode contact portion 170 in the cell region CR and the core / periphery region C / PR.

[0046] As Figure 5 shown, the first interconnect structure 150 passing through the first interlayer insulating layer 132 and the lower electrode contact portion 170 passing through the second interlayer insulating layer 142 may be disposed in the cell region CR. The information storage structure 180 may be disposed on the lower electrode contact portion 170. The first interconnect structure 150 passing through the first interlayer insulating layer 132 and the second interconnect structure 160 passing through the second interlayer insulating layer 142 may be disposed in the core / periphery region C / PR.

[0047] In one or more embodiments, a first interconnect structure 150 may be disposed in a first interlayer insulating layer 132, and the first interconnect structure 150 passes through the first interlayer insulating layer 132 in the cell region CR and the core / periphery region C / PR. Specifically, a first interconnect via 151 may extend through a first etch stop layer 131 into the first interlayer insulating layer 132, and a first interconnect line 152 may be disposed on the first interconnect via 151 in the first interlayer insulating layer 132.

[0048] In one or more embodiments, the vertical height of the upper surface of the first interlayer insulating layer 132 may be the same as the vertical height of the upper surface of the first interconnect structure 150. For example, the upper surface of the first interlayer insulating layer 132 may be at a first vertical height LV1, and the upper surface of the first interconnect structure 150 may be at the first vertical height LV1. For example, the upper surface of the first interconnect line 152 of the first interconnect structure 150 may be at the first vertical height LV1.

[0049] For example, the upper surface of the first interlayer insulating layer 132 may be coplanar with the upper surface of the first interconnect structure 150. For example, the upper surface of the first interlayer insulating layer 132 may be coplanar with the upper surface of the first interconnect line 152.

[0050] In one or more embodiments, a lower electrode contact portion 170 passing through a second interlayer insulating layer 142 in the cell region CR may be disposed in the second interlayer insulating layer 142. Specifically, the lower electrode contact portion 170 may pass through a second etch stop layer 141 and extend into the second interlayer insulating layer 142. For example, the lower electrode contact portion 170 may include portions surrounded by the second etch stop layer 141 and the second interlayer insulating layer 142, respectively.

[0051] In one or more embodiments, the lower electrode contact portion 170 may include a first barrier pattern 171 and a first metal pattern 172. For example, the first barrier pattern 171 may include a metal nitride (such as tungsten nitride, tantalum nitride, or titanium nitride) and / or a metal (such as tantalum or titanium), and the first metal pattern 172 may include a metal material having a low resistance, such as tungsten, copper, or aluminum. As described above, the lower electrode contact portion 170 may be connected to the first interconnect structure 150.

[0052] In one or more embodiments, the lower electrode contact portion 170 may land on the first interconnect structure 150. Specifically, the lower electrode contact portion 170 may land on the first interconnect line 152 of the first interconnect structure 150. Accordingly, the lower surface of the lower electrode contact portion 170 may be at the first vertical height LV1.

[0053] In one or more embodiments, a second interconnect structure 160 passing through a second interlayer insulating layer 142 in a core / periphery region C / P R may be disposed in the second interlayer insulating layer 142. Specifically, a second interconnect via 161 may extend through a second etch stop layer 141 into the second interlayer insulating layer 142, and a second interconnect line 162 may be disposed on the second interconnect via 161 in the second interlayer insulating layer 142.

[0054] In one or more embodiments, a second interconnect structure 160 in a core / periphery region C / P R may be disposed on and connected to a first interconnect structure 150. Specifically, a second interconnect via 161 of the second interconnect structure 160 may be disposed on a first interconnect line 152 of the first interconnect structure 150. A lower surface of the second interconnect structure 160 may be at a first vertical height LV1. For example, a lower surface of the second interconnect via 161 may be at the first vertical height LV1.

[0055] In one or more embodiments, an upper etch stop layer 143 covering the second interconnect structure 160 in a core / periphery region C / P R may be disposed on the second interconnect structure 160. In one or more embodiments, an upper surface of the second interconnect structure 160 may be at a second vertical height LV2. In one or more embodiments, an upper surface of a lower electrode contact portion 170 may be at a third vertical height LV3 higher than the second vertical height LV2. In one or more embodiments, an upper surface of the upper etch stop layer 143 may be at the same vertical height as the upper surface of the lower electrode contact portion 170. For example, the upper surface of the upper etch stop layer 143 may be at the third vertical height LV3.

[0056] In one or more embodiments, an upper surface of the lower electrode contact portion 170 may be at a vertical height higher than the upper surface of the upper etch stop layer 143.

[0057] In one or more embodiments, the first interconnect structure 150 may be the uppermost interconnect structure in a cell region CR. Specifically, the first interconnect structure 150 may be the uppermost one among a plurality of interconnect structures disposed on a substrate 110 and below a lower electrode contact portion 170 in the cell region CR. For example, the first interconnect structure 150 may be the uppermost interconnect structure on which the lower electrode contact portion 170 lands (i.e., contacts). Specifically, the first interconnect line 152 may be the uppermost interconnect line in the cell region CR. For example, the first interconnect line 152 may be the uppermost interconnect line on which the lower electrode contact portion 170 lands (i.e., contacts).

[0058] In one or more embodiments, the first interconnect structure 150 may not be the topmost interconnect structure in the core / periphery region C / PR. In the core / periphery region C / PR, the second interconnect structure 160 on the first interconnect structure 150 may be the topmost interconnect structure. Specifically, in the core / periphery region C / PR, the second interconnect structure 160 may be the topmost one among a plurality of interconnect structures disposed on the substrate 110 and at a vertical height equal to or lower than the vertical height of the information storage structure 180. Specifically, the second interconnect structure 160 may be the topmost interconnect line in the core / periphery region C / PR.

[0059] In one or more embodiments, the topmost interconnect structure in the cell region CR and the topmost interconnect structure in the core / periphery region C / PR may be at different vertical heights. In other words, the first interconnect structure 150, which is the topmost interconnect structure in the cell region CR, and the second interconnect structure 160, which is the topmost interconnect structure in the core / periphery region C / PR, may be at different vertical heights. That is to say, the topmost interconnect structure in the cell region CR may be at a vertical height lower than that of the topmost interconnect structure in the core / periphery region C / PR.

[0060] In one or more embodiments, the lower electrode contact portion 170 in the cell region CR may overlap with the second interconnect structure 160 in the core / periphery region C / PR in the first horizontal direction (X direction). For example, the lower electrode contact portion 170 in the cell region CR may overlap with each of the second interconnect via 161 and the second interconnect line 162 in the core / periphery region C / PR in the first horizontal direction (X direction).

[0061] In one or more embodiments, the lower electrode contact portion 170 in the cell region CR may overlap with the second etch stop layer 141 and the second interlayer insulating layer 142 in the core / periphery region C / PR in the first horizontal direction (X direction).

[0062] In one or more embodiments, the vertical height of the lower electrode contact portion 170 in the cell region CR may be greater than the vertical thickness of the second interlayer insulating layer 142. For example, the vertical height of the lower electrode contact portion 170 in the cell region CR may be greater than the sum of the vertical thicknesses of the second interlayer insulating layer 142 and the upper etch stop layer 143 in the core / periphery region C / PR.

[0063] In one or more embodiments, the vertical thickness of the second interlayer insulating layer 142 in the cell region CR may be different from the vertical thickness of the second interlayer insulating layer 142 in the core / periphery region C / PR. For example, the vertical height of the lower surface of the second interlayer insulating layer 142 in the cell region CR may be the same as the vertical height of the lower surface of the second interlayer insulating layer 142 in the core / periphery region C / PR, while the vertical height of the upper surface of the second interlayer insulating layer 142 in the cell region CR may be different from the vertical height of the upper surface of the second interlayer insulating layer 142 in the core / periphery region C / PR. For example, the upper surface of the second interlayer insulating layer 142 in the cell region CR may be at a third vertical height LV3, while the upper surface of the second interlayer insulating layer 142 in the core / periphery region C / PR may be at a second vertical height LV2.

[0064] In one or more embodiments, for example, the upper surface of the second interlayer insulating layer 142 in the cell region CR may be at a vertical height higher than the third vertical height LV3.

[0065] In one or more embodiments, the vertical height of the lower surface of the lower electrode contact portion 170 in the cell region CR may be lower than the vertical height of the upper surface of the second interconnecting structure 160 in the core / periphery region C / PR. For example, the lower surface of the lower electrode contact portion 170 in the cell region CR may be at a first vertical height LV1, and the upper surface of the second interconnecting structure 160 in the core / periphery region C / PR may be at a second vertical height LV2. That is to say, the vertical height of the lower surface of the lower electrode contact portion 170 in the cell region CR may be lower than the vertical height of the upper surface of the uppermost interconnecting structure in the core / periphery region C / PR. That is to say, the vertical height of the lower surface of the lower electrode contact portion 170 in the cell region CR may be lower than the vertical height of the upper surface of the uppermost interconnecting line in the core / periphery region C / PR.

[0066] In one or more embodiments, the vertical height of the lower surface of the lower electrode contact portion 170 in the cell region CR may be lower than the vertical height of the upper surface of the second interlayer insulating layer 142 in the core / periphery region C / PR. For example, the lower surface of the lower electrode contact portion 170 in the cell region CR may be at a first vertical height LV1, and the lower surface of the second interlayer insulating layer 142 in the core / periphery region C / PR may be at a second vertical height LV2.

[0067] In one or more embodiments, the vertical height of the lower surface of the lower electrode contact portion 170 in the cell region CR may be lower than the vertical height of the upper surface of the upper etch stop layer 143 in the core / periphery region C / PR. For example, the upper surface of the upper etch stop layer 143 may be at a third vertical height LV3.

[0068] On the cell region CR of the substrate 110, the information storage structure 180 may be disposed on the lower electrode contact portion 170. The information storage structure 180 may not be disposed on the core / peripheral region C / P R of the substrate 110. The information storage structure 180 may include a lower electrode 181, a magnetic tunnel junction structure 185, and an upper electrode 187. The magnetic tunnel junction structure 185 may correspond to the magnetic tunnel junction MTJ described with reference to Figure 1 . The lower electrode 181 and the upper electrode 187 may be separated from each other, and the magnetic tunnel junction structure 185 is interposed therebetween. The lower electrode 181 may be disposed between the magnetic tunnel junction structure 185 and the lower electrode contact portion 170. The information storage structure 180 may be disposed on the lower electrode contact portion 170 and connected to the lower electrode 181.

[0069] Specifically, with reference to Figure 3 , the information storage structure 180 may include a lower electrode 181, a magnetic tunnel junction structure 185, and an upper electrode 187. The magnetic tunnel junction structure 185 may include a first magnetic layer 182, a tunnel barrier layer 183, and a second magnetic layer 184 stacked on the lower electrode 181. The first magnetic layer 182, the tunnel barrier layer 183, and the second magnetic layer 184 may correspond to the magnetic layer ML1, the tunnel barrier TBL, and the magnetic layer ML2 described with reference to Figure 1 , respectively.

[0070] The lower electrode 181 may include at least one of a metal (such as titanium or tantalum) and a metal nitride (such as titanium nitride or tantalum nitride). In one or more embodiments, the lower electrode 181 may include tungsten, copper, platinum, nickel, silver, gold, etc. The upper electrode 187 may include at least one of a metal (such as titanium or tantalum) and a metal nitride (such as titanium nitride or tantalum nitride). In one or more embodiments, the upper electrode 187 may include tungsten, copper, platinum, nickel, silver, gold, etc.

[0071] In one or more embodiments, the first magnetic layer 182 may be set as a fixed layer having a fixed magnetization direction. Specifically, the first magnetic layer 182 may include a fixed pattern, a lower ferromagnetic pattern, an antiferromagnetic coupling spacer pattern, and an upper ferromagnetic pattern. In this case, the fixed pattern may include, for example, iron manganese (FeMn), iridium manganese (IrMn), platinum manganese (PtMn), manganese oxide (MnO), manganese sulfide (MnS), manganese telluride (MnTe), manganese fluoride (MnF2), iron fluoride (FeF2), iron chloride (FeCl2), iron oxide (FeO), cobalt chloride (CoCl2), cobalt oxide (CoO), nickel chloride (NiCl2), nickel oxide (NiO), or chromium (Cr). For example, the upper ferromagnetic pattern and the lower ferromagnetic pattern may include a ferromagnetic material including at least one of iron (Fe), nickel (Ni), and cobalt (Co). For example, the antiferromagnetic coupling spacer pattern may include at least one of ruthenium (Ru), iridium (Ir), and rhodium (Rh).

[0072] In one or more embodiments, the second magnetic layer 184 may be configured as a free layer having a variable magnetization direction.

[0073] In this case, the second magnetic layer 184 may include a ferromagnetic material such as iron (Fe), cobalt (Co), nickel (Ni), chromium (Cr), or platinum (Pt). The second magnetic layer 184 may also include boron (B) or silicon (Si). These may be used alone or in combination of two or more. For example, the second magnetic layer 184 may include a composite material such as CoFe, NiFe, FeCr, CoFeNi, PtCr, CoCrPt, CoFeB, NiFeSiB, or CoFeSiB.

[0074] In one or more embodiments, the tunnel barrier layer 183 may be disposed between the first magnetic layer 182 and the second magnetic layer 184. The first magnetic layer 182 and the second magnetic layer 184 may be separated from each other with the tunnel barrier layer 183 therebetween. The tunnel barrier layer 183 may include a metal oxide having insulating properties. For example, the tunnel barrier layer 183 may include magnesium oxide (MgO x ) or aluminum oxide (AlO x ).

[0075] In one or more embodiments, the second magnetic layer 184 may be disposed between the tunnel barrier layer 183 and the upper electrode 187, but the present disclosure is not limited thereto. For example, the second magnetic layer 184 may be disposed between the tunnel barrier layer 183 and the lower electrode 181.

[0076] Referring to Figure 4A and Figure 4B , the first magnetic layer 182 may have a first magnetization direction MD1 fixed in one direction, and the second magnetic layer 184 may have a second magnetization direction MD2 that can be changed to be parallel or antiparallel to the first magnetization direction MD1 of the first magnetic layer 182.

[0077] As Figure 4A shown, the magnetization direction MD1 of the first magnetic layer 182 and the magnetization direction MD2 of the second magnetic layer 184 may be parallel to the interface between the tunnel barrier layer 183 and the second magnetic layer 184. In this case, each of the first magnetic layer 182 and the second magnetic layer 184 may include a ferromagnetic material. The first magnetic layer 182 may further include an antiferromagnetic material to fix the magnetization direction of the ferromagnetic material in the first magnetic layer 182.

[0078] As Figure 4BAs shown, the magnetization direction MD1 of the first magnetic layer 182 and the magnetization direction MD2 of the second magnetic layer 184 can be perpendicular to the interface between the tunnel barrier layer 183 and the second magnetic layer 184. In this case, each of the first magnetic layer 182 and the second magnetic layer 184 can include at least one of a perpendicular magnetic material (e.g., CoFeTb, CoFeGd, or CoFeDy), a perpendicular magnetic material having an L10 structure, CoPt having a hexagonal close-packed lattice structure, and a perpendicular magnetic structure. The perpendicular magnetic material having an L10 structure can include at least one of FePt having an L10 structure, FePd having an L10 structure, CoPd having an L10 structure, or CoPt having an L10 structure. The perpendicular magnetic structure can include alternately and repeatedly stacked magnetic layers and non-magnetic layers. As an example, the perpendicular magnetic structure can include at least one of (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, and (CoCr / Pd)n (where n is the number of stacks).

[0079] In the cell region CR of the MRAM device 100 according to an embodiment, the second interconnect structure 160 may not be present, and the first interconnect structure 150 may be connected to the lower electrode contact portion 170 as the topmost interconnect structure.

[0080] Figures 6 to 8 is a cross-sectional view showing MRAM devices 101, 102, and 103 according to one or more embodiments. Hereinafter, the differences from the MRAM device 100 described with reference to Figure 2 and Figure 3 will be described in detail.

[0081] Referring to Figure 6 , the MRAM device 101 can include a lower conductive region 121, a first interconnect structure 150, a second interconnect structure 160, and / or a lower electrode contact portion 170 disposed on a substrate 110 including a cell region CR and a core / peripheral region C / P R.

[0082] In one or more embodiments, an interlayer dielectric layer 120 and a lower conductive region 121 passing through the interlayer dielectric layer 120, a first interlayer dielectric layer 132 and a first interconnect structure 150 passing through the first interlayer dielectric layer 132, and a second interlayer dielectric layer 142 and a lower electrode contact portion 170 passing through the second interlayer dielectric layer 142 may be disposed in a cell region CR. The lower electrode contact portion 170 may be surrounded by a second etch stop layer 141 and the second interlayer dielectric layer 142. In one or more embodiments, an upper etch stop layer 143 may also be disposed on the second interlayer dielectric layer 142. The lower electrode contact portion 170 may also include a portion surrounded by the upper etch stop layer 143. The upper etch stop layer 143 in the cell region CR may be at the same vertical height as the upper etch stop layer 143 in the core / periphery region C / PR.

[0083] In one or more embodiments, the vertical thickness of the second interlayer dielectric layer 142 in the cell region CR may be the same as the vertical thickness of the second interlayer dielectric layer 142 in the core / periphery region C / PR. For example, the vertical height of the lower surface of the second interlayer dielectric layer 142 in the cell region CR may be the same as the vertical height of the lower surface of the second interlayer dielectric layer 142 in the core / periphery region C / PR. For example, the vertical height of the upper surface of the second interlayer dielectric layer 142 in the cell region CR may be the same as the vertical height of the upper surface of the second interlayer dielectric layer 142 in the core / periphery region C / PR.

[0084] Referring Figure 7 , the MRAM device 102 may include a lower conductive region 121, a first interconnect structure 150, a second interconnect structure 160, and / or a lower electrode contact portion 170 disposed on a substrate 110 including a cell region CR and a core / periphery region C / PR.

[0085] In one or more embodiments, an interlayer dielectric layer 120 and a lower conductive region 121 passing through the interlayer dielectric layer 120, a first interlayer dielectric layer 132 and a first interconnect structure passing through the first interlayer dielectric layer 132, and a second interlayer dielectric layer 142 and a lower electrode contact portion 170 passing through the second interlayer dielectric layer 142 may be disposed in a cell region CR. The lower electrode contact portion 170 may be surrounded by a second etch stop layer 141 and the second interlayer dielectric layer 142.

[0086] In one or more embodiments, a portion 143P of the upper etch stop layer 143 may be disposed within the second interlayer dielectric layer 142. When the upper etch stop layer 143 is disposed on the second interlayer dielectric layer 142, the portion 143P may be formed, and during a subsequent process of forming the information storage structure 180, the upper etch stop layer 143 except for the portion 143P is removed, and then a material constituting the second interlayer dielectric layer 142 is applied.

[0087] In one or more embodiments, the vertical thickness of the second interlayer insulating layer 142 in the cell region CR may be different from the vertical thickness of the second interlayer insulating layer 142 in the core / peripheral region C / PR. For example, the upper surface of the second interlayer insulating layer 142 in the cell region CR may be at the third vertical height LV3 (refer to Figure 5 ) or at a height higher than the third vertical height LV3, while the upper surface of the second interlayer insulating layer 142 in the core / peripheral region C / PR may be at the second vertical height LV2 (refer to Figure 5 ).

[0088] Refer to Figure 8 , the MRAM device 103 may include a lower conductive region 121, a first interconnect structure 150, a second interconnect structure 160, and / or a lower electrode contact portion 170 disposed on a substrate 110 including the cell region CR and the core / peripheral region C / PR.

[0089] In one or more embodiments, the lower interlayer insulating layer 120, the lower conductive region 121 passing through the lower interlayer insulating layer 120, the first interlayer insulating layer 132, the first interconnect structure passing through the first interlayer insulating layer 132, and the second interlayer insulating layer 142 and the lower electrode contact portion 170 passing through the second interlayer insulating layer 142 may be disposed in the cell region CR. The lower electrode contact portion 170 may be surrounded by the second etch stop layer 141 and the second interlayer insulating layer 142.

[0090] In one or more embodiments, in the core / peripheral region C / PR, an upper insulating layer 144 may also be disposed on the upper etch stop layer 143. For example, the upper insulating layer 144 may include an oxide layer, a silicon nitride layer, or a combination thereof.

[0091] In one or more embodiments, the upper surface of the second interlayer insulating layer 142 in the cell region CR may be at a vertical height higher than the upper surface of the upper etch stop layer 143 in the core / peripheral region C / PR. The upper surface of the second interlayer insulating layer 142 in the cell region CR may be at the same vertical height as the upper surface of the upper insulating layer 144 on the core / peripheral region C / PR.

[0092] Figure 9 FIG. is a cross-sectional view showing an MRAM device 200 according to one or more embodiments.

[0093] Refer to Figure 9, the MRAM device 200 may include a substrate 210, which includes a cell region CR and a core / peripheral region C / PR. On the substrate 210, the cell region CR and the core / peripheral region C / PR may be arranged along a first horizontal direction (X direction) (i.e., offset relative to each other). A device isolation layer 211 may be disposed in the substrate 210 to define an active region AC.

[0094] A cell gate structure 218 may be disposed in the cell region CR of the substrate 210. In an embodiment, the cell gate structure 218 may be a buried gate structure, where a gate line 214 is disposed inside a trench formed in the substrate 210. The gate line 214 may correspond to the word line WL described with reference to Figure 1 description.

[0095] The cell gate structure 218 may include: a gate dielectric layer 212 covering the inner walls and bottom of the trench forming the cell gate structure 218, a gate line 214 extending in a second horizontal direction (Y direction) within the substrate 210, and a buried insulating layer 216 on the gate line 214.

[0096] The gate dielectric layer 212 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the gate dielectric layer 212 may have a dielectric constant of about 10 to about 25. In one or more embodiments, the gate dielectric layer 212 may include at least one material selected from the following materials: hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric layer 212 may include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0097] The gate line 214 may include a metal material or a conductive metal nitride, such as Ti, TiN, Ta, or TaN. The gate line 214 may include doped polysilicon, a metal material (such as W), a conductive metal nitride (such as WN, TiSiN, or WSiN), or a combination thereof.

[0098] The buried insulating layer 216 may include at least one material selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0099] The first impurity region SD1 and the second impurity region SD2 can be respectively disposed on both sides of the unit gate structure 218. In one or more embodiments, the first impurity region SD1 can be a drain region, and the second impurity region SD2 can be a source region. The unit gate structure 218, the first impurity region SD1, and the second impurity region SD2 can form a unit transistor.

[0100] The core / peripheral transistor 225 can be disposed in the core / peripheral region C / P R of the substrate 210. In one or more embodiments, the core / peripheral transistor 225 can be a planar transistor.

[0101] The first interlayer insulating layer 220 and the second interlayer insulating layer 223 covering the unit transistor and the core / peripheral transistor 225 can be disposed on the substrate 210. The first interlayer insulating layer 220 and the second interlayer insulating layer 223 can form the lower interlayer insulating layer 120 described with reference to Figure 2 the description.

[0102] The contact plug 221 passing through the first interlayer insulating layer 220 and the second interlayer insulating layer 223 can be disposed in the cell region CR. The contact plug 221 can be connected to the first impurity region SD1 and can extend within the first interlayer insulating layer 220 and the second interlayer insulating layer 223. The source contact portion 222 passing through the first interlayer insulating layer 220 can be disposed in the cell region CR. The source contact portion 222 can be connected to the second impurity region SD2 and can extend within the first interlayer insulating layer 220.

[0103] In the core / peripheral region C / P R, the contact plug 221 passing through the first interlayer insulating layer 220 and the second interlayer insulating layer 223 can be disposed. The contact plug 221 can be connected to the active region AC and can extend within the first interlayer insulating layer 220 and the second interlayer insulating layer 223.

[0104] The unit transistor, the core / peripheral transistor 225, the contact plug 221, and the source contact portion 222 can form the lower conductive region 121 described with reference to Figure 2 the description.

[0105] In the cell region CR, the first interconnect structure 250 and the lower electrode contact portion 270 may be disposed on the contact plug 221. The first interconnect structure 250 may be similar to the first interconnect structure 150 and may include a first interconnect via 251 and a first interconnect line 252. One or more first interconnect lines 252 disposed in the cell region may also be referred to as cell interconnect lines. The lower electrode contact portion 270 may pass through the second etch stop layer 241 and the second interlayer insulating layer 242 and be connected to the first interconnect structure 250. The first interconnect structure 250 may pass through the first etch stop layer 231 and the first interlayer insulating layer 232 and be connected to the contact plug 221. The lower electrode contact portion 270 and the first interconnect structure 250 may be connected to the first impurity region SD1 through the contact plug 221. The lower electrode contact portion 270 and the first interconnect structure 250 may be connected to the cell transistor through the contact plug 221.

[0106] In the core / peripheral region C / P R, the first interconnect structure 250 and the second interconnect structure 260 may be disposed on the contact plug 221. The second interconnect structure 260 may be similar to the second interconnect structure 160 and may include a first interconnect via 261 and a second interconnect line 262. The second interconnect structure 260 may pass through the second etch stop layer 241 and the second interlayer insulating layer 242 and be connected to the first interconnect structure 250. The first interconnect structure 250 may pass through the first etch stop layer 231 and the first interlayer insulating layer 232 and be connected to the contact plug 221. The first interconnect structure 250 and the second interconnect structure 260 may be connected to the active region AC through the contact plug 221. The first interconnect structure 250 and the second interconnect structure 260 may be connected to the core / peripheral transistor 225 through the contact plug 221. One or more of the first interconnect line 252, the second interconnect line 262, and the upper interconnect line 294 disposed in the core / peripheral region C / P R may be collectively referred to as core / peripheral interconnect lines.

[0107] In the cell region CR, the information storage structure 280 may be disposed on the lower electrode contact portion 270. The information storage structure 280 may be similar to the information storage structure 180 and may include a lower electrode 281, a magnetic tunnel junction structure 285, and an upper electrode 287. The information storage structure 280 may pass through the upper interlayer insulating layer 288 and be connected to the lower electrode contact portion 270. The upper interlayer insulating layer 288 may include an oxide layer, a silicon nitride layer, or a combination thereof.

[0108] The bit line 290 may be disposed on the information storage structure 280. In one or more embodiments, the bit line 290 may extend in a first horizontal direction (X direction). The bit line 290 may include a second barrier pattern 291 and a second metal pattern 292. For example, the second barrier pattern 291 may include a metal nitride (such as tungsten nitride, tantalum nitride, or titanium nitride) and / or a metal (such as tantalum or titanium), and the second metal pattern 292 may include tungsten, copper, or aluminum. The bit line 290 may correspond to the bit line BL described with reference to Figure 1 Description of the bit line BL.

[0109] The upper interconnect structure 295 may be disposed on the second interconnect structure 260 in the core / peripheral region C / P R. The upper interconnect structure 295 may be connected to the second interconnect structure 260 by passing through the upper etch stop layer 243 and the upper interlayer dielectric layer 288. The upper interconnect structure 295 may include upper interconnect vias 293 and upper interconnect lines 294.

[0110] Figures 10 to 18 Is a cross-sectional view showing a method of manufacturing an MRAM device 100 according to an embodiment.

[0111] Referring to Figure 10 , a substrate 110 including a cell region CR and a core / peripheral region C / P R may be provided. A device isolation layer 111 may be formed in the substrate 110. On the substrate 110, a lower interlayer dielectric layer 120 and a lower conductive region 121 passing through the lower interlayer dielectric layer 120 may be formed. The lower interlayer dielectric layer 120 and the lower conductive region 121 may be formed by the same process in the cell region CR and the core / peripheral region C / P R. The lower interlayer dielectric layer 120 and the lower conductive region 121 may be at the same vertical height in the cell region CR and the core / peripheral region C / PR.

[0112] Referring to Figure 11 , a first etch stop layer 131, a first interlayer dielectric layer 132, and a first interconnect structure 150 passing through the first etch stop layer 131 and the first interlayer dielectric layer 132 may be formed on the lower interlayer dielectric layer 120. Specifically, the first etch stop layer 131 and the first interlayer dielectric layer 132 may be formed sequentially, and the first interconnect via 151 and the first interconnect line 152 may be formed sequentially.

[0113] The first etch stop layer 131, the first interlayer dielectric layer 132, and the first interconnect structure 150 passing through the first etch stop layer 131 and the first interlayer dielectric layer 132 may be formed in the cell region CR and the core / peripheral region C / P R. The first etch stop layer 131, the first interlayer dielectric layer 132, and the first interconnect structure 150 passing through the first etch stop layer 131 and the first interlayer dielectric layer 132 may be at the same vertical height in the cell region CR and the core / peripheral region C / P R.

[0114] Referring to Figure 12 , a second etch stop layer 141 and a second interlayer insulating layer 142 can be formed on the first interlayer insulating layer 132. The second etch stop layer 141 and the second interlayer insulating layer 142 can be formed in the cell region CR and the core / peripheral region C / PR by the same process. The second etch stop layer 141 and the second interlayer insulating layer 142 can be at the same vertical height in the cell region CR and the core / peripheral region C / PR.

[0115] Subsequently, a second interconnect structure 160 passing through the second etch stop layer 141 and the second interlayer insulating layer 142 can be formed in the core / peripheral region C / PR. The second interconnect structure 160 can not be formed in the cell region CR. Specifically, the second etch stop layer 141 and the second interlayer insulating layer 142 can be sequentially formed in the core / peripheral region C / PR, and the second interconnect via 161 and the second interconnect line 162 can be sequentially formed.

[0116] Referring to Figure 13 , in the cell region CR and the core / peripheral region C / PR, an upper etch stop layer 143 can be formed on the second interlayer insulating layer 142. The upper etch stop layer 143 can be at the same vertical height in the cell region CR and the core / peripheral region C / PR. In some other embodiments, an upper insulating layer 144 can also be formed on the upper etch stop layer 143 (referring to Figure 8 ).

[0117] Subsequently, a lower electrode contact hole 170H can be formed in the cell region CR, and the lower electrode contact hole 170H sequentially passes through the upper etch stop layer 143, the second interlayer insulating layer 142, and the second etch stop layer 141. In the cell region CR, the first interconnect line 152 of the first interconnect structure 150 can be exposed through the lower electrode contact hole 170H.

[0118] Referring to Figure 14 , in the cell region CR, a lower electrode contact portion 170 can be formed to fill the lower electrode contact hole 170H.

[0119] Referring to Figure 15 , in the cell region CR and the core / peripheral region C / PR, a free first electrode layer P181, a free magnetic tunnel junction layer P185, and a free second electrode layer P187 can be sequentially formed on the lower electrode contact portion 170.

[0120] Referring to Figure 16 , in the cell region CR, an upper electrode 187 can be formed by removing a part of the free second electrode layer P187. In this case, in the core / peripheral region C / PR, the free second electrode layer P187 can be removed to expose the free magnetic tunnel junction layer P185.

[0121] Referring to Figure 17 , in the cell region CR, the lower electrode 181 and the magnetic tunnel junction structure 185 can be formed by etching portions of the free first electrode layer P181 and the free magnetic tunnel junction layer P185. Etching portions of the free first electrode layer P181 and the free magnetic tunnel junction layer P185 can include using the upper electrode 187 as an etch mask.

[0122] In one or more embodiments, the step of forming the lower electrode 181 and the magnetic tunnel junction structure 185 by removing portions of the free first electrode layer P181 and the free magnetic tunnel junction layer P185 can be performed using an ion beam etching (IBE) process. When removing portions of the free first electrode layer P181 and the free magnetic tunnel junction layer P185, portions of the upper etch stop layer 143 and the second interlayer insulating layer 142 surrounding the lower electrode contact portion 170 can also be removed.

[0123] When removing portions of the free first electrode layer P181 and the free magnetic tunnel junction layer P185 in the cell region CR, the free magnetic tunnel junction layer P185 and the free second electrode layer P187 can be removed in the core / periphery region C / P R without removing the upper etch stop layer 143 and the second interlayer insulating layer 142. To this end, a capping block can be formed on the upper etch stop layer 143 in the etching process. The capping block can be removed later.

[0124] Referring to Figure 18 , in the cell region CR, the second interlayer insulating layer 142 surrounding the upper portion of the lower electrode contact portion 170 can be formed again. As a result, the MRAM device 100 can be formed.

[0125] In one or more embodiments according to the technical idea of the present disclosure, as described above, in the cell region CR, the second interconnect structure 160 may not exist, and the first interconnect structure 150 may be connected to the lower electrode contact portion 170 as the uppermost interconnect structure. Thus, when a portion of the free first electrode layer P181 and the free magnetic tunnel junction layer P185 is removed and also a portion of the upper etch stop layer 143 and the second interlayer insulating layer 142 is removed, the first interconnect structure 150 is not exposed. In other words, in an embodiment according to the technical idea of the present disclosure, as in the cell region CR, the first interconnect structure 150 as the uppermost interconnect structure is connected to the lower electrode contact portion 170, and the lower electrode contact portion 170 can ensure a sufficient vertical height. Therefore, the lower interconnect structure (the first interconnect structure 150) is not exposed during the IBE process. In the comparative example, when the second interconnect structure 160 is provided in the cell region CR, as in the core / peripheral region C / PR, the second interconnect structure 160 is below the lower electrode contact portion 170 and is connected to the lower electrode contact portion 170. When a portion of the free first electrode layer P181 and the free magnetic tunnel junction layer P185 is removed and also a portion of the upper etch stop layer 143 and the second interlayer insulating layer 142 is removed, the second interconnect structure 160 may be exposed and cause defects. That is, an MRAM device 100 having improved performance and reliability can be provided according to an embodiment of the technical idea of the present disclosure.

[0126] In one or more embodiments according to the technical idea of the present disclosure, since the lower electrode contact portion 170 ensures a sufficient vertical height, the key open mask process can be skipped in the process of manufacturing the MRAM device 100. Specifically, in the comparative example where the lower electrode contact portion 170 does not ensure a sufficient vertical height, the key open mask process must be performed to align the key of the lower electrode contact portion 170. That is, an MRAM device 100 having a reduced manufacturing process can be provided according to an embodiment of the technical idea of the present disclosure.

[0127] Although the present disclosure has been specifically shown and described with reference to its embodiments, it should be understood that various changes in form and detail can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A magnetoresistive random access memory (MRAM) device, comprising: A cell region on a substrate; A core peripheral region on the substrate and adjacent to the cell region in a horizontal direction; A first interlayer insulating layer in the cell region and the core peripheral region; A second interlayer insulating layer on the first interlayer insulating layer; A first interconnecting line in the first interlayer insulating layer, wherein the first interconnecting line is in the cell region and the core peripheral region; A second interconnecting line in the second interlayer insulating layer, wherein the second interconnecting line is in the core peripheral region and connected to the first interconnecting line; A lower electrode contact portion on the first interconnecting line in the cell region; and A magnetic tunnel junction structure on the lower electrode contact portion, wherein the lower electrode contact portion and the second interconnecting line overlap each other in the horizontal direction.

2. The MRAM device according to claim 1, wherein The second interconnecting line is above the first interconnecting line in the core peripheral region, and an upper surface of the second interconnecting line is at a vertical height that is the same as or lower than a vertical height of a lower surface of the magnetic tunnel junction structure.

3. The MRAM device according to claim 1, wherein, The lower electrode contact portion contacts the first interconnecting line.

4. The MRAM device according to claim 1, further comprising: A lower electrode between the lower electrode contact portion and the magnetic tunnel junction structure; and And An upper electrode spaced apart from the lower electrode, wherein the magnetic tunnel junction structure is between the lower electrode and the upper electrode.

5. The MRAM device according to claim 1, wherein, An upper surface of the first interlayer insulating layer is coplanar with an upper surface of the first interconnecting line.

6. The MRAM device according to claim 1 further comprises: An interconnect via connecting the second interconnecting line to the first interconnecting line, wherein the interconnect via is surrounded by the second interlayer insulating layer, and wherein the interconnect via overlaps the lower electrode contact portion in the horizontal direction.

7. The MRAM device according to claim 6, further comprising: An etch stop layer between the first interlayer insulating layer and the second interlayer insulating layer, wherein a part of the lower electrode contact portion is surrounded by the etch stop layer.

8. The MRAM device according to claim 1, wherein, A vertical thickness of the lower electrode contact portion is greater than a vertical thickness of the second interlayer insulating layer.

9. The MRAM device according to claim 1, wherein, The lower electrode contact portion penetrates through the second interlayer insulating layer.

10. A magnetoresistive random access memory (MRAM) device, comprising: A cell region on a substrate; A core peripheral region on the substrate and adjacent to the cell region in a horizontal direction; A cell transistor in the cell region; A core peripheral transistor in the core peripheral region; A cell interconnecting line in the cell region, wherein the cell interconnecting line is connected to the cell transistor; A core peripheral interconnecting line in the core peripheral region, wherein the core peripheral interconnecting line is connected to the core peripheral transistor; A lower electrode contact portion connected to the cell interconnecting line; and A magnetic tunnel junction structure on the lower electrode contact portion, wherein an upper surface of each of the cell interconnecting line and the core peripheral interconnecting line is at a vertical height that is the same as or lower than a vertical height of a lower surface of the magnetic tunnel junction structure, and Wherein, at least a part of the vertical height of the core peripheral interconnect overlaps with the vertical height of the lower electrode contact portion in the horizontal direction.

11. The MRAM device according to claim 10, further comprising: A plurality of cell interconnects, in the cell region including the cell interconnects, wherein the plurality of cell interconnects are connected to the cell transistors; and A plurality of core peripheral interconnects, in the core peripheral region including the core peripheral interconnects, wherein the plurality of core peripheral interconnects are connected to the core peripheral transistors, Wherein, the vertical height of the uppermost cell interconnect among the plurality of cell interconnects is lower than the vertical height of the uppermost core peripheral interconnect among the plurality of core peripheral interconnects.

12. The MRAM device according to claim 11, wherein, The lower electrode contact portion contacts the uppermost cell interconnect.

13. The MRAM device according to claim 10, further comprising: A lower electrode, between the lower electrode contact portion and the magnetic tunnel junction structure; And An upper electrode, spaced apart from the lower electrode, wherein the magnetic tunnel junction structure is between the lower electrode and the upper electrode.

14. The MRAM device according to claim 10, further comprising: A plurality of core peripheral interconnects, in the core peripheral region including the core peripheral interconnects, wherein the plurality of core peripheral interconnects are connected to the core peripheral transistors, Wherein, the vertical height of the lower surface of the lower electrode contact portion is lower than the vertical height of the upper surface of the uppermost core peripheral interconnect among the plurality of core peripheral interconnects.

15. The MRAM device according to claim 10 further comprises: An interlayer insulating layer, the core peripheral interconnects passing through the interlayer insulating layer, Wherein, the vertical height of the upper surface of the interlayer insulating layer is higher than the vertical height of the lower surface of the lower electrode contact portion.

16. The MRAM device according to claim 10, further comprising: Cell contact plugs, connecting the cell interconnects to the cell transistors; And Core peripheral contact plugs, connecting the core peripheral interconnects to the core peripheral transistors.

17. The MRAM device according to claim 10 further includes: A bit line, on the magnetic tunnel junction structure.

18. A magnetoresistive random access memory (MRAM) device, comprising: A cell region, on a substrate; A core peripheral region, on the substrate and adjacent to the cell region in the horizontal direction; Cell transistors, in the cell region; Core peripheral transistors, in the core peripheral region; A cell interlayer insulating layer, on the cell transistors; A core peripheral interlayer insulating layer, on the core peripheral transistors; A plurality of cell interconnects, connected to the cell transistors; A plurality of core peripheral interconnects, connected to the core peripheral transistors; A lower electrode contact portion, on the uppermost cell interconnect among the plurality of cell interconnects; An information storage structure, on the lower electrode contact portion, the information storage structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode, wherein the lower electrode, the magnetic tunnel junction structure, and the upper electrode are stacked in sequence; and A bit line, on the information storage structure, Among them, the multiple unit interconnection lines pass through the unit interlayer insulating layer at a vertical height that is the same as or lower than the vertical height of the lower surface of the magnetic tunnel junction structure. Among them, the multiple core-periphery interconnection lines pass through the core-periphery interlayer insulating layer at a vertical height that is the same as or lower than the vertical height of the lower surface of the magnetic tunnel junction structure, and Among them, the lower electrode contact portion overlaps with the uppermost core-periphery interconnection line among the multiple core-periphery interconnection lines in the horizontal direction.

19. The MRAM device according to claim 18, wherein, The lower electrode contact portion contacts the uppermost unit interconnection line.

20. The MRAM device according to claim 18, wherein, The vertical height of the uppermost unit interconnection line is lower than the vertical height of the uppermost core-periphery interconnection line.

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