Thin film transistor and preparation method thereof, substrate and display device

Abstract

The embodiment of the invention provides a thin film transistor, a preparation method thereof, a substrate and a display device. The thin film transistor comprises a gate electrode, a gate insulating layer, an active layer and a source and drain electrode layer which are sequentially arranged on one side of a substrate in a stacked mode, the source and drain electrode layer comprises a first electrode and a second electrode which are arranged at intervals in the first direction, and the intersecting part of the orthographic projection of the gate electrode on the substrate and the orthographic projection of the first electrode on the substrate is a first overlapping part; the orthographic projection of the first overlapping part on the substrate is located in the orthographic projection of the active layer on the substrate. According to the technical scheme, the DGS occurrence rate can be effectively reduced, the product yield is improved, and the stability of the product quality is guaranteed.

Description

[0001] This application is a divisional application of a Chinese patent application with an application date of April 26, 2023, an application number of 202310464596.X, and an invention title of "A Thin Film Transistor and Its Manufacturing Method, Substrate, and Display Device". Technical Field

[0002] The present disclosure relates to the field of display technologies, and particularly to a thin film transistor and its manufacturing method, a substrate, and a display device. Background Art

[0003] Liquid Crystal Displays (LCDs) have been widely used and gradually become dominant due to their characteristics such as small size, low power consumption, no radiation, and high display resolution. In related technologies, thin film transistors (TFTs) are widely used in display devices. However, due to various problems in thin film transistors, the yield of products is affected. Summary of the Invention

[0004] Embodiments of the present disclosure provide a thin film transistor and its manufacturing method, a substrate, and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a thin film transistor, including a gate electrode, a gate insulating layer, an active layer, and a source-drain electrode layer that are sequentially stacked on one side of a substrate. The source-drain electrode layer includes a first pole and a second pole that are spaced apart along a first direction. The overlapping part of the orthographic projection of the gate electrode on the substrate and the orthographic projection of the first pole on the substrate is a first overlapping part, and the orthographic projection of the first overlapping part on the substrate is located within the orthographic projection of the active layer on the substrate.

[0006] In some possible implementation manners, the active layer includes a first part and a second part that are connected to each other. The first part extends along a second direction, and the second part extends along the first direction. The projection of the first overlapping part on the substrate is located within the orthographic projection of the first part on the substrate, and the first direction intersects with the second direction.

[0007] In some possible implementation manners, in the first direction, the boundary of the orthographic projection of the first overlapping part on the substrate is located inside the boundary of the orthographic projection of the first part on the substrate, and the distance between the boundary of the first part and the boundary of the first overlapping part is 1.0 μm - 3.5 μm.

[0008] In some possible implementation manners, in the second direction, the orthographic projection boundary of the first overlapping portion on the substrate is located inside the orthographic projection boundary of the first portion on the substrate, and the distance between the boundary of the first portion and the boundary of the first overlapping portion is 1.0 μm - 3.5 μm.

[0009] In some possible implementation manners, in the second direction, the orthographic projection boundary of the gate electrode on the substrate is located inside the orthographic projection boundary of the first portion on the substrate, and the orthographic projection boundary of the first portion on the substrate is located inside the orthographic projection boundary of the first pole on the substrate.

[0010] In some possible implementation manners, first sidewalls are formed on both sides of the gate electrode, second sidewalls are formed on both sides of the first pole, and the slope angle of the second sidewalls is smaller than the slope angle of the first sidewalls.

[0011] In some possible implementation manners, the dimension range of the first pole in the first direction is 2 μm - 6 μm.

[0012] In some possible implementation manners, a recessed portion is provided on a side boundary of the first portion away from the second portion, and the groove edge of the recessed portion is flush with the boundary of the first pole away from the second pole.

[0013] In some possible implementation manners, the recessed portion includes a first side and a second side located on both sides of the groove edge, and the angle range between the first side or the second side and the groove edge is 120° - 150°.

[0014] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for manufacturing a thin film transistor, including:

[0015] Forming a gate electrode, a gate insulating layer, an active layer, and a source-drain electrode layer on one side of a substrate, the source-drain electrode layer including a first pole and a second pole spaced apart in the first direction;

[0016] The overlapping portion of the orthographic projection of the gate electrode on the substrate and the orthographic projection of the first pole on the substrate is the first overlapping portion, and the orthographic projection of the first overlapping portion on the substrate is located inside the orthographic projection of the active layer on the substrate.

[0017] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a substrate, including: a substrate and the thin film transistor according to any one of the embodiments of the present disclosure, the thin film transistor being disposed on the substrate.

[0018] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the substrate according to the embodiments of the present disclosure.

[0019] The technical solutions of the embodiments of the present disclosure can achieve the following beneficial effects: the incidence rate of DGS can be effectively reduced, the yield of products can be improved, and the stability of product quality can be ensured.

[0020] The above summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In the drawings, unless otherwise specified, the same reference numerals throughout the several views represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments in accordance with the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0022] Figure 1 Schematic diagram of a thin film transistor under an electron microscope in the related art;

[0023] Figure 2 Microscopic morphology diagram of a thin film transistor provided by an embodiment of the present disclosure;

[0024] Figure 3A Top view of a thin film transistor in the related art;

[0025] Figure 3B is Figure 3A Cross-sectional view of the thin film transistor in [[]] along the section line A-A;

[0026] Figure 3C is Figure 3A Cross-sectional view of the thin film transistor in [[]] along the section line B-B;

[0027] Figure 4A Top view of a thin film transistor according to an embodiment of the present disclosure;

[0028] Figure 4B is Figure 4A Cross-sectional view of the thin film transistor in [[]] along the section line C-C;

[0029] Figure 5 Top view of another thin film transistor according to an embodiment of the present disclosure;

[0030] Figure 6 Top view of yet another thin film transistor according to an embodiment of the present disclosure;

[0031] Figure 7 Cross-sectional view of a thin film transistor according to an embodiment of the present disclosure;

[0032] Figure 8 Top view of a thin film transistor according to an embodiment of the present disclosure;

[0033] Figure 9Schematic cross-sectional view of a substrate according to an embodiment of the present disclosure.

[0034] Description of reference numerals:

[0035] 100, gate electrode; 200, gate insulating layer; 300, active layer; 400, source-drain metal layer; 410, first pole; 420, second pole; 310, recess; 311, groove edge; 312, first side; 313, second side. Detailed implementation manners

[0036] In the following, only some exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive.

[0037] Thin-film transistors formed using Oxide technology have characteristics such as good uniformity and high mobility, and occupy an important position in the field of thin-film transistors. In order to reduce power consumption, oxide thin-film transistors are widely used in various display panels, especially in high-end display panels. However, the defect rate of thin-film transistors based on oxide technology is higher than that of thin-film transistors based on silicon technology, which seriously affects product quality and reduces product yield.

[0038] As the production volume of oxide thin-film transistor products increases, it is urgent to solve various defects of oxide thin-film transistors. Among them, the short-circuit defect between the gate and the source-drain (DGS Issue, Data-Gate Short Issue) is particularly a pain point of oxide thin-film transistors. For example, within a month, the defect rate of products due to DGS on a certain production line is as high as 6429 ppm, which not only reduces product quality but also seriously affects the production line yield.

[0039] Figure 1 Schematic diagram of a thin-film transistor under an electron microscope in the related art. The inventor has found through research that the main reasons for DGS are as follows: As Figure 1 shown, there is an insulating layer, that is, a gate insulating layer GI, between the source-drain electrode layer SD and the gate electrode Gate. During the film formation process of the gate insulating layer GI of the thin-film transistor, foreign substances in the chamber environment, such as particles (Particle), fall into the gate insulating layer GI, and since the subsequently deposited film cannot perfectly wrap this foreign substance, and the film quality around the foreign substance is loose and thus prone to form holes. When the display module is lit, there is an alternating electric field between the gate electrode Gate and the source-drain electrode layer SD, and the metal electrode near the foreign substance is affected by the alternating electric field and diffuses along the foreign substance and the surrounding film layer to form a conductive channel, thus causing a short circuit between the gate electrode Gate and the source-drain electrode layer SD.

[0040] By statistically analyzing the products with DGS occurring in the production line, the inventor found that DGS mostly occurs at the ramp of the drain metal to the gate metal. Figure 2 This is a micrograph of a thin film transistor provided by an embodiment of the present disclosure. As Figure 2 shown, DGS appears in the product at the ramp of the drain metal to the gate metal. To solve the DGS problem, the production environment and conditions of the gate insulating layer GI can be optimized. At the same time, rework (Sorting) can be carried out through aging tests at the module stage, that is, defective products in the products are screened out, thereby reducing the incidence of DGS. However, this still cannot completely solve the DGS problem. Therefore, to solve the DGS problem, optimization or improvement is required in all aspects of product design and production.

[0041] Figure 3A This is a planar schematic diagram of a thin film transistor in the related art; Figure 3B This is Figure 3A a cross-sectional view of the thin film transistor in Figure 3C along the section line A-A; Figure 3A This is Figures 3A - 3C a cross-sectional view of the thin film transistor in Figure 3A along the section line B-B. Referring to

[0042] As Figure 3C shown, the active layer 300 is strip-shaped and extends along the first direction X. The first pole 410 extends along the second direction Y. The first direction X intersects with the second direction Y, and both the first direction X and the second direction Y are set along the direction parallel to the substrate P. The overlapping part of the orthographic projection of the gate electrode 100 on the substrate P and the orthographic projection of the first pole 410 on the substrate P is the first overlapping part S. The dimension of the first overlapping part S along the second direction Y is greater than the dimension of the active layer 300 along the second direction Y. That is, in the second direction Y, the boundary of the orthographic projection of the active layer 300 on the substrate P is located inside the boundary of the orthographic projection of the first overlapping part S on the substrate P.

[0043] To solve the DGS problem of thin-film transistors in related technologies, embodiments of the present disclosure provide a thin-film transistor. The technical solution of the present disclosure will be introduced in detail through embodiments below.

[0044] Figure 4A It is a top view of a thin-film transistor in an embodiment of the present disclosure; Figure 4B is Figure 4A a cross-sectional view of the thin-film transistor in along the section line C-C. As Figure 4A and Figure 4B shown, a thin-film transistor provided by an embodiment of the present disclosure includes a gate electrode 100, a gate insulating layer 200, an active layer 300, and a source-drain electrode layer 400 that are sequentially stacked on one side of a substrate P. The source-drain electrode layer 400 includes a first electrode 410 and a second electrode 420 that are spaced apart along a first direction X. Exemplarily, the first electrode 410 may be a source electrode, and the second electrode 420 may be a drain electrode; alternatively, the first electrode 410 may be a drain electrode, and the second electrode 420 may be a source electrode.

[0045] As Figure 4B shown, exemplarily, in the direction perpendicular to the substrate P of the thin-film transistor of the embodiment of the present disclosure, the gate electrode 100 is located below the first electrode 410 and the second electrode 420, that is, the gate electrode 100 is disposed closer to the substrate P side. Such a thin-film transistor can be called a bottom-gate thin-film transistor.

[0046] In the direction perpendicular to the substrate P, the gate electrode 100, the gate insulating layer 200, the active layer 300, and the source-drain electrode layer 400 are sequentially stacked along the direction away from the substrate P. The gate electrode 100 is located on the substrate P, the gate insulating layer 200 is located on the side of the gate electrode 100 away from the substrate P, the active layer 300 is located on the side of the gate insulating layer 200 away from the substrate P, and the source-drain electrode layer 400 is disposed on the side of the active layer 400 away from the substrate P.

[0047] Referring to Figure 4A , the overlapping part of the orthographic projection of the gate electrode 100 on the substrate P and the orthographic projection of the first electrode 410 on the substrate P is a first overlapping part S, and the orthographic projection of the first overlapping part S on the substrate P is located within the orthographic projection of the active layer 300 on the substrate P.

[0048] Exemplarily, the first electrode 410 extends along the second direction Y. The dimension of the gate electrode 100 in the second direction Y is less than or equal to the dimension of the first electrode 410 on the substrate P, that is, the boundary of the first electrode 410 in the second direction Y is located outside the boundary of the gate electrode 100 in the second direction Y. The dimension of the gate electrode 100 in the first direction X is greater than the dimension of the first electrode 410 in the first direction X, that is, the boundary of the gate electrode 100 in the first direction X is located outside the boundary of the first electrode 410 in the first direction X. The first direction X and the second direction Y are not parallel, or rather, the first direction X intersects with the second direction Y. Exemplarily, the first direction X may be perpendicular to the second direction Y. The first overlapping portion S represents the overlapping portion of the positive projection of the gate electrode 100 on the substrate P and the positive projection of the first electrode 410 on the substrate P, that is, the intersecting portion of the gate electrode 100 and the first electrode 410 on the plane parallel to the substrate P. The boundary of the first overlapping portion S along the first direction X is a part of the boundary of the positive projection of the first electrode 410 on the substrate P along the first direction Y, and the boundary of the first overlapping portion S along the second direction Y is a part of the boundary of the positive projection of the gate electrode 100 on the substrate P along the second direction Y.

[0049] The positive projection of the first overlapping portion S on the substrate P is located within the positive projection of the active layer 300 on the substrate P. In this way, in the direction perpendicular to the substrate P, there are all gate insulating layer 200 and active layer 300 between the gate electrode 100 and the first electrode 410, thereby increasing the vertical distance between the gate electrode 100 and the first electrode 410.

[0050] The thin film transistor of the embodiment of the present disclosure is a bottom-gate thin film transistor. The gate electrode 100 is located on the substrate P, the gate insulating layer 200 is located on the side of the gate electrode 100 away from the substrate P, the active layer 300 is located on the side of the gate insulating layer 200 away from the substrate P, the source-drain electrode layer 400 is disposed on the side of the active layer 400 away from the substrate P. The intersecting portion of the positive projection of the gate electrode 100 on the substrate P and the positive projection of the first electrode 410 on the substrate P is the first overlapping portion S. The positive projection of the first overlapping portion S on the substrate P is located within the positive projection of the active layer 300 on the substrate P. For such a thin film transistor, in the direction perpendicular to the substrate P, there are all gate insulating layer 200 and active layer 300 between the gate electrode 100 and the first electrode 410. In this way, the vertical distance between the gate electrode 100 and the first electrode 410 can be increased, and the electron movement distance is increased. Even if there are impurity particles (Particles) in the gate insulating layer 200, the active layer 300 on the upper side of the gate insulating layer 200 is still an insulating layer, thereby preventing the gate electrode 100 and the first electrode 410 from short-circuiting, effectively reducing the occurrence rate of DGS of the thin film transistor, and improving the quality of the thin film transistor.

[0051] In one embodiment, the material of the gate electrode 100 may include a metal, and the shape of the gate electrode 100 may include a cube or a cylinder, etc. When the shape of the gate electrode 100 is a cube, the orthographic projection of the gate electrode 100 on the substrate is a rectangle. The embodiments of the present disclosure do not specifically limit the shape, material, thickness, etc. of the gate electrode.

[0052] In one embodiment, the material of the active layer 300 may include an oxide semiconductor material. Exemplarily, the active layer 300 may adopt indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), etc. The embodiments of the present disclosure do not specifically limit the oxide semiconductor material, and it can be set according to actual usage requirements. Exemplarily, the shape of the active layer 300 may include a cube, a cylinder, etc. When the shape of the active layer 300 is a cube, the shape of the orthographic projection of the active layer 300 on the substrate P is a rectangle.

[0053] In the related art, a gate insulating layer 200 is covered on the side of the gate electrode 100 facing away from the substrate. The gate insulating layer 200 is disposed between the gate electrode 100 and the active layer 300. Only the gate insulating layer 200 exists at the edge of the gate electrode 100 and the first electrode 410. Considering the comprehensive process conditions, the dimension of the gate insulating layer 200 in the direction perpendicular to the substrate P is generally 3500 angstroms or 4000 angstroms. Foreign matter adheres during the film formation process of the gate insulating layer 200, resulting in a loose film layer at the foreign matter adhesion site. When foreign matter exists, when an alternating current signal is applied between the gate electrode 100 and the first electrode 410 of the thin film transistor, there is a large voltage difference between the gate electrode 100 and the first electrode 410, forming an alternating electric field. The electric field formed between the gate electrode 100 and the first electrode 410 can break down foreign matter or other weak links, causing the metal electrode near the foreign matter to diffuse along the loose film layer around the foreign matter under the influence of the alternating electric field to form a conductive channel. Refer to Figure 4B As shown, in the thin film transistor of the embodiments of the present disclosure, the gate insulating layer 200 protrudes on the side of the gate electrode 100 facing away from the substrate P, and the active layer 300 covers the protrusion. In Figure 4BIn [the structure], the size of the active layer 300 along the second direction Y is greater than the size of the gate electrode 100 along the second direction Y, so that the entire active layer 300 exists under the first electrode 410 on the gate electrode 100. In this way, the gate insulating layer 200 and the active layer 300 exist entirely between the gate electrode 100 and the first electrode 410. Even if there are foreign objects in the gate insulating layer 200, the active layer 300 on the side of the gate insulating layer 200 away from the substrate P can act as an insulating layer, which can increase the vertical distance between the gate electrode 100 and the first electrode 410, increase the electron movement distance, and thus reduce the short - circuit incidence rate between the gate electrode 100 and the first electrode 410.

[0054] In one embodiment, the gate insulating layer 200 can provide good insulation between the gate electrode 100 and the active layer and the source - drain electrode layer. The embodiments of the present disclosure do not make specific limitations on the thickness, shape, material, etc. of the gate insulating layer 200. Exemplarily, the material of the gate insulating layer 200 can be any one of silicon nitride, silicon oxide, or silicon oxynitride. For example, the shape of the gate insulating layer 200 can include a cube, a cylinder, etc. When the shape of the gate insulating layer 200 is a cube, the shape of the orthographic projection of the gate insulating layer 200 on the substrate is a rectangle.

[0055] In one embodiment, the source - drain electrode layer 400 can include Figure 4A a first electrode 410 and a second electrode 420 arranged at intervals along the first direction X as shown. The materials of both the first electrode 410 and the second electrode 420 include metals. The shapes and sizes of the first electrode 410 and the second electrode 420 are different, and the shapes of both the first electrode 410 and the second electrode 420 can include a cube, a cylinder, etc. It should be noted that the embodiments of the present disclosure do not make specific limitations on the materials, shapes, and thicknesses of the first electrode 410 and the second electrode 420.

[0056] In one implementation manner, the active layer 300 includes a first part 300a and a second part 300b connected to each other. The first part 300a extends along the second direction Y, and the second part 300b extends along the first direction X. The orthographic projection of the first overlapping part S on the substrate P is located within the orthographic projection of the first part 300a on the substrate P. The first direction X and the second direction Y intersect. In this way, the second part 300b can be covered in the area where the gate electrode 100 is directly opposite the first electrode 410 in the direction perpendicular to the substrate, reducing the capacitance between the second part 300b and the gate electrode 100 and the second electrode. Exemplarily, the first direction X and the second direction Y are perpendicular to each other.

[0057] Referring to Figure 4A , the active layer 300 is in a T - shape along the first direction X. The first part 300a is located Figure 4A on the right side in Figure 4AOn the left side in [description], the second part 300b has a dimension in the second direction Y that is greater than the dimension of the first part 300a in the first direction. The first pole 410 extends along the second direction Y, and the boundary of the first pole 410 in the first direction X is located within the boundary of the first part 300a in the first direction X. The orthographic projection of the first part 300a on the substrate 100 overlaps partially with the orthographic projection of the first pole 410 on the substrate, and the orthographic projection of the second part 300b on the substrate 100 overlaps partially with the orthographic projection of the second pole 420 on the substrate. Exemplarily, the orthographic projection of the second part 300b on the substrate 100 is located within the orthographic projection of the second pole 420 on the substrate.

[0058] Figure 5 This is a top view of another thin-film transistor according to an embodiment of the present disclosure. In one embodiment, in the first direction X, the boundary of the orthographic projection of the first overlapping portion S on the substrate P is located inside the boundary of the orthographic projection of the first part 300a on the substrate P, and the distance between the boundary of the first part 300a and the boundary of the first overlapping portion S is 1.0 μm - 3.5 μm. The boundary of the first part 300a refers to the boundaries on both sides of the orthographic projection of the first part 300a on the substrate in the first direction, and the boundary of the first overlapping portion S refers to the boundaries on both sides of the orthographic projection of the first overlapping portion S on the substrate in the first direction. It should be noted that the "distance between the boundary of A and the boundary of B" in the present disclosure should be understood as the distance between the boundary of the orthographic projection of A on the substrate and the boundary of the orthographic projection of B on the substrate.

[0059] Exemplarily, the fact that the boundary of the orthographic projection of the first overlapping portion S on the substrate P is located inside the boundary of the orthographic projection of the first part 300a on the substrate P can be understood as that the boundary of the orthographic projection of the first part 300a on the substrate extends beyond the boundary of the orthographic projection of the first overlapping portion S on the substrate P by a certain distance. The boundaries of both the first part 300a and the first overlapping portion S are straight lines along the second direction, or the boundaries of the first part 300a and the first overlapping portion S can also be oblique lines forming an angle with the second direction, or the boundaries of the first part 300a and the first overlapping portion S can also be arcs.

[0060] Referring to Figure 5 As shown, in one embodiment, in the first direction, the distance between the boundary of the first part 300a and the boundary of the first overlapping portion S is c, and the range of c can be 1.0 μm - 3.5 μm. For example, c can be 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, etc. In this way, the vertical distance between the gate electrode and the first pole in some partial regions on both sides in the first direction X increases by the thickness of the active layer 300, thereby preventing the gate electrode and the first pole from being short-circuited.

[0061] Exemplarily, in one embodiment, the range of c can be 1.3 μm - 2.5 μm. For example, c can be 1.3 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2.1 μm, 2.3 μm, 2.5 μm.

[0062] Figure 6 FIG. 4 is a top view of another thin film transistor according to an embodiment of the present disclosure. In one embodiment, in the second direction Y, the positive projection boundary of the first overlapping portion S on the substrate P is located inside the positive projection boundary of the first portion 300a on the substrate P, and the distance between the boundary of the first portion 300a and the boundary of the first overlapping portion S is 1.0 μm - 3.5 μm. The boundary of the first portion 300a represents the boundaries on both sides of the positive projection of the first portion 300a on the substrate in the second direction, and the boundary of the first overlapping portion S represents the boundaries on both sides of the positive projection of the first overlapping portion S on the substrate in the second direction. Exemplarily, the fact that the positive projection boundary of the first overlapping portion S on the substrate P is located inside the positive projection boundary of the first portion 300a on the substrate P can be understood as that in the second direction, the positive projection boundary of the first portion 300a on the substrate extends beyond the positive projection boundary of the first overlapping portion S on the substrate P by a certain distance. The boundaries of both the first portion 300a and the first overlapping portion S are straight lines along the first direction, or the boundaries of the first portion 300a and the first overlapping portion S can also be oblique lines forming an angle with the first direction, or the boundaries of the first portion 300a and the first overlapping portion S can also be arcs.

[0063] Refer to Figure 6 As shown, in one embodiment, in the second direction, the distance between the boundary of the first portion 300a and the boundary of the first overlapping portion S is a, and the range of a can be 1.0 μm - 3.5 μm. For example, a can be 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, etc. In this way, the vertical distance between the gate electrode and the first electrode in partial regions on both sides of the second direction Y increases the thickness of the active layer 300, thereby preventing the gate electrode and the first electrode from being short-circuited.

[0064] Exemplarily, in one embodiment, the range of a can be 1.3 μm - 2.5 μm. For example, a can be 1.3 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2.1 μm, 2.3 μm, 2.5 μm

[0065] In one embodiment, in the first direction X, the orthographic projection boundary of the first overlapping portion S on the substrate P is located inside the orthographic projection boundary of the first portion 300a on the substrate P, and the distance between the boundary of the first portion 300a and the boundary of the first overlapping portion S is 1.0 μm - 3.5 μm. In the second direction Y, the orthographic projection boundary of the first overlapping portion on the substrate is located inside the orthographic projection boundary of the first portion on the substrate, and the distance between the boundary of the first portion and the boundary of the first overlapping portion is 1.0 μm - 3.5 μm.

[0066] Referring to Figure 4A As shown, in the first direction, the distance between the boundary of the first portion 300a and the boundary of the first overlapping portion S is c, and in the second direction, the distance between the boundary of the first portion 300a and the boundary of the first overlapping portion S is a. That is, the first portion 300a is widened by a certain distance relative to the first overlapping portion in both the first direction and the second direction, which further reduces the incidence of short circuits between the gate electrode and the first pole.

[0067] Referring to Figure 4A As shown, in one embodiment, in the second direction Y, the orthographic projection boundary of the gate electrode 100 on the substrate P is located inside the orthographic projection boundary of the first portion 300a on the substrate P, and the orthographic projection boundary of the first portion 300a on the substrate P is located inside the orthographic projection boundary of the first pole 410 on the substrate 100. That is, in the second direction Y, the size of the first portion 300a is larger than the size of the gate electrode 100, the boundary of the first portion 300a extends beyond the boundary of the gate electrode 100, the size of the first pole 410 is larger than the size of the first portion 300a, and the boundary of the first pole 410 extends beyond the boundary of the first portion 300a.

[0068] Figure 7 A cross-sectional view of a thin film transistor according to an embodiment of the present disclosure. Referring to Figure 7 , in one embodiment, in the second direction Y, the gate electrode 100 is formed with a first sidewall M1, the first pole 410 is formed with a second sidewall M2, and the slope angle of the second sidewall M2 is smaller than the slope angle of the first sidewall M1. Taking the first pole as the drain as an example, in Figure 7 , the first sidewall M1 can be the right sidewall of the gate electrode 100, the second sidewall M2 can be the sidewall where the drain is in contact with the active layer 300. The slope angle of the first sidewall M1 represents the included angle m formed by the first sidewall M1 and the second direction, and the slope angle of the second sidewall M2 represents the included angle n formed by the second sidewall M2 and the second direction. Setting n less than m can reduce the line width b of the drain at the edge of the gate electrode 100, that is, reduce the size of the drain along the first direction, which can reduce the load on the drain metal line.

[0069] The film thickness of the gate electrode 100 is generally greater than 3000 angstroms, that is, the dimension of the gate electrode 100 in the direction perpendicular to the substrate P is greater than 3000 angstroms. In the related art, the drain metal climbs along the sidewall of the gate insulating layer, and the slope angle of the sidewall of the gate insulating layer 200 is approximately equal to the slope angle of the first sidewall M1. In this way, when the drain metal climbs along the slope angle of the first sidewall M1, due to the relatively large slope angle of the first sidewall M1 of the gate electrode 100, the drain metal is prone to an open circuit problem. In order to prevent the drain open circuit, in the related art, the width of the drain metal is generally set to be greater than 4 μm, which makes the size limitation of the drain metal line more stringent and increases the load on the drain metal line. In the embodiment of the present disclosure, the first part 300a of the active layer 300 is set to extend beyond the gate electrode 100, that is, the boundary of the positive projection of the first part 300a on the substrate is located outside the boundary of the positive projection of the gate electrode 100 on the substrate. In this way, the drain metal climbs along the bottom sidewall of the active layer 300, and the slope angle of the bottom sidewall of the active layer 300 is approximately equal to the slope angle of the second sidewall M2. That is, the drain metal will first climb along the slope angle of the active layer 300, and then the slope becomes gentler when climbing the gate electrode, thereby effectively reducing the occurrence rate of drain metal open, and thus relaxing the line width limitation of the drain metal corresponding to the edge of the gate electrode.

[0070] When the active layer 300 does not extend beyond the gate electrode 100 in the second direction Y, the slope angle of the first pole 410 climbing the gate electrode is the slope angle of the first sidewall M1. When the active layer 300 extends beyond the gate electrode 100 in the second direction Y, the slope angle of the first pole 410 climbing the gate electrode is the slope angle of the second sidewall M2.

[0071] Exemplarily, the range of the slope angle of the first sidewall M1 can be 40° - 55°. For example, the slope angle of the first sidewall M1 can be 40°, 45°, 50°, 55°, etc. When the thickness of the gate electrode 100 is 3000 angstroms, the thickness of the gate insulating layer 200 is 4000 angstroms, the thickness of the active layer 300 is 900 angstroms, and the distance between the boundary of the first part 300a of the active layer 300 and the boundary of the first overlapping part S is 1.3 μm, it can be determined that the range of the slope angle of the second sidewall M2 can be 25° - 31°, that is, the slope angle of the second sidewall M2 can be determined according to the slope angle of the first sidewall M1 and other parameters of the thin film transistor. It should be noted that the slope angle of the first sidewall M1 and the slope angle of the second sidewall M1 are not limited herein and can be set according to actual usage requirements.

[0072] In the thin film transistor of the embodiment of the present disclosure, since the slope angle of the second sidewall M2 is smaller than the slope angle of the first sidewall M1, the line width of the first pole 410 corresponding to the edge of the gate electrode 100 can be effectively reduced, that is, the dimension of the first pole 410 in the first direction X can be reduced, thereby reducing the load on the first pole 410.

[0073] In one embodiment, the size of the first electrode 410 along the first direction X ranges from 2 μm to 6 μm. In the related art, in order to prevent the Open problem of the first electrode due to the slope angle of the first sidewall M1, the width of the first electrode 410 at the edge corresponding to the gate electrode is required to be greater than 4 μm, that is, the size requirements of the first electrode 410 along the first direction are different. In the embodiments of the present disclosure, the size requirements of the first electrode 410 along the first direction X are the same, and the sizes of the first electrode 410 in the first direction X can be set to be equal, that is, the first electrode 410 can be a strip with equal width in the first direction X. Therefore, the load on the first electrode 410 can be reduced, and the pattern shape of the first electrode 410 is simple and easy to control in the process, which can improve the product yield.

[0074] Referring to Figure 4A , exemplarily, the size of the first electrode 410 along the first direction X is b, and b can be from 3 μm to 6 μm. For example, the size of the first electrode 410 along the first direction X can be 3 μm, 4 μm, 5 μm, 6 μm, etc. The embodiments of the present disclosure do not limit the specific size of the first electrode 410, which can be set according to actual use.

[0075] Figure 8 The top view of a thin film transistor according to an embodiment of the present disclosure is shown in reference to Figure 8 As shown, in one embodiment, a recess 310 is provided on the side boundary of the first part 300a away from the second part 300b. The groove edge 311 of the recess 310 is flush with the boundary of the first electrode 410 on the side away from the second electrode 420, that is, the positive projection of the groove edge 311 of the recess 310 on the substrate P coincides with the positive projection of the boundary of the first electrode 410 on the side away from the second electrode 420 on the substrate P. It should be noted that the specific shape of the recess 310 is not limited herein.

[0076] In the embodiments of the present disclosure, the active layer 300 is widened by a certain distance along the first direction X and the second direction Y, so that the facing area between the active layer 300 and the gate electrode 100 in the direction perpendicular to the substrate P is increased, and the capacitance between the gate electrode 100 and the first part 300a is increased. As Figure 6 shown, in the embodiments of the present disclosure, an opening is provided on the boundary of the first electrode 410 on the side away from the second electrode 420, and a recess 310 is provided on the side of the first part 300a away from the second part 300b. In this way, the facing area between the first electrode 410 and the first part 300a in the direction perpendicular to the substrate P can be reduced, so that the capacitance between the first electrode 410 and the first part 300a can be reduced. That is, in the embodiments of the present disclosure, by setting the shape of the active layer 300, the gate capacitance of a single thin film transistor is increased and the first electrode capacitance is reduced, and the thin film transistor can meet the requirements of low load and low power consumption.

[0077] Schematic Table of Capacitance Parameters of Thin Film Transistors in the Related Art and Thin Film Transistors of Embodiments of the Present Disclosure

[0078] Item Conventional TFT Embodiments of the present disclosure Remark C - gate / fF 16.93 18.36 Increased by 8.4% C - drain / fF 6.24 5.63 Decreased by 9.8%

[0079] Table 1 shows the parameters of the gate capacitance and drain capacitance of thin film transistors in the prior art and thin film transistors of this embodiment of the present disclosure. Referring to Table 1, the gate capacitance of the thin film transistor in the related art is 16.93 fF, and the drain capacitance is 6.24 fF. The gate capacitance of the thin film transistor of the embodiment of the present disclosure is 18.36 fF, and the drain capacitance is 5.63 fF. The size of the first pole 410 of the thin film transistor in the related art along the first direction is 4 μm, and the size of the first pole 410 of the thin film transistor of the embodiment of the present disclosure along the first direction is 3.5 μm. In the second direction Y, the distance between the boundary of the first part 300a and the boundary of the first overlapping part S is 1.3 μm, and the size data of the remaining parts are the same for both. It can be seen from the table that, compared with the thin film transistor in the related art, the gate capacitance of the thin film transistor of the embodiment of the present disclosure has increased by 8.4%, and the drain capacitance has decreased by 9.8%. Therefore, the load capacitance of the thin film transistor of the embodiment of the present disclosure has not increased, and even decreased, compared with the load capacitance of the thin film transistor in the related art, which can meet the requirements of low load and low power consumption of the product.

[0080] Referring to Figure 8 , in an embodiment, the recess 310 includes a first side 312 and a second side 313 located on both sides of the groove edge 311. The angle range between the first side 312 or the second side 313 and the groove edge 311 is 120° - 150°. Exemplarily, the groove edge 311 extends along the second direction Y, and the angle range between the first side 312 or the second side 313 and the groove edge 311 is 120° - 150°. In this way, the width of the first part 300a gradually increases from the middle to both sides along the second direction Y. The width represents the size of the first part 300a along the first direction. The groove edge 311 of the recess 310 is flush with the boundary of the first pole 410 on the side away from the second pole 420. In this way, the width of the first pole 410 gradually increases from the middle to both sides along the second direction Y, so as to reduce the facing area between the first pole 410 and the active layer 300 in the direction perpendicular to the substrate P, reduce the capacitance between the first pole 410 and the active layer 300, and the width of the first pole 410 on both sides in the second direction is relatively large, which can prevent an open circuit from occurring when the first pole climbs the gate electrode 100.

[0081] Referring to Figure 8, Exemplarily, the angle between the first side 312 and the groove side 311 is α1, and the range of α1 is 120° - 150°. The angle range between the first side 312 and the groove side 311 is 120°, 125°, 130°, 135°, 140°, 145°, 150°.

[0082] Refer to Figure 8 , Exemplarily, the angle range between the second side 313 and the groove side 311 is α2, and the range of α2 is 120° - 150°. The angle range between the second side 313 and the groove side 311 is 120°, 125°, 130°, 135°, 140°, 145°, 150°.

[0083] It should be noted that the included angle between the first side 312 and the groove side 311 can be equal to the included angle between the second side 313 and the groove side 311, that is, the first side 312 and the second side 313 are symmetrically arranged with respect to the midline of the groove side 311. Or, the included angle between the first side 312 and the groove side 311 can also be unequal to the included angle between the second side 313 and the groove side 311, but their ranges are both between 120° - 150°.

[0084] Next, in combination with Figure 4A and Figure 4B The preparation process of the thin - film transistor of the present disclosure will be introduced in detail. It can be understood that when the material for patterning is an inorganic material or a metal, "patterning" includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping. When the material for patterning is an organic material, "patterning" includes processes such as mask exposure and development. Evaporation, deposition, coating, etc. mentioned in this article are all mature preparation processes in related technologies.

[0085] The preparation method of the thin - film transistor according to the embodiment of the present disclosure includes:

[0086] Form a substrate P;

[0087] Form a gate electrode 100 on one side of the substrate P;

[0088] Form a gate insulating layer 200 on the side of the gate electrode 100 facing away from the substrate P. The thickness of the gate insulating layer 200 can be 3500 angstroms - 4000 angstroms, and the material of the gate insulating layer 200 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0089] Form an active layer 300 on the side of the gate insulating layer 200 facing away from the substrate P. The material of the active layer 300 can include an oxide semiconductor material;

[0090] A source-drain electrode layer 400 is formed on a side of the active layer facing away from the substrate P. The source-drain electrode layer 400 includes a first electrode 410 and a second electrode 420 which are spaced apart along a first direction X. A portion where a positive projection of the gate electrode 100 on the substrate P intersects with a positive projection of the first electrode 410 on the substrate P is a first overlapping portion S, and a positive projection of the first overlapping portion S on the substrate P is located within a positive projection of the active layer 300 on the substrate P.

[0091] Thus, by making the positive projection of the first overlapping portion S on the substrate P be located within the positive projection of the active layer 300 on the substrate P, it is ensured that there are the gate insulating layer 200 and the active layer 300 between the gate electrode 100 and the first electrode 410 in all cases, increasing the vertical distance between the gate electrode 100 and the first electrode 410, thereby increasing the electron movement distance and reducing the short-circuit incidence rate between the gate electrode 100 and the first electrode 410.

[0092] Figure 9 A schematic diagram of a substrate according to an embodiment of the present disclosure. Referring to Figure 9 the present disclosure also provides a substrate, including: a substrate P and a thin-film transistor according to any embodiment of the present disclosure, and the thin-film transistor is disposed on the substrate P. Exemplarily, the substrate may include a plurality of switching units disposed on the substrate P. For example, one switching unit may be disposed in a sub-pixel region, and the respective switching units may be arranged in an array. The switching unit may be configured to control the light-emitting brightness of the sub-pixel region. Specifically, a switching unit includes at least one thin-film transistor, and the at least one thin-film transistor is disposed on the substrate. By the on and off of the at least one thin-film transistor, the switching unit can control the light-emitting brightness of the sub-pixel region, thereby realizing the image display function of the display panel.

[0093] In one embodiment, the substrate P is a rigid substrate. For example, the rigid substrate may be a glass substrate or a polymethyl methacrylate (PMMA) substrate, etc. Alternatively, the substrate P may also be a flexible substrate. For example, the flexible substrate may be any one of a polyethylene terephthalate (PET) substrate, a polyimide (PI) substrate, or an ultra-thin glass. The material of the substrate P is not limited herein and can be selected according to actual situations.

[0094] In one embodiment, the substrate can be an array substrate in any one of an organic light-emitting diode display panel (OLED) and a quantum dot light-emitting diodes display panel (QLED). Exemplarily, a switching unit in the substrate can include a plurality of thin-film transistors, and the thin-film transistors can be coupled to each other to form a pixel driving circuit. The pixel driving circuit can be coupled to a light-emitting device and is configured to drive the light-emitting device to emit light and control the light-emitting brightness of the light-emitting device, thereby controlling the light output brightness to implement the image display function of the display panel.

[0095] In one embodiment, the substrate can be an array substrate in a liquid crystal display panel. The liquid crystal display panel can further include a color filter substrate, and the color filter substrate is disposed opposite to the substrate. The liquid crystal display panel can include liquid crystal located between the substrate and the color filter substrate. At this time, in the substrate, a switching unit can include a single thin-film transistor, and the thin-film transistors can be arranged in an array.

[0096] In one embodiment, the substrate can further include a data line and a gate line. The data line and the gate line can be coupled to at least one thin-film transistor in the switching unit and are configured to write an electrical signal to the thin-film transistor. Exemplarily, a first pole 410 of the thin-film transistor can be coupled to a pixel electrode, a second pole 420 can be coupled to the data line, and a gate electrode 100 can be coupled to the gate line. In this way, in response to the electrical signal written from the gate line to the gate electrode, the thin-film transistor can be turned on and off. When the thin-film transistor is in an on state, the electrical signal on the data line can be written to the pixel electrode through the thin-film transistor, thereby driving the sub-pixel to emit light.

[0097] Another embodiment of the present disclosure provides a display device including the substrate of the embodiment of the present disclosure or the display panel in the embodiment of the present disclosure.

[0098] The display device provided by the embodiment of the present disclosure can be, for example, any product or component having display and touch functions such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, an in-vehicle display, an e-book, a biometric device such as a smart skin device, a soft robot, and a biomedical device.

[0099] The thin-film transistors, substrates, and other components of the display device in the above embodiments can adopt various technical solutions known to those of ordinary skill in the art now and in the future, and will not be described in detail here.

[0100] In the description of this specification, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure.

[0101] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0102] In the present disclosure, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0103] In the present disclosure, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over", and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "beneath", and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely means that the horizontal height of the first feature is lower than that of the second feature.

[0104] The foregoing disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. To simplify the present disclosure, components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0105] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of various changes or substitutions, and these should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A thin film transistor, characterized in that, Comprising, A gate electrode, a gate insulating layer, an active layer, and a source-drain electrode layer that are sequentially stacked on one side of a substrate, wherein the source-drain electrode layer includes a first pole and a second pole that are spaced apart along a first direction; A portion where the orthographic projection of the gate electrode on the substrate intersects with the orthographic projection of the first pole on the substrate is a first overlapping portion, and the orthographic projection of the first overlapping portion on the substrate is located within the orthographic projection of the active layer on the substrate; The active layer includes a first part and a second part that are connected to each other, the first part extends along a second direction, the second part extends along the first direction, the first direction intersects with the second direction, the orthographic projection of the first part on the substrate partially overlaps with the orthographic projection of the first pole on the substrate, and the orthographic projection of the second part on the substrate partially overlaps with the orthographic projection of the second pole on the substrate.

2. The thin film transistor according to claim 1, characterized in that, The projection of the first overlapping portion on the substrate is located within the orthographic projection of the first part on the substrate.

3. The thin film transistor according to claim 2, wherein, In the first direction, the boundary of the orthographic projection of the first overlapping portion on the substrate is located inside the boundary of the orthographic projection of the first part on the substrate, and the distance between the boundary of the first part and the boundary of the first overlapping portion is 1.0 μm - 3.5 μm.

4. The thin film transistor according to claim 2, characterized in that, In the second direction, the boundary of the orthographic projection of the first overlapping portion on the substrate is located inside the boundary of the orthographic projection of the first part on the substrate, and the distance between the boundary of the first part and the boundary of the first overlapping portion is 1.0 μm - 3.5 μm.

5. The thin film transistor according to claim 2, characterized in that, In the second direction, the boundary of the orthographic projection of the gate electrode on the substrate is located inside the boundary of the orthographic projection of the first part on the substrate, and the boundary of the orthographic projection of the first part on the substrate is located inside the boundary of the orthographic projection of the first pole on the substrate.

6. The thin film transistor according to claim 5, characterized in that, On both sides of the gate electrode in the second direction, first sidewalls are formed, and on both sides of the first pole, second sidewalls are formed, and the slope angle of the second sidewalls is smaller than the slope angle of the first sidewalls.

7. The thin film transistor according to claim 5, wherein the range of the size of the first pole along the first direction is 2 μm - 6 μm.

8. The thin film transistor according to claim 2, wherein A recess is provided on a side boundary of the first part away from the second part, and the groove edge of the recess is flush with the boundary of the first pole away from the second pole.

9. The thin film transistor according to claim 8, wherein, The recess includes a first side edge and a second side edge located on both sides of the groove edge, and the angle range between the first side edge or the second side edge and the groove edge is 120° - 150°.

10. A method for manufacturing a thin film transistor, characterized in that, Including: Forming a gate electrode, a gate insulating layer, an active layer, and a source-drain electrode layer on one side of a substrate, wherein the source-drain electrode layer includes a first pole and a second pole that are spaced apart along a first direction; A portion where the orthographic projection of the gate electrode on the substrate intersects with the orthographic projection of the first pole on the substrate is a first overlapping portion, and the orthographic projection of the first overlapping portion on the substrate is located within the orthographic projection of the active layer on the substrate; The active layer includes a first part and a second part connected to each other. The first part extends along a second direction, and the second part extends along the first direction. The first direction and the second direction intersect. A positive projection of the first part on the substrate overlaps with a positive projection of the first electrode on the substrate in part, and a positive projection of the second part on the substrate overlaps with a positive projection of the second electrode on the substrate in part.

11. A substrate, characterized in that, Comprising: A substrate; The thin film transistor according to any one of claims 1 to 9, disposed on the substrate.

12. A display device, characterized in that, Comprising the substrate according to claim 11.

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