Method of forming semiconductor device structure

Abstract

Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure over a substrate, forming an insulating material proximate the fin structure, depositing a gate dielectric layer over the fin structure, depositing a gate electrode layer on the gate dielectric layer, and forming an opening within the insulating material through the gate electrode layer and the gate dielectric layer via a cyclic process. The cycling process includes performing a first number of cycles, each cycle of the first number of cycles including a first primary etch process having a first plasma bias, performing a second number of cycles, and each cycle of the second number of cycles includes a second primary etch process having a second plasma bias substantially greater than the first plasma bias. The method further includes filling the opening with a dielectric material.

Description

Technical Field

[0001] Multiple embodiments of the present disclosure relate to methods for forming semiconductor device structures, particularly for forming a dielectric material between adjacent gate electrodes. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced multiple generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling also increases the complexity of processing and manufacturing integrated circuits.

[0003] Therefore, there is a need to improve the processes and manufacturing of integrated circuits. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor device structure, comprising: forming a fin structure over a substrate; forming an insulating material adjacent to the fin structure; depositing a gate dielectric layer over the fin structure and the insulating material; depositing a gate electrode layer over the gate dielectric layer; forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material via a cyclic process, wherein the cyclic process comprises: performing a first number of cycles, each cycle of the first number of cycles including a first main etching process having a first plasma bias; and performing a second number of cycles, each cycle of the second number of cycles including a second main etching process having a second plasma bias substantially greater than the first plasma bias; and filling the opening with a dielectric material.

[0005] Other embodiments of the present disclosure provide a method for forming a semiconductor device structure, comprising: forming an insulating material over a substrate; depositing a gate dielectric layer over the insulating material; depositing a gate electrode layer over the gate dielectric layer; forming a mask structure over the gate electrode layer; performing a cyclic process to form an opening through the mask structure and the gate electrode layer; performing a trimming process to remove portions of the mask structure, wherein the trimming process comprises introducing an etchant and a carbon-containing gas; and filling the opening with a dielectric material.

[0006] Some other embodiments of the present disclosure provide a method of forming a semiconductor device structure, comprising: forming an insulating material over a substrate; depositing a gate dielectric layer over the insulating material; depositing a gate electrode layer over the gate dielectric layer; forming a mask structure over the gate electrode layer; performing a cyclic process to form an opening through the mask structure and the gate electrode layer, wherein the opening has a first critical dimension at a top of the mask structure, a second critical dimension at a top of the gate electrode layer, and a third critical dimension at a position below the second critical dimension, and the second critical dimension is substantially larger than the first critical dimension and substantially smaller than the third critical dimension; performing a trimming process to remove portions of the mask structure, wherein after the trimming process the first critical dimension is substantially larger than the second critical dimension, and the second critical dimension is substantially larger than the third critical dimension; and filling the opening with a dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure may be best understood from the following detailed description when read with the accompanying Figure 1 drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 6 is a perspective view of various stages of manufacturing a semiconductor device structure in accordance with some embodiments;

[0009] Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line A-A of Figure 6 in accordance with some embodiments;

[0010] Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line B-B of Figure 6 in accordance with some embodiments;

[0011] Figure 7C 、 Figure 8C 、 Figure 9C 、 Figure 10C 、 Figure 11C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line C-C of Figure 6 in accordance with some embodiments;

[0012] Figures 12A to 12D are cross-sectional side views of respective stages of fabricating a semiconductor device structure taken along line B-B Figure 6 in accordance with some embodiments;

[0013] Figures 13A to 13C are respective views of one of the respective stages of fabricating a semiconductor device structure in accordance with some embodiments;

[0014] Figure 14 is a cross-sectional side view of one of the respective stages of fabricating a semiconductor device structure in accordance with alternative embodiments.

[0015]

Symbol Description

[0016] 100: Semiconductor device structure

[0017] 101: Substrate

[0018] 104: Stack of semiconductor multilayers

[0019] 106: First semiconductor layer (semiconductor layer)

[0020] 108: Second semiconductor layer (semiconductor layer)

[0021] 108-1, 108-2, 108-3: Second semiconductor layer

[0022] 112: Fin structure

[0023] 114: Trench

[0024] 116: Well portion

[0025] 118: Insulating material

[0026] 119: Depression

[0027] 120: Isolation region

[0028] 130: Sacrificial gate structure

[0029] 132: Sacrificial gate dielectric layer

[0030] 134: Sacrificial gate electrode layer

[0031] 136: Mask layer

[0032] 138: Gate spacer

[0033] 144: Dielectric spacer

[0034] 146: Source / drain region

[0035] 162: Contact etch stop layer

[0036] 164: Interlayer dielectric layer

[0037] 170: Gate dielectric layer

[0038] 172: Gate electrode layer

[0039] 180: Mask structure

[0040] 181: Opening

[0041] 182: First dielectric layer

[0042] 184: Semiconductor layer

[0043] 186: Second dielectric layer

[0044] 190: Resist structure

[0045] 191: Dielectric material

[0046] 192: Bottom layer

[0047] 193: Conductive feature

[0048] 194: Intermediate layer

[0049] 195: Silicide layer

[0050] 196: Photoresist layer

[0051] 197: Seam

[0052] 202: Fin structure

[0053] A: Angle

[0054] A - A: Line

[0055] B: Angle

[0056] B - B: Line

[0057] BL: Bottom layer

[0058] C - C: Line

[0059] CD1: Critical dimension

[0060] CD2: Critical dimension

[0061] CD3: Critical dimension

[0062] CD4: Critical dimension

[0063] X: Direction

[0064] Y: Direction

[0065] Z: Direction Detailed Implementation Modes

[0066] The following disclosure provides many different implementation modes or embodiments for implementing different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and not restrictive. For example, in the following description, forming a first feature above or on a second feature may include an implementation mode in which the first feature and the second feature are formed in direct contact, and may also include an implementation mode in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplicity and clarity, and the repetition itself does not imply a relationship between the various implementation modes and / or configurations being discussed.

[0067] Furthermore, to facilitate the description of the relationship between one element or feature and another element or feature as depicted in the drawings, spatial relative terms may be used herein, such as "below", "beneath", "lower", "above", "on top", "upon", "top", "upper", and similar terms. Except for the directions depicted in the drawings, spatial relative terms are intended to encompass different directions of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and accordingly, the spatial relative descriptors used herein may be interpreted in the same manner.

[0068] Although the implementation modes of the present disclosure are discussed with respect to nanostructure channel field-effect transistors, such as gate-all-around (GAA) field-effect transistors, like horizontal gate-all-around (HGAA) field-effect transistors or vertical gate-all-around (VGAA) field-effect transistors, the implementation of some aspects of the present disclosure can be used for other processes and / or other devices, such as planar field-effect transistors, fin field-effect transistors, and other suitable devices. Those of ordinary skill in the art will readily understand other modifications that can be made within the scope of the present disclosure. In the case of adopting a gate-all-around (GAA) transistor structure, the patterned gate-all-around transistor structure can be formed via any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the pattern to be created to have, for example, a smaller pitch (smaller than the pitch obtained using a single direct photolithography process). For example, in one implementation mode, a sacrificial layer is formed above the substrate, and the sacrificial layer is patterned using a photolithography process. Multiple spacers are formed along the sidewalls of the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the remaining spacers can be used to pattern the gate-all-around structure.

[0069] Figures 1 to 13C illustrates an exemplary process for fabricating a semiconductor device structure 100 in accordance with various embodiments of the present disclosure. It should be understood that for additional embodiments of this method, additional operations may be provided before, during, and after the Figures 1 to 13C process shown, and some of the operations described below may be replaced or eliminated. The order of the operations / processes is not restrictive and is interchangeable.

[0070] Figures 1 to 6 is a perspective view of various stages of fabricating a semiconductor device structure 100 in accordance with some embodiments. As shown in Figure 1 , the semiconductor device structure 100 includes a stack 104 of semiconductor multilayers formed above the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0071] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for an n-type field-effect transistor (NFET) and boron for a p-type field-effect transistor (PFET).

[0072] The stack 104 of semiconductor multilayers includes alternating semiconductor layers made of different materials to facilitate the formation of multiple nanostructured channels in a multi-gate device, such as a nanostructured channel field-effect transistor. In some embodiments, the stack 104 of semiconductor multilayers includes a plurality of first semiconductor layers 106 and a plurality of second semiconductor layers 108. In some embodiments, the stack 104 of semiconductor multilayers includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layers 106 and the second semiconductor layers 108 are made of a variety of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0073] The first semiconductor layer 106 and the second semiconductor layer 108 are formed via any suitable deposition process, such as epitaxy. For example, epitaxial growth of the multiple layers of the stack 104 of semiconductor multilayers may be performed via a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0074] The first semiconductor layer 106 or portions thereof may form multiple nanostructured channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term nanostructure is used herein to denote any material portion having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Thus, this term denotes elongated material portions with circular and substantially circular cross-sections, as well as elongated or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructured transistors. The nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0075] Each first semiconductor layer 106 may have a thickness in the range between about 5 nanometers and about 30 nanometers. Each second semiconductor layer 108 may have a thickness that is equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 may have a thickness in the range between about 2 nanometers and about 50 nanometers. As shown in Figure 1 As depicted, three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged, for illustrative purposes only and not to limit what is specifically recited in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the stack 104 of semiconductor multilayers, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0076] In Figure 2 As shown, the fin structure 112 is formed from the stack 104 of semiconductor multilayers. Each fin structure 112 has an upper portion including the semiconductor layers 106, 108, and a well portion 116 formed by the substrate 101. Forming the fin structure 112 may be via patterning a hard mask layer (not shown) formed on the stack 104 of semiconductor multilayers, using a multi-patterning operation including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer into a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form a patterned mask may be performed using an electron beam (e-beam) lithography process. The etching process passes through the hard mask layer, through the stack 104 of semiconductor multilayers, and into the substrate 101 in unprotected areas, forming a plurality of trenches 114, thereby leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. Etching the trenches 114 may use dry etching (such as RIE), wet etching, and / or a combination thereof.

[0077] In Figure 3In, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between the adjacent multiple fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation is performed, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, thereby exposing the tops of the fin structures 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric material, or any suitable dielectric material. The insulating material 118 can be formed via any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0078] In Figure 4 In, the insulating material 118 is recessed to form a plurality of isolation regions 120. The recessing of the insulating material 118 exposes multiple portions of the fin structures 112, such as the stack 104 of semiconductor multilayers. The recessing of the insulating material 118 reveals the trenches 114 between the adjacent multiple fin structures 112. The isolation regions 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101.

[0079] In Figure 5In [description], one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing multiple blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning those layers into the sacrificial gate structure 130. Then, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers for the gate spacers 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portions of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0080] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacers 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0081] Multiple portions of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 are used as channel regions for the semiconductor device structure 100.

[0082] In Figure 6 [description], multiple portions of the fin structure 112 not covered by the sacrificial gate structure 130 and the gate spacers 138 are recessed to a plane that is higher than, equal to, or lower than the top surface of the isolation region 120. The recess 119 of the multiple portions of the fin structure 112 can be accomplished via an etching process, which can be an isotropic or anisotropic etching process, and the etching process can be selective with respect to one or more crystal planes of the substrate 101. The etching process can be dry etching, such as reactive ion etching, neutral beam etching, or the like, or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0083] Figure 7A 、 Figure 7B and Figure 7C are respectively alongFigure 6 1 is a cross-sectional side view of the semiconductor device structure 100 taken along lines AA, BB, and CC.

[0084] Figure 8A , Figure 8B and Figure 8C According to some embodiments, respectively along Figure 6 AA, BB, and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 8A As shown in , multiple edge portions of each second semiconductor layer 108 (e.g., second semiconductor layers 108-1, 108-2, and 108-3) of the semiconductor multilayer stack 104 are horizontally removed along the X direction. The removal of multiple edge portions of the multiple second semiconductor layers 108 forms multiple cavities. In some embodiments, multiple portions of the multiple second semiconductor layers 108 are removed via a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0085] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the plurality of cavities to form a plurality of dielectric spacers 144. The dielectric spacers 144 may be made of a low dielectric constant dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., atomic layer deposition), followed by anisotropic etching to remove portions of the conformal dielectric layer except for the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is covered between the plurality of dielectric spacers 144 along the X direction.

[0086] Figure 9A , Figure 9B and Figure 9C According to some embodiments, respectively along Figure 6 AA, BB, and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 9A and Figure 9CAs shown, the source / drain (S / D) region 146 is formed by the well portion 116. The source / drain region 146 can grow both vertically and horizontally to form multiple crystal planes, which can correspond to the crystal planes of the material for the well portion 116. In the present disclosure, the source region and the drain region can be used interchangeably, and their structures are substantially the same. In addition, the source / drain region can refer to the source or the drain, individually or jointly depending on the context. The source / drain region 146 can be made of one or more layers of Si, SiP, SiC, and SiCP for n-channel field-effect transistors, or Si, SiGe, Ge for p-channel field-effect transistors. For p-channel field-effect transistors, p-type dopants such as boron (B) can also be included in the source / drain region 146. The source / drain region 146 can be formed via an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy.

[0087] Figure 10A , Figure 10B and Figure 10C are cross-sectional side views of one of the respective stages of manufacturing the semiconductor device structure 100 taken along Figure 6 the lines A-A, B-B, and C-C, respectively, according to some embodiments. In Figure 10A , Figure 10B and Figure 10C , a contact etch stop layer (CESL) 162 is conformally formed on multiple exposed surfaces of the semiconductor device structure 100. The contact etch stop layer 162 covers multiple sidewalls of the sacrificial gate structure 130, the insulating material 118, and the source / drain region 146. The contact etch stop layer 162 can include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and can be formed via chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the contact etch stop layer 162 above the semiconductor device structure 100. The material for the interlayer dielectric layer 164 can include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials such as polymers can also be used for the interlayer dielectric layer 164. The interlayer dielectric layer 164 can be deposited via a plasma-enhanced chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after the formation of the interlayer dielectric layer 164, the semiconductor device structure 100 can be subjected to a heat treatment to anneal the interlayer dielectric layer 164.

[0088] After the interlayer dielectric layer 164 is formed, a planarization operation, such as chemical mechanical planarization, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in Figure 10Aand Figure 10B as shown in

[0089] Figure 11A 、 Figure 11B and Figure 11C are cross-sectional side views of one of the respective stages of fabricating the semiconductor device structure 100 taken along lines A-A, B-B, and C-C of Figure 6 as shown in Figure 11A and Figure 11B the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. Removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms openings between the gate spacers 138 and between the first semiconductor layer 106. During the removal process, the interlayer dielectric layer 164 protects the source / drain regions 146. Removal of the sacrificial gate structure 130 can use plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can first be removed via any suitable process, such as dry etching, wet etching, or a combination thereof, and subsequently the sacrificial gate dielectric layer 132 can also be removed via any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the interlayer dielectric layer 164, and the contact etch stop layer 162.

[0090] Removal of multiple portions of the second semiconductor layer 108 can use a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe while substantially not affecting the Si, the dielectric material of the gate spacers 138, and the dielectric spacers 144. In one embodiment, removal of the second semiconductor layer 108 can use a wet etchant, a dry etchant, or any suitable isotropic etchant, such as but not limited to hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4) for the wet etchant, and fluorine-based gases (such as F2) or chlorine-based gases (such as Cl2) for the dry etchant.

[0091] After the formation of the nanostructured channels (i.e., the exposed portions of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the plurality of exposed portions of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the plurality of exposed surfaces of the plurality of first semiconductor layers 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed via chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The gate electrode layer 172 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, tin, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 may be formed via chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited above the upper surface of the interlayer dielectric layer 164. Then, by using, for example, chemical mechanical planarization, the gate dielectric layer 170 and the gate electrode layer 172 formed above the interlayer dielectric layer 164 are removed until the top surface of the interlayer dielectric layer 164 is exposed.

[0092] Figures 12A to 12D is a cross-sectional side view of various stages of the fabrication of the semiconductor device structure 100 taken along line B-B according to some embodiments. As shown in Figure 6 Figure 12A ​As shown in [FIGURE REFERENCE], a mask structure 180 is formed on the gate electrode layer 172 and the interlayer dielectric layer 164, and a resist structure 190 is formed on the mask structure 180. In some embodiments, the mask structure 180 includes a first dielectric layer 182, a semiconductor layer 184 deposited on the first dielectric layer, and a second dielectric layer 186 deposited on the semiconductor layer 184. The first dielectric layer 182 and the second dielectric layer 186 may include any suitable dielectric material. In some embodiments, the first dielectric layer 182 and the second dielectric layer 186 are SiN layers. The semiconductor layer 184 can be any suitable semiconductor layer. In some embodiments, the semiconductor layer 184 is an amorphous silicon layer. In some embodiments, the resist structure 190 is a three-layer photoresist. For example, the resist structure 190 may include a bottom layer 192 deposited on the mask structure 180, an intermediate layer 194 deposited on the bottom layer 192, and a photoresist layer 196 deposited on the intermediate layer 194. The bottom layer 192 and the intermediate layer 194 are made of different materials such that the optical and / or etching characteristics of the bottom layer 192 and the intermediate layer 194 are different from each other. In some embodiments, the bottom layer 192 can be a carbon layer and the intermediate layer 194 can be a silicon-rich layer designed to provide an etching selectivity between the intermediate layer 194 and the bottom layer 192. The photoresist layer 196 can be a chemically amplified photoresist layer and can be a positive-type photoresist or a negative-type photoresist. The photoresist layer 196 may include a polymer such as a phenolic resin, a poly(norbornene)-co-maleic anhydride (COMA) polymer, a poly(4-hydroxystyrene) (PHS) polymer, a phenolic (bakelite) polymer, a polyethylene (PE) polymer, a polypropylene (PP) polymer, a polycarbonate polymer, a polyester polymer, or an acrylate-based polymer such as a polymethyl methacrylate (PMMA) polymer, or a poly(methacrylic acid) (PMAA). The photoresist layer 196 can be formed by spin coating. The photoresist layer 196 can be patterned to form an opening 181 therein.

[0093] As shown in Figure 12B As shown in [FIGURE REFERENCE], the opening 181 extends into the intermediate layer 194, the bottom layer 192, and the mask structure 180. The opening 181 can be extended into the intermediate layer 194, the bottom layer 192, and the mask structure 180 via one or more etching processes. In some embodiments, the resist structure 190 is removed during one or more etching processes to extend the opening 181 into the mask structure 180. In some embodiments, the resist structure 190 is removed after the opening 181 is extended into the mask structure 180. A portion of the gate electrode layer 172 is exposed in the opening 181.

[0094] As shown in Figure 12CAs shown, the exposed portion of the gate electrode layer 172 is removed. The removal of the exposed portion of the gate electrode layer 172 can be via any suitable method. In some embodiments, a cyclic process is performed to remove the exposed portion of the gate electrode layer 172. This cyclic process includes a plurality of cycles, and each cycle includes depositing a layer on the exposed portion of the gate electrode layer 172, oxidizing this layer to form an oxide layer, removing multiple portions of the oxide layer, and removing a portion of the exposed portion of the gate electrode layer 172. In some embodiments, this layer can be a silicon-containing layer and can be formed via any suitable process, such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. A silicon-containing precursor (such as SiCl4) can be introduced into the processing chamber in which the semiconductor device structure 100 is disposed, and this silicon-containing layer is formed on multiple exposed surfaces of the semiconductor device structure 100. In some embodiments, the silicon-containing layer is formed on the second dielectric layer 186, the first dielectric layer 182 in the opening 181, the sidewalls of the semiconductor layer 184 and the second dielectric layer 186, and the exposed surface of the gate electrode layer 172. Next, an oxidation process is performed to oxidize the silicon-containing layer to form an oxide layer, such as a silicon oxide layer. The oxidation process can be any suitable oxidation process, such as a thermal oxidation process. Next, a breakthrough etching process is performed to remove multiple portions of the oxide layer formed on the horizontal surfaces of the semiconductor device structure 100, such as multiple portions of the oxide layer formed on the second dielectric layer 186 and the exposed surface of the gate electrode layer 172. The breakthrough etching process can be an anisotropic dry etching process, such as a plasma etching process. In some embodiments, a fluorine-containing etchant (such as C4F6) can be used in the anisotropic dry etching process. After the breakthrough etching process, the portion of the gate electrode layer 172 located at the bottom of the opening 181 is exposed, and a main etching process is performed to remove a portion of the gate electrode layer 172. In some embodiments, this main etching process is a dry etching process, such as an anisotropic plasma etching process. One or more etchants can be used in the main etching process. In some embodiments, one or more chlorine-containing etchants, such as BCl3 and / or Cl2, can be used. The oxide layer formed on the sidewalls in the opening 181 can also be removed via one or more chlorine-containing etchants. In some embodiments, a deposition gas (such as a silicon-containing gas, like SiCl4) can be introduced into the processing chamber together with the etchant. As the opening 181 extends into the gate electrode layer 172, the deposition gas can form a layer on the sidewalls of the gate electrode layer 172 in the opening 181. This layer protects the sidewalls of the gate electrode layer 172 during the main etching process. In other words, the oxide layer formed on the sidewalls of the opening 181 can be removed by the etchant of the main etching process, and the deposition gas of the main etching process forms this layer on the sidewalls in the opening 181, and this layer can be a silicon layer.In some embodiments, the duration of the main etch process can be rather short, e.g., from about 10 seconds to about 20 seconds.

[0095] A cycle that is repeated multiple times deposits a layer on the exposed portion of the gate electrode layer 172, oxidizes this layer to form an oxide layer, removes multiple portions of the oxide layer, and removes a portion of the exposed portion of the gate electrode layer 172 such that the opening 181 extends through the gate electrode layer 172 and into the insulating material 118, as shown in Figure 12C As shown. After the opening 181 first extends into the gate electrode layer 172, the cycle process deposits a layer on the exposed portion of the gate electrode layer 172 and oxidizes this layer to form an oxide layer, and this oxide layer is formed on multiple sidewalls of the gate electrode layer 172 in the opening 181 to protect the multiple sidewalls of the gate electrode layer 172. In some embodiments, the number of cycles ranges from about 8 to about 15, e.g., 12. At the end of the cycle, the opening 181 extends through the gate electrode layer 172. In some embodiments, the opening 181 extends through the gate dielectric layer 170 and the insulating material 118 and into the substrate 101, as shown in Figure 12C As shown. In some embodiments, the opening 181 extends into the substrate 101 by about 5 nanometers to about 35 nanometers.

[0096] In some embodiments, one or more wet cleaning processes may be performed between multiple cycles to remove by-products formed in the etching process. For example, in some embodiments, after seven cycles, a wet cleaning process is performed. The wet cleaning process substantially does not affect the materials of the semiconductor device structure 100, such as the gate electrode layer 172 and the gate dielectric layer 170. The wet cleaning process is performed after a first number of cycles, and a second number of cycles are performed after the wet cleaning process. In some embodiments, the first number of cycles is greater than the second number of cycles. For example, the first number of cycles includes seven cycles, and the second number of cycles includes five cycles. In some embodiments, each cycle of the first number of cycles includes a main etching process having a first plasma bias, and each cycle of the second number of cycles includes a main etching process having a second plasma bias that is substantially greater than the first plasma bias. For example, the main etching process of the first number of cycles has a first plasma bias ranging from about 150 V to about 250 V, and the main etching process of the second number of cycles has a second plasma bias ranging from about 800 V to about 1200 V. In some embodiments, the second plasma bias is about three to about seven times the first plasma bias. A higher plasma bias may result in a more anisotropic etching process, which reduces the critical dimension CD3 but increases the critical dimensions CD1 and CD2. The higher the bias, the more the critical dimension CD2 may increase due to more plasma bombardment. In some embodiments, the critical dimension CD1 is substantially greater than the critical dimension CD2 of the opening 181 at the top of the mask structure 180, and is substantially less than the critical dimension CD3 of the opening 181 at a position below the portion below the opening 181 having the critical dimension CD1, as shown in Figure 12C as shown. In some embodiments, the critical dimension CD3 is located at a position adjacent to the top surface of the topmost first semiconductor layer 106, as shown in Figure 12C as shown. Because the main etching process is substantially selective (i.e., the gate electrode layer 172 is etched at a much faster rate than the material of the mask structure 180), the critical dimension CD1 is substantially less than the critical dimension CD2. As described above, the second plasma bias is substantially greater than the first plasma bias. As a result, the critical dimension CD3 is substantially greater than the critical dimension CD1.

[0097] As shown in Figure 12DAs shown, a trimming process can be performed to remove multiple portions of the mask structure 180, thereby widening the opening 181 in the mask structure 180. In other words, the trimming process enlarges the critical dimension CD2. In some embodiments, a plasma etching process is performed to trim the mask structure 180. The plasma etching process can utilize a fluorine-containing etchant, such as C4F6. In some embodiments, the critical dimension CD1 is also enlarged via the trimming process. If the critical dimension CD1 becomes too large, the conductive contacts formed on the gate electrode layer 172 may then be on a portion of the dielectric material 191 formed in the opening 181 ( Figure 13B ), resulting in an increase in contact resistance. In some embodiments, to prevent the critical dimension CD1 from becoming too large, a carbon-containing gas (such as CH4) is introduced together with the fluorine-containing etchant during the plasma etching process. The carbon-containing gas can form a polymer layer on multiple sidewalls of the opening 181. As a result, the angle A formed between the sidewall of the mask structure 180 exposed to the opening 181 and the top surface of the gate electrode layer 172 is greater than about 75 degrees, for example, from about 75 degrees to about 90 degrees. If the angle A is greater than about 90 degrees, the critical dimension CD2 may be too small, and large seams or voids may be formed in the dielectric material 191 ( Figure 13B ). On the other hand, if the angle A is less than about 75 degrees, the top portion of the gate electrode layer 172 exposed to the opening 181 may be removed, resulting in an increased critical dimension CD1. In some embodiments, an angle B is formed between the sidewall of the gate electrode layer 172 exposed in the opening 181 and the top surface of the gate electrode layer 172, and the range of the angle B is from about 90 degrees to about 95 degrees. In some embodiments, the angle B is substantially greater than the angle A.

[0098] In some embodiments, a polymer layer is formed on multiple sidewalls of the mask structure 180, the gate electrode layer 172, and the insulating material 118 exposed to the opening 181. A plasma process can be performed to remove the polymer layer. In some embodiments, the plasma process is an oxygen plasma combustion process, in which the polymer layer is removed via an oxygen-containing plasma. The plasma process is different from the trimming process.

[0099] After the trimming process and the plasma process, a wet cleaning process may be performed to remove any by-products generated from the trimming process. In some embodiments, after the wet cleaning process, the critical dimension CD1 may range from about 19 nanometers to about 26 nanometers, and the critical dimension CD3 may range from about 19 nanometers to about 26 nanometers. In some embodiments, the critical dimension CD3 is less than the critical dimension CD1. The critical dimension CD4 located at the bottom of the opening 181 may be in the range from about 12 nanometers to about 16 nanometers. In some embodiments, the width of the first semiconductor layer 106 in the Y direction ranges from about 20 nanometers to about 40 nanometers. In some embodiments, the width of the first semiconductor layer 106 may be greater than the critical dimension CD1. In some embodiments, the width of the first semiconductor layer 106 may be less than the critical dimension CD1.

[0100] Figures 13A to 13C are various views of one of the various stages of manufacturing the semiconductor device structure 100 according to some embodiments. As shown in Figures 13A to 13C , a dielectric material 191 is formed in the opening 181, the mask structure 180 is removed, and a conductive feature 193 is formed in the interlayer dielectric layer 164. A silicide layer 195 may be formed between the source / drain region 146 and the conductive feature 193. The dielectric material 191 may include any suitable dielectric material, such as SiN, HfO, SiNO x , or ZrO. The conductive feature 193 may include any suitable conductive material, such as a metal. The silicide layer 195 may be a metal silicide layer, which is the result of a reaction between the metal of the conductive feature 193 and the semiconductor material of the source / drain region 146. In some embodiments, a seam 197 is formed in the dielectric material 191. Since the critical dimension CD1 is greater than the critical dimension CD3, the seam 197 may have a dimension less than about 1 nanometer in the Y direction.

[0101] Figure 14 is a cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100 according to an alternative embodiment. As described above, the semiconductor device structure 100 may include a nanostructure channel field-effect transistor. In some embodiments, the semiconductor device structure 100 includes a fin field-effect transistor. As shown in Figure 14 , the semiconductor device structure 100 includes one or more fin structures 202 extending from the substrate 101, a gate dielectric layer 170 formed around the fin structures 202, and a gate electrode layer 172 formed on the gate dielectric layer 170. An opening 181 is formed in the mask structure 180, the gate electrode layer 172, the insulating material 118, and into the substrate 101. In some embodiments, the width of the fin structures 202 in the Y direction ranges from about 5 nanometers to about 8 nanometers, and the critical dimension CD4 is substantially greater than the width of the fin structures 202.

[0102] Multiple embodiments of the present disclosure provide a method of forming a semiconductor device structure 100. The method includes forming an opening through a gate electrode layer 172 via a cyclic process and performing a trimming process to remove portions of a mask structure 180. The cyclic process includes a first plurality of cycles, a second plurality of cycles, and a cleaning process separating the first plurality of cycles and the second plurality of cycles. The main etching process of the first plurality of cycles includes a first plasma bias that is substantially less than a second plasma bias of the main etching process of the second plurality of cycles. Some embodiments can achieve multiple advantages. For example, as the plasma bias increases, the critical dimension CD1 of the portion of the opening 181 located at the top of the gate electrode layer 172 remains small. In addition, the trimming process includes a carbon-containing gas to form a polymer layer on the sidewalls of the opening 181, and the critical dimension CD1 is not unnecessarily enlarged.

[0103] One embodiment is a method. The method includes forming a fin structure above a substrate, forming an insulating material adjacent to the fin structure, depositing a gate dielectric layer over the fin structure and the insulating material, depositing a gate electrode layer over the gate dielectric layer, and forming an opening through the gate electrode layer and the gate dielectric layer within the insulating material via a cyclic process. The cyclic process includes performing a first number of cycles, each cycle of the first number of cycles including a first main etching process having a first plasma bias, performing a second number of cycles, and each cycle of the second number of cycles including a second main etching process having a second plasma bias that is substantially greater than the first plasma bias. The method further includes filling the opening with a dielectric material.

[0104] In some embodiments, the fin structure includes a plurality of semiconductor layers, and the gate dielectric layer and the gate electrode layer surround a portion of each of the plurality of semiconductor layers.

[0105] In some embodiments, the first plasma bias ranges from about 150V to about 250V, and the second plasma bias ranges from about 800V to about 1200V.

[0106] In some embodiments, the first number of cycles includes more cycles than the second number of cycles.

[0107] In some embodiments, each cycle of the first number of cycles includes: depositing a layer over the gate electrode layer; oxidizing the layer to form an oxide layer; removing a portion of the oxide layer; and performing the first main etching process to remove a portion of the gate electrode layer.

[0108] In some embodiments, the first main etching process uses one or more chlorine-containing etchants.

[0109] In some embodiments, the one or more chlorine-containing etchants comprise BCl3 and Cl2.

[0110] In some embodiments, the method further comprises performing a cleaning process between the first number of cycles and the second number of cycles.

[0111] Another embodiment is a method. The method includes forming an insulating material over a substrate, depositing a gate dielectric layer over the insulating material, depositing a gate electrode layer over the gate dielectric layer, forming a mask structure over the gate electrode layer, performing a cyclic process to form an opening through the mask structure and the gate electrode layer, and performing a trimming process to remove portions of the mask structure. The trimming process includes introducing an etchant and a carbon-containing gas. The method further includes filling the opening with a dielectric material.

[0112] In some embodiments, the trimming process is a plasma etch process.

[0113] In some embodiments, a polymer layer is formed on sidewalls of the opening during the trimming process.

[0114] In some embodiments, the method further comprises a plasma process to remove the polymer layer after the trimming process.

[0115] In some embodiments, the plasma process forms an oxygen-containing plasma.

[0116] Another embodiment is a method. The method includes forming an insulating material over a substrate, depositing a gate dielectric layer over the insulating material, depositing a gate electrode layer over the gate dielectric layer, forming a mask structure over the gate electrode layer, and performing a cyclic process to form an opening through the mask structure and the gate electrode layer. The opening has a first critical dimension at the top of the mask structure, a second critical dimension at the top of the gate electrode layer, a third critical dimension at a position below the second critical dimension, and the second critical dimension is substantially greater than the first critical dimension and substantially less than the third critical dimension. The method further includes performing a trimming process to remove portions of the mask structure. After the trimming process, the first critical dimension is substantially greater than the second critical dimension, and the second critical dimension is substantially greater than the third critical dimension. The method further includes filling the opening with a dielectric material.

[0117] In some embodiments, after the trimming process, a first angle is formed between a sidewall of the mask structure exposed in the opening and a top surface of the gate electrode layer, and the first angle ranges from about 75 degrees to about 90 degrees.

[0118] In some embodiments, after the trimming process, a second angle is formed between a sidewall of the gate electrode layer exposed in the opening and the top surface of the gate electrode layer, and the range of the second angle is from about 90 degrees to about 95 degrees.

[0119] In some embodiments, the second angle is substantially greater than the first angle.

[0120] In some embodiments, the method further includes forming a plurality of semiconductor layers, wherein the gate dielectric layer and the gate electrode layer surround the plurality of semiconductor layers.

[0121] In some embodiments, the method further includes forming a fin structure, wherein the gate dielectric layer and the gate electrode layer are disposed around the fin structure.

[0122] In some embodiments, the method further includes, after the trimming process, performing a plasma process to remove a polymer layer from the sidewalls of the opening.

[0123] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor device structure, characterized in that, Comprising: Forming a fin structure above a substrate; Forming an insulating material adjacent to the fin structure; Depositing a gate dielectric layer above the fin structure and the insulating material; Depositing a gate electrode layer on the gate dielectric layer; Forming an opening through the gate electrode layer and the gate dielectric layer into the insulating material via a cyclic process, wherein the cyclic process comprises: Performing a first number of cycles, wherein each cycle of the first number of cycles includes a first main etching process having a first plasma bias; And Performing a second number of cycles, wherein each cycle of the second number of cycles includes a second main etching process having a second plasma bias substantially greater than the first plasma bias; and Filling the opening with a dielectric material.

2. The method of forming a semiconductor device structure according to claim 1, wherein, The first plasma bias ranges from 150V to 250V, and the second plasma bias ranges from 800V to 1200V.

3. The method of forming a semiconductor device structure according to claim 1, wherein Each cycle of the first number of cycles comprises: Depositing a layer on the gate electrode layer; Oxidizing the layer to form an oxide layer; Removing a portion of the oxide layer; And Performing the first main etching process to remove a portion of the gate electrode layer.

4. The method of forming a semiconductor device structure according to claim 1, wherein, Also comprising performing a cleaning process between the first number of cycles and the second number of cycles.

5. A method of forming a semiconductor device structure, characterized in that, Comprising: Forming an insulating material above a substrate; Depositing a gate dielectric layer on the insulating material; Depositing a gate electrode layer on the gate dielectric layer; Forming a mask structure on the gate electrode layer; Performing a cyclic process to form an opening through the mask structure and the gate electrode layer; Performing a trimming process to remove multiple portions of the mask structure, wherein the trimming process comprises introducing an etchant and a carbon-containing gas; And Filling the opening with a dielectric material.

6. The method of forming a semiconductor device structure according to claim 5, wherein, The trimming process is a plasma etching process.

7. The method for forming a semiconductor device structure according to claim 6, wherein, Forming a polymer layer on multiple sidewalls of the opening during the trimming process.

8. A method of forming a semiconductor device structure, characterized in that, Comprising: Forming an insulating material above a substrate; Depositing a gate dielectric layer on the insulating material; Depositing a gate electrode layer on the gate dielectric layer; Forming a mask structure on the gate electrode layer; Performing a cyclic process to form an opening through the mask structure and the gate electrode layer, wherein the opening has a first critical dimension at a top of the mask structure, a second critical dimension at a top of the gate electrode layer, a third critical dimension at a position below the second critical dimension, and the second critical dimension is substantially greater than the first critical dimension and substantially less than the third critical dimension; Performing a trimming process to remove multiple portions of the mask structure, wherein after the trimming process the first critical dimension is substantially greater than the second critical dimension, and the second critical dimension is substantially greater than the third critical dimension; and Filling the opening with a dielectric material.

9. The method of forming a semiconductor device structure as claimed in claim 8, wherein, After the trimming process, forming a first angle between a sidewall of the mask structure exposed in the opening and a top surface of the gate electrode layer, and the first angle ranges from 75 degrees to 90 degrees.

10. The method of forming a semiconductor device structure according to claim 8, wherein, It further includes that after the trimming process, a plasma process is performed to remove a polymer layer from multiple sidewalls of the opening.

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